1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Tegra 124 cpufreq driver
4 */
5
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8 #include <linux/clk.h>
9 #include <linux/cpufreq.h>
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_opp.h>
17 #include <linux/types.h>
18
19 struct tegra124_cpufreq_priv {
20 struct clk *cpu_clk;
21 struct clk *pllp_clk;
22 struct clk *pllx_clk;
23 struct clk *dfll_clk;
24 struct platform_device *cpufreq_dt_pdev;
25 };
26
tegra124_cpu_switch_to_dfll(struct tegra124_cpufreq_priv * priv)27 static int tegra124_cpu_switch_to_dfll(struct tegra124_cpufreq_priv *priv)
28 {
29 struct clk *orig_parent;
30 int ret;
31
32 ret = clk_set_rate(priv->dfll_clk, clk_get_rate(priv->cpu_clk));
33 if (ret)
34 return ret;
35
36 orig_parent = clk_get_parent(priv->cpu_clk);
37 clk_set_parent(priv->cpu_clk, priv->pllp_clk);
38
39 ret = clk_prepare_enable(priv->dfll_clk);
40 if (ret)
41 goto out;
42
43 clk_set_parent(priv->cpu_clk, priv->dfll_clk);
44
45 return 0;
46
47 out:
48 clk_set_parent(priv->cpu_clk, orig_parent);
49
50 return ret;
51 }
52
tegra124_cpufreq_probe(struct platform_device * pdev)53 static int tegra124_cpufreq_probe(struct platform_device *pdev)
54 {
55 struct device_node *np __free(device_node) = of_cpu_device_node_get(0);
56 struct tegra124_cpufreq_priv *priv;
57 struct device *cpu_dev;
58 struct platform_device_info cpufreq_dt_devinfo = {};
59 int ret;
60
61 if (!np)
62 return -ENODEV;
63
64 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
65 if (!priv)
66 return -ENOMEM;
67
68 cpu_dev = get_cpu_device(0);
69 if (!cpu_dev)
70 return -ENODEV;
71
72 priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");
73 if (IS_ERR(priv->cpu_clk))
74 return PTR_ERR(priv->cpu_clk);
75
76 priv->dfll_clk = of_clk_get_by_name(np, "dfll");
77 if (IS_ERR(priv->dfll_clk)) {
78 ret = PTR_ERR(priv->dfll_clk);
79 goto out_put_cpu_clk;
80 }
81
82 priv->pllx_clk = of_clk_get_by_name(np, "pll_x");
83 if (IS_ERR(priv->pllx_clk)) {
84 ret = PTR_ERR(priv->pllx_clk);
85 goto out_put_dfll_clk;
86 }
87
88 priv->pllp_clk = of_clk_get_by_name(np, "pll_p");
89 if (IS_ERR(priv->pllp_clk)) {
90 ret = PTR_ERR(priv->pllp_clk);
91 goto out_put_pllx_clk;
92 }
93
94 ret = tegra124_cpu_switch_to_dfll(priv);
95 if (ret)
96 goto out_put_pllp_clk;
97
98 cpufreq_dt_devinfo.name = "cpufreq-dt";
99 cpufreq_dt_devinfo.parent = &pdev->dev;
100
101 priv->cpufreq_dt_pdev =
102 platform_device_register_full(&cpufreq_dt_devinfo);
103 if (IS_ERR(priv->cpufreq_dt_pdev)) {
104 ret = PTR_ERR(priv->cpufreq_dt_pdev);
105 goto out_put_pllp_clk;
106 }
107
108 platform_set_drvdata(pdev, priv);
109
110 return 0;
111
112 out_put_pllp_clk:
113 clk_put(priv->pllp_clk);
114 out_put_pllx_clk:
115 clk_put(priv->pllx_clk);
116 out_put_dfll_clk:
117 clk_put(priv->dfll_clk);
118 out_put_cpu_clk:
119 clk_put(priv->cpu_clk);
120
121 return ret;
122 }
123
tegra124_cpufreq_suspend(struct device * dev)124 static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev)
125 {
126 struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
127 int err;
128
129 /*
130 * PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to
131 * use during suspend and resume. So, switch the CPU clock source
132 * to PLLP and disable DFLL.
133 */
134 err = clk_set_parent(priv->cpu_clk, priv->pllp_clk);
135 if (err < 0) {
136 dev_err(dev, "failed to reparent to PLLP: %d\n", err);
137 return err;
138 }
139
140 clk_disable_unprepare(priv->dfll_clk);
141
142 return 0;
143 }
144
tegra124_cpufreq_resume(struct device * dev)145 static int __maybe_unused tegra124_cpufreq_resume(struct device *dev)
146 {
147 struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
148 int err;
149
150 /*
151 * Warmboot code powers up the CPU with PLLP clock source.
152 * Enable DFLL clock and switch CPU clock source back to DFLL.
153 */
154 err = clk_prepare_enable(priv->dfll_clk);
155 if (err < 0) {
156 dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err);
157 goto disable_cpufreq;
158 }
159
160 err = clk_set_parent(priv->cpu_clk, priv->dfll_clk);
161 if (err < 0) {
162 dev_err(dev, "failed to reparent to DFLL clock: %d\n", err);
163 goto disable_dfll;
164 }
165
166 return 0;
167
168 disable_dfll:
169 clk_disable_unprepare(priv->dfll_clk);
170 disable_cpufreq:
171 disable_cpufreq();
172
173 return err;
174 }
175
176 static const struct dev_pm_ops tegra124_cpufreq_pm_ops = {
177 SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend,
178 tegra124_cpufreq_resume)
179 };
180
181 static struct platform_driver tegra124_cpufreq_platdrv = {
182 .driver.name = "cpufreq-tegra124",
183 .driver.pm = &tegra124_cpufreq_pm_ops,
184 .probe = tegra124_cpufreq_probe,
185 };
186
tegra_cpufreq_init(void)187 static int __init tegra_cpufreq_init(void)
188 {
189 int ret;
190 struct platform_device *pdev;
191
192 if (!(of_machine_is_compatible("nvidia,tegra124") ||
193 of_machine_is_compatible("nvidia,tegra210")))
194 return -ENODEV;
195
196 /*
197 * Platform driver+device required for handling EPROBE_DEFER with
198 * the regulator and the DFLL clock
199 */
200 ret = platform_driver_register(&tegra124_cpufreq_platdrv);
201 if (ret)
202 return ret;
203
204 pdev = platform_device_register_simple("cpufreq-tegra124", -1, NULL, 0);
205 if (IS_ERR(pdev)) {
206 platform_driver_unregister(&tegra124_cpufreq_platdrv);
207 return PTR_ERR(pdev);
208 }
209
210 return 0;
211 }
212 module_init(tegra_cpufreq_init);
213
214 MODULE_AUTHOR("Tuomas Tynkkynen <ttynkkynen@nvidia.com>");
215 MODULE_DESCRIPTION("cpufreq driver for NVIDIA Tegra124");
216