1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASM_X86_APIC_H 3 #define _ASM_X86_APIC_H 4 5 #include <linux/cpumask.h> 6 #include <linux/static_call.h> 7 8 #include <asm/alternative.h> 9 #include <asm/cpufeature.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 #include <asm/hardirq.h> 16 #include <asm/io.h> 17 #include <asm/posted_intr.h> 18 19 #define ARCH_APICTIMER_STOPS_ON_C3 1 20 21 /* Macros for apic_extnmi which controls external NMI masking */ 22 #define APIC_EXTNMI_BSP 0 /* Default */ 23 #define APIC_EXTNMI_ALL 1 24 #define APIC_EXTNMI_NONE 2 25 26 /* 27 * Debugging macros 28 */ 29 #define APIC_QUIET 0 30 #define APIC_VERBOSE 1 31 #define APIC_DEBUG 2 32 33 /* 34 * Define the default level of output to be very little This can be turned 35 * up by using apic=verbose for more information and apic=debug for _lots_ 36 * of information. apic_verbosity is defined in apic.c 37 */ 38 #define apic_printk(v, s, a...) \ 39 do { \ 40 if ((v) <= apic_verbosity) \ 41 printk(s, ##a); \ 42 } while (0) 43 44 #define apic_pr_verbose(s, a...) apic_printk(APIC_VERBOSE, KERN_INFO s, ##a) 45 #define apic_pr_debug(s, a...) apic_printk(APIC_DEBUG, KERN_DEBUG s, ##a) 46 #define apic_pr_debug_cont(s, a...) apic_printk(APIC_DEBUG, KERN_CONT s, ##a) 47 /* Unconditional debug prints for code which is guarded by apic_verbosity already */ 48 #define apic_dbg(s, a...) printk(KERN_DEBUG s, ##a) 49 50 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 51 extern void x86_32_probe_apic(void); 52 #else 53 static inline void x86_32_probe_apic(void) { } 54 #endif 55 56 extern u32 cpuid_to_apicid[]; 57 58 #define CPU_ACPIID_INVALID U32_MAX 59 60 #ifdef CONFIG_X86_LOCAL_APIC 61 62 extern int apic_verbosity; 63 extern int local_apic_timer_c2_ok; 64 65 extern bool apic_is_disabled; 66 extern unsigned int lapic_timer_period; 67 68 extern enum apic_intr_mode_id apic_intr_mode; 69 enum apic_intr_mode_id { 70 APIC_PIC, 71 APIC_VIRTUAL_WIRE, 72 APIC_VIRTUAL_WIRE_NO_CONFIG, 73 APIC_SYMMETRIC_IO, 74 APIC_SYMMETRIC_IO_NO_ROUTING 75 }; 76 77 /* 78 * With 82489DX we can't rely on apic feature bit 79 * retrieved via cpuid but still have to deal with 80 * such an apic chip so we assume that SMP configuration 81 * is found from MP table (64bit case uses ACPI mostly 82 * which set smp presence flag as well so we are safe 83 * to use this helper too). 84 */ 85 static inline bool apic_from_smp_config(void) 86 { 87 return smp_found_config && !apic_is_disabled; 88 } 89 90 /* 91 * Basic functions accessing APICs. 92 */ 93 static inline void native_apic_mem_write(u32 reg, u32 v) 94 { 95 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 96 97 alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP, 98 ASM_OUTPUT("=r" (v), "=m" (*addr)), 99 ASM_INPUT("0" (v), "m" (*addr))); 100 } 101 102 static inline u32 native_apic_mem_read(u32 reg) 103 { 104 return readl((void __iomem *)(APIC_BASE + reg)); 105 } 106 107 static inline void native_apic_mem_eoi(void) 108 { 109 native_apic_mem_write(APIC_EOI, APIC_EOI_ACK); 110 } 111 112 extern void native_apic_icr_write(u32 low, u32 id); 113 extern u64 native_apic_icr_read(void); 114 115 static inline bool apic_is_x2apic_enabled(void) 116 { 117 u64 msr; 118 119 if (rdmsrq_safe(MSR_IA32_APICBASE, &msr)) 120 return false; 121 return msr & X2APIC_ENABLE; 122 } 123 124 extern void enable_IR_x2apic(void); 125 126 extern int lapic_get_maxlvt(void); 127 extern void clear_local_APIC(void); 128 extern void disconnect_bsp_APIC(int virt_wire_setup); 129 extern void disable_local_APIC(void); 130 extern void apic_soft_disable(void); 131 extern void lapic_shutdown(void); 132 extern void sync_Arb_IDs(void); 133 extern void init_bsp_APIC(void); 134 extern void apic_intr_mode_select(void); 135 extern void apic_intr_mode_init(void); 136 extern void init_apic_mappings(void); 137 void register_lapic_address(unsigned long address); 138 extern void setup_boot_APIC_clock(void); 139 extern void setup_secondary_APIC_clock(void); 140 extern void lapic_update_tsc_freq(void); 141 142 #ifdef CONFIG_X86_64 143 static inline bool apic_force_enable(unsigned long addr) 144 { 145 return false; 146 } 147 #else 148 extern bool apic_force_enable(unsigned long addr); 149 #endif 150 151 extern void apic_ap_setup(void); 152 153 /* 154 * On 32bit this is mach-xxx local 155 */ 156 #ifdef CONFIG_X86_64 157 extern int apic_is_clustered_box(void); 158 #else 159 static inline int apic_is_clustered_box(void) 160 { 161 return 0; 162 } 163 #endif 164 165 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 166 extern void lapic_assign_system_vectors(void); 167 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 168 extern void lapic_update_legacy_vectors(void); 169 extern void lapic_online(void); 170 extern void lapic_offline(void); 171 extern bool apic_needs_pit(void); 172 173 extern void apic_send_IPI_allbutself(unsigned int vector); 174 175 extern void topology_register_apic(u32 apic_id, u32 acpi_id, bool present); 176 extern void topology_register_boot_apic(u32 apic_id); 177 extern int topology_hotplug_apic(u32 apic_id, u32 acpi_id); 178 extern void topology_hotunplug_apic(unsigned int cpu); 179 extern void topology_apply_cmdline_limits_early(void); 180 extern void topology_init_possible_cpus(void); 181 extern void topology_reset_possible_cpus_up(void); 182 183 #else /* !CONFIG_X86_LOCAL_APIC */ 184 static inline void lapic_shutdown(void) { } 185 #define local_apic_timer_c2_ok 1 186 static inline void init_apic_mappings(void) { } 187 static inline void disable_local_APIC(void) { } 188 # define setup_boot_APIC_clock x86_init_noop 189 # define setup_secondary_APIC_clock x86_init_noop 190 static inline void lapic_update_tsc_freq(void) { } 191 static inline void init_bsp_APIC(void) { } 192 static inline void apic_intr_mode_select(void) { } 193 static inline void apic_intr_mode_init(void) { } 194 static inline void lapic_assign_system_vectors(void) { } 195 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 196 static inline bool apic_needs_pit(void) { return true; } 197 static inline void topology_apply_cmdline_limits_early(void) { } 198 static inline void topology_init_possible_cpus(void) { } 199 #endif /* !CONFIG_X86_LOCAL_APIC */ 200 201 #ifdef CONFIG_X86_X2APIC 202 static inline void native_apic_msr_write(u32 reg, u32 v) 203 { 204 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 205 reg == APIC_LVR) 206 return; 207 208 wrmsrq(APIC_BASE_MSR + (reg >> 4), v); 209 } 210 211 static inline void native_apic_msr_eoi(void) 212 { 213 native_wrmsrq(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK); 214 } 215 216 static inline u32 native_apic_msr_read(u32 reg) 217 { 218 u64 msr; 219 220 if (reg == APIC_DFR) 221 return -1; 222 223 rdmsrq(APIC_BASE_MSR + (reg >> 4), msr); 224 return (u32)msr; 225 } 226 227 static inline void native_x2apic_icr_write(u32 low, u32 id) 228 { 229 wrmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 230 } 231 232 static inline u64 native_x2apic_icr_read(void) 233 { 234 unsigned long val; 235 236 rdmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), val); 237 return val; 238 } 239 240 extern int x2apic_mode; 241 extern int x2apic_phys; 242 extern void __init x2apic_set_max_apicid(u32 apicid); 243 extern void x2apic_setup(void); 244 static inline int x2apic_enabled(void) 245 { 246 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 247 } 248 249 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 250 #else /* !CONFIG_X86_X2APIC */ 251 static inline void x2apic_setup(void) { } 252 static inline int x2apic_enabled(void) { return 0; } 253 static inline u32 native_apic_msr_read(u32 reg) { BUG(); } 254 #define x2apic_mode (0) 255 #define x2apic_supported() (0) 256 #endif /* !CONFIG_X86_X2APIC */ 257 extern void __init check_x2apic(void); 258 259 struct irq_data; 260 261 /* 262 * Copyright 2004 James Cleverdon, IBM. 263 * 264 * Generic APIC sub-arch data struct. 265 * 266 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 267 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 268 * James Cleverdon. 269 */ 270 struct apic { 271 /* Hotpath functions first */ 272 void (*eoi)(void); 273 void (*native_eoi)(void); 274 void (*write)(u32 reg, u32 v); 275 u32 (*read)(u32 reg); 276 277 /* IPI related functions */ 278 void (*wait_icr_idle)(void); 279 u32 (*safe_wait_icr_idle)(void); 280 281 void (*send_IPI)(int cpu, int vector); 282 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 283 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 284 void (*send_IPI_allbutself)(int vector); 285 void (*send_IPI_all)(int vector); 286 void (*send_IPI_self)(int vector); 287 288 u32 disable_esr : 1, 289 dest_mode_logical : 1, 290 x2apic_set_max_apicid : 1, 291 nmi_to_offline_cpu : 1; 292 293 u32 (*calc_dest_apicid)(unsigned int cpu); 294 295 /* ICR related functions */ 296 u64 (*icr_read)(void); 297 void (*icr_write)(u32 low, u32 high); 298 299 /* The limit of the APIC ID space. */ 300 u32 max_apic_id; 301 302 /* Probe, setup and smpboot functions */ 303 int (*probe)(void); 304 void (*setup)(void); 305 void (*teardown)(void); 306 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 307 308 void (*init_apic_ldr)(void); 309 u32 (*cpu_present_to_apicid)(int mps_cpu); 310 311 u32 (*get_apic_id)(u32 id); 312 313 /* wakeup_secondary_cpu */ 314 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip, unsigned int cpu); 315 /* wakeup secondary CPU using 64-bit wakeup point */ 316 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip, unsigned int cpu); 317 318 void (*update_vector)(unsigned int cpu, unsigned int vector, bool set); 319 320 char *name; 321 }; 322 323 struct apic_override { 324 void (*eoi)(void); 325 void (*native_eoi)(void); 326 void (*write)(u32 reg, u32 v); 327 u32 (*read)(u32 reg); 328 void (*send_IPI)(int cpu, int vector); 329 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 330 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 331 void (*send_IPI_allbutself)(int vector); 332 void (*send_IPI_all)(int vector); 333 void (*send_IPI_self)(int vector); 334 u64 (*icr_read)(void); 335 void (*icr_write)(u32 low, u32 high); 336 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip, unsigned int cpu); 337 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip, unsigned int cpu); 338 }; 339 340 /* 341 * Pointer to the local APIC driver in use on this system (there's 342 * always just one such driver in use - the kernel decides via an 343 * early probing process which one it picks - and then sticks to it): 344 */ 345 extern struct apic *apic; 346 347 /* 348 * APIC drivers are probed based on how they are listed in the .apicdrivers 349 * section. So the order is important and enforced by the ordering 350 * of different apic driver files in the Makefile. 351 */ 352 #define apic_driver(sym) \ 353 static const struct apic *__apicdrivers_##sym __used \ 354 __aligned(sizeof(struct apic *)) \ 355 __section(".apicdrivers") = { &sym } 356 357 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 358 359 /* 360 * APIC functionality to boot other CPUs - only used on SMP: 361 */ 362 #ifdef CONFIG_SMP 363 extern int lapic_can_unplug_cpu(void); 364 #endif 365 366 #ifdef CONFIG_X86_LOCAL_APIC 367 extern struct apic_override __x86_apic_override; 368 369 void __init apic_setup_apic_calls(void); 370 void __init apic_install_driver(struct apic *driver); 371 372 #define apic_update_callback(_callback, _fn) { \ 373 __x86_apic_override._callback = _fn; \ 374 apic->_callback = _fn; \ 375 static_call_update(apic_call_##_callback, _fn); \ 376 pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \ 377 } 378 379 #define DECLARE_APIC_CALL(__cb) \ 380 DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb) 381 382 DECLARE_APIC_CALL(eoi); 383 DECLARE_APIC_CALL(native_eoi); 384 DECLARE_APIC_CALL(icr_read); 385 DECLARE_APIC_CALL(icr_write); 386 DECLARE_APIC_CALL(read); 387 DECLARE_APIC_CALL(send_IPI); 388 DECLARE_APIC_CALL(send_IPI_mask); 389 DECLARE_APIC_CALL(send_IPI_mask_allbutself); 390 DECLARE_APIC_CALL(send_IPI_allbutself); 391 DECLARE_APIC_CALL(send_IPI_all); 392 DECLARE_APIC_CALL(send_IPI_self); 393 DECLARE_APIC_CALL(wait_icr_idle); 394 DECLARE_APIC_CALL(wakeup_secondary_cpu); 395 DECLARE_APIC_CALL(wakeup_secondary_cpu_64); 396 DECLARE_APIC_CALL(write); 397 398 static __always_inline u32 apic_read(u32 reg) 399 { 400 return static_call(apic_call_read)(reg); 401 } 402 403 static __always_inline void apic_write(u32 reg, u32 val) 404 { 405 static_call(apic_call_write)(reg, val); 406 } 407 408 static __always_inline void apic_eoi(void) 409 { 410 static_call(apic_call_eoi)(); 411 } 412 413 static __always_inline void apic_native_eoi(void) 414 { 415 static_call(apic_call_native_eoi)(); 416 } 417 418 static __always_inline u64 apic_icr_read(void) 419 { 420 return static_call(apic_call_icr_read)(); 421 } 422 423 static __always_inline void apic_icr_write(u32 low, u32 high) 424 { 425 static_call(apic_call_icr_write)(low, high); 426 } 427 428 static __always_inline void __apic_send_IPI(int cpu, int vector) 429 { 430 static_call(apic_call_send_IPI)(cpu, vector); 431 } 432 433 static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector) 434 { 435 static_call_mod(apic_call_send_IPI_mask)(mask, vector); 436 } 437 438 static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 439 { 440 static_call(apic_call_send_IPI_mask_allbutself)(mask, vector); 441 } 442 443 static __always_inline void __apic_send_IPI_allbutself(int vector) 444 { 445 static_call(apic_call_send_IPI_allbutself)(vector); 446 } 447 448 static __always_inline void __apic_send_IPI_all(int vector) 449 { 450 static_call(apic_call_send_IPI_all)(vector); 451 } 452 453 static __always_inline void __apic_send_IPI_self(int vector) 454 { 455 static_call_mod(apic_call_send_IPI_self)(vector); 456 } 457 458 static __always_inline void apic_wait_icr_idle(void) 459 { 460 static_call_cond(apic_call_wait_icr_idle)(); 461 } 462 463 static __always_inline u32 safe_apic_wait_icr_idle(void) 464 { 465 return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; 466 } 467 468 static __always_inline bool apic_id_valid(u32 apic_id) 469 { 470 return apic_id <= apic->max_apic_id; 471 } 472 473 static __always_inline void apic_update_vector(unsigned int cpu, unsigned int vector, bool set) 474 { 475 if (apic->update_vector) 476 apic->update_vector(cpu, vector, set); 477 } 478 479 #else /* CONFIG_X86_LOCAL_APIC */ 480 481 static inline u32 apic_read(u32 reg) { return 0; } 482 static inline void apic_write(u32 reg, u32 val) { } 483 static inline void apic_eoi(void) { } 484 static inline u64 apic_icr_read(void) { return 0; } 485 static inline void apic_icr_write(u32 low, u32 high) { } 486 static inline void apic_wait_icr_idle(void) { } 487 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 488 static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); } 489 static inline void apic_setup_apic_calls(void) { } 490 static inline void apic_update_vector(unsigned int cpu, unsigned int vector, bool set) { } 491 492 #define apic_update_callback(_callback, _fn) do { } while (0) 493 494 #endif /* CONFIG_X86_LOCAL_APIC */ 495 496 extern void apic_ack_irq(struct irq_data *data); 497 498 #define APIC_VECTOR_TO_BIT_NUMBER(v) ((unsigned int)(v) % 32) 499 #define APIC_VECTOR_TO_REG_OFFSET(v) ((unsigned int)(v) / 32 * 0x10) 500 501 static inline bool lapic_vector_set_in_irr(unsigned int vector) 502 { 503 u32 irr = apic_read(APIC_IRR + APIC_VECTOR_TO_REG_OFFSET(vector)); 504 505 return !!(irr & (1U << APIC_VECTOR_TO_BIT_NUMBER(vector))); 506 } 507 508 static inline bool is_vector_pending(unsigned int vector) 509 { 510 return lapic_vector_set_in_irr(vector) || pi_pending_this_cpu(vector); 511 } 512 513 #define MAX_APIC_VECTOR 256 514 #define APIC_VECTORS_PER_REG 32 515 516 /* 517 * Vector states are maintained by APIC in 32-bit registers that are 518 * 16 bytes aligned. The status of each vector is kept in a single 519 * bit. 520 */ 521 static inline int apic_find_highest_vector(void *bitmap) 522 { 523 int vec; 524 u32 *reg; 525 526 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; vec >= 0; vec -= APIC_VECTORS_PER_REG) { 527 reg = bitmap + APIC_VECTOR_TO_REG_OFFSET(vec); 528 if (*reg) 529 return __fls(*reg) + vec; 530 } 531 532 return -1; 533 } 534 535 static inline u32 apic_get_reg(void *regs, int reg) 536 { 537 return *((u32 *) (regs + reg)); 538 } 539 540 static inline void apic_set_reg(void *regs, int reg, u32 val) 541 { 542 *((u32 *) (regs + reg)) = val; 543 } 544 545 static __always_inline u64 apic_get_reg64(void *regs, int reg) 546 { 547 BUILD_BUG_ON(reg != APIC_ICR); 548 return *((u64 *) (regs + reg)); 549 } 550 551 static __always_inline void apic_set_reg64(void *regs, int reg, u64 val) 552 { 553 BUILD_BUG_ON(reg != APIC_ICR); 554 *((u64 *) (regs + reg)) = val; 555 } 556 557 static inline void apic_clear_vector(int vec, void *bitmap) 558 { 559 clear_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFFSET(vec)); 560 } 561 562 static inline void apic_set_vector(int vec, void *bitmap) 563 { 564 set_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFFSET(vec)); 565 } 566 567 static inline int apic_test_vector(int vec, void *bitmap) 568 { 569 return test_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFFSET(vec)); 570 } 571 572 /* 573 * Warm reset vector position: 574 */ 575 #define TRAMPOLINE_PHYS_LOW 0x467 576 #define TRAMPOLINE_PHYS_HIGH 0x469 577 578 #ifdef CONFIG_X86_LOCAL_APIC 579 580 #include <asm/smp.h> 581 582 extern struct apic apic_noop; 583 584 static inline u32 read_apic_id(void) 585 { 586 u32 reg = apic_read(APIC_ID); 587 588 return apic->get_apic_id(reg); 589 } 590 591 #ifdef CONFIG_X86_64 592 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); 593 extern int default_acpi_madt_oem_check(char *, char *); 594 extern void x86_64_probe_apic(void); 595 #else 596 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } 597 static inline void x86_64_probe_apic(void) { } 598 #endif 599 600 extern u32 apic_default_calc_apicid(unsigned int cpu); 601 extern u32 apic_flat_calc_apicid(unsigned int cpu); 602 603 extern u32 default_cpu_present_to_apicid(int mps_cpu); 604 605 void apic_send_nmi_to_offline_cpu(unsigned int cpu); 606 607 #else /* CONFIG_X86_LOCAL_APIC */ 608 609 static inline u32 read_apic_id(void) { return 0; } 610 611 #endif /* !CONFIG_X86_LOCAL_APIC */ 612 613 #ifdef CONFIG_SMP 614 void apic_smt_update(void); 615 #else 616 static inline void apic_smt_update(void) { } 617 #endif 618 619 struct msi_msg; 620 struct irq_cfg; 621 622 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 623 bool dmar); 624 625 extern void ioapic_zap_locks(void); 626 627 #endif /* _ASM_X86_APIC_H */ 628