1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
4 *
5 * Copyright (C) 2014-2024 Broadcom
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/spinlock.h>
15 #include <linux/of.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_address.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/io.h>
21 #include <linux/irqdomain.h>
22 #include <linux/irqchip.h>
23 #include <linux/irqchip/chained_irq.h>
24
25 struct brcmstb_intc_init_params {
26 irq_flow_handler_t handler;
27 int cpu_status;
28 int cpu_clear;
29 int cpu_mask_status;
30 int cpu_mask_set;
31 int cpu_mask_clear;
32 };
33
34 /* Register offsets in the L2 latched interrupt controller */
35 static const struct brcmstb_intc_init_params l2_edge_intc_init = {
36 .handler = handle_edge_irq,
37 .cpu_status = 0x00,
38 .cpu_clear = 0x08,
39 .cpu_mask_status = 0x0c,
40 .cpu_mask_set = 0x10,
41 .cpu_mask_clear = 0x14
42 };
43
44 /* Register offsets in the L2 level interrupt controller */
45 static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
46 .handler = handle_level_irq,
47 .cpu_status = 0x00,
48 .cpu_clear = -1, /* Register not present */
49 .cpu_mask_status = 0x04,
50 .cpu_mask_set = 0x08,
51 .cpu_mask_clear = 0x0C
52 };
53
54 /* L2 intc private data structure */
55 struct brcmstb_l2_intc_data {
56 struct irq_domain *domain;
57 struct irq_chip_generic *gc;
58 int status_offset;
59 int mask_offset;
60 bool can_wake;
61 u32 saved_mask; /* for suspend/resume */
62 };
63
64 /**
65 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
66 * @d: irq_data
67 *
68 * Chip has separate enable/disable registers instead of a single mask
69 * register and pending interrupt is acknowledged by setting a bit.
70 *
71 * Note: This function is generic and could easily be added to the
72 * generic irqchip implementation if there ever becomes a will to do so.
73 * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
74 *
75 * e.g.: https://patchwork.kernel.org/patch/9831047/
76 */
brcmstb_l2_mask_and_ack(struct irq_data * d)77 static void brcmstb_l2_mask_and_ack(struct irq_data *d)
78 {
79 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
80 struct irq_chip_type *ct = irq_data_get_chip_type(d);
81 u32 mask = d->mask;
82
83 irq_gc_lock(gc);
84 irq_reg_writel(gc, mask, ct->regs.disable);
85 *ct->mask_cache &= ~mask;
86 irq_reg_writel(gc, mask, ct->regs.ack);
87 irq_gc_unlock(gc);
88 }
89
brcmstb_l2_intc_irq_handle(struct irq_desc * desc)90 static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
91 {
92 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
93 struct irq_chip *chip = irq_desc_get_chip(desc);
94 unsigned int irq;
95 u32 status;
96
97 chained_irq_enter(chip, desc);
98
99 status = irq_reg_readl(b->gc, b->status_offset) &
100 ~(irq_reg_readl(b->gc, b->mask_offset));
101
102 if (status == 0) {
103 raw_spin_lock(&desc->lock);
104 handle_bad_irq(desc);
105 raw_spin_unlock(&desc->lock);
106 goto out;
107 }
108
109 do {
110 irq = ffs(status) - 1;
111 status &= ~(1 << irq);
112 generic_handle_domain_irq(b->domain, irq);
113 } while (status);
114 out:
115 /* Don't ack parent before all device writes are done */
116 wmb();
117
118 chained_irq_exit(chip, desc);
119 }
120
__brcmstb_l2_intc_suspend(struct irq_data * d,bool save)121 static void __brcmstb_l2_intc_suspend(struct irq_data *d, bool save)
122 {
123 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
124 struct irq_chip_type *ct = irq_data_get_chip_type(d);
125 struct brcmstb_l2_intc_data *b = gc->private;
126 unsigned long flags;
127
128 irq_gc_lock_irqsave(gc, flags);
129 /* Save the current mask */
130 if (save)
131 b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
132
133 if (b->can_wake) {
134 /* Program the wakeup mask */
135 irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
136 irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
137 }
138 irq_gc_unlock_irqrestore(gc, flags);
139 }
140
brcmstb_l2_intc_shutdown(struct irq_data * d)141 static void brcmstb_l2_intc_shutdown(struct irq_data *d)
142 {
143 __brcmstb_l2_intc_suspend(d, false);
144 }
145
brcmstb_l2_intc_suspend(struct irq_data * d)146 static void brcmstb_l2_intc_suspend(struct irq_data *d)
147 {
148 __brcmstb_l2_intc_suspend(d, true);
149 }
150
brcmstb_l2_intc_resume(struct irq_data * d)151 static void brcmstb_l2_intc_resume(struct irq_data *d)
152 {
153 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
154 struct irq_chip_type *ct = irq_data_get_chip_type(d);
155 struct brcmstb_l2_intc_data *b = gc->private;
156 unsigned long flags;
157
158 irq_gc_lock_irqsave(gc, flags);
159 if (ct->chip.irq_ack) {
160 /* Clear unmasked non-wakeup interrupts */
161 irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
162 ct->regs.ack);
163 }
164
165 /* Restore the saved mask */
166 irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
167 irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
168 irq_gc_unlock_irqrestore(gc, flags);
169 }
170
brcmstb_l2_intc_of_init(struct device_node * np,struct device_node * parent,const struct brcmstb_intc_init_params * init_params)171 static int __init brcmstb_l2_intc_of_init(struct device_node *np,
172 struct device_node *parent,
173 const struct brcmstb_intc_init_params
174 *init_params)
175 {
176 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
177 unsigned int set = 0;
178 struct brcmstb_l2_intc_data *data;
179 struct irq_chip_type *ct;
180 int ret;
181 unsigned int flags;
182 int parent_irq;
183 void __iomem *base;
184
185 data = kzalloc(sizeof(*data), GFP_KERNEL);
186 if (!data)
187 return -ENOMEM;
188
189 base = of_iomap(np, 0);
190 if (!base) {
191 pr_err("failed to remap intc L2 registers\n");
192 ret = -ENOMEM;
193 goto out_free;
194 }
195
196 /* Disable all interrupts by default */
197 writel(0xffffffff, base + init_params->cpu_mask_set);
198
199 /* Wakeup interrupts may be retained from S5 (cold boot) */
200 data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
201 if (!data->can_wake && (init_params->cpu_clear >= 0))
202 writel(0xffffffff, base + init_params->cpu_clear);
203
204 parent_irq = irq_of_parse_and_map(np, 0);
205 if (!parent_irq) {
206 pr_err("failed to find parent interrupt\n");
207 ret = -EINVAL;
208 goto out_unmap;
209 }
210
211 data->domain = irq_domain_add_linear(np, 32,
212 &irq_generic_chip_ops, NULL);
213 if (!data->domain) {
214 ret = -ENOMEM;
215 goto out_unmap;
216 }
217
218 /* MIPS chips strapped for BE will automagically configure the
219 * peripheral registers for CPU-native byte order.
220 */
221 flags = 0;
222 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
223 flags |= IRQ_GC_BE_IO;
224
225 if (init_params->handler == handle_level_irq)
226 set |= IRQ_LEVEL;
227
228 /* Allocate a single Generic IRQ chip for this node */
229 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
230 np->full_name, init_params->handler, clr, set, flags);
231 if (ret) {
232 pr_err("failed to allocate generic irq chip\n");
233 goto out_free_domain;
234 }
235
236 /* Set the IRQ chaining logic */
237 irq_set_chained_handler_and_data(parent_irq,
238 brcmstb_l2_intc_irq_handle, data);
239
240 data->gc = irq_get_domain_generic_chip(data->domain, 0);
241 data->gc->reg_base = base;
242 data->gc->private = data;
243 data->status_offset = init_params->cpu_status;
244 data->mask_offset = init_params->cpu_mask_status;
245
246 ct = data->gc->chip_types;
247
248 if (init_params->cpu_clear >= 0) {
249 ct->regs.ack = init_params->cpu_clear;
250 ct->chip.irq_ack = irq_gc_ack_set_bit;
251 ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
252 } else {
253 /* No Ack - but still slightly more efficient to define this */
254 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
255 }
256
257 ct->chip.irq_mask = irq_gc_mask_disable_reg;
258 ct->regs.disable = init_params->cpu_mask_set;
259 ct->regs.mask = init_params->cpu_mask_status;
260
261 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
262 ct->regs.enable = init_params->cpu_mask_clear;
263
264 ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
265 ct->chip.irq_resume = brcmstb_l2_intc_resume;
266 ct->chip.irq_pm_shutdown = brcmstb_l2_intc_shutdown;
267
268 if (data->can_wake) {
269 /* This IRQ chip can wake the system, set all child interrupts
270 * in wake_enabled mask
271 */
272 data->gc->wake_enabled = 0xffffffff;
273 ct->chip.irq_set_wake = irq_gc_set_wake;
274 enable_irq_wake(parent_irq);
275 }
276
277 pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);
278
279 return 0;
280
281 out_free_domain:
282 irq_domain_remove(data->domain);
283 out_unmap:
284 iounmap(base);
285 out_free:
286 kfree(data);
287 return ret;
288 }
289
brcmstb_l2_edge_intc_of_init(struct device_node * np,struct device_node * parent)290 static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
291 struct device_node *parent)
292 {
293 return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
294 }
295
brcmstb_l2_lvl_intc_of_init(struct device_node * np,struct device_node * parent)296 static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
297 struct device_node *parent)
298 {
299 return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
300 }
301
302 IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2)
303 IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init)
304 IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init)
305 IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init)
306 IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init)
307 IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2)
308 MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");
309 MODULE_LICENSE("GPL v2");
310