1 // SPDX-License-Identifier: GPL-2.0
2
3 /*
4 * Hyper-V specific APIC code.
5 *
6 * Copyright (C) 2018, Microsoft, Inc.
7 *
8 * Author : K. Y. Srinivasan <kys@microsoft.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
17 * NON INFRINGEMENT. See the GNU General Public License for more
18 * details.
19 *
20 */
21
22 #include <linux/types.h>
23 #include <linux/vmalloc.h>
24 #include <linux/mm.h>
25 #include <linux/clockchips.h>
26 #include <linux/slab.h>
27 #include <linux/cpuhotplug.h>
28 #include <asm/hypervisor.h>
29 #include <asm/mshyperv.h>
30 #include <asm/apic.h>
31 #include <asm/msr.h>
32
33 #include <asm/trace/hyperv.h>
34
35 static struct apic orig_apic;
36
hv_apic_icr_read(void)37 static u64 hv_apic_icr_read(void)
38 {
39 u64 reg_val;
40
41 rdmsrq(HV_X64_MSR_ICR, reg_val);
42 return reg_val;
43 }
44
hv_apic_icr_write(u32 low,u32 id)45 static void hv_apic_icr_write(u32 low, u32 id)
46 {
47 u64 reg_val;
48
49 reg_val = SET_XAPIC_DEST_FIELD(id);
50 reg_val = reg_val << 32;
51 reg_val |= low;
52
53 wrmsrq(HV_X64_MSR_ICR, reg_val);
54 }
55
hv_enable_coco_interrupt(unsigned int cpu,unsigned int vector,bool set)56 void hv_enable_coco_interrupt(unsigned int cpu, unsigned int vector, bool set)
57 {
58 apic_update_vector(cpu, vector, set);
59 }
60
hv_apic_read(u32 reg)61 static u32 hv_apic_read(u32 reg)
62 {
63 u32 reg_val, hi;
64
65 switch (reg) {
66 case APIC_EOI:
67 rdmsr(HV_X64_MSR_EOI, reg_val, hi);
68 (void)hi;
69 return reg_val;
70 case APIC_TASKPRI:
71 rdmsr(HV_X64_MSR_TPR, reg_val, hi);
72 (void)hi;
73 return reg_val;
74
75 default:
76 return native_apic_mem_read(reg);
77 }
78 }
79
hv_apic_write(u32 reg,u32 val)80 static void hv_apic_write(u32 reg, u32 val)
81 {
82 switch (reg) {
83 case APIC_EOI:
84 wrmsrq(HV_X64_MSR_EOI, val);
85 break;
86 case APIC_TASKPRI:
87 wrmsrq(HV_X64_MSR_TPR, val);
88 break;
89 default:
90 native_apic_mem_write(reg, val);
91 }
92 }
93
hv_apic_eoi_write(void)94 static void hv_apic_eoi_write(void)
95 {
96 struct hv_vp_assist_page *hvp = hv_vp_assist_page[smp_processor_id()];
97
98 if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1))
99 return;
100
101 wrmsrq(HV_X64_MSR_EOI, APIC_EOI_ACK);
102 }
103
cpu_is_self(int cpu)104 static bool cpu_is_self(int cpu)
105 {
106 return cpu == smp_processor_id();
107 }
108
109 /*
110 * IPI implementation on Hyper-V.
111 */
__send_ipi_mask_ex(const struct cpumask * mask,int vector,bool exclude_self)112 static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector,
113 bool exclude_self)
114 {
115 struct hv_send_ipi_ex *ipi_arg;
116 unsigned long flags;
117 int nr_bank = 0;
118 u64 status = HV_STATUS_INVALID_PARAMETER;
119
120 if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
121 return false;
122
123 local_irq_save(flags);
124 ipi_arg = *this_cpu_ptr(hyperv_pcpu_input_arg);
125
126 if (unlikely(!ipi_arg))
127 goto ipi_mask_ex_done;
128
129 ipi_arg->vector = vector;
130 ipi_arg->reserved = 0;
131 ipi_arg->vp_set.valid_bank_mask = 0;
132
133 /*
134 * Use HV_GENERIC_SET_ALL and avoid converting cpumask to VP_SET
135 * when the IPI is sent to all currently present CPUs.
136 */
137 if (!cpumask_equal(mask, cpu_present_mask) || exclude_self) {
138 ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
139
140 nr_bank = cpumask_to_vpset_skip(&ipi_arg->vp_set, mask,
141 exclude_self ? cpu_is_self : NULL);
142
143 /*
144 * 'nr_bank <= 0' means some CPUs in cpumask can't be
145 * represented in VP_SET. Return an error and fall back to
146 * native (architectural) method of sending IPIs.
147 */
148 if (nr_bank <= 0)
149 goto ipi_mask_ex_done;
150 } else {
151 ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;
152 }
153
154 /*
155 * For this hypercall, Hyper-V treats the valid_bank_mask field
156 * of ipi_arg->vp_set as part of the fixed size input header.
157 * So the variable input header size is equal to nr_bank.
158 */
159 status = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank,
160 ipi_arg, NULL);
161
162 ipi_mask_ex_done:
163 local_irq_restore(flags);
164 return hv_result_success(status);
165 }
166
__send_ipi_mask(const struct cpumask * mask,int vector,bool exclude_self)167 static bool __send_ipi_mask(const struct cpumask *mask, int vector,
168 bool exclude_self)
169 {
170 int cur_cpu, vcpu, this_cpu = smp_processor_id();
171 struct hv_send_ipi ipi_arg;
172 u64 status;
173 unsigned int weight;
174
175 trace_hyperv_send_ipi_mask(mask, vector);
176
177 weight = cpumask_weight(mask);
178
179 /*
180 * Do nothing if
181 * 1. the mask is empty
182 * 2. the mask only contains self when exclude_self is true
183 */
184 if (weight == 0 ||
185 (exclude_self && weight == 1 && cpumask_test_cpu(this_cpu, mask)))
186 return true;
187
188 /* A fully enlightened TDX VM uses GHCI rather than hv_hypercall_pg. */
189 if (!hv_hypercall_pg) {
190 if (ms_hyperv.paravisor_present || !hv_isolation_type_tdx())
191 return false;
192 }
193
194 if (vector < HV_IPI_LOW_VECTOR || vector > HV_IPI_HIGH_VECTOR)
195 return false;
196
197 /*
198 * From the supplied CPU set we need to figure out if we can get away
199 * with cheaper HVCALL_SEND_IPI hypercall. This is possible when the
200 * highest VP number in the set is < 64. As VP numbers are usually in
201 * ascending order and match Linux CPU ids, here is an optimization:
202 * we check the VP number for the highest bit in the supplied set first
203 * so we can quickly find out if using HVCALL_SEND_IPI_EX hypercall is
204 * a must. We will also check all VP numbers when walking the supplied
205 * CPU set to remain correct in all cases.
206 */
207 if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64)
208 goto do_ex_hypercall;
209
210 ipi_arg.vector = vector;
211 ipi_arg.cpu_mask = 0;
212
213 for_each_cpu(cur_cpu, mask) {
214 if (exclude_self && cur_cpu == this_cpu)
215 continue;
216 vcpu = hv_cpu_number_to_vp_number(cur_cpu);
217 if (vcpu == VP_INVAL)
218 return false;
219
220 /*
221 * This particular version of the IPI hypercall can
222 * only target up to 64 CPUs.
223 */
224 if (vcpu >= 64)
225 goto do_ex_hypercall;
226
227 __set_bit(vcpu, (unsigned long *)&ipi_arg.cpu_mask);
228 }
229
230 status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, ipi_arg.vector,
231 ipi_arg.cpu_mask);
232 return hv_result_success(status);
233
234 do_ex_hypercall:
235 return __send_ipi_mask_ex(mask, vector, exclude_self);
236 }
237
__send_ipi_one(int cpu,int vector)238 static bool __send_ipi_one(int cpu, int vector)
239 {
240 int vp = hv_cpu_number_to_vp_number(cpu);
241 u64 status;
242
243 trace_hyperv_send_ipi_one(cpu, vector);
244
245 if (vp == VP_INVAL)
246 return false;
247
248 /* A fully enlightened TDX VM uses GHCI rather than hv_hypercall_pg. */
249 if (!hv_hypercall_pg) {
250 if (ms_hyperv.paravisor_present || !hv_isolation_type_tdx())
251 return false;
252 }
253
254 if (vector < HV_IPI_LOW_VECTOR || vector > HV_IPI_HIGH_VECTOR)
255 return false;
256
257 if (vp >= 64)
258 return __send_ipi_mask_ex(cpumask_of(cpu), vector, false);
259
260 status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, vector, BIT_ULL(vp));
261 return hv_result_success(status);
262 }
263
hv_send_ipi(int cpu,int vector)264 static void hv_send_ipi(int cpu, int vector)
265 {
266 if (!__send_ipi_one(cpu, vector))
267 orig_apic.send_IPI(cpu, vector);
268 }
269
hv_send_ipi_mask(const struct cpumask * mask,int vector)270 static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
271 {
272 if (!__send_ipi_mask(mask, vector, false))
273 orig_apic.send_IPI_mask(mask, vector);
274 }
275
hv_send_ipi_mask_allbutself(const struct cpumask * mask,int vector)276 static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
277 {
278 if (!__send_ipi_mask(mask, vector, true))
279 orig_apic.send_IPI_mask_allbutself(mask, vector);
280 }
281
hv_send_ipi_allbutself(int vector)282 static void hv_send_ipi_allbutself(int vector)
283 {
284 hv_send_ipi_mask_allbutself(cpu_online_mask, vector);
285 }
286
hv_send_ipi_all(int vector)287 static void hv_send_ipi_all(int vector)
288 {
289 if (!__send_ipi_mask(cpu_online_mask, vector, false))
290 orig_apic.send_IPI_all(vector);
291 }
292
hv_send_ipi_self(int vector)293 static void hv_send_ipi_self(int vector)
294 {
295 if (!__send_ipi_one(smp_processor_id(), vector))
296 orig_apic.send_IPI_self(vector);
297 }
298
hv_apic_init(void)299 void __init hv_apic_init(void)
300 {
301 if (cc_platform_has(CC_ATTR_SNP_SECURE_AVIC))
302 return;
303
304 if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
305 pr_info("Hyper-V: Using IPI hypercalls\n");
306 /*
307 * Set the IPI entry points.
308 */
309 orig_apic = *apic;
310
311 apic_update_callback(send_IPI, hv_send_ipi);
312 apic_update_callback(send_IPI_mask, hv_send_ipi_mask);
313 apic_update_callback(send_IPI_mask_allbutself, hv_send_ipi_mask_allbutself);
314 apic_update_callback(send_IPI_allbutself, hv_send_ipi_allbutself);
315 apic_update_callback(send_IPI_all, hv_send_ipi_all);
316 apic_update_callback(send_IPI_self, hv_send_ipi_self);
317 }
318
319 if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
320 pr_info("Hyper-V: Using enlightened APIC (%s mode)",
321 x2apic_enabled() ? "x2apic" : "xapic");
322 /*
323 * When in x2apic mode, don't use the Hyper-V specific APIC
324 * accessors since the field layout in the ICR register is
325 * different in x2apic mode. Furthermore, the architectural
326 * x2apic MSRs function just as well as the Hyper-V
327 * synthetic APIC MSRs, so there's no benefit in having
328 * separate Hyper-V accessors for x2apic mode. The only
329 * exception is hv_apic_eoi_write, because it benefits from
330 * lazy EOI when available, but the same accessor works for
331 * both xapic and x2apic because the field layout is the same.
332 */
333 apic_update_callback(eoi, hv_apic_eoi_write);
334 if (!x2apic_enabled()) {
335 apic_update_callback(read, hv_apic_read);
336 apic_update_callback(write, hv_apic_write);
337 apic_update_callback(icr_write, hv_apic_icr_write);
338 apic_update_callback(icr_read, hv_apic_icr_read);
339 }
340 }
341 }
342