1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_CAPS_H 3 #define __KVM_X86_VMX_CAPS_H 4 5 #include <asm/vmx.h> 6 7 #include "../lapic.h" 8 #include "../x86.h" 9 #include "../pmu.h" 10 #include "../cpuid.h" 11 12 extern bool __read_mostly enable_vpid; 13 extern bool __read_mostly flexpriority_enabled; 14 extern bool __read_mostly enable_ept; 15 extern bool __read_mostly enable_unrestricted_guest; 16 extern bool __read_mostly enable_ept_ad_bits; 17 extern bool __read_mostly enable_pml; 18 extern bool __read_mostly enable_ipiv; 19 extern int __read_mostly pt_mode; 20 21 #define PT_MODE_SYSTEM 0 22 #define PT_MODE_HOST_GUEST 1 23 24 #define PMU_CAP_FW_WRITES (1ULL << 13) 25 #define PMU_CAP_LBR_FMT 0x3f 26 27 struct nested_vmx_msrs { 28 /* 29 * We only store the "true" versions of the VMX capability MSRs. We 30 * generate the "non-true" versions by setting the must-be-1 bits 31 * according to the SDM. 32 */ 33 u32 procbased_ctls_low; 34 u32 procbased_ctls_high; 35 u32 secondary_ctls_low; 36 u32 secondary_ctls_high; 37 u32 pinbased_ctls_low; 38 u32 pinbased_ctls_high; 39 u32 exit_ctls_low; 40 u32 exit_ctls_high; 41 u32 entry_ctls_low; 42 u32 entry_ctls_high; 43 u32 misc_low; 44 u32 misc_high; 45 u32 ept_caps; 46 u32 vpid_caps; 47 u64 basic; 48 u64 cr0_fixed0; 49 u64 cr0_fixed1; 50 u64 cr4_fixed0; 51 u64 cr4_fixed1; 52 u64 vmcs_enum; 53 u64 vmfunc_controls; 54 }; 55 56 struct vmcs_config { 57 u64 basic; 58 u32 pin_based_exec_ctrl; 59 u32 cpu_based_exec_ctrl; 60 u32 cpu_based_2nd_exec_ctrl; 61 u64 cpu_based_3rd_exec_ctrl; 62 u32 vmexit_ctrl; 63 u32 vmentry_ctrl; 64 u64 misc; 65 struct nested_vmx_msrs nested; 66 }; 67 extern struct vmcs_config vmcs_config __ro_after_init; 68 69 struct vmx_capability { 70 u32 ept; 71 u32 vpid; 72 }; 73 extern struct vmx_capability vmx_capability __ro_after_init; 74 cpu_has_vmx_basic_inout(void)75static inline bool cpu_has_vmx_basic_inout(void) 76 { 77 return vmcs_config.basic & VMX_BASIC_INOUT; 78 } 79 cpu_has_virtual_nmis(void)80static inline bool cpu_has_virtual_nmis(void) 81 { 82 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS && 83 vmcs_config.cpu_based_exec_ctrl & CPU_BASED_NMI_WINDOW_EXITING; 84 } 85 cpu_has_vmx_preemption_timer(void)86static inline bool cpu_has_vmx_preemption_timer(void) 87 { 88 return vmcs_config.pin_based_exec_ctrl & 89 PIN_BASED_VMX_PREEMPTION_TIMER; 90 } 91 cpu_has_vmx_posted_intr(void)92static inline bool cpu_has_vmx_posted_intr(void) 93 { 94 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; 95 } 96 cpu_has_load_ia32_efer(void)97static inline bool cpu_has_load_ia32_efer(void) 98 { 99 return vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_EFER; 100 } 101 cpu_has_load_perf_global_ctrl(void)102static inline bool cpu_has_load_perf_global_ctrl(void) 103 { 104 return vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 105 } 106 cpu_has_vmx_mpx(void)107static inline bool cpu_has_vmx_mpx(void) 108 { 109 return vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS; 110 } 111 cpu_has_vmx_tpr_shadow(void)112static inline bool cpu_has_vmx_tpr_shadow(void) 113 { 114 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; 115 } 116 cpu_need_tpr_shadow(struct kvm_vcpu * vcpu)117static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) 118 { 119 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); 120 } 121 cpu_has_vmx_msr_bitmap(void)122static inline bool cpu_has_vmx_msr_bitmap(void) 123 { 124 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; 125 } 126 cpu_has_secondary_exec_ctrls(void)127static inline bool cpu_has_secondary_exec_ctrls(void) 128 { 129 return vmcs_config.cpu_based_exec_ctrl & 130 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 131 } 132 cpu_has_tertiary_exec_ctrls(void)133static inline bool cpu_has_tertiary_exec_ctrls(void) 134 { 135 return vmcs_config.cpu_based_exec_ctrl & 136 CPU_BASED_ACTIVATE_TERTIARY_CONTROLS; 137 } 138 cpu_has_vmx_virtualize_apic_accesses(void)139static inline bool cpu_has_vmx_virtualize_apic_accesses(void) 140 { 141 return vmcs_config.cpu_based_2nd_exec_ctrl & 142 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 143 } 144 cpu_has_vmx_ept(void)145static inline bool cpu_has_vmx_ept(void) 146 { 147 return vmcs_config.cpu_based_2nd_exec_ctrl & 148 SECONDARY_EXEC_ENABLE_EPT; 149 } 150 vmx_umip_emulated(void)151static inline bool vmx_umip_emulated(void) 152 { 153 return !boot_cpu_has(X86_FEATURE_UMIP) && 154 (vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_DESC); 155 } 156 cpu_has_vmx_rdtscp(void)157static inline bool cpu_has_vmx_rdtscp(void) 158 { 159 return vmcs_config.cpu_based_2nd_exec_ctrl & 160 SECONDARY_EXEC_ENABLE_RDTSCP; 161 } 162 cpu_has_vmx_virtualize_x2apic_mode(void)163static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) 164 { 165 return vmcs_config.cpu_based_2nd_exec_ctrl & 166 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 167 } 168 cpu_has_vmx_vpid(void)169static inline bool cpu_has_vmx_vpid(void) 170 { 171 return vmcs_config.cpu_based_2nd_exec_ctrl & 172 SECONDARY_EXEC_ENABLE_VPID; 173 } 174 cpu_has_vmx_wbinvd_exit(void)175static inline bool cpu_has_vmx_wbinvd_exit(void) 176 { 177 return vmcs_config.cpu_based_2nd_exec_ctrl & 178 SECONDARY_EXEC_WBINVD_EXITING; 179 } 180 cpu_has_vmx_unrestricted_guest(void)181static inline bool cpu_has_vmx_unrestricted_guest(void) 182 { 183 return vmcs_config.cpu_based_2nd_exec_ctrl & 184 SECONDARY_EXEC_UNRESTRICTED_GUEST; 185 } 186 cpu_has_vmx_apic_register_virt(void)187static inline bool cpu_has_vmx_apic_register_virt(void) 188 { 189 return vmcs_config.cpu_based_2nd_exec_ctrl & 190 SECONDARY_EXEC_APIC_REGISTER_VIRT; 191 } 192 cpu_has_vmx_virtual_intr_delivery(void)193static inline bool cpu_has_vmx_virtual_intr_delivery(void) 194 { 195 return vmcs_config.cpu_based_2nd_exec_ctrl & 196 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; 197 } 198 cpu_has_vmx_ple(void)199static inline bool cpu_has_vmx_ple(void) 200 { 201 return vmcs_config.cpu_based_2nd_exec_ctrl & 202 SECONDARY_EXEC_PAUSE_LOOP_EXITING; 203 } 204 cpu_has_vmx_rdrand(void)205static inline bool cpu_has_vmx_rdrand(void) 206 { 207 return vmcs_config.cpu_based_2nd_exec_ctrl & 208 SECONDARY_EXEC_RDRAND_EXITING; 209 } 210 cpu_has_vmx_invpcid(void)211static inline bool cpu_has_vmx_invpcid(void) 212 { 213 return vmcs_config.cpu_based_2nd_exec_ctrl & 214 SECONDARY_EXEC_ENABLE_INVPCID; 215 } 216 cpu_has_vmx_vmfunc(void)217static inline bool cpu_has_vmx_vmfunc(void) 218 { 219 return vmcs_config.cpu_based_2nd_exec_ctrl & 220 SECONDARY_EXEC_ENABLE_VMFUNC; 221 } 222 cpu_has_vmx_shadow_vmcs(void)223static inline bool cpu_has_vmx_shadow_vmcs(void) 224 { 225 /* check if the cpu supports writing r/o exit information fields */ 226 if (!(vmcs_config.misc & VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) 227 return false; 228 229 return vmcs_config.cpu_based_2nd_exec_ctrl & 230 SECONDARY_EXEC_SHADOW_VMCS; 231 } 232 cpu_has_vmx_encls_vmexit(void)233static inline bool cpu_has_vmx_encls_vmexit(void) 234 { 235 return vmcs_config.cpu_based_2nd_exec_ctrl & 236 SECONDARY_EXEC_ENCLS_EXITING; 237 } 238 cpu_has_vmx_rdseed(void)239static inline bool cpu_has_vmx_rdseed(void) 240 { 241 return vmcs_config.cpu_based_2nd_exec_ctrl & 242 SECONDARY_EXEC_RDSEED_EXITING; 243 } 244 cpu_has_vmx_pml(void)245static inline bool cpu_has_vmx_pml(void) 246 { 247 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; 248 } 249 cpu_has_vmx_xsaves(void)250static inline bool cpu_has_vmx_xsaves(void) 251 { 252 return vmcs_config.cpu_based_2nd_exec_ctrl & 253 SECONDARY_EXEC_ENABLE_XSAVES; 254 } 255 cpu_has_vmx_waitpkg(void)256static inline bool cpu_has_vmx_waitpkg(void) 257 { 258 return vmcs_config.cpu_based_2nd_exec_ctrl & 259 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 260 } 261 cpu_has_vmx_tsc_scaling(void)262static inline bool cpu_has_vmx_tsc_scaling(void) 263 { 264 return vmcs_config.cpu_based_2nd_exec_ctrl & 265 SECONDARY_EXEC_TSC_SCALING; 266 } 267 cpu_has_vmx_bus_lock_detection(void)268static inline bool cpu_has_vmx_bus_lock_detection(void) 269 { 270 return vmcs_config.cpu_based_2nd_exec_ctrl & 271 SECONDARY_EXEC_BUS_LOCK_DETECTION; 272 } 273 cpu_has_vmx_apicv(void)274static inline bool cpu_has_vmx_apicv(void) 275 { 276 return cpu_has_vmx_apic_register_virt() && 277 cpu_has_vmx_virtual_intr_delivery() && 278 cpu_has_vmx_posted_intr(); 279 } 280 cpu_has_vmx_ipiv(void)281static inline bool cpu_has_vmx_ipiv(void) 282 { 283 return vmcs_config.cpu_based_3rd_exec_ctrl & TERTIARY_EXEC_IPI_VIRT; 284 } 285 cpu_has_vmx_flexpriority(void)286static inline bool cpu_has_vmx_flexpriority(void) 287 { 288 return cpu_has_vmx_tpr_shadow() && 289 cpu_has_vmx_virtualize_apic_accesses(); 290 } 291 cpu_has_vmx_ept_execute_only(void)292static inline bool cpu_has_vmx_ept_execute_only(void) 293 { 294 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; 295 } 296 cpu_has_vmx_ept_4levels(void)297static inline bool cpu_has_vmx_ept_4levels(void) 298 { 299 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; 300 } 301 cpu_has_vmx_ept_5levels(void)302static inline bool cpu_has_vmx_ept_5levels(void) 303 { 304 return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT; 305 } 306 cpu_has_vmx_ept_mt_wb(void)307static inline bool cpu_has_vmx_ept_mt_wb(void) 308 { 309 return vmx_capability.ept & VMX_EPTP_WB_BIT; 310 } 311 cpu_has_vmx_ept_2m_page(void)312static inline bool cpu_has_vmx_ept_2m_page(void) 313 { 314 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; 315 } 316 cpu_has_vmx_ept_1g_page(void)317static inline bool cpu_has_vmx_ept_1g_page(void) 318 { 319 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; 320 } 321 ept_caps_to_lpage_level(u32 ept_caps)322static inline int ept_caps_to_lpage_level(u32 ept_caps) 323 { 324 if (ept_caps & VMX_EPT_1GB_PAGE_BIT) 325 return PG_LEVEL_1G; 326 if (ept_caps & VMX_EPT_2MB_PAGE_BIT) 327 return PG_LEVEL_2M; 328 return PG_LEVEL_4K; 329 } 330 cpu_has_vmx_ept_ad_bits(void)331static inline bool cpu_has_vmx_ept_ad_bits(void) 332 { 333 return vmx_capability.ept & VMX_EPT_AD_BIT; 334 } 335 cpu_has_vmx_invept_context(void)336static inline bool cpu_has_vmx_invept_context(void) 337 { 338 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; 339 } 340 cpu_has_vmx_invept_global(void)341static inline bool cpu_has_vmx_invept_global(void) 342 { 343 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; 344 } 345 cpu_has_vmx_invvpid(void)346static inline bool cpu_has_vmx_invvpid(void) 347 { 348 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT; 349 } 350 cpu_has_vmx_invvpid_individual_addr(void)351static inline bool cpu_has_vmx_invvpid_individual_addr(void) 352 { 353 return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT; 354 } 355 cpu_has_vmx_invvpid_single(void)356static inline bool cpu_has_vmx_invvpid_single(void) 357 { 358 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; 359 } 360 cpu_has_vmx_invvpid_global(void)361static inline bool cpu_has_vmx_invvpid_global(void) 362 { 363 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; 364 } 365 cpu_has_vmx_intel_pt(void)366static inline bool cpu_has_vmx_intel_pt(void) 367 { 368 return (vmcs_config.misc & VMX_MISC_INTEL_PT) && 369 (vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_PT_USE_GPA) && 370 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_RTIT_CTL); 371 } 372 373 /* 374 * Processor Trace can operate in one of three modes: 375 * a. system-wide: trace both host/guest and output to host buffer 376 * b. host-only: only trace host and output to host buffer 377 * c. host-guest: trace host and guest simultaneously and output to their 378 * respective buffer 379 * 380 * KVM currently only supports (a) and (c). 381 */ vmx_pt_mode_is_system(void)382static inline bool vmx_pt_mode_is_system(void) 383 { 384 return pt_mode == PT_MODE_SYSTEM; 385 } vmx_pt_mode_is_host_guest(void)386static inline bool vmx_pt_mode_is_host_guest(void) 387 { 388 return pt_mode == PT_MODE_HOST_GUEST; 389 } 390 vmx_pebs_supported(void)391static inline bool vmx_pebs_supported(void) 392 { 393 return boot_cpu_has(X86_FEATURE_PEBS) && kvm_pmu_cap.pebs_ept; 394 } 395 cpu_has_notify_vmexit(void)396static inline bool cpu_has_notify_vmexit(void) 397 { 398 return vmcs_config.cpu_based_2nd_exec_ctrl & 399 SECONDARY_EXEC_NOTIFY_VM_EXITING; 400 } 401 402 #endif /* __KVM_X86_VMX_CAPS_H */ 403