1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/arm_pmuv3.h> 81 #include <asm/cpu.h> 82 #include <asm/cpufeature.h> 83 #include <asm/cpu_ops.h> 84 #include <asm/fpsimd.h> 85 #include <asm/hwcap.h> 86 #include <asm/insn.h> 87 #include <asm/kvm_host.h> 88 #include <asm/mmu.h> 89 #include <asm/mmu_context.h> 90 #include <asm/mpam.h> 91 #include <asm/mte.h> 92 #include <asm/hypervisor.h> 93 #include <asm/processor.h> 94 #include <asm/smp.h> 95 #include <asm/sysreg.h> 96 #include <asm/traps.h> 97 #include <asm/vectors.h> 98 #include <asm/virt.h> 99 100 #include <asm/spectre.h> 101 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 102 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 103 104 #ifdef CONFIG_COMPAT 105 #define COMPAT_ELF_HWCAP_DEFAULT \ 106 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 107 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 108 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 109 COMPAT_HWCAP_LPAE) 110 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 111 unsigned int compat_elf_hwcap2 __read_mostly; 112 unsigned int compat_elf_hwcap3 __read_mostly; 113 #endif 114 115 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 116 EXPORT_SYMBOL(system_cpucaps); 117 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 118 119 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 120 121 /* 122 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 123 * ends up in the .bss section where it is initialized in early_map_kernel() 124 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 125 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 126 * may end up generating an incorrect idmap page table attributes. 127 */ 128 bool arm64_use_ng_mappings __read_mostly = false; 129 EXPORT_SYMBOL(arm64_use_ng_mappings); 130 131 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 132 133 /* 134 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 135 * support it? 136 */ 137 static bool __read_mostly allow_mismatched_32bit_el0; 138 139 /* 140 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 141 * seen at least one CPU capable of 32-bit EL0. 142 */ 143 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 144 145 /* 146 * Mask of CPUs supporting 32-bit EL0. 147 * Only valid if arm64_mismatched_32bit_el0 is enabled. 148 */ 149 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 150 151 void dump_cpu_features(void) 152 { 153 /* file-wide pr_fmt adds "CPU features: " prefix */ 154 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 155 } 156 157 #define __ARM64_MAX_POSITIVE(reg, field) \ 158 ((reg##_##field##_SIGNED ? \ 159 BIT(reg##_##field##_WIDTH - 1) : \ 160 BIT(reg##_##field##_WIDTH)) - 1) 161 162 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 163 164 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 165 .sys_reg = SYS_##reg, \ 166 .field_pos = reg##_##field##_SHIFT, \ 167 .field_width = reg##_##field##_WIDTH, \ 168 .sign = reg##_##field##_SIGNED, \ 169 .min_field_value = min_value, \ 170 .max_field_value = max_value, 171 172 /* 173 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 174 * an implicit maximum that depends on the sign-ess of the field. 175 * 176 * An unsigned field will be capped at all ones, while a signed field 177 * will be limited to the positive half only. 178 */ 179 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 180 __ARM64_CPUID_FIELDS(reg, field, \ 181 SYS_FIELD_VALUE(reg, field, min_value), \ 182 __ARM64_MAX_POSITIVE(reg, field)) 183 184 /* 185 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 186 * implicit minimal value to max_value. This should be used when 187 * matching a non-implemented property. 188 */ 189 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 190 __ARM64_CPUID_FIELDS(reg, field, \ 191 __ARM64_MIN_NEGATIVE(reg, field), \ 192 SYS_FIELD_VALUE(reg, field, max_value)) 193 194 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 195 { \ 196 .sign = SIGNED, \ 197 .visible = VISIBLE, \ 198 .strict = STRICT, \ 199 .type = TYPE, \ 200 .shift = SHIFT, \ 201 .width = WIDTH, \ 202 .safe_val = SAFE_VAL, \ 203 } 204 205 /* Define a feature with unsigned values */ 206 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 207 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 208 209 /* Define a feature with a signed value */ 210 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 211 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 212 213 #define ARM64_FTR_END \ 214 { \ 215 .width = 0, \ 216 } 217 218 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 219 220 static bool __system_matches_cap(unsigned int n); 221 222 /* 223 * NOTE: Any changes to the visibility of features should be kept in 224 * sync with the documentation of the CPU feature register ABI. 225 */ 226 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 241 ARM64_FTR_END, 242 }; 243 244 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LS64_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 254 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 256 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 261 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 263 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 265 ARM64_FTR_END, 266 }; 267 268 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 276 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 278 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 281 ARM64_FTR_END, 282 }; 283 284 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 285 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSUI_SHIFT, 4, ID_AA64ISAR3_EL1_LSUI_NI), 287 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0), 288 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 289 ARM64_FTR_END, 290 }; 291 292 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 300 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 303 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 304 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 309 ARM64_FTR_END, 310 }; 311 312 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_DF2_SHIFT, 4, 0), 314 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 315 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 316 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 317 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 318 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 322 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 323 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 324 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 325 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 326 ARM64_FTR_END, 327 }; 328 329 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 330 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_GCIE_SHIFT, 4, ID_AA64PFR2_EL1_GCIE_NI), 332 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 333 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), 334 ARM64_FTR_END, 335 }; 336 337 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 338 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 339 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 341 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 342 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 343 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 345 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 346 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 347 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 349 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 350 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 351 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 353 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 354 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 355 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 356 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 357 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 358 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 359 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 360 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 361 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 362 ARM64_FTR_END, 363 }; 364 365 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 366 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 367 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 368 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 369 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 371 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 373 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 375 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 376 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 377 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 378 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 379 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 380 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 381 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 382 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 383 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 384 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 385 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 386 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 387 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 388 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 389 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 390 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 391 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 392 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 393 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 394 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 395 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 396 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 397 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 398 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 399 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 400 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 401 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 402 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 403 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 404 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 405 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 406 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 407 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 408 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 409 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 410 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 411 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 412 ARM64_FTR_END, 413 }; 414 415 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 416 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 417 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 418 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 419 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 420 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 421 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 422 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 423 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 424 ARM64_FTR_END, 425 }; 426 427 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 428 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 431 /* 432 * Page size not being supported at Stage-2 is not fatal. You 433 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 434 * your favourite nesting hypervisor. 435 * 436 * There is a small corner case where the hypervisor explicitly 437 * advertises a given granule size at Stage-2 (value 2) on some 438 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 439 * vCPUs. Although this is not forbidden by the architecture, it 440 * indicates that the hypervisor is being silly (or buggy). 441 * 442 * We make no effort to cope with this and pretend that if these 443 * fields are inconsistent across vCPUs, then it isn't worth 444 * trying to bring KVM up. 445 */ 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 449 /* 450 * We already refuse to boot CPUs that don't support our configured 451 * page size, so we can only detect mismatches for a page size other 452 * than the one we're currently using. Unfortunately, SoCs like this 453 * exist in the wild so, even though we don't like it, we'll have to go 454 * along with it and treat them as non-strict. 455 */ 456 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 457 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 459 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 461 /* Linux shouldn't care about secure memory */ 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 465 /* 466 * Differing PARange is fine as long as all peripherals and memory are mapped 467 * within the minimum PARange of all CPUs 468 */ 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 470 ARM64_FTR_END, 471 }; 472 473 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 488 ARM64_FTR_END, 489 }; 490 491 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 507 ARM64_FTR_END, 508 }; 509 510 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 511 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 512 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_SCTLRX_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 516 ARM64_FTR_END, 517 }; 518 519 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 520 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 522 ARM64_FTR_END, 523 }; 524 525 static const struct arm64_ftr_bits ftr_ctr[] = { 526 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 527 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 528 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 529 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 530 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 531 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 532 /* 533 * Linux can handle differing I-cache policies. Userspace JITs will 534 * make use of *minLine. 535 * If we have differing I-cache policies, report it as the weakest - VIPT. 536 */ 537 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 538 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 539 ARM64_FTR_END, 540 }; 541 542 static struct arm64_ftr_override __ro_after_init no_override = { }; 543 544 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 545 .name = "SYS_CTR_EL0", 546 .ftr_bits = ftr_ctr, 547 .override = &no_override, 548 }; 549 550 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 551 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 556 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 559 ARM64_FTR_END, 560 }; 561 562 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 563 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 564 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 565 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 566 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 568 /* 569 * We can instantiate multiple PMU instances with different levels 570 * of support. 571 */ 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 574 ARM64_FTR_END, 575 }; 576 577 static const struct arm64_ftr_bits ftr_mvfr0[] = { 578 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 581 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 586 ARM64_FTR_END, 587 }; 588 589 static const struct arm64_ftr_bits ftr_mvfr1[] = { 590 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 591 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 592 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 593 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 594 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 596 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 597 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 598 ARM64_FTR_END, 599 }; 600 601 static const struct arm64_ftr_bits ftr_mvfr2[] = { 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 604 ARM64_FTR_END, 605 }; 606 607 static const struct arm64_ftr_bits ftr_dczid[] = { 608 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 609 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 610 ARM64_FTR_END, 611 }; 612 613 static const struct arm64_ftr_bits ftr_gmid[] = { 614 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 615 ARM64_FTR_END, 616 }; 617 618 static const struct arm64_ftr_bits ftr_id_isar0[] = { 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 621 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 626 ARM64_FTR_END, 627 }; 628 629 static const struct arm64_ftr_bits ftr_id_isar5[] = { 630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 631 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 632 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 633 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 634 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 635 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 636 ARM64_FTR_END, 637 }; 638 639 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 640 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 641 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 642 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 643 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 644 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 645 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 646 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 647 648 /* 649 * SpecSEI = 1 indicates that the PE might generate an SError on an 650 * external abort on speculative read. It is safe to assume that an 651 * SError might be generated than it will not be. Hence it has been 652 * classified as FTR_HIGHER_SAFE. 653 */ 654 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 655 ARM64_FTR_END, 656 }; 657 658 static const struct arm64_ftr_bits ftr_id_isar4[] = { 659 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 660 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 661 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 662 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 663 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 664 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 665 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 666 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 667 ARM64_FTR_END, 668 }; 669 670 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 671 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 672 ARM64_FTR_END, 673 }; 674 675 static const struct arm64_ftr_bits ftr_id_isar6[] = { 676 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 677 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 679 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 680 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 683 ARM64_FTR_END, 684 }; 685 686 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 687 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 688 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 689 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 690 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 691 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 693 ARM64_FTR_END, 694 }; 695 696 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 697 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 698 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 699 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 700 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 701 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 702 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 703 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 704 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 705 ARM64_FTR_END, 706 }; 707 708 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 709 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 710 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 711 ARM64_FTR_END, 712 }; 713 714 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 715 /* [31:28] TraceFilt */ 716 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 717 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 718 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 719 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 720 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 721 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 722 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 723 ARM64_FTR_END, 724 }; 725 726 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 727 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 728 ARM64_FTR_END, 729 }; 730 731 static const struct arm64_ftr_bits ftr_mpamidr[] = { 732 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 733 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 734 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 735 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 736 ARM64_FTR_END, 737 }; 738 739 /* 740 * Common ftr bits for a 32bit register with all hidden, strict 741 * attributes, with 4bit feature fields and a default safe value of 742 * 0. Covers the following 32bit registers: 743 * id_isar[1-3], id_mmfr[1-3] 744 */ 745 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 746 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 747 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 748 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 749 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 750 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 751 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 752 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 753 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 754 ARM64_FTR_END, 755 }; 756 757 /* Table for a single 32bit feature value */ 758 static const struct arm64_ftr_bits ftr_single32[] = { 759 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 760 ARM64_FTR_END, 761 }; 762 763 static const struct arm64_ftr_bits ftr_raz[] = { 764 ARM64_FTR_END, 765 }; 766 767 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 768 .sys_id = id, \ 769 .reg = &(struct arm64_ftr_reg){ \ 770 .name = id_str, \ 771 .override = (ovr), \ 772 .ftr_bits = &((table)[0]), \ 773 }} 774 775 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 776 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 777 778 #define ARM64_FTR_REG(id, table) \ 779 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 780 781 struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 782 struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 783 struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 784 struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 785 struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 786 struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 787 struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 788 struct arm64_ftr_override __read_mostly id_aa64isar1_override; 789 struct arm64_ftr_override __read_mostly id_aa64isar2_override; 790 791 struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 792 793 static const struct __ftr_reg_entry { 794 u32 sys_id; 795 struct arm64_ftr_reg *reg; 796 } arm64_ftr_regs[] = { 797 798 /* Op1 = 0, CRn = 0, CRm = 1 */ 799 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 800 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 801 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 802 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 803 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 804 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 805 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 806 807 /* Op1 = 0, CRn = 0, CRm = 2 */ 808 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 809 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 810 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 811 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 812 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 813 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 814 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 815 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 816 817 /* Op1 = 0, CRn = 0, CRm = 3 */ 818 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 819 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 820 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 821 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 822 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 823 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 824 825 /* Op1 = 0, CRn = 0, CRm = 4 */ 826 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 827 &id_aa64pfr0_override), 828 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 829 &id_aa64pfr1_override), 830 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 831 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 832 &id_aa64zfr0_override), 833 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 834 &id_aa64smfr0_override), 835 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 836 837 /* Op1 = 0, CRn = 0, CRm = 5 */ 838 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 839 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 840 841 /* Op1 = 0, CRn = 0, CRm = 6 */ 842 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 843 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 844 &id_aa64isar1_override), 845 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 846 &id_aa64isar2_override), 847 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 848 849 /* Op1 = 0, CRn = 0, CRm = 7 */ 850 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 851 &id_aa64mmfr0_override), 852 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 853 &id_aa64mmfr1_override), 854 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 855 &id_aa64mmfr2_override), 856 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 857 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 858 859 /* Op1 = 0, CRn = 10, CRm = 4 */ 860 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 861 862 /* Op1 = 1, CRn = 0, CRm = 0 */ 863 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 864 865 /* Op1 = 3, CRn = 0, CRm = 0 */ 866 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 867 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 868 869 /* Op1 = 3, CRn = 14, CRm = 0 */ 870 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 871 }; 872 873 static int search_cmp_ftr_reg(const void *id, const void *regp) 874 { 875 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 876 } 877 878 /* 879 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 880 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 881 * ascending order of sys_id, we use binary search to find a matching 882 * entry. 883 * 884 * returns - Upon success, matching ftr_reg entry for id. 885 * - NULL on failure. It is upto the caller to decide 886 * the impact of a failure. 887 */ 888 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 889 { 890 const struct __ftr_reg_entry *ret; 891 892 ret = bsearch((const void *)(unsigned long)sys_id, 893 arm64_ftr_regs, 894 ARRAY_SIZE(arm64_ftr_regs), 895 sizeof(arm64_ftr_regs[0]), 896 search_cmp_ftr_reg); 897 if (ret) 898 return ret->reg; 899 return NULL; 900 } 901 902 /* 903 * get_arm64_ftr_reg - Looks up a feature register entry using 904 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 905 * 906 * returns - Upon success, matching ftr_reg entry for id. 907 * - NULL on failure but with an WARN_ON(). 908 */ 909 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 910 { 911 struct arm64_ftr_reg *reg; 912 913 reg = get_arm64_ftr_reg_nowarn(sys_id); 914 915 /* 916 * Requesting a non-existent register search is an error. Warn 917 * and let the caller handle it. 918 */ 919 WARN_ON(!reg); 920 return reg; 921 } 922 923 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 924 s64 ftr_val) 925 { 926 u64 mask = arm64_ftr_mask(ftrp); 927 928 reg &= ~mask; 929 reg |= (ftr_val << ftrp->shift) & mask; 930 return reg; 931 } 932 933 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 934 s64 cur) 935 { 936 s64 ret = 0; 937 938 switch (ftrp->type) { 939 case FTR_EXACT: 940 ret = ftrp->safe_val; 941 break; 942 case FTR_LOWER_SAFE: 943 ret = min(new, cur); 944 break; 945 case FTR_HIGHER_OR_ZERO_SAFE: 946 if (!cur || !new) 947 break; 948 fallthrough; 949 case FTR_HIGHER_SAFE: 950 ret = max(new, cur); 951 break; 952 default: 953 BUG(); 954 } 955 956 return ret; 957 } 958 959 static void __init sort_ftr_regs(void) 960 { 961 unsigned int i; 962 963 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 964 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 965 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 966 unsigned int j = 0; 967 968 /* 969 * Features here must be sorted in descending order with respect 970 * to their shift values and should not overlap with each other. 971 */ 972 for (; ftr_bits->width != 0; ftr_bits++, j++) { 973 unsigned int width = ftr_reg->ftr_bits[j].width; 974 unsigned int shift = ftr_reg->ftr_bits[j].shift; 975 unsigned int prev_shift; 976 977 WARN((shift + width) > 64, 978 "%s has invalid feature at shift %d\n", 979 ftr_reg->name, shift); 980 981 /* 982 * Skip the first feature. There is nothing to 983 * compare against for now. 984 */ 985 if (j == 0) 986 continue; 987 988 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 989 WARN((shift + width) > prev_shift, 990 "%s has feature overlap at shift %d\n", 991 ftr_reg->name, shift); 992 } 993 994 /* 995 * Skip the first register. There is nothing to 996 * compare against for now. 997 */ 998 if (i == 0) 999 continue; 1000 /* 1001 * Registers here must be sorted in ascending order with respect 1002 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 1003 * to work correctly. 1004 */ 1005 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 1006 } 1007 } 1008 1009 /* 1010 * Initialise the CPU feature register from Boot CPU values. 1011 * Also initialises the strict_mask for the register. 1012 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1013 * RES0 for the system-wide value, and must strictly match. 1014 */ 1015 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1016 { 1017 u64 val = 0; 1018 u64 strict_mask = ~0x0ULL; 1019 u64 user_mask = 0; 1020 u64 valid_mask = 0; 1021 1022 const struct arm64_ftr_bits *ftrp; 1023 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1024 1025 if (!reg) 1026 return; 1027 1028 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1029 u64 ftr_mask = arm64_ftr_mask(ftrp); 1030 s64 ftr_new = arm64_ftr_value(ftrp, new); 1031 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1032 1033 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1034 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1035 char *str = NULL; 1036 1037 if (ftr_ovr != tmp) { 1038 /* Unsafe, remove the override */ 1039 reg->override->mask &= ~ftr_mask; 1040 reg->override->val &= ~ftr_mask; 1041 tmp = ftr_ovr; 1042 str = "ignoring override"; 1043 } else if (ftr_new != tmp) { 1044 /* Override was valid */ 1045 ftr_new = tmp; 1046 str = "forced"; 1047 } else { 1048 /* Override was the safe value */ 1049 str = "already set"; 1050 } 1051 1052 pr_warn("%s[%d:%d]: %s to %llx\n", 1053 reg->name, 1054 ftrp->shift + ftrp->width - 1, 1055 ftrp->shift, str, 1056 tmp & (BIT(ftrp->width) - 1)); 1057 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1058 reg->override->val &= ~ftr_mask; 1059 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1060 reg->name, 1061 ftrp->shift + ftrp->width - 1, 1062 ftrp->shift); 1063 } 1064 1065 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1066 1067 valid_mask |= ftr_mask; 1068 if (!ftrp->strict) 1069 strict_mask &= ~ftr_mask; 1070 if (ftrp->visible) 1071 user_mask |= ftr_mask; 1072 else 1073 reg->user_val = arm64_ftr_set_value(ftrp, 1074 reg->user_val, 1075 ftrp->safe_val); 1076 } 1077 1078 val &= valid_mask; 1079 1080 reg->sys_val = val; 1081 reg->strict_mask = strict_mask; 1082 reg->user_mask = user_mask; 1083 } 1084 1085 extern const struct arm64_cpu_capabilities arm64_errata[]; 1086 static const struct arm64_cpu_capabilities arm64_features[]; 1087 1088 static void __init 1089 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1090 { 1091 for (; caps->matches; caps++) { 1092 if (WARN(caps->capability >= ARM64_NCAPS, 1093 "Invalid capability %d\n", caps->capability)) 1094 continue; 1095 if (WARN(cpucap_ptrs[caps->capability], 1096 "Duplicate entry for capability %d\n", 1097 caps->capability)) 1098 continue; 1099 cpucap_ptrs[caps->capability] = caps; 1100 } 1101 } 1102 1103 static void __init init_cpucap_indirect_list(void) 1104 { 1105 init_cpucap_indirect_list_from_array(arm64_features); 1106 init_cpucap_indirect_list_from_array(arm64_errata); 1107 } 1108 1109 static void __init setup_boot_cpu_capabilities(void); 1110 1111 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1112 { 1113 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1114 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1115 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1116 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1117 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1118 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1119 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1120 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1121 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1122 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1123 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1124 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1125 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1126 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1127 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1128 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1129 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1130 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1131 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1132 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1133 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1134 } 1135 1136 #ifdef CONFIG_ARM64_PSEUDO_NMI 1137 static bool enable_pseudo_nmi; 1138 1139 static int __init early_enable_pseudo_nmi(char *p) 1140 { 1141 return kstrtobool(p, &enable_pseudo_nmi); 1142 } 1143 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1144 1145 static __init void detect_system_supports_pseudo_nmi(void) 1146 { 1147 struct device_node *np; 1148 1149 if (!enable_pseudo_nmi) 1150 return; 1151 1152 /* 1153 * Detect broken MediaTek firmware that doesn't properly save and 1154 * restore GIC priorities. 1155 */ 1156 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1157 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1158 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1159 enable_pseudo_nmi = false; 1160 } 1161 of_node_put(np); 1162 } 1163 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1164 static inline void detect_system_supports_pseudo_nmi(void) { } 1165 #endif 1166 1167 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1168 { 1169 /* Before we start using the tables, make sure it is sorted */ 1170 sort_ftr_regs(); 1171 1172 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1173 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1174 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1175 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1176 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1177 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1178 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1179 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1180 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1181 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1182 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1183 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1184 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1185 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1186 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1187 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1188 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1189 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1190 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1191 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1192 1193 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1194 init_32bit_cpu_features(&info->aarch32); 1195 1196 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1197 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1198 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1199 1200 vec_init_vq_map(ARM64_VEC_SVE); 1201 1202 cpacr_restore(cpacr); 1203 } 1204 1205 if (IS_ENABLED(CONFIG_ARM64_SME) && 1206 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1207 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1208 1209 vec_init_vq_map(ARM64_VEC_SME); 1210 1211 cpacr_restore(cpacr); 1212 } 1213 1214 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1215 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1216 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1217 } 1218 1219 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1220 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1221 } 1222 1223 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1224 { 1225 const struct arm64_ftr_bits *ftrp; 1226 1227 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1228 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1229 s64 ftr_new = arm64_ftr_value(ftrp, new); 1230 1231 if (ftr_cur == ftr_new) 1232 continue; 1233 /* Find a safe value */ 1234 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1235 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1236 } 1237 1238 } 1239 1240 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1241 { 1242 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1243 1244 if (!regp) 1245 return 0; 1246 1247 update_cpu_ftr_reg(regp, val); 1248 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1249 return 0; 1250 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1251 regp->name, boot, cpu, val); 1252 return 1; 1253 } 1254 1255 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1256 { 1257 const struct arm64_ftr_bits *ftrp; 1258 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1259 1260 if (!regp) 1261 return; 1262 1263 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1264 if (ftrp->shift == field) { 1265 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1266 break; 1267 } 1268 } 1269 1270 /* Bogus field? */ 1271 WARN_ON(!ftrp->width); 1272 } 1273 1274 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1275 struct cpuinfo_arm64 *boot) 1276 { 1277 static bool boot_cpu_32bit_regs_overridden = false; 1278 1279 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1280 return; 1281 1282 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1283 return; 1284 1285 boot->aarch32 = info->aarch32; 1286 init_32bit_cpu_features(&boot->aarch32); 1287 boot_cpu_32bit_regs_overridden = true; 1288 } 1289 1290 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1291 struct cpuinfo_32bit *boot) 1292 { 1293 int taint = 0; 1294 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1295 1296 /* 1297 * If we don't have AArch32 at EL1, then relax the strictness of 1298 * EL1-dependent register fields to avoid spurious sanity check fails. 1299 */ 1300 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1301 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1302 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1303 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1304 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1305 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1306 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1307 } 1308 1309 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1310 info->reg_id_dfr0, boot->reg_id_dfr0); 1311 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1312 info->reg_id_dfr1, boot->reg_id_dfr1); 1313 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1314 info->reg_id_isar0, boot->reg_id_isar0); 1315 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1316 info->reg_id_isar1, boot->reg_id_isar1); 1317 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1318 info->reg_id_isar2, boot->reg_id_isar2); 1319 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1320 info->reg_id_isar3, boot->reg_id_isar3); 1321 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1322 info->reg_id_isar4, boot->reg_id_isar4); 1323 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1324 info->reg_id_isar5, boot->reg_id_isar5); 1325 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1326 info->reg_id_isar6, boot->reg_id_isar6); 1327 1328 /* 1329 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1330 * ACTLR formats could differ across CPUs and therefore would have to 1331 * be trapped for virtualization anyway. 1332 */ 1333 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1334 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1335 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1336 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1337 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1338 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1339 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1340 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1341 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1342 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1343 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1344 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1345 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1346 info->reg_id_pfr0, boot->reg_id_pfr0); 1347 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1348 info->reg_id_pfr1, boot->reg_id_pfr1); 1349 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1350 info->reg_id_pfr2, boot->reg_id_pfr2); 1351 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1352 info->reg_mvfr0, boot->reg_mvfr0); 1353 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1354 info->reg_mvfr1, boot->reg_mvfr1); 1355 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1356 info->reg_mvfr2, boot->reg_mvfr2); 1357 1358 return taint; 1359 } 1360 1361 /* 1362 * Update system wide CPU feature registers with the values from a 1363 * non-boot CPU. Also performs SANITY checks to make sure that there 1364 * aren't any insane variations from that of the boot CPU. 1365 */ 1366 void update_cpu_features(int cpu, 1367 struct cpuinfo_arm64 *info, 1368 struct cpuinfo_arm64 *boot) 1369 { 1370 int taint = 0; 1371 1372 /* 1373 * The kernel can handle differing I-cache policies, but otherwise 1374 * caches should look identical. Userspace JITs will make use of 1375 * *minLine. 1376 */ 1377 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1378 info->reg_ctr, boot->reg_ctr); 1379 1380 /* 1381 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1382 * could result in too much or too little memory being zeroed if a 1383 * process is preempted and migrated between CPUs. 1384 */ 1385 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1386 info->reg_dczid, boot->reg_dczid); 1387 1388 /* If different, timekeeping will be broken (especially with KVM) */ 1389 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1390 info->reg_cntfrq, boot->reg_cntfrq); 1391 1392 /* 1393 * The kernel uses self-hosted debug features and expects CPUs to 1394 * support identical debug features. We presently need CTX_CMPs, WRPs, 1395 * and BRPs to be identical. 1396 * ID_AA64DFR1 is currently RES0. 1397 */ 1398 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1399 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1400 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1401 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1402 /* 1403 * Even in big.LITTLE, processors should be identical instruction-set 1404 * wise. 1405 */ 1406 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1407 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1408 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1409 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1410 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1411 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1412 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1413 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1414 1415 /* 1416 * Differing PARange support is fine as long as all peripherals and 1417 * memory are mapped within the minimum PARange of all CPUs. 1418 * Linux should not care about secure memory. 1419 */ 1420 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1421 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1422 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1423 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1424 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1425 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1426 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1427 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1428 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 1429 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 1430 1431 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1432 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1433 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1434 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1435 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1436 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1437 1438 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1439 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1440 1441 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1442 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1443 1444 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1445 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1446 1447 /* Probe vector lengths */ 1448 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1449 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1450 if (!system_capabilities_finalized()) { 1451 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1452 1453 vec_update_vq_map(ARM64_VEC_SVE); 1454 1455 cpacr_restore(cpacr); 1456 } 1457 } 1458 1459 if (IS_ENABLED(CONFIG_ARM64_SME) && 1460 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1461 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1462 1463 /* Probe vector lengths */ 1464 if (!system_capabilities_finalized()) 1465 vec_update_vq_map(ARM64_VEC_SME); 1466 1467 cpacr_restore(cpacr); 1468 } 1469 1470 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1471 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1472 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1473 info->reg_mpamidr, boot->reg_mpamidr); 1474 } 1475 1476 /* 1477 * The kernel uses the LDGM/STGM instructions and the number of tags 1478 * they read/write depends on the GMID_EL1.BS field. Check that the 1479 * value is the same on all CPUs. 1480 */ 1481 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1482 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1483 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1484 info->reg_gmid, boot->reg_gmid); 1485 } 1486 1487 /* 1488 * If we don't have AArch32 at all then skip the checks entirely 1489 * as the register values may be UNKNOWN and we're not going to be 1490 * using them for anything. 1491 * 1492 * This relies on a sanitised view of the AArch64 ID registers 1493 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1494 */ 1495 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1496 lazy_init_32bit_cpu_features(info, boot); 1497 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1498 &boot->aarch32); 1499 } 1500 1501 /* 1502 * Mismatched CPU features are a recipe for disaster. Don't even 1503 * pretend to support them. 1504 */ 1505 if (taint) { 1506 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1507 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1508 } 1509 } 1510 1511 u64 read_sanitised_ftr_reg(u32 id) 1512 { 1513 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1514 1515 if (!regp) 1516 return 0; 1517 return regp->sys_val; 1518 } 1519 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1520 1521 #define read_sysreg_case(r) \ 1522 case r: val = read_sysreg_s(r); break; 1523 1524 /* 1525 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1526 * Read the system register on the current CPU 1527 */ 1528 u64 __read_sysreg_by_encoding(u32 sys_id) 1529 { 1530 struct arm64_ftr_reg *regp; 1531 u64 val; 1532 1533 switch (sys_id) { 1534 read_sysreg_case(SYS_ID_PFR0_EL1); 1535 read_sysreg_case(SYS_ID_PFR1_EL1); 1536 read_sysreg_case(SYS_ID_PFR2_EL1); 1537 read_sysreg_case(SYS_ID_DFR0_EL1); 1538 read_sysreg_case(SYS_ID_DFR1_EL1); 1539 read_sysreg_case(SYS_ID_MMFR0_EL1); 1540 read_sysreg_case(SYS_ID_MMFR1_EL1); 1541 read_sysreg_case(SYS_ID_MMFR2_EL1); 1542 read_sysreg_case(SYS_ID_MMFR3_EL1); 1543 read_sysreg_case(SYS_ID_MMFR4_EL1); 1544 read_sysreg_case(SYS_ID_MMFR5_EL1); 1545 read_sysreg_case(SYS_ID_ISAR0_EL1); 1546 read_sysreg_case(SYS_ID_ISAR1_EL1); 1547 read_sysreg_case(SYS_ID_ISAR2_EL1); 1548 read_sysreg_case(SYS_ID_ISAR3_EL1); 1549 read_sysreg_case(SYS_ID_ISAR4_EL1); 1550 read_sysreg_case(SYS_ID_ISAR5_EL1); 1551 read_sysreg_case(SYS_ID_ISAR6_EL1); 1552 read_sysreg_case(SYS_MVFR0_EL1); 1553 read_sysreg_case(SYS_MVFR1_EL1); 1554 read_sysreg_case(SYS_MVFR2_EL1); 1555 1556 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1557 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1558 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1559 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1560 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1561 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1562 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1563 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1564 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1565 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1566 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1567 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1568 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1569 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1570 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1571 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1572 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1573 1574 read_sysreg_case(SYS_CNTFRQ_EL0); 1575 read_sysreg_case(SYS_CTR_EL0); 1576 read_sysreg_case(SYS_DCZID_EL0); 1577 1578 default: 1579 BUG(); 1580 return 0; 1581 } 1582 1583 regp = get_arm64_ftr_reg(sys_id); 1584 if (regp) { 1585 val &= ~regp->override->mask; 1586 val |= (regp->override->val & regp->override->mask); 1587 } 1588 1589 return val; 1590 } 1591 1592 #include <linux/irqchip/arm-gic-v3.h> 1593 1594 static bool 1595 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1596 { 1597 return true; 1598 } 1599 1600 static bool 1601 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1602 { 1603 int val, min, max; 1604 u64 tmp; 1605 1606 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1607 entry->field_width, 1608 entry->sign); 1609 1610 tmp = entry->min_field_value; 1611 tmp <<= entry->field_pos; 1612 1613 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1614 entry->field_width, 1615 entry->sign); 1616 1617 tmp = entry->max_field_value; 1618 tmp <<= entry->field_pos; 1619 1620 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1621 entry->field_width, 1622 entry->sign); 1623 1624 return val >= min && val <= max; 1625 } 1626 1627 static u64 1628 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1629 { 1630 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1631 if (scope == SCOPE_SYSTEM) 1632 return read_sanitised_ftr_reg(entry->sys_reg); 1633 else 1634 return __read_sysreg_by_encoding(entry->sys_reg); 1635 } 1636 1637 static bool 1638 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1639 { 1640 int mask; 1641 struct arm64_ftr_reg *regp; 1642 u64 val = read_scoped_sysreg(entry, scope); 1643 1644 regp = get_arm64_ftr_reg(entry->sys_reg); 1645 if (!regp) 1646 return false; 1647 1648 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1649 entry->field_pos, 1650 entry->field_width); 1651 if (!mask) 1652 return false; 1653 1654 return feature_matches(val, entry); 1655 } 1656 1657 static bool 1658 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1659 { 1660 u64 val = read_scoped_sysreg(entry, scope); 1661 return feature_matches(val, entry); 1662 } 1663 1664 const struct cpumask *system_32bit_el0_cpumask(void) 1665 { 1666 if (!system_supports_32bit_el0()) 1667 return cpu_none_mask; 1668 1669 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1670 return cpu_32bit_el0_mask; 1671 1672 return cpu_possible_mask; 1673 } 1674 1675 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1676 { 1677 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_DOMAIN)); 1678 } 1679 1680 static int __init parse_32bit_el0_param(char *str) 1681 { 1682 allow_mismatched_32bit_el0 = true; 1683 return 0; 1684 } 1685 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1686 1687 static ssize_t aarch32_el0_show(struct device *dev, 1688 struct device_attribute *attr, char *buf) 1689 { 1690 const struct cpumask *mask = system_32bit_el0_cpumask(); 1691 1692 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1693 } 1694 static const DEVICE_ATTR_RO(aarch32_el0); 1695 1696 static int __init aarch32_el0_sysfs_init(void) 1697 { 1698 struct device *dev_root; 1699 int ret = 0; 1700 1701 if (!allow_mismatched_32bit_el0) 1702 return 0; 1703 1704 dev_root = bus_get_dev_root(&cpu_subsys); 1705 if (dev_root) { 1706 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1707 put_device(dev_root); 1708 } 1709 return ret; 1710 } 1711 device_initcall(aarch32_el0_sysfs_init); 1712 1713 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1714 { 1715 if (!has_cpuid_feature(entry, scope)) 1716 return allow_mismatched_32bit_el0; 1717 1718 if (scope == SCOPE_SYSTEM) 1719 pr_info("detected: 32-bit EL0 Support\n"); 1720 1721 return true; 1722 } 1723 1724 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1725 { 1726 bool has_sre; 1727 1728 if (!has_cpuid_feature(entry, scope)) 1729 return false; 1730 1731 has_sre = gic_enable_sre(); 1732 if (!has_sre) 1733 pr_warn_once("%s present but disabled by higher exception level\n", 1734 entry->desc); 1735 1736 return has_sre; 1737 } 1738 1739 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1740 int scope) 1741 { 1742 u64 ctr; 1743 1744 if (scope == SCOPE_SYSTEM) 1745 ctr = arm64_ftr_reg_ctrel0.sys_val; 1746 else 1747 ctr = read_cpuid_effective_cachetype(); 1748 1749 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1750 } 1751 1752 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1753 { 1754 /* 1755 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1756 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1757 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1758 * value. 1759 */ 1760 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1761 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1762 } 1763 1764 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1765 int scope) 1766 { 1767 u64 ctr; 1768 1769 if (scope == SCOPE_SYSTEM) 1770 ctr = arm64_ftr_reg_ctrel0.sys_val; 1771 else 1772 ctr = read_cpuid_cachetype(); 1773 1774 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1775 } 1776 1777 static bool __maybe_unused 1778 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1779 { 1780 /* 1781 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1782 * may share TLB entries with a CPU stuck in the crashed 1783 * kernel. 1784 */ 1785 if (is_kdump_kernel()) 1786 return false; 1787 1788 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1789 return false; 1790 1791 return has_cpuid_feature(entry, scope); 1792 } 1793 1794 static bool __meltdown_safe = true; 1795 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1796 1797 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1798 int scope) 1799 { 1800 /* List of CPUs that are not vulnerable and don't need KPTI */ 1801 static const struct midr_range kpti_safe_list[] = { 1802 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1803 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1804 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1805 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1806 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1807 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1808 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1809 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1810 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1811 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1812 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1813 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1814 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1815 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1816 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1817 { /* sentinel */ } 1818 }; 1819 char const *str = "kpti command line option"; 1820 bool meltdown_safe; 1821 1822 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1823 1824 /* Defer to CPU feature registers */ 1825 if (has_cpuid_feature(entry, scope)) 1826 meltdown_safe = true; 1827 1828 if (!meltdown_safe) 1829 __meltdown_safe = false; 1830 1831 /* 1832 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1833 * ThunderX leads to apparent I-cache corruption of kernel text, which 1834 * ends as well as you might imagine. Don't even try. We cannot rely 1835 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1836 * because cpucap detection order may change. However, since we know 1837 * affected CPUs are always in a homogeneous configuration, it is 1838 * safe to rely on this_cpu_has_cap() here. 1839 */ 1840 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1841 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1842 __kpti_forced = -1; 1843 } 1844 1845 /* Useful for KASLR robustness */ 1846 if (kaslr_enabled() && kaslr_requires_kpti()) { 1847 if (!__kpti_forced) { 1848 str = "KASLR"; 1849 __kpti_forced = 1; 1850 } 1851 } 1852 1853 if (cpu_mitigations_off() && !__kpti_forced) { 1854 str = "mitigations=off"; 1855 __kpti_forced = -1; 1856 } 1857 1858 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1859 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1860 return false; 1861 } 1862 1863 /* Forced? */ 1864 if (__kpti_forced) { 1865 pr_info_once("kernel page table isolation forced %s by %s\n", 1866 __kpti_forced > 0 ? "ON" : "OFF", str); 1867 return __kpti_forced > 0; 1868 } 1869 1870 return !meltdown_safe; 1871 } 1872 1873 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1874 { 1875 /* 1876 * Although the Apple M2 family appears to support NV1, the 1877 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1878 * that it doesn't support NV1 at all. 1879 */ 1880 static const struct midr_range nv1_ni_list[] = { 1881 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1882 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1883 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1884 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1885 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1886 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1887 {} 1888 }; 1889 1890 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1891 !(has_cpuid_feature(entry, scope) || 1892 is_midr_in_range_list(nv1_ni_list))); 1893 } 1894 1895 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1896 static bool has_lpa2_at_stage1(u64 mmfr0) 1897 { 1898 unsigned int tgran; 1899 1900 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1901 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1902 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1903 } 1904 1905 static bool has_lpa2_at_stage2(u64 mmfr0) 1906 { 1907 unsigned int tgran; 1908 1909 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1910 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1911 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1912 } 1913 1914 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1915 { 1916 u64 mmfr0; 1917 1918 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1919 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1920 } 1921 #else 1922 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1923 { 1924 return false; 1925 } 1926 #endif 1927 1928 #ifdef CONFIG_HW_PERF_EVENTS 1929 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1930 { 1931 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1932 unsigned int pmuver; 1933 1934 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1935 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1936 1937 return pmuv3_implemented(pmuver); 1938 } 1939 #endif 1940 1941 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1942 { 1943 if (__this_cpu_read(this_cpu_vector) == vectors) { 1944 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1945 1946 __this_cpu_write(this_cpu_vector, v); 1947 } 1948 1949 } 1950 1951 static int __init parse_kpti(char *str) 1952 { 1953 bool enabled; 1954 int ret = kstrtobool(str, &enabled); 1955 1956 if (ret) 1957 return ret; 1958 1959 __kpti_forced = enabled ? 1 : -1; 1960 return 0; 1961 } 1962 early_param("kpti", parse_kpti); 1963 1964 #ifdef CONFIG_ARM64_HW_AFDBM 1965 static struct cpumask dbm_cpus __read_mostly; 1966 1967 static inline void __cpu_enable_hw_dbm(void) 1968 { 1969 u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_HD; 1970 1971 write_sysreg(tcr, tcr_el1); 1972 isb(); 1973 local_flush_tlb_all(); 1974 } 1975 1976 static bool cpu_has_broken_dbm(void) 1977 { 1978 /* List of CPUs which have broken DBM support. */ 1979 static const struct midr_range cpus[] = { 1980 #ifdef CONFIG_ARM64_ERRATUM_1024718 1981 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1982 /* Kryo4xx Silver (rdpe => r1p0) */ 1983 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1984 #endif 1985 #ifdef CONFIG_ARM64_ERRATUM_2051678 1986 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1987 #endif 1988 {}, 1989 }; 1990 1991 return is_midr_in_range_list(cpus); 1992 } 1993 1994 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1995 { 1996 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1997 !cpu_has_broken_dbm(); 1998 } 1999 2000 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2001 { 2002 if (cpu_can_use_dbm(cap)) { 2003 __cpu_enable_hw_dbm(); 2004 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2005 } 2006 } 2007 2008 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2009 int __unused) 2010 { 2011 /* 2012 * DBM is a non-conflicting feature. i.e, the kernel can safely 2013 * run a mix of CPUs with and without the feature. So, we 2014 * unconditionally enable the capability to allow any late CPU 2015 * to use the feature. We only enable the control bits on the 2016 * CPU, if it is supported. 2017 */ 2018 2019 return true; 2020 } 2021 2022 #endif 2023 2024 #ifdef CONFIG_ARM64_AMU_EXTN 2025 2026 /* 2027 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2028 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2029 * information regarding all the events that it supports. When a CPU bit is 2030 * set in the cpumask, the user of this feature can only rely on the presence 2031 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2032 * counters are enabled or access to these counters is enabled by code 2033 * executed at higher exception levels (firmware). 2034 */ 2035 static struct cpumask amu_cpus __read_mostly; 2036 2037 bool cpu_has_amu_feat(int cpu) 2038 { 2039 return cpumask_test_cpu(cpu, &amu_cpus); 2040 } 2041 2042 int get_cpu_with_amu_feat(void) 2043 { 2044 return cpumask_any(&amu_cpus); 2045 } 2046 2047 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2048 { 2049 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2050 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2051 2052 /* 0 reference values signal broken/disabled counters */ 2053 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2054 update_freq_counters_refs(); 2055 } 2056 } 2057 2058 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2059 int __unused) 2060 { 2061 /* 2062 * The AMU extension is a non-conflicting feature: the kernel can 2063 * safely run a mix of CPUs with and without support for the 2064 * activity monitors extension. Therefore, unconditionally enable 2065 * the capability to allow any late CPU to use the feature. 2066 * 2067 * With this feature unconditionally enabled, the cpu_enable 2068 * function will be called for all CPUs that match the criteria, 2069 * including secondary and hotplugged, marking this feature as 2070 * present on that respective CPU. The enable function will also 2071 * print a detection message. 2072 */ 2073 2074 return true; 2075 } 2076 #else 2077 int get_cpu_with_amu_feat(void) 2078 { 2079 return nr_cpu_ids; 2080 } 2081 #endif 2082 2083 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2084 { 2085 return is_kernel_in_hyp_mode(); 2086 } 2087 2088 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2089 { 2090 /* 2091 * Copy register values that aren't redirected by hardware. 2092 * 2093 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2094 * this value to tpidr_el2 before we patch the code. Once we've done 2095 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2096 * do anything here. 2097 */ 2098 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2099 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2100 } 2101 2102 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2103 int scope) 2104 { 2105 if (kvm_get_mode() != KVM_MODE_NV) 2106 return false; 2107 2108 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2109 pr_warn("unavailable: %s\n", cap->desc); 2110 return false; 2111 } 2112 2113 return true; 2114 } 2115 2116 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2117 int __unused) 2118 { 2119 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2120 } 2121 2122 bool cpu_supports_bbml2_noabort(void) 2123 { 2124 /* 2125 * We want to allow usage of BBML2 in as wide a range of kernel contexts 2126 * as possible. This list is therefore an allow-list of known-good 2127 * implementations that both support BBML2 and additionally, fulfill the 2128 * extra constraint of never generating TLB conflict aborts when using 2129 * the relaxed BBML2 semantics (such aborts make use of BBML2 in certain 2130 * kernel contexts difficult to prove safe against recursive aborts). 2131 * 2132 * Note that implementations can only be considered "known-good" if their 2133 * implementors attest to the fact that the implementation never raises 2134 * TLB conflict aborts for BBML2 mapping granularity changes. 2135 */ 2136 static const struct midr_range supports_bbml2_noabort_list[] = { 2137 MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), 2138 MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), 2139 MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf), 2140 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 2141 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 2142 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 2143 {} 2144 }; 2145 2146 /* Does our cpu guarantee to never raise TLB conflict aborts? */ 2147 if (!is_midr_in_range_list(supports_bbml2_noabort_list)) 2148 return false; 2149 2150 /* 2151 * We currently ignore the ID_AA64MMFR2_EL1 register, and only care 2152 * about whether the MIDR check passes. 2153 */ 2154 2155 return true; 2156 } 2157 2158 static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int scope) 2159 { 2160 return cpu_supports_bbml2_noabort(); 2161 } 2162 2163 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2164 { 2165 /* 2166 * We modify PSTATE. This won't work from irq context as the PSTATE 2167 * is discarded once we return from the exception. 2168 */ 2169 WARN_ON_ONCE(in_interrupt()); 2170 2171 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2172 set_pstate_pan(1); 2173 } 2174 2175 #ifdef CONFIG_ARM64_RAS_EXTN 2176 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2177 { 2178 /* Firmware may have left a deferred SError in this register. */ 2179 write_sysreg_s(0, SYS_DISR_EL1); 2180 } 2181 static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope) 2182 { 2183 const struct arm64_cpu_capabilities rasv1p1_caps[] = { 2184 { 2185 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1) 2186 }, 2187 { 2188 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2189 }, 2190 { 2191 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1) 2192 }, 2193 }; 2194 2195 return (has_cpuid_feature(&rasv1p1_caps[0], scope) || 2196 (has_cpuid_feature(&rasv1p1_caps[1], scope) && 2197 has_cpuid_feature(&rasv1p1_caps[2], scope))); 2198 } 2199 #endif /* CONFIG_ARM64_RAS_EXTN */ 2200 2201 #ifdef CONFIG_ARM64_PTR_AUTH 2202 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2203 { 2204 int boot_val, sec_val; 2205 2206 /* We don't expect to be called with SCOPE_SYSTEM */ 2207 WARN_ON(scope == SCOPE_SYSTEM); 2208 /* 2209 * The ptr-auth feature levels are not intercompatible with lower 2210 * levels. Hence we must match ptr-auth feature level of the secondary 2211 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2212 * from the sanitised register whereas direct register read is done for 2213 * the secondary CPUs. 2214 * The sanitised feature state is guaranteed to match that of the 2215 * boot CPU as a mismatched secondary CPU is parked before it gets 2216 * a chance to update the state, with the capability. 2217 */ 2218 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2219 entry->field_pos, entry->sign); 2220 if (scope & SCOPE_BOOT_CPU) 2221 return boot_val >= entry->min_field_value; 2222 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2223 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2224 entry->field_pos, entry->sign); 2225 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2226 } 2227 2228 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2229 int scope) 2230 { 2231 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2232 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2233 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2234 2235 return apa || apa3 || api; 2236 } 2237 2238 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2239 int __unused) 2240 { 2241 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2242 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2243 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2244 2245 return gpa || gpa3 || gpi; 2246 } 2247 #endif /* CONFIG_ARM64_PTR_AUTH */ 2248 2249 #ifdef CONFIG_ARM64_E0PD 2250 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2251 { 2252 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2253 sysreg_clear_set(tcr_el1, 0, TCR_EL1_E0PD1); 2254 } 2255 #endif /* CONFIG_ARM64_E0PD */ 2256 2257 static void cpu_enable_ls64(struct arm64_cpu_capabilities const *cap) 2258 { 2259 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnALS, SCTLR_EL1_EnALS); 2260 } 2261 2262 static void cpu_enable_ls64_v(struct arm64_cpu_capabilities const *cap) 2263 { 2264 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnASR, 0); 2265 } 2266 2267 #ifdef CONFIG_ARM64_PSEUDO_NMI 2268 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2269 int scope) 2270 { 2271 /* 2272 * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU 2273 * feature, so will be detected earlier. 2274 */ 2275 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); 2276 if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) 2277 return false; 2278 2279 return enable_pseudo_nmi; 2280 } 2281 2282 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2283 int scope) 2284 { 2285 /* 2286 * If we're not using priority masking then we won't be poking PMR_EL1, 2287 * and there's no need to relax synchronization of writes to it, and 2288 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2289 * that. 2290 * 2291 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2292 * feature, so will be detected earlier. 2293 */ 2294 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2295 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2296 return false; 2297 2298 /* 2299 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2300 * hint for interrupt distribution, a DSB is not necessary when 2301 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2302 * 2303 * Linux itself doesn't use 1:N distribution, so has no need to 2304 * set PMHE. The only reason to have it set is if EL3 requires it 2305 * (and we can't change it). 2306 */ 2307 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2308 } 2309 #endif 2310 2311 static bool can_trap_icv_dir_el1(const struct arm64_cpu_capabilities *entry, 2312 int scope) 2313 { 2314 static const struct midr_range has_vgic_v3[] = { 2315 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), 2316 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), 2317 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), 2318 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), 2319 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), 2320 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), 2321 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 2322 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 2323 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 2324 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 2325 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 2326 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 2327 {}, 2328 }; 2329 struct arm_smccc_res res = {}; 2330 2331 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV3_CPUIF); 2332 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV5_LEGACY); 2333 if (!is_hyp_mode_available()) 2334 return false; 2335 2336 if (this_cpu_has_cap(ARM64_HAS_GICV5_LEGACY)) 2337 return true; 2338 2339 if (!this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF) && 2340 !is_midr_in_range_list(has_vgic_v3)) 2341 return false; 2342 2343 /* 2344 * pKVM prevents late onlining of CPUs. This means that whatever 2345 * state the capability is in after deprivilege cannot be affected 2346 * by a new CPU booting -- this is garanteed to be a CPU we have 2347 * already seen, and the cap is therefore unchanged. 2348 */ 2349 if (system_capabilities_finalized() && is_protected_kvm_enabled()) 2350 return cpus_have_final_cap(ARM64_HAS_ICH_HCR_EL2_TDIR); 2351 2352 if (is_kernel_in_hyp_mode()) 2353 res.a1 = read_sysreg_s(SYS_ICH_VTR_EL2); 2354 else 2355 arm_smccc_1_1_hvc(HVC_GET_ICH_VTR_EL2, &res); 2356 2357 if (res.a0 == HVC_STUB_ERR) 2358 return false; 2359 2360 return res.a1 & ICH_VTR_EL2_TDS; 2361 } 2362 2363 #ifdef CONFIG_ARM64_BTI 2364 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2365 { 2366 /* 2367 * Use of X16/X17 for tail-calls and trampolines that jump to 2368 * function entry points using BR is a requirement for 2369 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2370 * So, be strict and forbid other BRs using other registers to 2371 * jump onto a PACIxSP instruction: 2372 */ 2373 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2374 isb(); 2375 } 2376 #endif /* CONFIG_ARM64_BTI */ 2377 2378 #ifdef CONFIG_ARM64_MTE 2379 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2380 { 2381 static bool cleared_zero_page = false; 2382 2383 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2384 2385 mte_cpu_setup(); 2386 2387 /* 2388 * Clear the tags in the zero page. This needs to be done via the 2389 * linear map which has the Tagged attribute. Since this page is 2390 * always mapped as pte_special(), set_pte_at() will not attempt to 2391 * clear the tags or set PG_mte_tagged. 2392 */ 2393 if (!cleared_zero_page) { 2394 cleared_zero_page = true; 2395 mte_clear_page_tags(lm_alias(empty_zero_page)); 2396 } 2397 2398 kasan_init_hw_tags_cpu(); 2399 } 2400 #endif /* CONFIG_ARM64_MTE */ 2401 2402 static void user_feature_fixup(void) 2403 { 2404 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2405 struct arm64_ftr_reg *regp; 2406 2407 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2408 if (regp) 2409 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2410 } 2411 2412 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2413 struct arm64_ftr_reg *regp; 2414 2415 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2416 if (regp) 2417 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2418 } 2419 } 2420 2421 static void elf_hwcap_fixup(void) 2422 { 2423 #ifdef CONFIG_COMPAT 2424 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2425 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2426 #endif /* CONFIG_COMPAT */ 2427 } 2428 2429 #ifdef CONFIG_KVM 2430 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2431 { 2432 return kvm_get_mode() == KVM_MODE_PROTECTED; 2433 } 2434 #endif /* CONFIG_KVM */ 2435 2436 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2437 { 2438 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2439 } 2440 2441 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2442 { 2443 set_pstate_dit(1); 2444 } 2445 2446 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2447 { 2448 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2449 } 2450 2451 #ifdef CONFIG_ARM64_POE 2452 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2453 { 2454 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2455 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2456 } 2457 #endif 2458 2459 #ifdef CONFIG_ARM64_GCS 2460 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2461 { 2462 /* GCSPR_EL0 is always readable */ 2463 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2464 } 2465 #endif 2466 2467 /* Internal helper functions to match cpu capability type */ 2468 static bool 2469 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2470 { 2471 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2472 } 2473 2474 static bool 2475 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2476 { 2477 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2478 } 2479 2480 static bool 2481 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2482 { 2483 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2484 } 2485 2486 static bool 2487 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2488 { 2489 if (!has_cpuid_feature(entry, scope)) 2490 return false; 2491 2492 /* Check firmware actually enabled MPAM on this cpu. */ 2493 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2494 } 2495 2496 static void 2497 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2498 { 2499 int cpu = smp_processor_id(); 2500 u64 regval = 0; 2501 2502 if (IS_ENABLED(CONFIG_ARM64_MPAM) && static_branch_likely(&mpam_enabled)) 2503 regval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); 2504 2505 write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1); 2506 if (cpus_have_cap(ARM64_SME)) 2507 write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D), SYS_MPAMSM_EL1); 2508 isb(); 2509 2510 /* Synchronising the EL0 write is left until the ERET to EL0 */ 2511 write_sysreg_s(regval, SYS_MPAM0_EL1); 2512 } 2513 2514 static bool 2515 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2516 { 2517 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2518 2519 return idr & MPAMIDR_EL1_HAS_HCR; 2520 } 2521 2522 static bool 2523 test_has_gicv5_legacy(const struct arm64_cpu_capabilities *entry, int scope) 2524 { 2525 if (!this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF)) 2526 return false; 2527 2528 return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY); 2529 } 2530 2531 static const struct arm64_cpu_capabilities arm64_features[] = { 2532 { 2533 .capability = ARM64_ALWAYS_BOOT, 2534 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2535 .matches = has_always, 2536 }, 2537 { 2538 .capability = ARM64_ALWAYS_SYSTEM, 2539 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2540 .matches = has_always, 2541 }, 2542 { 2543 .desc = "GICv3 CPU interface", 2544 .capability = ARM64_HAS_GICV3_CPUIF, 2545 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2546 .matches = has_useable_gicv3_cpuif, 2547 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2548 }, 2549 { 2550 .desc = "Enhanced Counter Virtualization", 2551 .capability = ARM64_HAS_ECV, 2552 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2553 .matches = has_cpuid_feature, 2554 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2555 }, 2556 { 2557 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2558 .capability = ARM64_HAS_ECV_CNTPOFF, 2559 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2560 .matches = has_cpuid_feature, 2561 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2562 }, 2563 { 2564 .desc = "Privileged Access Never", 2565 .capability = ARM64_HAS_PAN, 2566 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2567 .matches = has_cpuid_feature, 2568 .cpu_enable = cpu_enable_pan, 2569 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2570 }, 2571 #ifdef CONFIG_ARM64_EPAN 2572 { 2573 .desc = "Enhanced Privileged Access Never", 2574 .capability = ARM64_HAS_EPAN, 2575 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2576 .matches = has_cpuid_feature, 2577 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2578 }, 2579 #endif /* CONFIG_ARM64_EPAN */ 2580 { 2581 .desc = "LSE atomic instructions", 2582 .capability = ARM64_HAS_LSE_ATOMICS, 2583 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2584 .matches = has_cpuid_feature, 2585 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2586 }, 2587 { 2588 .desc = "Virtualization Host Extensions", 2589 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2590 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2591 .matches = runs_at_el2, 2592 .cpu_enable = cpu_copy_el2regs, 2593 }, 2594 { 2595 .desc = "Nested Virtualization Support", 2596 .capability = ARM64_HAS_NESTED_VIRT, 2597 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2598 .matches = has_nested_virt_support, 2599 .match_list = (const struct arm64_cpu_capabilities []){ 2600 { 2601 .matches = has_cpuid_feature, 2602 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2603 }, 2604 { 2605 .matches = has_cpuid_feature, 2606 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2607 }, 2608 { /* Sentinel */ } 2609 }, 2610 }, 2611 { 2612 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2613 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2614 .matches = has_32bit_el0, 2615 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2616 }, 2617 #ifdef CONFIG_KVM 2618 { 2619 .desc = "32-bit EL1 Support", 2620 .capability = ARM64_HAS_32BIT_EL1, 2621 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2622 .matches = has_cpuid_feature, 2623 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2624 }, 2625 { 2626 .desc = "Protected KVM", 2627 .capability = ARM64_KVM_PROTECTED_MODE, 2628 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2629 .matches = is_kvm_protected_mode, 2630 }, 2631 { 2632 .desc = "HCRX_EL2 register", 2633 .capability = ARM64_HAS_HCX, 2634 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2635 .matches = has_cpuid_feature, 2636 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2637 }, 2638 #endif 2639 { 2640 .desc = "Kernel page table isolation (KPTI)", 2641 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2642 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2643 .cpu_enable = cpu_enable_kpti, 2644 .matches = unmap_kernel_at_el0, 2645 /* 2646 * The ID feature fields below are used to indicate that 2647 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2648 * more details. 2649 */ 2650 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2651 }, 2652 { 2653 .capability = ARM64_HAS_FPSIMD, 2654 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2655 .matches = has_cpuid_feature, 2656 .cpu_enable = cpu_enable_fpsimd, 2657 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2658 }, 2659 #ifdef CONFIG_ARM64_PMEM 2660 { 2661 .desc = "Data cache clean to Point of Persistence", 2662 .capability = ARM64_HAS_DCPOP, 2663 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2664 .matches = has_cpuid_feature, 2665 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2666 }, 2667 { 2668 .desc = "Data cache clean to Point of Deep Persistence", 2669 .capability = ARM64_HAS_DCPODP, 2670 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2671 .matches = has_cpuid_feature, 2672 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2673 }, 2674 #endif 2675 #ifdef CONFIG_ARM64_SVE 2676 { 2677 .desc = "Scalable Vector Extension", 2678 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2679 .capability = ARM64_SVE, 2680 .cpu_enable = cpu_enable_sve, 2681 .matches = has_cpuid_feature, 2682 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2683 }, 2684 #endif /* CONFIG_ARM64_SVE */ 2685 #ifdef CONFIG_ARM64_RAS_EXTN 2686 { 2687 .desc = "RAS Extension Support", 2688 .capability = ARM64_HAS_RAS_EXTN, 2689 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2690 .matches = has_cpuid_feature, 2691 .cpu_enable = cpu_clear_disr, 2692 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2693 }, 2694 { 2695 .desc = "RASv1p1 Extension Support", 2696 .capability = ARM64_HAS_RASV1P1_EXTN, 2697 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2698 .matches = has_rasv1p1, 2699 }, 2700 #endif /* CONFIG_ARM64_RAS_EXTN */ 2701 #ifdef CONFIG_ARM64_AMU_EXTN 2702 { 2703 .desc = "Activity Monitors Unit (AMU)", 2704 .capability = ARM64_HAS_AMU_EXTN, 2705 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2706 .matches = has_amu, 2707 .cpu_enable = cpu_amu_enable, 2708 .cpus = &amu_cpus, 2709 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2710 }, 2711 #endif /* CONFIG_ARM64_AMU_EXTN */ 2712 { 2713 .desc = "Data cache clean to the PoU not required for I/D coherence", 2714 .capability = ARM64_HAS_CACHE_IDC, 2715 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2716 .matches = has_cache_idc, 2717 .cpu_enable = cpu_emulate_effective_ctr, 2718 }, 2719 { 2720 .desc = "Instruction cache invalidation not required for I/D coherence", 2721 .capability = ARM64_HAS_CACHE_DIC, 2722 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2723 .matches = has_cache_dic, 2724 }, 2725 { 2726 .desc = "Stage-2 Force Write-Back", 2727 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2728 .capability = ARM64_HAS_STAGE2_FWB, 2729 .matches = has_cpuid_feature, 2730 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2731 }, 2732 { 2733 .desc = "ARMv8.4 Translation Table Level", 2734 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2735 .capability = ARM64_HAS_ARMv8_4_TTL, 2736 .matches = has_cpuid_feature, 2737 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2738 }, 2739 { 2740 .desc = "TLB range maintenance instructions", 2741 .capability = ARM64_HAS_TLB_RANGE, 2742 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2743 .matches = has_cpuid_feature, 2744 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2745 }, 2746 #ifdef CONFIG_ARM64_HW_AFDBM 2747 { 2748 .desc = "Hardware dirty bit management", 2749 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2750 .capability = ARM64_HW_DBM, 2751 .matches = has_hw_dbm, 2752 .cpu_enable = cpu_enable_hw_dbm, 2753 .cpus = &dbm_cpus, 2754 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2755 }, 2756 #endif 2757 #ifdef CONFIG_ARM64_HAFT 2758 { 2759 .desc = "Hardware managed Access Flag for Table Descriptors", 2760 /* 2761 * Contrary to the page/block access flag, the table access flag 2762 * cannot be emulated in software (no access fault will occur). 2763 * Therefore this should be used only if it's supported system 2764 * wide. 2765 */ 2766 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2767 .capability = ARM64_HAFT, 2768 .matches = has_cpuid_feature, 2769 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2770 }, 2771 #endif 2772 { 2773 .desc = "CRC32 instructions", 2774 .capability = ARM64_HAS_CRC32, 2775 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2776 .matches = has_cpuid_feature, 2777 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2778 }, 2779 { 2780 .desc = "Speculative Store Bypassing Safe (SSBS)", 2781 .capability = ARM64_SSBS, 2782 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2783 .matches = has_cpuid_feature, 2784 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2785 }, 2786 #ifdef CONFIG_ARM64_CNP 2787 { 2788 .desc = "Common not Private translations", 2789 .capability = ARM64_HAS_CNP, 2790 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2791 .matches = has_useable_cnp, 2792 .cpu_enable = cpu_enable_cnp, 2793 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2794 }, 2795 #endif 2796 { 2797 .desc = "Speculation barrier (SB)", 2798 .capability = ARM64_HAS_SB, 2799 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2800 .matches = has_cpuid_feature, 2801 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2802 }, 2803 #ifdef CONFIG_ARM64_PTR_AUTH 2804 { 2805 .desc = "Address authentication (architected QARMA5 algorithm)", 2806 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2807 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2808 .matches = has_address_auth_cpucap, 2809 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2810 }, 2811 { 2812 .desc = "Address authentication (architected QARMA3 algorithm)", 2813 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2814 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2815 .matches = has_address_auth_cpucap, 2816 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2817 }, 2818 { 2819 .desc = "Address authentication (IMP DEF algorithm)", 2820 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2821 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2822 .matches = has_address_auth_cpucap, 2823 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2824 }, 2825 { 2826 .capability = ARM64_HAS_ADDRESS_AUTH, 2827 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2828 .matches = has_address_auth_metacap, 2829 }, 2830 { 2831 .desc = "Generic authentication (architected QARMA5 algorithm)", 2832 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2833 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2834 .matches = has_cpuid_feature, 2835 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2836 }, 2837 { 2838 .desc = "Generic authentication (architected QARMA3 algorithm)", 2839 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2840 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2841 .matches = has_cpuid_feature, 2842 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2843 }, 2844 { 2845 .desc = "Generic authentication (IMP DEF algorithm)", 2846 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2847 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2848 .matches = has_cpuid_feature, 2849 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2850 }, 2851 { 2852 .capability = ARM64_HAS_GENERIC_AUTH, 2853 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2854 .matches = has_generic_auth, 2855 }, 2856 #endif /* CONFIG_ARM64_PTR_AUTH */ 2857 #ifdef CONFIG_ARM64_PSEUDO_NMI 2858 { 2859 /* 2860 * Depends on having GICv3 2861 */ 2862 .desc = "IRQ priority masking", 2863 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2864 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2865 .matches = can_use_gic_priorities, 2866 }, 2867 { 2868 /* 2869 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2870 */ 2871 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2872 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2873 .matches = has_gic_prio_relaxed_sync, 2874 }, 2875 #endif 2876 { 2877 /* 2878 * Depends on having GICv3 2879 */ 2880 .desc = "ICV_DIR_EL1 trapping", 2881 .capability = ARM64_HAS_ICH_HCR_EL2_TDIR, 2882 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 2883 .matches = can_trap_icv_dir_el1, 2884 }, 2885 #ifdef CONFIG_ARM64_E0PD 2886 { 2887 .desc = "E0PD", 2888 .capability = ARM64_HAS_E0PD, 2889 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2890 .cpu_enable = cpu_enable_e0pd, 2891 .matches = has_cpuid_feature, 2892 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2893 }, 2894 #endif 2895 { 2896 .desc = "Random Number Generator", 2897 .capability = ARM64_HAS_RNG, 2898 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2899 .matches = has_cpuid_feature, 2900 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2901 }, 2902 #ifdef CONFIG_ARM64_BTI 2903 { 2904 .desc = "Branch Target Identification", 2905 .capability = ARM64_BTI, 2906 #ifdef CONFIG_ARM64_BTI_KERNEL 2907 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2908 #else 2909 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2910 #endif 2911 .matches = has_cpuid_feature, 2912 .cpu_enable = bti_enable, 2913 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2914 }, 2915 #endif 2916 #ifdef CONFIG_ARM64_MTE 2917 { 2918 .desc = "Memory Tagging Extension", 2919 .capability = ARM64_MTE, 2920 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2921 .matches = has_cpuid_feature, 2922 .cpu_enable = cpu_enable_mte, 2923 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2924 }, 2925 { 2926 .desc = "Asymmetric MTE Tag Check Fault", 2927 .capability = ARM64_MTE_ASYMM, 2928 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2929 .matches = has_cpuid_feature, 2930 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2931 }, 2932 { 2933 .desc = "FAR on MTE Tag Check Fault", 2934 .capability = ARM64_MTE_FAR, 2935 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2936 .matches = has_cpuid_feature, 2937 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) 2938 }, 2939 { 2940 .desc = "Store Only MTE Tag Check", 2941 .capability = ARM64_MTE_STORE_ONLY, 2942 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2943 .matches = has_cpuid_feature, 2944 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) 2945 }, 2946 #endif /* CONFIG_ARM64_MTE */ 2947 { 2948 .desc = "RCpc load-acquire (LDAPR)", 2949 .capability = ARM64_HAS_LDAPR, 2950 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2951 .matches = has_cpuid_feature, 2952 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2953 }, 2954 { 2955 .desc = "Fine Grained Traps", 2956 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2957 .capability = ARM64_HAS_FGT, 2958 .matches = has_cpuid_feature, 2959 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2960 }, 2961 { 2962 .desc = "Fine Grained Traps 2", 2963 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2964 .capability = ARM64_HAS_FGT2, 2965 .matches = has_cpuid_feature, 2966 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 2967 }, 2968 #ifdef CONFIG_ARM64_SME 2969 { 2970 .desc = "Scalable Matrix Extension", 2971 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2972 .capability = ARM64_SME, 2973 .matches = has_cpuid_feature, 2974 .cpu_enable = cpu_enable_sme, 2975 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2976 }, 2977 /* FA64 should be sorted after the base SME capability */ 2978 { 2979 .desc = "FA64", 2980 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2981 .capability = ARM64_SME_FA64, 2982 .matches = has_cpuid_feature, 2983 .cpu_enable = cpu_enable_fa64, 2984 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2985 }, 2986 { 2987 .desc = "SME2", 2988 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2989 .capability = ARM64_SME2, 2990 .matches = has_cpuid_feature, 2991 .cpu_enable = cpu_enable_sme2, 2992 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2993 }, 2994 #endif /* CONFIG_ARM64_SME */ 2995 { 2996 .desc = "WFx with timeout", 2997 .capability = ARM64_HAS_WFXT, 2998 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2999 .matches = has_cpuid_feature, 3000 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 3001 }, 3002 { 3003 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 3004 .capability = ARM64_HAS_TIDCP1, 3005 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3006 .matches = has_cpuid_feature, 3007 .cpu_enable = cpu_trap_el0_impdef, 3008 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 3009 }, 3010 { 3011 .desc = "Data independent timing control (DIT)", 3012 .capability = ARM64_HAS_DIT, 3013 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3014 .matches = has_cpuid_feature, 3015 .cpu_enable = cpu_enable_dit, 3016 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 3017 }, 3018 { 3019 .desc = "Memory Copy and Memory Set instructions", 3020 .capability = ARM64_HAS_MOPS, 3021 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3022 .matches = has_cpuid_feature, 3023 .cpu_enable = cpu_enable_mops, 3024 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 3025 }, 3026 { 3027 .capability = ARM64_HAS_TCR2, 3028 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3029 .matches = has_cpuid_feature, 3030 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 3031 }, 3032 { 3033 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 3034 .capability = ARM64_HAS_S1PIE, 3035 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3036 .matches = has_cpuid_feature, 3037 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 3038 }, 3039 { 3040 .desc = "VHE for hypervisor only", 3041 .capability = ARM64_KVM_HVHE, 3042 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3043 .matches = hvhe_possible, 3044 }, 3045 { 3046 .desc = "Enhanced Virtualization Traps", 3047 .capability = ARM64_HAS_EVT, 3048 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3049 .matches = has_cpuid_feature, 3050 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 3051 }, 3052 { 3053 .desc = "BBM Level 2 without TLB conflict abort", 3054 .capability = ARM64_HAS_BBML2_NOABORT, 3055 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3056 .matches = has_bbml2_noabort, 3057 }, 3058 { 3059 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 3060 .capability = ARM64_HAS_LPA2, 3061 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3062 .matches = has_lpa2, 3063 }, 3064 { 3065 .desc = "FPMR", 3066 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3067 .capability = ARM64_HAS_FPMR, 3068 .matches = has_cpuid_feature, 3069 .cpu_enable = cpu_enable_fpmr, 3070 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 3071 }, 3072 #ifdef CONFIG_ARM64_VA_BITS_52 3073 { 3074 .capability = ARM64_HAS_VA52, 3075 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3076 .matches = has_cpuid_feature, 3077 #ifdef CONFIG_ARM64_64K_PAGES 3078 .desc = "52-bit Virtual Addressing (LVA)", 3079 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 3080 #else 3081 .desc = "52-bit Virtual Addressing (LPA2)", 3082 #ifdef CONFIG_ARM64_4K_PAGES 3083 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 3084 #else 3085 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 3086 #endif 3087 #endif 3088 }, 3089 #endif 3090 { 3091 .desc = "Memory Partitioning And Monitoring", 3092 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3093 .capability = ARM64_MPAM, 3094 .matches = test_has_mpam, 3095 .cpu_enable = cpu_enable_mpam, 3096 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 3097 }, 3098 { 3099 .desc = "Memory Partitioning And Monitoring Virtualisation", 3100 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3101 .capability = ARM64_MPAM_HCR, 3102 .matches = test_has_mpam_hcr, 3103 }, 3104 { 3105 .desc = "NV1", 3106 .capability = ARM64_HAS_HCR_NV1, 3107 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3108 .matches = has_nv1, 3109 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3110 }, 3111 #ifdef CONFIG_ARM64_POE 3112 { 3113 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3114 .capability = ARM64_HAS_S1POE, 3115 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3116 .matches = has_cpuid_feature, 3117 .cpu_enable = cpu_enable_poe, 3118 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3119 }, 3120 #endif 3121 #ifdef CONFIG_ARM64_GCS 3122 { 3123 .desc = "Guarded Control Stack (GCS)", 3124 .capability = ARM64_HAS_GCS, 3125 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3126 .cpu_enable = cpu_enable_gcs, 3127 .matches = has_cpuid_feature, 3128 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3129 }, 3130 #endif 3131 #ifdef CONFIG_HW_PERF_EVENTS 3132 { 3133 .desc = "PMUv3", 3134 .capability = ARM64_HAS_PMUV3, 3135 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3136 .matches = has_pmuv3, 3137 }, 3138 #endif 3139 { 3140 .desc = "SCTLR2", 3141 .capability = ARM64_HAS_SCTLR2, 3142 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3143 .matches = has_cpuid_feature, 3144 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, SCTLRX, IMP) 3145 }, 3146 { 3147 .desc = "GICv5 CPU interface", 3148 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 3149 .capability = ARM64_HAS_GICV5_CPUIF, 3150 .matches = has_cpuid_feature, 3151 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) 3152 }, 3153 { 3154 .desc = "GICv5 Legacy vCPU interface", 3155 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3156 .capability = ARM64_HAS_GICV5_LEGACY, 3157 .matches = test_has_gicv5_legacy, 3158 }, 3159 { 3160 .desc = "XNX", 3161 .capability = ARM64_HAS_XNX, 3162 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3163 .matches = has_cpuid_feature, 3164 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, XNX, IMP) 3165 }, 3166 { 3167 .desc = "LS64", 3168 .capability = ARM64_HAS_LS64, 3169 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3170 .matches = has_cpuid_feature, 3171 .cpu_enable = cpu_enable_ls64, 3172 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64) 3173 }, 3174 { 3175 .desc = "LS64_V", 3176 .capability = ARM64_HAS_LS64_V, 3177 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3178 .matches = has_cpuid_feature, 3179 .cpu_enable = cpu_enable_ls64_v, 3180 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64_V) 3181 }, 3182 #ifdef CONFIG_ARM64_LSUI 3183 { 3184 .desc = "Unprivileged Load Store Instructions (LSUI)", 3185 .capability = ARM64_HAS_LSUI, 3186 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3187 .matches = has_cpuid_feature, 3188 ARM64_CPUID_FIELDS(ID_AA64ISAR3_EL1, LSUI, IMP) 3189 }, 3190 #endif 3191 {}, 3192 }; 3193 3194 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3195 .matches = has_user_cpuid_feature, \ 3196 ARM64_CPUID_FIELDS(reg, field, min_value) 3197 3198 #define __HWCAP_CAP(name, cap_type, cap) \ 3199 .desc = name, \ 3200 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3201 .hwcap_type = cap_type, \ 3202 .hwcap = cap, \ 3203 3204 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3205 { \ 3206 __HWCAP_CAP(#cap, cap_type, cap) \ 3207 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3208 } 3209 3210 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3211 { \ 3212 __HWCAP_CAP(#cap, cap_type, cap) \ 3213 .matches = cpucap_multi_entry_cap_matches, \ 3214 .match_list = list, \ 3215 } 3216 3217 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3218 { \ 3219 __HWCAP_CAP(#cap, cap_type, cap) \ 3220 .matches = match, \ 3221 } 3222 3223 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3224 { \ 3225 __HWCAP_CAP(#cap, cap_type, cap) \ 3226 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3227 .matches = match, \ 3228 } 3229 3230 #ifdef CONFIG_ARM64_PTR_AUTH 3231 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3232 { 3233 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3234 }, 3235 { 3236 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3237 }, 3238 { 3239 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3240 }, 3241 {}, 3242 }; 3243 3244 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3245 { 3246 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3247 }, 3248 { 3249 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3250 }, 3251 { 3252 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3253 }, 3254 {}, 3255 }; 3256 #endif 3257 3258 #ifdef CONFIG_ARM64_SVE 3259 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3260 { 3261 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3262 } 3263 #endif 3264 3265 #ifdef CONFIG_ARM64_SME 3266 static bool has_sme_feature(const struct arm64_cpu_capabilities *cap, int scope) 3267 { 3268 return system_supports_sme() && has_user_cpuid_feature(cap, scope); 3269 } 3270 #endif 3271 3272 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3273 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3274 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3275 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3276 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3277 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3278 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3279 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3280 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3281 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3282 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3283 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3284 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3285 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3286 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3287 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3288 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3289 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3290 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3291 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3292 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3293 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3294 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3295 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3296 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3297 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3298 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3299 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3300 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3301 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3302 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3303 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3304 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3305 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3306 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3307 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3308 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3309 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3310 HWCAP_CAP(ID_AA64ISAR1_EL1, LS64, LS64, CAP_HWCAP, KERNEL_HWCAP_LS64), 3311 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3312 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3313 HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE), 3314 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3315 #ifdef CONFIG_ARM64_SVE 3316 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3317 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3318 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3319 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3320 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3321 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3322 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3323 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3324 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3325 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3326 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3327 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3328 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3329 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3330 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3331 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3332 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3333 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3334 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3335 #endif 3336 #ifdef CONFIG_ARM64_GCS 3337 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3338 #endif 3339 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3340 #ifdef CONFIG_ARM64_BTI 3341 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3342 #endif 3343 #ifdef CONFIG_ARM64_PTR_AUTH 3344 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3345 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3346 #endif 3347 #ifdef CONFIG_ARM64_MTE 3348 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3349 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3350 HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), 3351 HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MTE_STORE_ONLY), 3352 #endif /* CONFIG_ARM64_MTE */ 3353 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3354 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3355 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3356 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3357 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3358 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3359 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3360 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3361 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3362 #ifdef CONFIG_ARM64_SME 3363 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3364 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3365 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3366 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3367 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3368 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3369 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3370 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3371 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3372 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3373 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3374 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3375 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3376 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3377 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3378 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3379 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3380 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3381 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3382 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3383 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3384 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3385 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3386 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3387 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3388 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3389 #endif /* CONFIG_ARM64_SME */ 3390 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3391 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3392 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3393 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3394 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3395 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3396 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3397 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3398 #ifdef CONFIG_ARM64_POE 3399 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3400 #endif 3401 {}, 3402 }; 3403 3404 #ifdef CONFIG_COMPAT 3405 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3406 { 3407 /* 3408 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3409 * in line with that of arm32 as in vfp_init(). We make sure that the 3410 * check is future proof, by making sure value is non-zero. 3411 */ 3412 u32 mvfr1; 3413 3414 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3415 if (scope == SCOPE_SYSTEM) 3416 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3417 else 3418 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3419 3420 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3421 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3422 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3423 } 3424 #endif 3425 3426 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3427 #ifdef CONFIG_COMPAT 3428 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3429 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3430 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3431 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3432 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3433 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3434 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3435 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3436 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3437 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3438 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3439 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3440 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3441 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3442 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3443 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3444 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3445 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3446 #endif 3447 {}, 3448 }; 3449 3450 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3451 { 3452 switch (cap->hwcap_type) { 3453 case CAP_HWCAP: 3454 cpu_set_feature(cap->hwcap); 3455 break; 3456 #ifdef CONFIG_COMPAT 3457 case CAP_COMPAT_HWCAP: 3458 compat_elf_hwcap |= (u32)cap->hwcap; 3459 break; 3460 case CAP_COMPAT_HWCAP2: 3461 compat_elf_hwcap2 |= (u32)cap->hwcap; 3462 break; 3463 #endif 3464 default: 3465 WARN_ON(1); 3466 break; 3467 } 3468 } 3469 3470 /* Check if we have a particular HWCAP enabled */ 3471 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3472 { 3473 bool rc; 3474 3475 switch (cap->hwcap_type) { 3476 case CAP_HWCAP: 3477 rc = cpu_have_feature(cap->hwcap); 3478 break; 3479 #ifdef CONFIG_COMPAT 3480 case CAP_COMPAT_HWCAP: 3481 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3482 break; 3483 case CAP_COMPAT_HWCAP2: 3484 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3485 break; 3486 #endif 3487 default: 3488 WARN_ON(1); 3489 rc = false; 3490 } 3491 3492 return rc; 3493 } 3494 3495 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3496 { 3497 /* We support emulation of accesses to CPU ID feature registers */ 3498 cpu_set_named_feature(CPUID); 3499 for (; hwcaps->matches; hwcaps++) 3500 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3501 cap_set_elf_hwcap(hwcaps); 3502 } 3503 3504 static void update_cpu_capabilities(u16 scope_mask) 3505 { 3506 int i; 3507 const struct arm64_cpu_capabilities *caps; 3508 3509 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3510 for (i = 0; i < ARM64_NCAPS; i++) { 3511 bool match_all = false; 3512 bool caps_set = false; 3513 bool boot_cpu = false; 3514 3515 caps = cpucap_ptrs[i]; 3516 if (!caps || !(caps->type & scope_mask)) 3517 continue; 3518 3519 match_all = cpucap_match_all_early_cpus(caps); 3520 caps_set = cpus_have_cap(caps->capability); 3521 boot_cpu = scope_mask & SCOPE_BOOT_CPU; 3522 3523 /* 3524 * Unless it's a match-all CPUs feature, avoid probing if 3525 * already detected. 3526 */ 3527 if (!match_all && caps_set) 3528 continue; 3529 3530 /* 3531 * A match-all CPUs capability is only set when probing the 3532 * boot CPU. It may be cleared subsequently if not detected on 3533 * secondary ones. 3534 */ 3535 if (match_all && !caps_set && !boot_cpu) 3536 continue; 3537 3538 if (!caps->matches(caps, cpucap_default_scope(caps))) { 3539 if (match_all) 3540 __clear_bit(caps->capability, system_cpucaps); 3541 continue; 3542 } 3543 3544 /* 3545 * Match-all CPUs capabilities are logged later when the 3546 * system capabilities are finalised. 3547 */ 3548 if (!match_all && caps->desc && !caps->cpus) 3549 pr_info("detected: %s\n", caps->desc); 3550 3551 __set_bit(caps->capability, system_cpucaps); 3552 3553 if (boot_cpu && (caps->type & SCOPE_BOOT_CPU)) 3554 set_bit(caps->capability, boot_cpucaps); 3555 } 3556 } 3557 3558 /* 3559 * Enable all the available capabilities on this CPU. The capabilities 3560 * with BOOT_CPU scope are handled separately and hence skipped here. 3561 */ 3562 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3563 { 3564 int i; 3565 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3566 3567 for_each_available_cap(i) { 3568 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3569 3570 if (WARN_ON(!cap)) 3571 continue; 3572 3573 if (!(cap->type & non_boot_scope)) 3574 continue; 3575 3576 if (cap->cpu_enable) 3577 cap->cpu_enable(cap); 3578 } 3579 return 0; 3580 } 3581 3582 /* 3583 * Run through the enabled capabilities and enable() it on all active 3584 * CPUs 3585 */ 3586 static void __init enable_cpu_capabilities(u16 scope_mask) 3587 { 3588 int i; 3589 const struct arm64_cpu_capabilities *caps; 3590 bool boot_scope; 3591 3592 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3593 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3594 3595 for (i = 0; i < ARM64_NCAPS; i++) { 3596 caps = cpucap_ptrs[i]; 3597 if (!caps || !(caps->type & scope_mask) || 3598 !cpus_have_cap(caps->capability)) 3599 continue; 3600 3601 if (boot_scope && caps->cpu_enable) 3602 /* 3603 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3604 * before any secondary CPU boots. Thus, each secondary 3605 * will enable the capability as appropriate via 3606 * check_local_cpu_capabilities(). The only exception is 3607 * the boot CPU, for which the capability must be 3608 * enabled here. This approach avoids costly 3609 * stop_machine() calls for this case. 3610 */ 3611 caps->cpu_enable(caps); 3612 } 3613 3614 /* 3615 * For all non-boot scope capabilities, use stop_machine() 3616 * as it schedules the work allowing us to modify PSTATE, 3617 * instead of on_each_cpu() which uses an IPI, giving us a 3618 * PSTATE that disappears when we return. 3619 */ 3620 if (!boot_scope) 3621 stop_machine(cpu_enable_non_boot_scope_capabilities, 3622 NULL, cpu_online_mask); 3623 } 3624 3625 /* 3626 * Run through the list of capabilities to check for conflicts. 3627 * If the system has already detected a capability, take necessary 3628 * action on this CPU. 3629 */ 3630 static void verify_local_cpu_caps(u16 scope_mask) 3631 { 3632 int i; 3633 bool cpu_has_cap, system_has_cap; 3634 const struct arm64_cpu_capabilities *caps; 3635 3636 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3637 3638 for (i = 0; i < ARM64_NCAPS; i++) { 3639 caps = cpucap_ptrs[i]; 3640 if (!caps || !(caps->type & scope_mask)) 3641 continue; 3642 3643 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3644 system_has_cap = cpus_have_cap(caps->capability); 3645 3646 if (system_has_cap) { 3647 /* 3648 * Check if the new CPU misses an advertised feature, 3649 * which is not safe to miss. 3650 */ 3651 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3652 break; 3653 /* 3654 * We have to issue cpu_enable() irrespective of 3655 * whether the CPU has it or not, as it is enabeld 3656 * system wide. It is upto the call back to take 3657 * appropriate action on this CPU. 3658 */ 3659 if (caps->cpu_enable) 3660 caps->cpu_enable(caps); 3661 } else { 3662 /* 3663 * Check if the CPU has this capability if it isn't 3664 * safe to have when the system doesn't. 3665 */ 3666 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3667 break; 3668 } 3669 } 3670 3671 if (i < ARM64_NCAPS) { 3672 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3673 smp_processor_id(), caps->capability, 3674 caps->desc, system_has_cap, cpu_has_cap); 3675 3676 if (cpucap_panic_on_conflict(caps)) 3677 cpu_panic_kernel(); 3678 else 3679 cpu_die_early(); 3680 } 3681 } 3682 3683 /* 3684 * Check for CPU features that are used in early boot 3685 * based on the Boot CPU value. 3686 */ 3687 static void check_early_cpu_features(void) 3688 { 3689 verify_cpu_asid_bits(); 3690 3691 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3692 } 3693 3694 static void 3695 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3696 { 3697 3698 for (; caps->matches; caps++) 3699 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3700 pr_crit("CPU%d: missing HWCAP: %s\n", 3701 smp_processor_id(), caps->desc); 3702 cpu_die_early(); 3703 } 3704 } 3705 3706 static void verify_local_elf_hwcaps(void) 3707 { 3708 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3709 3710 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3711 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3712 } 3713 3714 static void verify_sve_features(void) 3715 { 3716 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3717 3718 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3719 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3720 smp_processor_id()); 3721 cpu_die_early(); 3722 } 3723 3724 cpacr_restore(cpacr); 3725 } 3726 3727 static void verify_sme_features(void) 3728 { 3729 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3730 3731 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3732 pr_crit("CPU%d: SME: vector length support mismatch\n", 3733 smp_processor_id()); 3734 cpu_die_early(); 3735 } 3736 3737 cpacr_restore(cpacr); 3738 } 3739 3740 static void verify_hyp_capabilities(void) 3741 { 3742 u64 safe_mmfr1, mmfr0, mmfr1; 3743 int parange, ipa_max; 3744 unsigned int safe_vmid_bits, vmid_bits; 3745 3746 if (!IS_ENABLED(CONFIG_KVM)) 3747 return; 3748 3749 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3750 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3751 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3752 3753 /* Verify VMID bits */ 3754 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3755 vmid_bits = get_vmid_bits(mmfr1); 3756 if (vmid_bits < safe_vmid_bits) { 3757 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3758 cpu_die_early(); 3759 } 3760 3761 /* Verify IPA range */ 3762 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3763 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3764 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3765 if (ipa_max < get_kvm_ipa_limit()) { 3766 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3767 cpu_die_early(); 3768 } 3769 } 3770 3771 static void verify_mpam_capabilities(void) 3772 { 3773 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3774 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3775 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3776 3777 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3778 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3779 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3780 cpu_die_early(); 3781 } 3782 3783 cpu_idr = read_cpuid(MPAMIDR_EL1); 3784 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3785 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3786 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3787 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3788 cpu_die_early(); 3789 } 3790 3791 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3792 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3793 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3794 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3795 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3796 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3797 cpu_die_early(); 3798 } 3799 } 3800 3801 /* 3802 * Run through the enabled system capabilities and enable() it on this CPU. 3803 * The capabilities were decided based on the available CPUs at the boot time. 3804 * Any new CPU should match the system wide status of the capability. If the 3805 * new CPU doesn't have a capability which the system now has enabled, we 3806 * cannot do anything to fix it up and could cause unexpected failures. So 3807 * we park the CPU. 3808 */ 3809 static void verify_local_cpu_capabilities(void) 3810 { 3811 /* 3812 * The capabilities with SCOPE_BOOT_CPU are checked from 3813 * check_early_cpu_features(), as they need to be verified 3814 * on all secondary CPUs. 3815 */ 3816 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3817 verify_local_elf_hwcaps(); 3818 3819 if (system_supports_sve()) 3820 verify_sve_features(); 3821 3822 if (system_supports_sme()) 3823 verify_sme_features(); 3824 3825 if (is_hyp_mode_available()) 3826 verify_hyp_capabilities(); 3827 3828 if (system_supports_mpam()) 3829 verify_mpam_capabilities(); 3830 } 3831 3832 void check_local_cpu_capabilities(void) 3833 { 3834 /* 3835 * All secondary CPUs should conform to the early CPU features 3836 * in use by the kernel based on boot CPU. 3837 */ 3838 check_early_cpu_features(); 3839 3840 /* 3841 * If we haven't finalised the system capabilities, this CPU gets 3842 * a chance to update the errata work arounds and local features. 3843 * Otherwise, this CPU should verify that it has all the system 3844 * advertised capabilities. 3845 */ 3846 if (!system_capabilities_finalized()) 3847 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3848 else 3849 verify_local_cpu_capabilities(); 3850 } 3851 3852 bool this_cpu_has_cap(unsigned int n) 3853 { 3854 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3855 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3856 3857 if (cap) 3858 return cap->matches(cap, SCOPE_LOCAL_CPU); 3859 } 3860 3861 return false; 3862 } 3863 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3864 3865 /* 3866 * This helper function is used in a narrow window when, 3867 * - The system wide safe registers are set with all the SMP CPUs and, 3868 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3869 */ 3870 static bool __maybe_unused __system_matches_cap(unsigned int n) 3871 { 3872 if (n < ARM64_NCAPS) { 3873 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3874 3875 if (cap) 3876 return cap->matches(cap, SCOPE_SYSTEM); 3877 } 3878 return false; 3879 } 3880 3881 void cpu_set_feature(unsigned int num) 3882 { 3883 set_bit(num, elf_hwcap); 3884 } 3885 3886 bool cpu_have_feature(unsigned int num) 3887 { 3888 return test_bit(num, elf_hwcap); 3889 } 3890 EXPORT_SYMBOL_GPL(cpu_have_feature); 3891 3892 unsigned long cpu_get_elf_hwcap(void) 3893 { 3894 /* 3895 * We currently only populate the first 32 bits of AT_HWCAP. Please 3896 * note that for userspace compatibility we guarantee that bits 62 3897 * and 63 will always be returned as 0. 3898 */ 3899 return elf_hwcap[0]; 3900 } 3901 3902 unsigned long cpu_get_elf_hwcap2(void) 3903 { 3904 return elf_hwcap[1]; 3905 } 3906 3907 unsigned long cpu_get_elf_hwcap3(void) 3908 { 3909 return elf_hwcap[2]; 3910 } 3911 3912 static void __init setup_boot_cpu_capabilities(void) 3913 { 3914 kvm_arm_target_impl_cpu_init(); 3915 /* 3916 * The boot CPU's feature register values have been recorded. Detect 3917 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3918 * patch alternatives for the available boot cpucaps. 3919 */ 3920 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3921 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3922 apply_boot_alternatives(); 3923 } 3924 3925 void __init setup_boot_cpu_features(void) 3926 { 3927 /* 3928 * Initialize the indirect array of CPU capabilities pointers before we 3929 * handle the boot CPU. 3930 */ 3931 init_cpucap_indirect_list(); 3932 3933 /* 3934 * Detect broken pseudo-NMI. Must be called _before_ the call to 3935 * setup_boot_cpu_capabilities() since it interacts with 3936 * can_use_gic_priorities(). 3937 */ 3938 detect_system_supports_pseudo_nmi(); 3939 3940 setup_boot_cpu_capabilities(); 3941 } 3942 3943 static void __init setup_system_capabilities(void) 3944 { 3945 /* 3946 * The system-wide safe feature register values have been finalized. 3947 * Detect, enable, and patch alternatives for the available system 3948 * cpucaps. 3949 */ 3950 update_cpu_capabilities(SCOPE_SYSTEM); 3951 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3952 apply_alternatives_all(); 3953 3954 for (int i = 0; i < ARM64_NCAPS; i++) { 3955 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3956 3957 if (!caps || !caps->desc) 3958 continue; 3959 3960 /* 3961 * Log any cpucaps with a cpumask as these aren't logged by 3962 * update_cpu_capabilities(). 3963 */ 3964 if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids) 3965 pr_info("detected: %s on CPU%*pbl\n", 3966 caps->desc, cpumask_pr_args(caps->cpus)); 3967 3968 /* Log match-all CPUs capabilities */ 3969 if (cpucap_match_all_early_cpus(caps) && 3970 cpus_have_cap(caps->capability)) 3971 pr_info("detected: %s\n", caps->desc); 3972 } 3973 3974 /* 3975 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3976 */ 3977 if (system_uses_ttbr0_pan()) 3978 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3979 3980 /* 3981 * Report Spectre mitigations status. 3982 */ 3983 spectre_print_disabled_mitigations(); 3984 } 3985 3986 void __init setup_system_features(void) 3987 { 3988 setup_system_capabilities(); 3989 3990 linear_map_maybe_split_to_ptes(); 3991 kpti_install_ng_mappings(); 3992 3993 sve_setup(); 3994 sme_setup(); 3995 3996 /* 3997 * Check for sane CTR_EL0.CWG value. 3998 */ 3999 if (!cache_type_cwg()) 4000 pr_warn("No Cache Writeback Granule information, assuming %d\n", 4001 ARCH_DMA_MINALIGN); 4002 } 4003 4004 void __init setup_user_features(void) 4005 { 4006 user_feature_fixup(); 4007 4008 setup_elf_hwcaps(arm64_elf_hwcaps); 4009 4010 if (system_supports_32bit_el0()) { 4011 setup_elf_hwcaps(compat_elf_hwcaps); 4012 elf_hwcap_fixup(); 4013 } 4014 4015 minsigstksz_setup(); 4016 } 4017 4018 static int enable_mismatched_32bit_el0(unsigned int cpu) 4019 { 4020 /* 4021 * The first 32-bit-capable CPU we detected and so can no longer 4022 * be offlined by userspace. -1 indicates we haven't yet onlined 4023 * a 32-bit-capable CPU. 4024 */ 4025 static int lucky_winner = -1; 4026 4027 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 4028 bool cpu_32bit = false; 4029 4030 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 4031 if (!housekeeping_cpu(cpu, HK_TYPE_DOMAIN)) 4032 pr_info("Treating domain isolated CPU %u as 64-bit only\n", cpu); 4033 else 4034 cpu_32bit = true; 4035 } 4036 4037 if (cpu_32bit) { 4038 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 4039 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 4040 } 4041 4042 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 4043 return 0; 4044 4045 if (lucky_winner >= 0) 4046 return 0; 4047 4048 /* 4049 * We've detected a mismatch. We need to keep one of our CPUs with 4050 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 4051 * every CPU in the system for a 32-bit task. 4052 */ 4053 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 4054 cpu_active_mask); 4055 get_cpu_device(lucky_winner)->offline_disabled = true; 4056 setup_elf_hwcaps(compat_elf_hwcaps); 4057 elf_hwcap_fixup(); 4058 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 4059 cpu, lucky_winner); 4060 return 0; 4061 } 4062 4063 static int __init init_32bit_el0_mask(void) 4064 { 4065 if (!allow_mismatched_32bit_el0) 4066 return 0; 4067 4068 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 4069 return -ENOMEM; 4070 4071 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 4072 "arm64/mismatched_32bit_el0:online", 4073 enable_mismatched_32bit_el0, NULL); 4074 } 4075 subsys_initcall_sync(init_32bit_el0_mask); 4076 4077 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 4078 { 4079 cpu_enable_swapper_cnp(); 4080 } 4081 4082 /* 4083 * We emulate only the following system register space. 4084 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 4085 * See Table C5-6 System instruction encodings for System register accesses, 4086 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 4087 */ 4088 static inline bool __attribute_const__ is_emulated(u32 id) 4089 { 4090 return (sys_reg_Op0(id) == 0x3 && 4091 sys_reg_CRn(id) == 0x0 && 4092 sys_reg_Op1(id) == 0x0 && 4093 (sys_reg_CRm(id) == 0 || 4094 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 4095 } 4096 4097 /* 4098 * With CRm == 0, reg should be one of : 4099 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 4100 */ 4101 static inline int emulate_id_reg(u32 id, u64 *valp) 4102 { 4103 switch (id) { 4104 case SYS_MIDR_EL1: 4105 *valp = read_cpuid_id(); 4106 break; 4107 case SYS_MPIDR_EL1: 4108 *valp = SYS_MPIDR_SAFE_VAL; 4109 break; 4110 case SYS_REVIDR_EL1: 4111 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 4112 *valp = 0; 4113 break; 4114 default: 4115 return -EINVAL; 4116 } 4117 4118 return 0; 4119 } 4120 4121 static int emulate_sys_reg(u32 id, u64 *valp) 4122 { 4123 struct arm64_ftr_reg *regp; 4124 4125 if (!is_emulated(id)) 4126 return -EINVAL; 4127 4128 if (sys_reg_CRm(id) == 0) 4129 return emulate_id_reg(id, valp); 4130 4131 regp = get_arm64_ftr_reg_nowarn(id); 4132 if (regp) 4133 *valp = arm64_ftr_reg_user_value(regp); 4134 else 4135 /* 4136 * The untracked registers are either IMPLEMENTATION DEFINED 4137 * (e.g, ID_AFR0_EL1) or reserved RAZ. 4138 */ 4139 *valp = 0; 4140 return 0; 4141 } 4142 4143 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 4144 { 4145 int rc; 4146 u64 val; 4147 4148 rc = emulate_sys_reg(sys_reg, &val); 4149 if (!rc) { 4150 pt_regs_write_reg(regs, rt, val); 4151 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 4152 } 4153 return rc; 4154 } 4155 4156 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 4157 { 4158 u32 sys_reg, rt; 4159 4160 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 4161 return false; 4162 4163 /* 4164 * sys_reg values are defined as used in mrs/msr instruction. 4165 * shift the imm value to get the encoding. 4166 */ 4167 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 4168 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 4169 return do_emulate_mrs(regs, sys_reg, rt) == 0; 4170 } 4171 4172 enum mitigation_state arm64_get_meltdown_state(void) 4173 { 4174 if (__meltdown_safe) 4175 return SPECTRE_UNAFFECTED; 4176 4177 if (arm64_kernel_unmapped_at_el0()) 4178 return SPECTRE_MITIGATED; 4179 4180 return SPECTRE_VULNERABLE; 4181 } 4182 4183 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 4184 char *buf) 4185 { 4186 switch (arm64_get_meltdown_state()) { 4187 case SPECTRE_UNAFFECTED: 4188 return sprintf(buf, "Not affected\n"); 4189 4190 case SPECTRE_MITIGATED: 4191 return sprintf(buf, "Mitigation: PTI\n"); 4192 4193 default: 4194 return sprintf(buf, "Vulnerable\n"); 4195 } 4196 } 4197