1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/cpu.h> 81 #include <asm/cpufeature.h> 82 #include <asm/cpu_ops.h> 83 #include <asm/fpsimd.h> 84 #include <asm/hwcap.h> 85 #include <asm/insn.h> 86 #include <asm/kvm_host.h> 87 #include <asm/mmu.h> 88 #include <asm/mmu_context.h> 89 #include <asm/mte.h> 90 #include <asm/hypervisor.h> 91 #include <asm/processor.h> 92 #include <asm/smp.h> 93 #include <asm/sysreg.h> 94 #include <asm/traps.h> 95 #include <asm/vectors.h> 96 #include <asm/virt.h> 97 98 #include <asm/spectre.h> 99 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 100 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 101 102 #ifdef CONFIG_COMPAT 103 #define COMPAT_ELF_HWCAP_DEFAULT \ 104 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 105 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 106 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 107 COMPAT_HWCAP_LPAE) 108 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 109 unsigned int compat_elf_hwcap2 __read_mostly; 110 unsigned int compat_elf_hwcap3 __read_mostly; 111 #endif 112 113 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 114 EXPORT_SYMBOL(system_cpucaps); 115 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 116 117 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 118 119 /* 120 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 121 * ends up in the .bss section where it is initialized in early_map_kernel() 122 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 123 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 124 * may end up generating an incorrect idmap page table attributes. 125 */ 126 bool arm64_use_ng_mappings __read_mostly = false; 127 EXPORT_SYMBOL(arm64_use_ng_mappings); 128 129 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 130 131 /* 132 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 133 * support it? 134 */ 135 static bool __read_mostly allow_mismatched_32bit_el0; 136 137 /* 138 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 139 * seen at least one CPU capable of 32-bit EL0. 140 */ 141 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 142 143 /* 144 * Mask of CPUs supporting 32-bit EL0. 145 * Only valid if arm64_mismatched_32bit_el0 is enabled. 146 */ 147 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 148 149 void dump_cpu_features(void) 150 { 151 /* file-wide pr_fmt adds "CPU features: " prefix */ 152 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 153 } 154 155 #define __ARM64_MAX_POSITIVE(reg, field) \ 156 ((reg##_##field##_SIGNED ? \ 157 BIT(reg##_##field##_WIDTH - 1) : \ 158 BIT(reg##_##field##_WIDTH)) - 1) 159 160 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 161 162 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 163 .sys_reg = SYS_##reg, \ 164 .field_pos = reg##_##field##_SHIFT, \ 165 .field_width = reg##_##field##_WIDTH, \ 166 .sign = reg##_##field##_SIGNED, \ 167 .min_field_value = min_value, \ 168 .max_field_value = max_value, 169 170 /* 171 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 172 * an implicit maximum that depends on the sign-ess of the field. 173 * 174 * An unsigned field will be capped at all ones, while a signed field 175 * will be limited to the positive half only. 176 */ 177 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 178 __ARM64_CPUID_FIELDS(reg, field, \ 179 SYS_FIELD_VALUE(reg, field, min_value), \ 180 __ARM64_MAX_POSITIVE(reg, field)) 181 182 /* 183 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 184 * implicit minimal value to max_value. This should be used when 185 * matching a non-implemented property. 186 */ 187 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 188 __ARM64_CPUID_FIELDS(reg, field, \ 189 __ARM64_MIN_NEGATIVE(reg, field), \ 190 SYS_FIELD_VALUE(reg, field, max_value)) 191 192 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 193 { \ 194 .sign = SIGNED, \ 195 .visible = VISIBLE, \ 196 .strict = STRICT, \ 197 .type = TYPE, \ 198 .shift = SHIFT, \ 199 .width = WIDTH, \ 200 .safe_val = SAFE_VAL, \ 201 } 202 203 /* Define a feature with unsigned values */ 204 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 205 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 206 207 /* Define a feature with a signed value */ 208 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 209 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 210 211 #define ARM64_FTR_END \ 212 { \ 213 .width = 0, \ 214 } 215 216 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 217 218 static bool __system_matches_cap(unsigned int n); 219 220 /* 221 * NOTE: Any changes to the visibility of features should be kept in 222 * sync with the documentation of the CPU feature register ABI. 223 */ 224 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 239 ARM64_FTR_END, 240 }; 241 242 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LS64_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 252 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 254 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 256 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 259 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 261 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 263 ARM64_FTR_END, 264 }; 265 266 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 267 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 274 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 276 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 278 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 279 ARM64_FTR_END, 280 }; 281 282 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 283 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 284 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 286 ARM64_FTR_END, 287 }; 288 289 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 292 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 297 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 300 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 301 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 306 ARM64_FTR_END, 307 }; 308 309 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_DF2_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 312 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 313 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 314 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 315 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 318 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 319 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 320 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 321 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 322 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 323 ARM64_FTR_END, 324 }; 325 326 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 327 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 329 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), 330 ARM64_FTR_END, 331 }; 332 333 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 334 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 335 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 336 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 337 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 338 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 339 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 341 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 342 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 343 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 345 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 346 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 347 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 349 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 350 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 351 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 353 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 354 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 355 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 356 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 357 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 358 ARM64_FTR_END, 359 }; 360 361 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 362 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 363 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 364 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 365 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 366 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 367 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 369 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 371 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 372 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 373 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 375 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 376 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 377 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 378 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 379 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 380 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 381 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 382 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 383 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 384 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 385 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 386 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 387 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 388 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 389 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 390 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 391 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 392 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 393 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 394 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 395 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 396 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 397 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 398 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 399 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 400 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 401 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 402 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 403 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 404 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 405 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 406 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 407 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 408 ARM64_FTR_END, 409 }; 410 411 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 413 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 414 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 415 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 416 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 417 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 418 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 419 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 420 ARM64_FTR_END, 421 }; 422 423 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 424 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 427 /* 428 * Page size not being supported at Stage-2 is not fatal. You 429 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 430 * your favourite nesting hypervisor. 431 * 432 * There is a small corner case where the hypervisor explicitly 433 * advertises a given granule size at Stage-2 (value 2) on some 434 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 435 * vCPUs. Although this is not forbidden by the architecture, it 436 * indicates that the hypervisor is being silly (or buggy). 437 * 438 * We make no effort to cope with this and pretend that if these 439 * fields are inconsistent across vCPUs, then it isn't worth 440 * trying to bring KVM up. 441 */ 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 445 /* 446 * We already refuse to boot CPUs that don't support our configured 447 * page size, so we can only detect mismatches for a page size other 448 * than the one we're currently using. Unfortunately, SoCs like this 449 * exist in the wild so, even though we don't like it, we'll have to go 450 * along with it and treat them as non-strict. 451 */ 452 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 453 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 455 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 457 /* Linux shouldn't care about secure memory */ 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 461 /* 462 * Differing PARange is fine as long as all peripherals and memory are mapped 463 * within the minimum PARange of all CPUs 464 */ 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 466 ARM64_FTR_END, 467 }; 468 469 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 484 ARM64_FTR_END, 485 }; 486 487 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 503 ARM64_FTR_END, 504 }; 505 506 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 507 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 508 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_SCTLRX_SHIFT, 4, 0), 511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 512 ARM64_FTR_END, 513 }; 514 515 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 516 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 518 ARM64_FTR_END, 519 }; 520 521 static const struct arm64_ftr_bits ftr_ctr[] = { 522 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 523 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 524 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 525 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 526 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 528 /* 529 * Linux can handle differing I-cache policies. Userspace JITs will 530 * make use of *minLine. 531 * If we have differing I-cache policies, report it as the weakest - VIPT. 532 */ 533 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 534 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 535 ARM64_FTR_END, 536 }; 537 538 static struct arm64_ftr_override __ro_after_init no_override = { }; 539 540 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 541 .name = "SYS_CTR_EL0", 542 .ftr_bits = ftr_ctr, 543 .override = &no_override, 544 }; 545 546 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 547 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 552 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 555 ARM64_FTR_END, 556 }; 557 558 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 559 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 563 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 564 /* 565 * We can instantiate multiple PMU instances with different levels 566 * of support. 567 */ 568 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 570 ARM64_FTR_END, 571 }; 572 573 static const struct arm64_ftr_bits ftr_mvfr0[] = { 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 578 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 579 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 581 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 582 ARM64_FTR_END, 583 }; 584 585 static const struct arm64_ftr_bits ftr_mvfr1[] = { 586 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 589 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 590 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 591 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 592 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 593 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 594 ARM64_FTR_END, 595 }; 596 597 static const struct arm64_ftr_bits ftr_mvfr2[] = { 598 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 599 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 600 ARM64_FTR_END, 601 }; 602 603 static const struct arm64_ftr_bits ftr_dczid[] = { 604 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 605 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 606 ARM64_FTR_END, 607 }; 608 609 static const struct arm64_ftr_bits ftr_gmid[] = { 610 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 611 ARM64_FTR_END, 612 }; 613 614 static const struct arm64_ftr_bits ftr_id_isar0[] = { 615 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 616 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 617 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 621 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 622 ARM64_FTR_END, 623 }; 624 625 static const struct arm64_ftr_bits ftr_id_isar5[] = { 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 627 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 628 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 629 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 630 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 631 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 632 ARM64_FTR_END, 633 }; 634 635 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 640 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 641 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 642 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 643 644 /* 645 * SpecSEI = 1 indicates that the PE might generate an SError on an 646 * external abort on speculative read. It is safe to assume that an 647 * SError might be generated than it will not be. Hence it has been 648 * classified as FTR_HIGHER_SAFE. 649 */ 650 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 651 ARM64_FTR_END, 652 }; 653 654 static const struct arm64_ftr_bits ftr_id_isar4[] = { 655 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 656 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 657 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 659 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 660 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 661 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 662 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 663 ARM64_FTR_END, 664 }; 665 666 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 667 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 668 ARM64_FTR_END, 669 }; 670 671 static const struct arm64_ftr_bits ftr_id_isar6[] = { 672 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 673 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 674 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 675 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 676 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 677 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 679 ARM64_FTR_END, 680 }; 681 682 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 683 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 684 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 685 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 686 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 687 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 688 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 689 ARM64_FTR_END, 690 }; 691 692 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 696 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 697 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 698 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 699 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 700 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 701 ARM64_FTR_END, 702 }; 703 704 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 705 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 706 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 707 ARM64_FTR_END, 708 }; 709 710 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 711 /* [31:28] TraceFilt */ 712 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 713 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 714 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 715 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 716 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 717 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 718 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 719 ARM64_FTR_END, 720 }; 721 722 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 723 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 724 ARM64_FTR_END, 725 }; 726 727 static const struct arm64_ftr_bits ftr_mpamidr[] = { 728 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 729 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 730 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 731 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 732 ARM64_FTR_END, 733 }; 734 735 /* 736 * Common ftr bits for a 32bit register with all hidden, strict 737 * attributes, with 4bit feature fields and a default safe value of 738 * 0. Covers the following 32bit registers: 739 * id_isar[1-3], id_mmfr[1-3] 740 */ 741 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 742 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 743 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 744 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 745 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 746 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 747 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 748 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 749 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 750 ARM64_FTR_END, 751 }; 752 753 /* Table for a single 32bit feature value */ 754 static const struct arm64_ftr_bits ftr_single32[] = { 755 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 756 ARM64_FTR_END, 757 }; 758 759 static const struct arm64_ftr_bits ftr_raz[] = { 760 ARM64_FTR_END, 761 }; 762 763 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 764 .sys_id = id, \ 765 .reg = &(struct arm64_ftr_reg){ \ 766 .name = id_str, \ 767 .override = (ovr), \ 768 .ftr_bits = &((table)[0]), \ 769 }} 770 771 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 772 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 773 774 #define ARM64_FTR_REG(id, table) \ 775 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 776 777 struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 778 struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 779 struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 780 struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 781 struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 782 struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 783 struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 784 struct arm64_ftr_override __read_mostly id_aa64isar1_override; 785 struct arm64_ftr_override __read_mostly id_aa64isar2_override; 786 787 struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 788 789 static const struct __ftr_reg_entry { 790 u32 sys_id; 791 struct arm64_ftr_reg *reg; 792 } arm64_ftr_regs[] = { 793 794 /* Op1 = 0, CRn = 0, CRm = 1 */ 795 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 796 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 797 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 798 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 799 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 800 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 801 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 802 803 /* Op1 = 0, CRn = 0, CRm = 2 */ 804 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 805 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 806 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 807 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 808 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 809 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 810 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 811 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 812 813 /* Op1 = 0, CRn = 0, CRm = 3 */ 814 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 815 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 816 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 817 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 818 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 819 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 820 821 /* Op1 = 0, CRn = 0, CRm = 4 */ 822 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 823 &id_aa64pfr0_override), 824 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 825 &id_aa64pfr1_override), 826 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 827 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 828 &id_aa64zfr0_override), 829 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 830 &id_aa64smfr0_override), 831 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 832 833 /* Op1 = 0, CRn = 0, CRm = 5 */ 834 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 835 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 836 837 /* Op1 = 0, CRn = 0, CRm = 6 */ 838 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 839 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 840 &id_aa64isar1_override), 841 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 842 &id_aa64isar2_override), 843 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 844 845 /* Op1 = 0, CRn = 0, CRm = 7 */ 846 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 847 &id_aa64mmfr0_override), 848 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 849 &id_aa64mmfr1_override), 850 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 851 &id_aa64mmfr2_override), 852 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 853 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 854 855 /* Op1 = 0, CRn = 10, CRm = 4 */ 856 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 857 858 /* Op1 = 1, CRn = 0, CRm = 0 */ 859 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 860 861 /* Op1 = 3, CRn = 0, CRm = 0 */ 862 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 863 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 864 865 /* Op1 = 3, CRn = 14, CRm = 0 */ 866 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 867 }; 868 869 static int search_cmp_ftr_reg(const void *id, const void *regp) 870 { 871 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 872 } 873 874 /* 875 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 876 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 877 * ascending order of sys_id, we use binary search to find a matching 878 * entry. 879 * 880 * returns - Upon success, matching ftr_reg entry for id. 881 * - NULL on failure. It is upto the caller to decide 882 * the impact of a failure. 883 */ 884 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 885 { 886 const struct __ftr_reg_entry *ret; 887 888 ret = bsearch((const void *)(unsigned long)sys_id, 889 arm64_ftr_regs, 890 ARRAY_SIZE(arm64_ftr_regs), 891 sizeof(arm64_ftr_regs[0]), 892 search_cmp_ftr_reg); 893 if (ret) 894 return ret->reg; 895 return NULL; 896 } 897 898 /* 899 * get_arm64_ftr_reg - Looks up a feature register entry using 900 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 901 * 902 * returns - Upon success, matching ftr_reg entry for id. 903 * - NULL on failure but with an WARN_ON(). 904 */ 905 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 906 { 907 struct arm64_ftr_reg *reg; 908 909 reg = get_arm64_ftr_reg_nowarn(sys_id); 910 911 /* 912 * Requesting a non-existent register search is an error. Warn 913 * and let the caller handle it. 914 */ 915 WARN_ON(!reg); 916 return reg; 917 } 918 919 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 920 s64 ftr_val) 921 { 922 u64 mask = arm64_ftr_mask(ftrp); 923 924 reg &= ~mask; 925 reg |= (ftr_val << ftrp->shift) & mask; 926 return reg; 927 } 928 929 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 930 s64 cur) 931 { 932 s64 ret = 0; 933 934 switch (ftrp->type) { 935 case FTR_EXACT: 936 ret = ftrp->safe_val; 937 break; 938 case FTR_LOWER_SAFE: 939 ret = min(new, cur); 940 break; 941 case FTR_HIGHER_OR_ZERO_SAFE: 942 if (!cur || !new) 943 break; 944 fallthrough; 945 case FTR_HIGHER_SAFE: 946 ret = max(new, cur); 947 break; 948 default: 949 BUG(); 950 } 951 952 return ret; 953 } 954 955 static void __init sort_ftr_regs(void) 956 { 957 unsigned int i; 958 959 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 960 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 961 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 962 unsigned int j = 0; 963 964 /* 965 * Features here must be sorted in descending order with respect 966 * to their shift values and should not overlap with each other. 967 */ 968 for (; ftr_bits->width != 0; ftr_bits++, j++) { 969 unsigned int width = ftr_reg->ftr_bits[j].width; 970 unsigned int shift = ftr_reg->ftr_bits[j].shift; 971 unsigned int prev_shift; 972 973 WARN((shift + width) > 64, 974 "%s has invalid feature at shift %d\n", 975 ftr_reg->name, shift); 976 977 /* 978 * Skip the first feature. There is nothing to 979 * compare against for now. 980 */ 981 if (j == 0) 982 continue; 983 984 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 985 WARN((shift + width) > prev_shift, 986 "%s has feature overlap at shift %d\n", 987 ftr_reg->name, shift); 988 } 989 990 /* 991 * Skip the first register. There is nothing to 992 * compare against for now. 993 */ 994 if (i == 0) 995 continue; 996 /* 997 * Registers here must be sorted in ascending order with respect 998 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 999 * to work correctly. 1000 */ 1001 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 1002 } 1003 } 1004 1005 /* 1006 * Initialise the CPU feature register from Boot CPU values. 1007 * Also initialises the strict_mask for the register. 1008 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1009 * RES0 for the system-wide value, and must strictly match. 1010 */ 1011 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1012 { 1013 u64 val = 0; 1014 u64 strict_mask = ~0x0ULL; 1015 u64 user_mask = 0; 1016 u64 valid_mask = 0; 1017 1018 const struct arm64_ftr_bits *ftrp; 1019 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1020 1021 if (!reg) 1022 return; 1023 1024 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1025 u64 ftr_mask = arm64_ftr_mask(ftrp); 1026 s64 ftr_new = arm64_ftr_value(ftrp, new); 1027 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1028 1029 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1030 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1031 char *str = NULL; 1032 1033 if (ftr_ovr != tmp) { 1034 /* Unsafe, remove the override */ 1035 reg->override->mask &= ~ftr_mask; 1036 reg->override->val &= ~ftr_mask; 1037 tmp = ftr_ovr; 1038 str = "ignoring override"; 1039 } else if (ftr_new != tmp) { 1040 /* Override was valid */ 1041 ftr_new = tmp; 1042 str = "forced"; 1043 } else { 1044 /* Override was the safe value */ 1045 str = "already set"; 1046 } 1047 1048 pr_warn("%s[%d:%d]: %s to %llx\n", 1049 reg->name, 1050 ftrp->shift + ftrp->width - 1, 1051 ftrp->shift, str, 1052 tmp & (BIT(ftrp->width) - 1)); 1053 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1054 reg->override->val &= ~ftr_mask; 1055 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1056 reg->name, 1057 ftrp->shift + ftrp->width - 1, 1058 ftrp->shift); 1059 } 1060 1061 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1062 1063 valid_mask |= ftr_mask; 1064 if (!ftrp->strict) 1065 strict_mask &= ~ftr_mask; 1066 if (ftrp->visible) 1067 user_mask |= ftr_mask; 1068 else 1069 reg->user_val = arm64_ftr_set_value(ftrp, 1070 reg->user_val, 1071 ftrp->safe_val); 1072 } 1073 1074 val &= valid_mask; 1075 1076 reg->sys_val = val; 1077 reg->strict_mask = strict_mask; 1078 reg->user_mask = user_mask; 1079 } 1080 1081 extern const struct arm64_cpu_capabilities arm64_errata[]; 1082 static const struct arm64_cpu_capabilities arm64_features[]; 1083 1084 static void __init 1085 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1086 { 1087 for (; caps->matches; caps++) { 1088 if (WARN(caps->capability >= ARM64_NCAPS, 1089 "Invalid capability %d\n", caps->capability)) 1090 continue; 1091 if (WARN(cpucap_ptrs[caps->capability], 1092 "Duplicate entry for capability %d\n", 1093 caps->capability)) 1094 continue; 1095 cpucap_ptrs[caps->capability] = caps; 1096 } 1097 } 1098 1099 static void __init init_cpucap_indirect_list(void) 1100 { 1101 init_cpucap_indirect_list_from_array(arm64_features); 1102 init_cpucap_indirect_list_from_array(arm64_errata); 1103 } 1104 1105 static void __init setup_boot_cpu_capabilities(void); 1106 1107 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1108 { 1109 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1110 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1111 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1112 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1113 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1114 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1115 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1116 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1117 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1118 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1119 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1120 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1121 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1122 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1123 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1124 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1125 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1126 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1127 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1128 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1129 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1130 } 1131 1132 #ifdef CONFIG_ARM64_PSEUDO_NMI 1133 static bool enable_pseudo_nmi; 1134 1135 static int __init early_enable_pseudo_nmi(char *p) 1136 { 1137 return kstrtobool(p, &enable_pseudo_nmi); 1138 } 1139 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1140 1141 static __init void detect_system_supports_pseudo_nmi(void) 1142 { 1143 struct device_node *np; 1144 1145 if (!enable_pseudo_nmi) 1146 return; 1147 1148 /* 1149 * Detect broken MediaTek firmware that doesn't properly save and 1150 * restore GIC priorities. 1151 */ 1152 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1153 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1154 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1155 enable_pseudo_nmi = false; 1156 } 1157 of_node_put(np); 1158 } 1159 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1160 static inline void detect_system_supports_pseudo_nmi(void) { } 1161 #endif 1162 1163 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1164 { 1165 /* Before we start using the tables, make sure it is sorted */ 1166 sort_ftr_regs(); 1167 1168 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1169 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1170 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1171 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1172 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1173 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1174 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1175 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1176 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1177 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1178 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1179 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1180 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1181 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1182 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1183 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1184 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1185 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1186 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1187 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1188 1189 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1190 init_32bit_cpu_features(&info->aarch32); 1191 1192 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1193 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1194 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1195 1196 vec_init_vq_map(ARM64_VEC_SVE); 1197 1198 cpacr_restore(cpacr); 1199 } 1200 1201 if (IS_ENABLED(CONFIG_ARM64_SME) && 1202 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1203 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1204 1205 vec_init_vq_map(ARM64_VEC_SME); 1206 1207 cpacr_restore(cpacr); 1208 } 1209 1210 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1211 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1212 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1213 } 1214 1215 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1216 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1217 } 1218 1219 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1220 { 1221 const struct arm64_ftr_bits *ftrp; 1222 1223 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1224 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1225 s64 ftr_new = arm64_ftr_value(ftrp, new); 1226 1227 if (ftr_cur == ftr_new) 1228 continue; 1229 /* Find a safe value */ 1230 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1231 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1232 } 1233 1234 } 1235 1236 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1237 { 1238 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1239 1240 if (!regp) 1241 return 0; 1242 1243 update_cpu_ftr_reg(regp, val); 1244 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1245 return 0; 1246 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1247 regp->name, boot, cpu, val); 1248 return 1; 1249 } 1250 1251 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1252 { 1253 const struct arm64_ftr_bits *ftrp; 1254 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1255 1256 if (!regp) 1257 return; 1258 1259 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1260 if (ftrp->shift == field) { 1261 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1262 break; 1263 } 1264 } 1265 1266 /* Bogus field? */ 1267 WARN_ON(!ftrp->width); 1268 } 1269 1270 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1271 struct cpuinfo_arm64 *boot) 1272 { 1273 static bool boot_cpu_32bit_regs_overridden = false; 1274 1275 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1276 return; 1277 1278 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1279 return; 1280 1281 boot->aarch32 = info->aarch32; 1282 init_32bit_cpu_features(&boot->aarch32); 1283 boot_cpu_32bit_regs_overridden = true; 1284 } 1285 1286 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1287 struct cpuinfo_32bit *boot) 1288 { 1289 int taint = 0; 1290 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1291 1292 /* 1293 * If we don't have AArch32 at EL1, then relax the strictness of 1294 * EL1-dependent register fields to avoid spurious sanity check fails. 1295 */ 1296 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1297 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1298 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1299 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1300 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1301 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1302 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1303 } 1304 1305 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1306 info->reg_id_dfr0, boot->reg_id_dfr0); 1307 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1308 info->reg_id_dfr1, boot->reg_id_dfr1); 1309 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1310 info->reg_id_isar0, boot->reg_id_isar0); 1311 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1312 info->reg_id_isar1, boot->reg_id_isar1); 1313 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1314 info->reg_id_isar2, boot->reg_id_isar2); 1315 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1316 info->reg_id_isar3, boot->reg_id_isar3); 1317 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1318 info->reg_id_isar4, boot->reg_id_isar4); 1319 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1320 info->reg_id_isar5, boot->reg_id_isar5); 1321 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1322 info->reg_id_isar6, boot->reg_id_isar6); 1323 1324 /* 1325 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1326 * ACTLR formats could differ across CPUs and therefore would have to 1327 * be trapped for virtualization anyway. 1328 */ 1329 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1330 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1331 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1332 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1333 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1334 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1335 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1336 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1337 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1338 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1339 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1340 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1341 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1342 info->reg_id_pfr0, boot->reg_id_pfr0); 1343 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1344 info->reg_id_pfr1, boot->reg_id_pfr1); 1345 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1346 info->reg_id_pfr2, boot->reg_id_pfr2); 1347 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1348 info->reg_mvfr0, boot->reg_mvfr0); 1349 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1350 info->reg_mvfr1, boot->reg_mvfr1); 1351 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1352 info->reg_mvfr2, boot->reg_mvfr2); 1353 1354 return taint; 1355 } 1356 1357 /* 1358 * Update system wide CPU feature registers with the values from a 1359 * non-boot CPU. Also performs SANITY checks to make sure that there 1360 * aren't any insane variations from that of the boot CPU. 1361 */ 1362 void update_cpu_features(int cpu, 1363 struct cpuinfo_arm64 *info, 1364 struct cpuinfo_arm64 *boot) 1365 { 1366 int taint = 0; 1367 1368 /* 1369 * The kernel can handle differing I-cache policies, but otherwise 1370 * caches should look identical. Userspace JITs will make use of 1371 * *minLine. 1372 */ 1373 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1374 info->reg_ctr, boot->reg_ctr); 1375 1376 /* 1377 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1378 * could result in too much or too little memory being zeroed if a 1379 * process is preempted and migrated between CPUs. 1380 */ 1381 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1382 info->reg_dczid, boot->reg_dczid); 1383 1384 /* If different, timekeeping will be broken (especially with KVM) */ 1385 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1386 info->reg_cntfrq, boot->reg_cntfrq); 1387 1388 /* 1389 * The kernel uses self-hosted debug features and expects CPUs to 1390 * support identical debug features. We presently need CTX_CMPs, WRPs, 1391 * and BRPs to be identical. 1392 * ID_AA64DFR1 is currently RES0. 1393 */ 1394 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1395 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1396 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1397 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1398 /* 1399 * Even in big.LITTLE, processors should be identical instruction-set 1400 * wise. 1401 */ 1402 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1403 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1404 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1405 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1406 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1407 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1408 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1409 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1410 1411 /* 1412 * Differing PARange support is fine as long as all peripherals and 1413 * memory are mapped within the minimum PARange of all CPUs. 1414 * Linux should not care about secure memory. 1415 */ 1416 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1417 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1418 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1419 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1420 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1421 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1422 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1423 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1424 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 1425 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 1426 1427 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1428 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1429 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1430 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1431 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1432 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1433 1434 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1435 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1436 1437 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1438 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1439 1440 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1441 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1442 1443 /* Probe vector lengths */ 1444 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1445 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1446 if (!system_capabilities_finalized()) { 1447 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1448 1449 vec_update_vq_map(ARM64_VEC_SVE); 1450 1451 cpacr_restore(cpacr); 1452 } 1453 } 1454 1455 if (IS_ENABLED(CONFIG_ARM64_SME) && 1456 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1457 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1458 1459 /* Probe vector lengths */ 1460 if (!system_capabilities_finalized()) 1461 vec_update_vq_map(ARM64_VEC_SME); 1462 1463 cpacr_restore(cpacr); 1464 } 1465 1466 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1467 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1468 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1469 info->reg_mpamidr, boot->reg_mpamidr); 1470 } 1471 1472 /* 1473 * The kernel uses the LDGM/STGM instructions and the number of tags 1474 * they read/write depends on the GMID_EL1.BS field. Check that the 1475 * value is the same on all CPUs. 1476 */ 1477 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1478 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1479 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1480 info->reg_gmid, boot->reg_gmid); 1481 } 1482 1483 /* 1484 * If we don't have AArch32 at all then skip the checks entirely 1485 * as the register values may be UNKNOWN and we're not going to be 1486 * using them for anything. 1487 * 1488 * This relies on a sanitised view of the AArch64 ID registers 1489 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1490 */ 1491 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1492 lazy_init_32bit_cpu_features(info, boot); 1493 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1494 &boot->aarch32); 1495 } 1496 1497 /* 1498 * Mismatched CPU features are a recipe for disaster. Don't even 1499 * pretend to support them. 1500 */ 1501 if (taint) { 1502 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1503 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1504 } 1505 } 1506 1507 u64 read_sanitised_ftr_reg(u32 id) 1508 { 1509 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1510 1511 if (!regp) 1512 return 0; 1513 return regp->sys_val; 1514 } 1515 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1516 1517 #define read_sysreg_case(r) \ 1518 case r: val = read_sysreg_s(r); break; 1519 1520 /* 1521 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1522 * Read the system register on the current CPU 1523 */ 1524 u64 __read_sysreg_by_encoding(u32 sys_id) 1525 { 1526 struct arm64_ftr_reg *regp; 1527 u64 val; 1528 1529 switch (sys_id) { 1530 read_sysreg_case(SYS_ID_PFR0_EL1); 1531 read_sysreg_case(SYS_ID_PFR1_EL1); 1532 read_sysreg_case(SYS_ID_PFR2_EL1); 1533 read_sysreg_case(SYS_ID_DFR0_EL1); 1534 read_sysreg_case(SYS_ID_DFR1_EL1); 1535 read_sysreg_case(SYS_ID_MMFR0_EL1); 1536 read_sysreg_case(SYS_ID_MMFR1_EL1); 1537 read_sysreg_case(SYS_ID_MMFR2_EL1); 1538 read_sysreg_case(SYS_ID_MMFR3_EL1); 1539 read_sysreg_case(SYS_ID_MMFR4_EL1); 1540 read_sysreg_case(SYS_ID_MMFR5_EL1); 1541 read_sysreg_case(SYS_ID_ISAR0_EL1); 1542 read_sysreg_case(SYS_ID_ISAR1_EL1); 1543 read_sysreg_case(SYS_ID_ISAR2_EL1); 1544 read_sysreg_case(SYS_ID_ISAR3_EL1); 1545 read_sysreg_case(SYS_ID_ISAR4_EL1); 1546 read_sysreg_case(SYS_ID_ISAR5_EL1); 1547 read_sysreg_case(SYS_ID_ISAR6_EL1); 1548 read_sysreg_case(SYS_MVFR0_EL1); 1549 read_sysreg_case(SYS_MVFR1_EL1); 1550 read_sysreg_case(SYS_MVFR2_EL1); 1551 1552 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1553 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1554 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1555 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1556 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1557 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1558 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1559 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1560 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1561 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1562 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1563 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1564 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1565 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1566 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1567 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1568 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1569 1570 read_sysreg_case(SYS_CNTFRQ_EL0); 1571 read_sysreg_case(SYS_CTR_EL0); 1572 read_sysreg_case(SYS_DCZID_EL0); 1573 1574 default: 1575 BUG(); 1576 return 0; 1577 } 1578 1579 regp = get_arm64_ftr_reg(sys_id); 1580 if (regp) { 1581 val &= ~regp->override->mask; 1582 val |= (regp->override->val & regp->override->mask); 1583 } 1584 1585 return val; 1586 } 1587 1588 #include <linux/irqchip/arm-gic-v3.h> 1589 1590 static bool 1591 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1592 { 1593 return true; 1594 } 1595 1596 static bool 1597 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1598 { 1599 int val, min, max; 1600 u64 tmp; 1601 1602 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1603 entry->field_width, 1604 entry->sign); 1605 1606 tmp = entry->min_field_value; 1607 tmp <<= entry->field_pos; 1608 1609 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1610 entry->field_width, 1611 entry->sign); 1612 1613 tmp = entry->max_field_value; 1614 tmp <<= entry->field_pos; 1615 1616 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1617 entry->field_width, 1618 entry->sign); 1619 1620 return val >= min && val <= max; 1621 } 1622 1623 static u64 1624 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1625 { 1626 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1627 if (scope == SCOPE_SYSTEM) 1628 return read_sanitised_ftr_reg(entry->sys_reg); 1629 else 1630 return __read_sysreg_by_encoding(entry->sys_reg); 1631 } 1632 1633 static bool 1634 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1635 { 1636 int mask; 1637 struct arm64_ftr_reg *regp; 1638 u64 val = read_scoped_sysreg(entry, scope); 1639 1640 regp = get_arm64_ftr_reg(entry->sys_reg); 1641 if (!regp) 1642 return false; 1643 1644 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1645 entry->field_pos, 1646 entry->field_width); 1647 if (!mask) 1648 return false; 1649 1650 return feature_matches(val, entry); 1651 } 1652 1653 static bool 1654 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1655 { 1656 u64 val = read_scoped_sysreg(entry, scope); 1657 return feature_matches(val, entry); 1658 } 1659 1660 const struct cpumask *system_32bit_el0_cpumask(void) 1661 { 1662 if (!system_supports_32bit_el0()) 1663 return cpu_none_mask; 1664 1665 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1666 return cpu_32bit_el0_mask; 1667 1668 return cpu_possible_mask; 1669 } 1670 1671 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1672 { 1673 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_DOMAIN)); 1674 } 1675 1676 static int __init parse_32bit_el0_param(char *str) 1677 { 1678 allow_mismatched_32bit_el0 = true; 1679 return 0; 1680 } 1681 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1682 1683 static ssize_t aarch32_el0_show(struct device *dev, 1684 struct device_attribute *attr, char *buf) 1685 { 1686 const struct cpumask *mask = system_32bit_el0_cpumask(); 1687 1688 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1689 } 1690 static const DEVICE_ATTR_RO(aarch32_el0); 1691 1692 static int __init aarch32_el0_sysfs_init(void) 1693 { 1694 struct device *dev_root; 1695 int ret = 0; 1696 1697 if (!allow_mismatched_32bit_el0) 1698 return 0; 1699 1700 dev_root = bus_get_dev_root(&cpu_subsys); 1701 if (dev_root) { 1702 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1703 put_device(dev_root); 1704 } 1705 return ret; 1706 } 1707 device_initcall(aarch32_el0_sysfs_init); 1708 1709 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1710 { 1711 if (!has_cpuid_feature(entry, scope)) 1712 return allow_mismatched_32bit_el0; 1713 1714 if (scope == SCOPE_SYSTEM) 1715 pr_info("detected: 32-bit EL0 Support\n"); 1716 1717 return true; 1718 } 1719 1720 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1721 { 1722 bool has_sre; 1723 1724 if (!has_cpuid_feature(entry, scope)) 1725 return false; 1726 1727 has_sre = gic_enable_sre(); 1728 if (!has_sre) 1729 pr_warn_once("%s present but disabled by higher exception level\n", 1730 entry->desc); 1731 1732 return has_sre; 1733 } 1734 1735 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1736 int scope) 1737 { 1738 u64 ctr; 1739 1740 if (scope == SCOPE_SYSTEM) 1741 ctr = arm64_ftr_reg_ctrel0.sys_val; 1742 else 1743 ctr = read_cpuid_effective_cachetype(); 1744 1745 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1746 } 1747 1748 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1749 { 1750 /* 1751 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1752 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1753 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1754 * value. 1755 */ 1756 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1757 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1758 } 1759 1760 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1761 int scope) 1762 { 1763 u64 ctr; 1764 1765 if (scope == SCOPE_SYSTEM) 1766 ctr = arm64_ftr_reg_ctrel0.sys_val; 1767 else 1768 ctr = read_cpuid_cachetype(); 1769 1770 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1771 } 1772 1773 static bool __maybe_unused 1774 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1775 { 1776 /* 1777 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1778 * may share TLB entries with a CPU stuck in the crashed 1779 * kernel. 1780 */ 1781 if (is_kdump_kernel()) 1782 return false; 1783 1784 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1785 return false; 1786 1787 return has_cpuid_feature(entry, scope); 1788 } 1789 1790 static bool __meltdown_safe = true; 1791 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1792 1793 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1794 int scope) 1795 { 1796 /* List of CPUs that are not vulnerable and don't need KPTI */ 1797 static const struct midr_range kpti_safe_list[] = { 1798 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1799 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1800 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1801 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1802 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1803 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1804 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1805 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1806 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1807 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1808 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1809 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1810 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1811 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1812 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1813 { /* sentinel */ } 1814 }; 1815 char const *str = "kpti command line option"; 1816 bool meltdown_safe; 1817 1818 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1819 1820 /* Defer to CPU feature registers */ 1821 if (has_cpuid_feature(entry, scope)) 1822 meltdown_safe = true; 1823 1824 if (!meltdown_safe) 1825 __meltdown_safe = false; 1826 1827 /* 1828 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1829 * ThunderX leads to apparent I-cache corruption of kernel text, which 1830 * ends as well as you might imagine. Don't even try. We cannot rely 1831 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1832 * because cpucap detection order may change. However, since we know 1833 * affected CPUs are always in a homogeneous configuration, it is 1834 * safe to rely on this_cpu_has_cap() here. 1835 */ 1836 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1837 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1838 __kpti_forced = -1; 1839 } 1840 1841 /* Useful for KASLR robustness */ 1842 if (kaslr_enabled() && kaslr_requires_kpti()) { 1843 if (!__kpti_forced) { 1844 str = "KASLR"; 1845 __kpti_forced = 1; 1846 } 1847 } 1848 1849 if (cpu_mitigations_off() && !__kpti_forced) { 1850 str = "mitigations=off"; 1851 __kpti_forced = -1; 1852 } 1853 1854 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1855 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1856 return false; 1857 } 1858 1859 /* Forced? */ 1860 if (__kpti_forced) { 1861 pr_info_once("kernel page table isolation forced %s by %s\n", 1862 __kpti_forced > 0 ? "ON" : "OFF", str); 1863 return __kpti_forced > 0; 1864 } 1865 1866 return !meltdown_safe; 1867 } 1868 1869 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1870 { 1871 /* 1872 * Although the Apple M2 family appears to support NV1, the 1873 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1874 * that it doesn't support NV1 at all. 1875 */ 1876 static const struct midr_range nv1_ni_list[] = { 1877 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1878 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1879 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1880 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1881 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1882 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1883 {} 1884 }; 1885 1886 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1887 !(has_cpuid_feature(entry, scope) || 1888 is_midr_in_range_list(nv1_ni_list))); 1889 } 1890 1891 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1892 static bool has_lpa2_at_stage1(u64 mmfr0) 1893 { 1894 unsigned int tgran; 1895 1896 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1897 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1898 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1899 } 1900 1901 static bool has_lpa2_at_stage2(u64 mmfr0) 1902 { 1903 unsigned int tgran; 1904 1905 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1906 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1907 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1908 } 1909 1910 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1911 { 1912 u64 mmfr0; 1913 1914 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1915 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1916 } 1917 #else 1918 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1919 { 1920 return false; 1921 } 1922 #endif 1923 1924 #ifdef CONFIG_HW_PERF_EVENTS 1925 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1926 { 1927 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1928 unsigned int pmuver; 1929 1930 /* 1931 * PMUVer follows the standard ID scheme for an unsigned field with the 1932 * exception of 0xF (IMP_DEF) which is treated specially and implies 1933 * FEAT_PMUv3 is not implemented. 1934 * 1935 * See DDI0487L.a D24.1.3.2 for more details. 1936 */ 1937 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1938 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1939 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1940 return false; 1941 1942 return pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP; 1943 } 1944 #endif 1945 1946 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1947 { 1948 if (__this_cpu_read(this_cpu_vector) == vectors) { 1949 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1950 1951 __this_cpu_write(this_cpu_vector, v); 1952 } 1953 1954 } 1955 1956 static int __init parse_kpti(char *str) 1957 { 1958 bool enabled; 1959 int ret = kstrtobool(str, &enabled); 1960 1961 if (ret) 1962 return ret; 1963 1964 __kpti_forced = enabled ? 1 : -1; 1965 return 0; 1966 } 1967 early_param("kpti", parse_kpti); 1968 1969 #ifdef CONFIG_ARM64_HW_AFDBM 1970 static struct cpumask dbm_cpus __read_mostly; 1971 1972 static inline void __cpu_enable_hw_dbm(void) 1973 { 1974 u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_HD; 1975 1976 write_sysreg(tcr, tcr_el1); 1977 isb(); 1978 local_flush_tlb_all(); 1979 } 1980 1981 static bool cpu_has_broken_dbm(void) 1982 { 1983 /* List of CPUs which have broken DBM support. */ 1984 static const struct midr_range cpus[] = { 1985 #ifdef CONFIG_ARM64_ERRATUM_1024718 1986 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1987 /* Kryo4xx Silver (rdpe => r1p0) */ 1988 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1989 #endif 1990 #ifdef CONFIG_ARM64_ERRATUM_2051678 1991 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1992 #endif 1993 {}, 1994 }; 1995 1996 return is_midr_in_range_list(cpus); 1997 } 1998 1999 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2000 { 2001 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2002 !cpu_has_broken_dbm(); 2003 } 2004 2005 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2006 { 2007 if (cpu_can_use_dbm(cap)) { 2008 __cpu_enable_hw_dbm(); 2009 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2010 } 2011 } 2012 2013 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2014 int __unused) 2015 { 2016 /* 2017 * DBM is a non-conflicting feature. i.e, the kernel can safely 2018 * run a mix of CPUs with and without the feature. So, we 2019 * unconditionally enable the capability to allow any late CPU 2020 * to use the feature. We only enable the control bits on the 2021 * CPU, if it is supported. 2022 */ 2023 2024 return true; 2025 } 2026 2027 #endif 2028 2029 #ifdef CONFIG_ARM64_AMU_EXTN 2030 2031 /* 2032 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2033 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2034 * information regarding all the events that it supports. When a CPU bit is 2035 * set in the cpumask, the user of this feature can only rely on the presence 2036 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2037 * counters are enabled or access to these counters is enabled by code 2038 * executed at higher exception levels (firmware). 2039 */ 2040 static struct cpumask amu_cpus __read_mostly; 2041 2042 bool cpu_has_amu_feat(int cpu) 2043 { 2044 return cpumask_test_cpu(cpu, &amu_cpus); 2045 } 2046 2047 int get_cpu_with_amu_feat(void) 2048 { 2049 return cpumask_any(&amu_cpus); 2050 } 2051 2052 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2053 { 2054 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2055 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2056 2057 /* 0 reference values signal broken/disabled counters */ 2058 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2059 update_freq_counters_refs(); 2060 } 2061 } 2062 2063 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2064 int __unused) 2065 { 2066 /* 2067 * The AMU extension is a non-conflicting feature: the kernel can 2068 * safely run a mix of CPUs with and without support for the 2069 * activity monitors extension. Therefore, unconditionally enable 2070 * the capability to allow any late CPU to use the feature. 2071 * 2072 * With this feature unconditionally enabled, the cpu_enable 2073 * function will be called for all CPUs that match the criteria, 2074 * including secondary and hotplugged, marking this feature as 2075 * present on that respective CPU. The enable function will also 2076 * print a detection message. 2077 */ 2078 2079 return true; 2080 } 2081 #else 2082 int get_cpu_with_amu_feat(void) 2083 { 2084 return nr_cpu_ids; 2085 } 2086 #endif 2087 2088 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2089 { 2090 return is_kernel_in_hyp_mode(); 2091 } 2092 2093 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2094 { 2095 /* 2096 * Copy register values that aren't redirected by hardware. 2097 * 2098 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2099 * this value to tpidr_el2 before we patch the code. Once we've done 2100 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2101 * do anything here. 2102 */ 2103 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2104 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2105 } 2106 2107 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2108 int scope) 2109 { 2110 if (kvm_get_mode() != KVM_MODE_NV) 2111 return false; 2112 2113 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2114 pr_warn("unavailable: %s\n", cap->desc); 2115 return false; 2116 } 2117 2118 return true; 2119 } 2120 2121 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2122 int __unused) 2123 { 2124 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2125 } 2126 2127 bool cpu_supports_bbml2_noabort(void) 2128 { 2129 /* 2130 * We want to allow usage of BBML2 in as wide a range of kernel contexts 2131 * as possible. This list is therefore an allow-list of known-good 2132 * implementations that both support BBML2 and additionally, fulfill the 2133 * extra constraint of never generating TLB conflict aborts when using 2134 * the relaxed BBML2 semantics (such aborts make use of BBML2 in certain 2135 * kernel contexts difficult to prove safe against recursive aborts). 2136 * 2137 * Note that implementations can only be considered "known-good" if their 2138 * implementors attest to the fact that the implementation never raises 2139 * TLB conflict aborts for BBML2 mapping granularity changes. 2140 */ 2141 static const struct midr_range supports_bbml2_noabort_list[] = { 2142 MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), 2143 MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), 2144 MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf), 2145 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 2146 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 2147 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 2148 {} 2149 }; 2150 2151 /* Does our cpu guarantee to never raise TLB conflict aborts? */ 2152 if (!is_midr_in_range_list(supports_bbml2_noabort_list)) 2153 return false; 2154 2155 /* 2156 * We currently ignore the ID_AA64MMFR2_EL1 register, and only care 2157 * about whether the MIDR check passes. 2158 */ 2159 2160 return true; 2161 } 2162 2163 static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int scope) 2164 { 2165 return cpu_supports_bbml2_noabort(); 2166 } 2167 2168 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2169 { 2170 /* 2171 * We modify PSTATE. This won't work from irq context as the PSTATE 2172 * is discarded once we return from the exception. 2173 */ 2174 WARN_ON_ONCE(in_interrupt()); 2175 2176 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2177 set_pstate_pan(1); 2178 } 2179 2180 #ifdef CONFIG_ARM64_RAS_EXTN 2181 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2182 { 2183 /* Firmware may have left a deferred SError in this register. */ 2184 write_sysreg_s(0, SYS_DISR_EL1); 2185 } 2186 static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope) 2187 { 2188 const struct arm64_cpu_capabilities rasv1p1_caps[] = { 2189 { 2190 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1) 2191 }, 2192 { 2193 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2194 }, 2195 { 2196 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1) 2197 }, 2198 }; 2199 2200 return (has_cpuid_feature(&rasv1p1_caps[0], scope) || 2201 (has_cpuid_feature(&rasv1p1_caps[1], scope) && 2202 has_cpuid_feature(&rasv1p1_caps[2], scope))); 2203 } 2204 #endif /* CONFIG_ARM64_RAS_EXTN */ 2205 2206 #ifdef CONFIG_ARM64_PTR_AUTH 2207 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2208 { 2209 int boot_val, sec_val; 2210 2211 /* We don't expect to be called with SCOPE_SYSTEM */ 2212 WARN_ON(scope == SCOPE_SYSTEM); 2213 /* 2214 * The ptr-auth feature levels are not intercompatible with lower 2215 * levels. Hence we must match ptr-auth feature level of the secondary 2216 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2217 * from the sanitised register whereas direct register read is done for 2218 * the secondary CPUs. 2219 * The sanitised feature state is guaranteed to match that of the 2220 * boot CPU as a mismatched secondary CPU is parked before it gets 2221 * a chance to update the state, with the capability. 2222 */ 2223 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2224 entry->field_pos, entry->sign); 2225 if (scope & SCOPE_BOOT_CPU) 2226 return boot_val >= entry->min_field_value; 2227 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2228 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2229 entry->field_pos, entry->sign); 2230 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2231 } 2232 2233 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2234 int scope) 2235 { 2236 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2237 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2238 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2239 2240 return apa || apa3 || api; 2241 } 2242 2243 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2244 int __unused) 2245 { 2246 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2247 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2248 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2249 2250 return gpa || gpa3 || gpi; 2251 } 2252 #endif /* CONFIG_ARM64_PTR_AUTH */ 2253 2254 #ifdef CONFIG_ARM64_E0PD 2255 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2256 { 2257 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2258 sysreg_clear_set(tcr_el1, 0, TCR_EL1_E0PD1); 2259 } 2260 #endif /* CONFIG_ARM64_E0PD */ 2261 2262 static void cpu_enable_ls64(struct arm64_cpu_capabilities const *cap) 2263 { 2264 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnALS, SCTLR_EL1_EnALS); 2265 } 2266 2267 static void cpu_enable_ls64_v(struct arm64_cpu_capabilities const *cap) 2268 { 2269 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnASR, 0); 2270 } 2271 2272 #ifdef CONFIG_ARM64_PSEUDO_NMI 2273 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2274 int scope) 2275 { 2276 /* 2277 * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU 2278 * feature, so will be detected earlier. 2279 */ 2280 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); 2281 if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) 2282 return false; 2283 2284 return enable_pseudo_nmi; 2285 } 2286 2287 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2288 int scope) 2289 { 2290 /* 2291 * If we're not using priority masking then we won't be poking PMR_EL1, 2292 * and there's no need to relax synchronization of writes to it, and 2293 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2294 * that. 2295 * 2296 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2297 * feature, so will be detected earlier. 2298 */ 2299 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2300 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2301 return false; 2302 2303 /* 2304 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2305 * hint for interrupt distribution, a DSB is not necessary when 2306 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2307 * 2308 * Linux itself doesn't use 1:N distribution, so has no need to 2309 * set PMHE. The only reason to have it set is if EL3 requires it 2310 * (and we can't change it). 2311 */ 2312 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2313 } 2314 #endif 2315 2316 static bool can_trap_icv_dir_el1(const struct arm64_cpu_capabilities *entry, 2317 int scope) 2318 { 2319 static const struct midr_range has_vgic_v3[] = { 2320 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), 2321 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), 2322 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), 2323 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), 2324 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), 2325 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), 2326 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 2327 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 2328 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 2329 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 2330 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 2331 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 2332 {}, 2333 }; 2334 struct arm_smccc_res res = {}; 2335 2336 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV3_CPUIF); 2337 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV5_LEGACY); 2338 if (!this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF) && 2339 !is_midr_in_range_list(has_vgic_v3)) 2340 return false; 2341 2342 if (!is_hyp_mode_available()) 2343 return false; 2344 2345 if (this_cpu_has_cap(ARM64_HAS_GICV5_LEGACY)) 2346 return true; 2347 2348 if (is_kernel_in_hyp_mode()) 2349 res.a1 = read_sysreg_s(SYS_ICH_VTR_EL2); 2350 else 2351 arm_smccc_1_1_hvc(HVC_GET_ICH_VTR_EL2, &res); 2352 2353 if (res.a0 == HVC_STUB_ERR) 2354 return false; 2355 2356 return res.a1 & ICH_VTR_EL2_TDS; 2357 } 2358 2359 #ifdef CONFIG_ARM64_BTI 2360 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2361 { 2362 /* 2363 * Use of X16/X17 for tail-calls and trampolines that jump to 2364 * function entry points using BR is a requirement for 2365 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2366 * So, be strict and forbid other BRs using other registers to 2367 * jump onto a PACIxSP instruction: 2368 */ 2369 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2370 isb(); 2371 } 2372 #endif /* CONFIG_ARM64_BTI */ 2373 2374 #ifdef CONFIG_ARM64_MTE 2375 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2376 { 2377 static bool cleared_zero_page = false; 2378 2379 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2380 2381 mte_cpu_setup(); 2382 2383 /* 2384 * Clear the tags in the zero page. This needs to be done via the 2385 * linear map which has the Tagged attribute. Since this page is 2386 * always mapped as pte_special(), set_pte_at() will not attempt to 2387 * clear the tags or set PG_mte_tagged. 2388 */ 2389 if (!cleared_zero_page) { 2390 cleared_zero_page = true; 2391 mte_clear_page_tags(lm_alias(empty_zero_page)); 2392 } 2393 2394 kasan_init_hw_tags_cpu(); 2395 } 2396 #endif /* CONFIG_ARM64_MTE */ 2397 2398 static void user_feature_fixup(void) 2399 { 2400 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2401 struct arm64_ftr_reg *regp; 2402 2403 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2404 if (regp) 2405 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2406 } 2407 2408 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2409 struct arm64_ftr_reg *regp; 2410 2411 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2412 if (regp) 2413 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2414 } 2415 } 2416 2417 static void elf_hwcap_fixup(void) 2418 { 2419 #ifdef CONFIG_COMPAT 2420 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2421 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2422 #endif /* CONFIG_COMPAT */ 2423 } 2424 2425 #ifdef CONFIG_KVM 2426 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2427 { 2428 return kvm_get_mode() == KVM_MODE_PROTECTED; 2429 } 2430 #endif /* CONFIG_KVM */ 2431 2432 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2433 { 2434 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2435 } 2436 2437 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2438 { 2439 set_pstate_dit(1); 2440 } 2441 2442 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2443 { 2444 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2445 } 2446 2447 #ifdef CONFIG_ARM64_POE 2448 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2449 { 2450 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2451 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2452 } 2453 #endif 2454 2455 #ifdef CONFIG_ARM64_GCS 2456 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2457 { 2458 /* GCSPR_EL0 is always readable */ 2459 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2460 } 2461 #endif 2462 2463 /* Internal helper functions to match cpu capability type */ 2464 static bool 2465 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2466 { 2467 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2468 } 2469 2470 static bool 2471 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2472 { 2473 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2474 } 2475 2476 static bool 2477 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2478 { 2479 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2480 } 2481 2482 static bool 2483 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2484 { 2485 if (!has_cpuid_feature(entry, scope)) 2486 return false; 2487 2488 /* Check firmware actually enabled MPAM on this cpu. */ 2489 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2490 } 2491 2492 static void 2493 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2494 { 2495 /* 2496 * Access by the kernel (at EL1) should use the reserved PARTID 2497 * which is configured unrestricted. This avoids priority-inversion 2498 * where latency sensitive tasks have to wait for a task that has 2499 * been throttled to release the lock. 2500 */ 2501 write_sysreg_s(0, SYS_MPAM1_EL1); 2502 } 2503 2504 static bool 2505 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2506 { 2507 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2508 2509 return idr & MPAMIDR_EL1_HAS_HCR; 2510 } 2511 2512 static bool 2513 test_has_gicv5_legacy(const struct arm64_cpu_capabilities *entry, int scope) 2514 { 2515 if (!this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF)) 2516 return false; 2517 2518 return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY); 2519 } 2520 2521 static const struct arm64_cpu_capabilities arm64_features[] = { 2522 { 2523 .capability = ARM64_ALWAYS_BOOT, 2524 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2525 .matches = has_always, 2526 }, 2527 { 2528 .capability = ARM64_ALWAYS_SYSTEM, 2529 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2530 .matches = has_always, 2531 }, 2532 { 2533 .desc = "GICv3 CPU interface", 2534 .capability = ARM64_HAS_GICV3_CPUIF, 2535 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2536 .matches = has_useable_gicv3_cpuif, 2537 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2538 }, 2539 { 2540 .desc = "Enhanced Counter Virtualization", 2541 .capability = ARM64_HAS_ECV, 2542 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2543 .matches = has_cpuid_feature, 2544 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2545 }, 2546 { 2547 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2548 .capability = ARM64_HAS_ECV_CNTPOFF, 2549 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2550 .matches = has_cpuid_feature, 2551 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2552 }, 2553 { 2554 .desc = "Privileged Access Never", 2555 .capability = ARM64_HAS_PAN, 2556 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2557 .matches = has_cpuid_feature, 2558 .cpu_enable = cpu_enable_pan, 2559 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2560 }, 2561 #ifdef CONFIG_ARM64_EPAN 2562 { 2563 .desc = "Enhanced Privileged Access Never", 2564 .capability = ARM64_HAS_EPAN, 2565 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2566 .matches = has_cpuid_feature, 2567 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2568 }, 2569 #endif /* CONFIG_ARM64_EPAN */ 2570 { 2571 .desc = "LSE atomic instructions", 2572 .capability = ARM64_HAS_LSE_ATOMICS, 2573 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2574 .matches = has_cpuid_feature, 2575 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2576 }, 2577 { 2578 .desc = "Virtualization Host Extensions", 2579 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2580 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2581 .matches = runs_at_el2, 2582 .cpu_enable = cpu_copy_el2regs, 2583 }, 2584 { 2585 .desc = "Nested Virtualization Support", 2586 .capability = ARM64_HAS_NESTED_VIRT, 2587 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2588 .matches = has_nested_virt_support, 2589 .match_list = (const struct arm64_cpu_capabilities []){ 2590 { 2591 .matches = has_cpuid_feature, 2592 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2593 }, 2594 { 2595 .matches = has_cpuid_feature, 2596 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2597 }, 2598 { /* Sentinel */ } 2599 }, 2600 }, 2601 { 2602 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2603 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2604 .matches = has_32bit_el0, 2605 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2606 }, 2607 #ifdef CONFIG_KVM 2608 { 2609 .desc = "32-bit EL1 Support", 2610 .capability = ARM64_HAS_32BIT_EL1, 2611 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2612 .matches = has_cpuid_feature, 2613 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2614 }, 2615 { 2616 .desc = "Protected KVM", 2617 .capability = ARM64_KVM_PROTECTED_MODE, 2618 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2619 .matches = is_kvm_protected_mode, 2620 }, 2621 { 2622 .desc = "HCRX_EL2 register", 2623 .capability = ARM64_HAS_HCX, 2624 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2625 .matches = has_cpuid_feature, 2626 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2627 }, 2628 #endif 2629 { 2630 .desc = "Kernel page table isolation (KPTI)", 2631 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2632 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2633 .cpu_enable = cpu_enable_kpti, 2634 .matches = unmap_kernel_at_el0, 2635 /* 2636 * The ID feature fields below are used to indicate that 2637 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2638 * more details. 2639 */ 2640 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2641 }, 2642 { 2643 .capability = ARM64_HAS_FPSIMD, 2644 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2645 .matches = has_cpuid_feature, 2646 .cpu_enable = cpu_enable_fpsimd, 2647 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2648 }, 2649 #ifdef CONFIG_ARM64_PMEM 2650 { 2651 .desc = "Data cache clean to Point of Persistence", 2652 .capability = ARM64_HAS_DCPOP, 2653 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2654 .matches = has_cpuid_feature, 2655 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2656 }, 2657 { 2658 .desc = "Data cache clean to Point of Deep Persistence", 2659 .capability = ARM64_HAS_DCPODP, 2660 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2661 .matches = has_cpuid_feature, 2662 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2663 }, 2664 #endif 2665 #ifdef CONFIG_ARM64_SVE 2666 { 2667 .desc = "Scalable Vector Extension", 2668 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2669 .capability = ARM64_SVE, 2670 .cpu_enable = cpu_enable_sve, 2671 .matches = has_cpuid_feature, 2672 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2673 }, 2674 #endif /* CONFIG_ARM64_SVE */ 2675 #ifdef CONFIG_ARM64_RAS_EXTN 2676 { 2677 .desc = "RAS Extension Support", 2678 .capability = ARM64_HAS_RAS_EXTN, 2679 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2680 .matches = has_cpuid_feature, 2681 .cpu_enable = cpu_clear_disr, 2682 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2683 }, 2684 { 2685 .desc = "RASv1p1 Extension Support", 2686 .capability = ARM64_HAS_RASV1P1_EXTN, 2687 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2688 .matches = has_rasv1p1, 2689 }, 2690 #endif /* CONFIG_ARM64_RAS_EXTN */ 2691 #ifdef CONFIG_ARM64_AMU_EXTN 2692 { 2693 .desc = "Activity Monitors Unit (AMU)", 2694 .capability = ARM64_HAS_AMU_EXTN, 2695 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2696 .matches = has_amu, 2697 .cpu_enable = cpu_amu_enable, 2698 .cpus = &amu_cpus, 2699 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2700 }, 2701 #endif /* CONFIG_ARM64_AMU_EXTN */ 2702 { 2703 .desc = "Data cache clean to the PoU not required for I/D coherence", 2704 .capability = ARM64_HAS_CACHE_IDC, 2705 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2706 .matches = has_cache_idc, 2707 .cpu_enable = cpu_emulate_effective_ctr, 2708 }, 2709 { 2710 .desc = "Instruction cache invalidation not required for I/D coherence", 2711 .capability = ARM64_HAS_CACHE_DIC, 2712 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2713 .matches = has_cache_dic, 2714 }, 2715 { 2716 .desc = "Stage-2 Force Write-Back", 2717 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2718 .capability = ARM64_HAS_STAGE2_FWB, 2719 .matches = has_cpuid_feature, 2720 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2721 }, 2722 { 2723 .desc = "ARMv8.4 Translation Table Level", 2724 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2725 .capability = ARM64_HAS_ARMv8_4_TTL, 2726 .matches = has_cpuid_feature, 2727 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2728 }, 2729 { 2730 .desc = "TLB range maintenance instructions", 2731 .capability = ARM64_HAS_TLB_RANGE, 2732 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2733 .matches = has_cpuid_feature, 2734 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2735 }, 2736 #ifdef CONFIG_ARM64_HW_AFDBM 2737 { 2738 .desc = "Hardware dirty bit management", 2739 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2740 .capability = ARM64_HW_DBM, 2741 .matches = has_hw_dbm, 2742 .cpu_enable = cpu_enable_hw_dbm, 2743 .cpus = &dbm_cpus, 2744 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2745 }, 2746 #endif 2747 #ifdef CONFIG_ARM64_HAFT 2748 { 2749 .desc = "Hardware managed Access Flag for Table Descriptors", 2750 /* 2751 * Contrary to the page/block access flag, the table access flag 2752 * cannot be emulated in software (no access fault will occur). 2753 * Therefore this should be used only if it's supported system 2754 * wide. 2755 */ 2756 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2757 .capability = ARM64_HAFT, 2758 .matches = has_cpuid_feature, 2759 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2760 }, 2761 #endif 2762 { 2763 .desc = "CRC32 instructions", 2764 .capability = ARM64_HAS_CRC32, 2765 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2766 .matches = has_cpuid_feature, 2767 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2768 }, 2769 { 2770 .desc = "Speculative Store Bypassing Safe (SSBS)", 2771 .capability = ARM64_SSBS, 2772 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2773 .matches = has_cpuid_feature, 2774 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2775 }, 2776 #ifdef CONFIG_ARM64_CNP 2777 { 2778 .desc = "Common not Private translations", 2779 .capability = ARM64_HAS_CNP, 2780 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2781 .matches = has_useable_cnp, 2782 .cpu_enable = cpu_enable_cnp, 2783 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2784 }, 2785 #endif 2786 { 2787 .desc = "Speculation barrier (SB)", 2788 .capability = ARM64_HAS_SB, 2789 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2790 .matches = has_cpuid_feature, 2791 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2792 }, 2793 #ifdef CONFIG_ARM64_PTR_AUTH 2794 { 2795 .desc = "Address authentication (architected QARMA5 algorithm)", 2796 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2797 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2798 .matches = has_address_auth_cpucap, 2799 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2800 }, 2801 { 2802 .desc = "Address authentication (architected QARMA3 algorithm)", 2803 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2804 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2805 .matches = has_address_auth_cpucap, 2806 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2807 }, 2808 { 2809 .desc = "Address authentication (IMP DEF algorithm)", 2810 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2811 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2812 .matches = has_address_auth_cpucap, 2813 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2814 }, 2815 { 2816 .capability = ARM64_HAS_ADDRESS_AUTH, 2817 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2818 .matches = has_address_auth_metacap, 2819 }, 2820 { 2821 .desc = "Generic authentication (architected QARMA5 algorithm)", 2822 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2823 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2824 .matches = has_cpuid_feature, 2825 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2826 }, 2827 { 2828 .desc = "Generic authentication (architected QARMA3 algorithm)", 2829 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2830 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2831 .matches = has_cpuid_feature, 2832 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2833 }, 2834 { 2835 .desc = "Generic authentication (IMP DEF algorithm)", 2836 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2837 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2838 .matches = has_cpuid_feature, 2839 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2840 }, 2841 { 2842 .capability = ARM64_HAS_GENERIC_AUTH, 2843 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2844 .matches = has_generic_auth, 2845 }, 2846 #endif /* CONFIG_ARM64_PTR_AUTH */ 2847 #ifdef CONFIG_ARM64_PSEUDO_NMI 2848 { 2849 /* 2850 * Depends on having GICv3 2851 */ 2852 .desc = "IRQ priority masking", 2853 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2854 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2855 .matches = can_use_gic_priorities, 2856 }, 2857 { 2858 /* 2859 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2860 */ 2861 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2862 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2863 .matches = has_gic_prio_relaxed_sync, 2864 }, 2865 #endif 2866 { 2867 /* 2868 * Depends on having GICv3 2869 */ 2870 .desc = "ICV_DIR_EL1 trapping", 2871 .capability = ARM64_HAS_ICH_HCR_EL2_TDIR, 2872 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 2873 .matches = can_trap_icv_dir_el1, 2874 }, 2875 #ifdef CONFIG_ARM64_E0PD 2876 { 2877 .desc = "E0PD", 2878 .capability = ARM64_HAS_E0PD, 2879 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2880 .cpu_enable = cpu_enable_e0pd, 2881 .matches = has_cpuid_feature, 2882 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2883 }, 2884 #endif 2885 { 2886 .desc = "Random Number Generator", 2887 .capability = ARM64_HAS_RNG, 2888 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2889 .matches = has_cpuid_feature, 2890 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2891 }, 2892 #ifdef CONFIG_ARM64_BTI 2893 { 2894 .desc = "Branch Target Identification", 2895 .capability = ARM64_BTI, 2896 #ifdef CONFIG_ARM64_BTI_KERNEL 2897 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2898 #else 2899 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2900 #endif 2901 .matches = has_cpuid_feature, 2902 .cpu_enable = bti_enable, 2903 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2904 }, 2905 #endif 2906 #ifdef CONFIG_ARM64_MTE 2907 { 2908 .desc = "Memory Tagging Extension", 2909 .capability = ARM64_MTE, 2910 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2911 .matches = has_cpuid_feature, 2912 .cpu_enable = cpu_enable_mte, 2913 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2914 }, 2915 { 2916 .desc = "Asymmetric MTE Tag Check Fault", 2917 .capability = ARM64_MTE_ASYMM, 2918 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2919 .matches = has_cpuid_feature, 2920 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2921 }, 2922 { 2923 .desc = "FAR on MTE Tag Check Fault", 2924 .capability = ARM64_MTE_FAR, 2925 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2926 .matches = has_cpuid_feature, 2927 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) 2928 }, 2929 { 2930 .desc = "Store Only MTE Tag Check", 2931 .capability = ARM64_MTE_STORE_ONLY, 2932 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2933 .matches = has_cpuid_feature, 2934 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) 2935 }, 2936 #endif /* CONFIG_ARM64_MTE */ 2937 { 2938 .desc = "RCpc load-acquire (LDAPR)", 2939 .capability = ARM64_HAS_LDAPR, 2940 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2941 .matches = has_cpuid_feature, 2942 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2943 }, 2944 { 2945 .desc = "Fine Grained Traps", 2946 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2947 .capability = ARM64_HAS_FGT, 2948 .matches = has_cpuid_feature, 2949 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2950 }, 2951 { 2952 .desc = "Fine Grained Traps 2", 2953 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2954 .capability = ARM64_HAS_FGT2, 2955 .matches = has_cpuid_feature, 2956 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 2957 }, 2958 #ifdef CONFIG_ARM64_SME 2959 { 2960 .desc = "Scalable Matrix Extension", 2961 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2962 .capability = ARM64_SME, 2963 .matches = has_cpuid_feature, 2964 .cpu_enable = cpu_enable_sme, 2965 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2966 }, 2967 /* FA64 should be sorted after the base SME capability */ 2968 { 2969 .desc = "FA64", 2970 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2971 .capability = ARM64_SME_FA64, 2972 .matches = has_cpuid_feature, 2973 .cpu_enable = cpu_enable_fa64, 2974 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2975 }, 2976 { 2977 .desc = "SME2", 2978 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2979 .capability = ARM64_SME2, 2980 .matches = has_cpuid_feature, 2981 .cpu_enable = cpu_enable_sme2, 2982 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2983 }, 2984 #endif /* CONFIG_ARM64_SME */ 2985 { 2986 .desc = "WFx with timeout", 2987 .capability = ARM64_HAS_WFXT, 2988 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2989 .matches = has_cpuid_feature, 2990 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2991 }, 2992 { 2993 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2994 .capability = ARM64_HAS_TIDCP1, 2995 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2996 .matches = has_cpuid_feature, 2997 .cpu_enable = cpu_trap_el0_impdef, 2998 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2999 }, 3000 { 3001 .desc = "Data independent timing control (DIT)", 3002 .capability = ARM64_HAS_DIT, 3003 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3004 .matches = has_cpuid_feature, 3005 .cpu_enable = cpu_enable_dit, 3006 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 3007 }, 3008 { 3009 .desc = "Memory Copy and Memory Set instructions", 3010 .capability = ARM64_HAS_MOPS, 3011 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3012 .matches = has_cpuid_feature, 3013 .cpu_enable = cpu_enable_mops, 3014 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 3015 }, 3016 { 3017 .capability = ARM64_HAS_TCR2, 3018 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3019 .matches = has_cpuid_feature, 3020 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 3021 }, 3022 { 3023 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 3024 .capability = ARM64_HAS_S1PIE, 3025 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3026 .matches = has_cpuid_feature, 3027 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 3028 }, 3029 { 3030 .desc = "VHE for hypervisor only", 3031 .capability = ARM64_KVM_HVHE, 3032 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3033 .matches = hvhe_possible, 3034 }, 3035 { 3036 .desc = "Enhanced Virtualization Traps", 3037 .capability = ARM64_HAS_EVT, 3038 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3039 .matches = has_cpuid_feature, 3040 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 3041 }, 3042 { 3043 .desc = "BBM Level 2 without TLB conflict abort", 3044 .capability = ARM64_HAS_BBML2_NOABORT, 3045 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3046 .matches = has_bbml2_noabort, 3047 }, 3048 { 3049 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 3050 .capability = ARM64_HAS_LPA2, 3051 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3052 .matches = has_lpa2, 3053 }, 3054 { 3055 .desc = "FPMR", 3056 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3057 .capability = ARM64_HAS_FPMR, 3058 .matches = has_cpuid_feature, 3059 .cpu_enable = cpu_enable_fpmr, 3060 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 3061 }, 3062 #ifdef CONFIG_ARM64_VA_BITS_52 3063 { 3064 .capability = ARM64_HAS_VA52, 3065 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3066 .matches = has_cpuid_feature, 3067 #ifdef CONFIG_ARM64_64K_PAGES 3068 .desc = "52-bit Virtual Addressing (LVA)", 3069 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 3070 #else 3071 .desc = "52-bit Virtual Addressing (LPA2)", 3072 #ifdef CONFIG_ARM64_4K_PAGES 3073 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 3074 #else 3075 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 3076 #endif 3077 #endif 3078 }, 3079 #endif 3080 { 3081 .desc = "Memory Partitioning And Monitoring", 3082 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3083 .capability = ARM64_MPAM, 3084 .matches = test_has_mpam, 3085 .cpu_enable = cpu_enable_mpam, 3086 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 3087 }, 3088 { 3089 .desc = "Memory Partitioning And Monitoring Virtualisation", 3090 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3091 .capability = ARM64_MPAM_HCR, 3092 .matches = test_has_mpam_hcr, 3093 }, 3094 { 3095 .desc = "NV1", 3096 .capability = ARM64_HAS_HCR_NV1, 3097 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3098 .matches = has_nv1, 3099 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3100 }, 3101 #ifdef CONFIG_ARM64_POE 3102 { 3103 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3104 .capability = ARM64_HAS_S1POE, 3105 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3106 .matches = has_cpuid_feature, 3107 .cpu_enable = cpu_enable_poe, 3108 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3109 }, 3110 #endif 3111 #ifdef CONFIG_ARM64_GCS 3112 { 3113 .desc = "Guarded Control Stack (GCS)", 3114 .capability = ARM64_HAS_GCS, 3115 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3116 .cpu_enable = cpu_enable_gcs, 3117 .matches = has_cpuid_feature, 3118 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3119 }, 3120 #endif 3121 #ifdef CONFIG_HW_PERF_EVENTS 3122 { 3123 .desc = "PMUv3", 3124 .capability = ARM64_HAS_PMUV3, 3125 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3126 .matches = has_pmuv3, 3127 }, 3128 #endif 3129 { 3130 .desc = "SCTLR2", 3131 .capability = ARM64_HAS_SCTLR2, 3132 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3133 .matches = has_cpuid_feature, 3134 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, SCTLRX, IMP) 3135 }, 3136 { 3137 .desc = "GICv5 CPU interface", 3138 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 3139 .capability = ARM64_HAS_GICV5_CPUIF, 3140 .matches = has_cpuid_feature, 3141 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) 3142 }, 3143 { 3144 .desc = "GICv5 Legacy vCPU interface", 3145 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3146 .capability = ARM64_HAS_GICV5_LEGACY, 3147 .matches = test_has_gicv5_legacy, 3148 }, 3149 { 3150 .desc = "XNX", 3151 .capability = ARM64_HAS_XNX, 3152 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3153 .matches = has_cpuid_feature, 3154 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, XNX, IMP) 3155 }, 3156 { 3157 .desc = "LS64", 3158 .capability = ARM64_HAS_LS64, 3159 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3160 .matches = has_cpuid_feature, 3161 .cpu_enable = cpu_enable_ls64, 3162 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64) 3163 }, 3164 { 3165 .desc = "LS64_V", 3166 .capability = ARM64_HAS_LS64_V, 3167 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3168 .matches = has_cpuid_feature, 3169 .cpu_enable = cpu_enable_ls64_v, 3170 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64_V) 3171 }, 3172 {}, 3173 }; 3174 3175 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3176 .matches = has_user_cpuid_feature, \ 3177 ARM64_CPUID_FIELDS(reg, field, min_value) 3178 3179 #define __HWCAP_CAP(name, cap_type, cap) \ 3180 .desc = name, \ 3181 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3182 .hwcap_type = cap_type, \ 3183 .hwcap = cap, \ 3184 3185 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3186 { \ 3187 __HWCAP_CAP(#cap, cap_type, cap) \ 3188 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3189 } 3190 3191 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3192 { \ 3193 __HWCAP_CAP(#cap, cap_type, cap) \ 3194 .matches = cpucap_multi_entry_cap_matches, \ 3195 .match_list = list, \ 3196 } 3197 3198 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3199 { \ 3200 __HWCAP_CAP(#cap, cap_type, cap) \ 3201 .matches = match, \ 3202 } 3203 3204 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3205 { \ 3206 __HWCAP_CAP(#cap, cap_type, cap) \ 3207 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3208 .matches = match, \ 3209 } 3210 3211 #ifdef CONFIG_ARM64_PTR_AUTH 3212 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3213 { 3214 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3215 }, 3216 { 3217 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3218 }, 3219 { 3220 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3221 }, 3222 {}, 3223 }; 3224 3225 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3226 { 3227 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3228 }, 3229 { 3230 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3231 }, 3232 { 3233 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3234 }, 3235 {}, 3236 }; 3237 #endif 3238 3239 #ifdef CONFIG_ARM64_SVE 3240 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3241 { 3242 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3243 } 3244 #endif 3245 3246 #ifdef CONFIG_ARM64_SME 3247 static bool has_sme_feature(const struct arm64_cpu_capabilities *cap, int scope) 3248 { 3249 return system_supports_sme() && has_user_cpuid_feature(cap, scope); 3250 } 3251 #endif 3252 3253 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3254 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3255 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3256 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3257 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3258 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3259 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3260 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3261 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3262 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3263 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3264 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3265 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3266 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3267 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3268 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3269 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3270 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3271 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3272 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3273 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3274 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3275 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3276 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3277 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3278 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3279 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3280 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3281 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3282 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3283 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3284 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3285 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3286 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3287 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3288 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3289 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3290 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3291 HWCAP_CAP(ID_AA64ISAR1_EL1, LS64, LS64, CAP_HWCAP, KERNEL_HWCAP_LS64), 3292 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3293 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3294 HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE), 3295 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3296 #ifdef CONFIG_ARM64_SVE 3297 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3298 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3299 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3300 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3301 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3302 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3303 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3304 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3305 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3306 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3307 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3308 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3309 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3310 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3311 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3312 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3313 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3314 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3315 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3316 #endif 3317 #ifdef CONFIG_ARM64_GCS 3318 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3319 #endif 3320 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3321 #ifdef CONFIG_ARM64_BTI 3322 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3323 #endif 3324 #ifdef CONFIG_ARM64_PTR_AUTH 3325 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3326 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3327 #endif 3328 #ifdef CONFIG_ARM64_MTE 3329 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3330 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3331 HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), 3332 HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MTE_STORE_ONLY), 3333 #endif /* CONFIG_ARM64_MTE */ 3334 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3335 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3336 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3337 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3338 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3339 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3340 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3341 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3342 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3343 #ifdef CONFIG_ARM64_SME 3344 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3345 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3346 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3347 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3348 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3349 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3350 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3351 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3352 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3353 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3354 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3355 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3356 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3357 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3358 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3359 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3360 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3361 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3362 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3363 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3364 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3365 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3366 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3367 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3368 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3369 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3370 #endif /* CONFIG_ARM64_SME */ 3371 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3372 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3373 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3374 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3375 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3376 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3377 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3378 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3379 #ifdef CONFIG_ARM64_POE 3380 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3381 #endif 3382 {}, 3383 }; 3384 3385 #ifdef CONFIG_COMPAT 3386 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3387 { 3388 /* 3389 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3390 * in line with that of arm32 as in vfp_init(). We make sure that the 3391 * check is future proof, by making sure value is non-zero. 3392 */ 3393 u32 mvfr1; 3394 3395 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3396 if (scope == SCOPE_SYSTEM) 3397 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3398 else 3399 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3400 3401 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3402 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3403 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3404 } 3405 #endif 3406 3407 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3408 #ifdef CONFIG_COMPAT 3409 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3410 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3411 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3412 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3413 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3414 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3415 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3416 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3417 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3418 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3419 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3420 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3421 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3422 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3423 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3424 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3425 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3426 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3427 #endif 3428 {}, 3429 }; 3430 3431 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3432 { 3433 switch (cap->hwcap_type) { 3434 case CAP_HWCAP: 3435 cpu_set_feature(cap->hwcap); 3436 break; 3437 #ifdef CONFIG_COMPAT 3438 case CAP_COMPAT_HWCAP: 3439 compat_elf_hwcap |= (u32)cap->hwcap; 3440 break; 3441 case CAP_COMPAT_HWCAP2: 3442 compat_elf_hwcap2 |= (u32)cap->hwcap; 3443 break; 3444 #endif 3445 default: 3446 WARN_ON(1); 3447 break; 3448 } 3449 } 3450 3451 /* Check if we have a particular HWCAP enabled */ 3452 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3453 { 3454 bool rc; 3455 3456 switch (cap->hwcap_type) { 3457 case CAP_HWCAP: 3458 rc = cpu_have_feature(cap->hwcap); 3459 break; 3460 #ifdef CONFIG_COMPAT 3461 case CAP_COMPAT_HWCAP: 3462 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3463 break; 3464 case CAP_COMPAT_HWCAP2: 3465 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3466 break; 3467 #endif 3468 default: 3469 WARN_ON(1); 3470 rc = false; 3471 } 3472 3473 return rc; 3474 } 3475 3476 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3477 { 3478 /* We support emulation of accesses to CPU ID feature registers */ 3479 cpu_set_named_feature(CPUID); 3480 for (; hwcaps->matches; hwcaps++) 3481 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3482 cap_set_elf_hwcap(hwcaps); 3483 } 3484 3485 static void update_cpu_capabilities(u16 scope_mask) 3486 { 3487 int i; 3488 const struct arm64_cpu_capabilities *caps; 3489 3490 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3491 for (i = 0; i < ARM64_NCAPS; i++) { 3492 bool match_all = false; 3493 bool caps_set = false; 3494 bool boot_cpu = false; 3495 3496 caps = cpucap_ptrs[i]; 3497 if (!caps || !(caps->type & scope_mask)) 3498 continue; 3499 3500 match_all = cpucap_match_all_early_cpus(caps); 3501 caps_set = cpus_have_cap(caps->capability); 3502 boot_cpu = scope_mask & SCOPE_BOOT_CPU; 3503 3504 /* 3505 * Unless it's a match-all CPUs feature, avoid probing if 3506 * already detected. 3507 */ 3508 if (!match_all && caps_set) 3509 continue; 3510 3511 /* 3512 * A match-all CPUs capability is only set when probing the 3513 * boot CPU. It may be cleared subsequently if not detected on 3514 * secondary ones. 3515 */ 3516 if (match_all && !caps_set && !boot_cpu) 3517 continue; 3518 3519 if (!caps->matches(caps, cpucap_default_scope(caps))) { 3520 if (match_all) 3521 __clear_bit(caps->capability, system_cpucaps); 3522 continue; 3523 } 3524 3525 /* 3526 * Match-all CPUs capabilities are logged later when the 3527 * system capabilities are finalised. 3528 */ 3529 if (!match_all && caps->desc && !caps->cpus) 3530 pr_info("detected: %s\n", caps->desc); 3531 3532 __set_bit(caps->capability, system_cpucaps); 3533 3534 if (boot_cpu && (caps->type & SCOPE_BOOT_CPU)) 3535 set_bit(caps->capability, boot_cpucaps); 3536 } 3537 } 3538 3539 /* 3540 * Enable all the available capabilities on this CPU. The capabilities 3541 * with BOOT_CPU scope are handled separately and hence skipped here. 3542 */ 3543 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3544 { 3545 int i; 3546 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3547 3548 for_each_available_cap(i) { 3549 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3550 3551 if (WARN_ON(!cap)) 3552 continue; 3553 3554 if (!(cap->type & non_boot_scope)) 3555 continue; 3556 3557 if (cap->cpu_enable) 3558 cap->cpu_enable(cap); 3559 } 3560 return 0; 3561 } 3562 3563 /* 3564 * Run through the enabled capabilities and enable() it on all active 3565 * CPUs 3566 */ 3567 static void __init enable_cpu_capabilities(u16 scope_mask) 3568 { 3569 int i; 3570 const struct arm64_cpu_capabilities *caps; 3571 bool boot_scope; 3572 3573 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3574 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3575 3576 for (i = 0; i < ARM64_NCAPS; i++) { 3577 caps = cpucap_ptrs[i]; 3578 if (!caps || !(caps->type & scope_mask) || 3579 !cpus_have_cap(caps->capability)) 3580 continue; 3581 3582 if (boot_scope && caps->cpu_enable) 3583 /* 3584 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3585 * before any secondary CPU boots. Thus, each secondary 3586 * will enable the capability as appropriate via 3587 * check_local_cpu_capabilities(). The only exception is 3588 * the boot CPU, for which the capability must be 3589 * enabled here. This approach avoids costly 3590 * stop_machine() calls for this case. 3591 */ 3592 caps->cpu_enable(caps); 3593 } 3594 3595 /* 3596 * For all non-boot scope capabilities, use stop_machine() 3597 * as it schedules the work allowing us to modify PSTATE, 3598 * instead of on_each_cpu() which uses an IPI, giving us a 3599 * PSTATE that disappears when we return. 3600 */ 3601 if (!boot_scope) 3602 stop_machine(cpu_enable_non_boot_scope_capabilities, 3603 NULL, cpu_online_mask); 3604 } 3605 3606 /* 3607 * Run through the list of capabilities to check for conflicts. 3608 * If the system has already detected a capability, take necessary 3609 * action on this CPU. 3610 */ 3611 static void verify_local_cpu_caps(u16 scope_mask) 3612 { 3613 int i; 3614 bool cpu_has_cap, system_has_cap; 3615 const struct arm64_cpu_capabilities *caps; 3616 3617 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3618 3619 for (i = 0; i < ARM64_NCAPS; i++) { 3620 caps = cpucap_ptrs[i]; 3621 if (!caps || !(caps->type & scope_mask)) 3622 continue; 3623 3624 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3625 system_has_cap = cpus_have_cap(caps->capability); 3626 3627 if (system_has_cap) { 3628 /* 3629 * Check if the new CPU misses an advertised feature, 3630 * which is not safe to miss. 3631 */ 3632 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3633 break; 3634 /* 3635 * We have to issue cpu_enable() irrespective of 3636 * whether the CPU has it or not, as it is enabeld 3637 * system wide. It is upto the call back to take 3638 * appropriate action on this CPU. 3639 */ 3640 if (caps->cpu_enable) 3641 caps->cpu_enable(caps); 3642 } else { 3643 /* 3644 * Check if the CPU has this capability if it isn't 3645 * safe to have when the system doesn't. 3646 */ 3647 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3648 break; 3649 } 3650 } 3651 3652 if (i < ARM64_NCAPS) { 3653 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3654 smp_processor_id(), caps->capability, 3655 caps->desc, system_has_cap, cpu_has_cap); 3656 3657 if (cpucap_panic_on_conflict(caps)) 3658 cpu_panic_kernel(); 3659 else 3660 cpu_die_early(); 3661 } 3662 } 3663 3664 /* 3665 * Check for CPU features that are used in early boot 3666 * based on the Boot CPU value. 3667 */ 3668 static void check_early_cpu_features(void) 3669 { 3670 verify_cpu_asid_bits(); 3671 3672 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3673 } 3674 3675 static void 3676 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3677 { 3678 3679 for (; caps->matches; caps++) 3680 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3681 pr_crit("CPU%d: missing HWCAP: %s\n", 3682 smp_processor_id(), caps->desc); 3683 cpu_die_early(); 3684 } 3685 } 3686 3687 static void verify_local_elf_hwcaps(void) 3688 { 3689 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3690 3691 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3692 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3693 } 3694 3695 static void verify_sve_features(void) 3696 { 3697 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3698 3699 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3700 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3701 smp_processor_id()); 3702 cpu_die_early(); 3703 } 3704 3705 cpacr_restore(cpacr); 3706 } 3707 3708 static void verify_sme_features(void) 3709 { 3710 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3711 3712 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3713 pr_crit("CPU%d: SME: vector length support mismatch\n", 3714 smp_processor_id()); 3715 cpu_die_early(); 3716 } 3717 3718 cpacr_restore(cpacr); 3719 } 3720 3721 static void verify_hyp_capabilities(void) 3722 { 3723 u64 safe_mmfr1, mmfr0, mmfr1; 3724 int parange, ipa_max; 3725 unsigned int safe_vmid_bits, vmid_bits; 3726 3727 if (!IS_ENABLED(CONFIG_KVM)) 3728 return; 3729 3730 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3731 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3732 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3733 3734 /* Verify VMID bits */ 3735 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3736 vmid_bits = get_vmid_bits(mmfr1); 3737 if (vmid_bits < safe_vmid_bits) { 3738 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3739 cpu_die_early(); 3740 } 3741 3742 /* Verify IPA range */ 3743 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3744 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3745 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3746 if (ipa_max < get_kvm_ipa_limit()) { 3747 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3748 cpu_die_early(); 3749 } 3750 } 3751 3752 static void verify_mpam_capabilities(void) 3753 { 3754 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3755 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3756 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3757 3758 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3759 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3760 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3761 cpu_die_early(); 3762 } 3763 3764 cpu_idr = read_cpuid(MPAMIDR_EL1); 3765 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3766 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3767 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3768 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3769 cpu_die_early(); 3770 } 3771 3772 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3773 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3774 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3775 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3776 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3777 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3778 cpu_die_early(); 3779 } 3780 } 3781 3782 /* 3783 * Run through the enabled system capabilities and enable() it on this CPU. 3784 * The capabilities were decided based on the available CPUs at the boot time. 3785 * Any new CPU should match the system wide status of the capability. If the 3786 * new CPU doesn't have a capability which the system now has enabled, we 3787 * cannot do anything to fix it up and could cause unexpected failures. So 3788 * we park the CPU. 3789 */ 3790 static void verify_local_cpu_capabilities(void) 3791 { 3792 /* 3793 * The capabilities with SCOPE_BOOT_CPU are checked from 3794 * check_early_cpu_features(), as they need to be verified 3795 * on all secondary CPUs. 3796 */ 3797 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3798 verify_local_elf_hwcaps(); 3799 3800 if (system_supports_sve()) 3801 verify_sve_features(); 3802 3803 if (system_supports_sme()) 3804 verify_sme_features(); 3805 3806 if (is_hyp_mode_available()) 3807 verify_hyp_capabilities(); 3808 3809 if (system_supports_mpam()) 3810 verify_mpam_capabilities(); 3811 } 3812 3813 void check_local_cpu_capabilities(void) 3814 { 3815 /* 3816 * All secondary CPUs should conform to the early CPU features 3817 * in use by the kernel based on boot CPU. 3818 */ 3819 check_early_cpu_features(); 3820 3821 /* 3822 * If we haven't finalised the system capabilities, this CPU gets 3823 * a chance to update the errata work arounds and local features. 3824 * Otherwise, this CPU should verify that it has all the system 3825 * advertised capabilities. 3826 */ 3827 if (!system_capabilities_finalized()) 3828 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3829 else 3830 verify_local_cpu_capabilities(); 3831 } 3832 3833 bool this_cpu_has_cap(unsigned int n) 3834 { 3835 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3836 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3837 3838 if (cap) 3839 return cap->matches(cap, SCOPE_LOCAL_CPU); 3840 } 3841 3842 return false; 3843 } 3844 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3845 3846 /* 3847 * This helper function is used in a narrow window when, 3848 * - The system wide safe registers are set with all the SMP CPUs and, 3849 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3850 */ 3851 static bool __maybe_unused __system_matches_cap(unsigned int n) 3852 { 3853 if (n < ARM64_NCAPS) { 3854 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3855 3856 if (cap) 3857 return cap->matches(cap, SCOPE_SYSTEM); 3858 } 3859 return false; 3860 } 3861 3862 void cpu_set_feature(unsigned int num) 3863 { 3864 set_bit(num, elf_hwcap); 3865 } 3866 3867 bool cpu_have_feature(unsigned int num) 3868 { 3869 return test_bit(num, elf_hwcap); 3870 } 3871 EXPORT_SYMBOL_GPL(cpu_have_feature); 3872 3873 unsigned long cpu_get_elf_hwcap(void) 3874 { 3875 /* 3876 * We currently only populate the first 32 bits of AT_HWCAP. Please 3877 * note that for userspace compatibility we guarantee that bits 62 3878 * and 63 will always be returned as 0. 3879 */ 3880 return elf_hwcap[0]; 3881 } 3882 3883 unsigned long cpu_get_elf_hwcap2(void) 3884 { 3885 return elf_hwcap[1]; 3886 } 3887 3888 unsigned long cpu_get_elf_hwcap3(void) 3889 { 3890 return elf_hwcap[2]; 3891 } 3892 3893 static void __init setup_boot_cpu_capabilities(void) 3894 { 3895 kvm_arm_target_impl_cpu_init(); 3896 /* 3897 * The boot CPU's feature register values have been recorded. Detect 3898 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3899 * patch alternatives for the available boot cpucaps. 3900 */ 3901 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3902 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3903 apply_boot_alternatives(); 3904 } 3905 3906 void __init setup_boot_cpu_features(void) 3907 { 3908 /* 3909 * Initialize the indirect array of CPU capabilities pointers before we 3910 * handle the boot CPU. 3911 */ 3912 init_cpucap_indirect_list(); 3913 3914 /* 3915 * Detect broken pseudo-NMI. Must be called _before_ the call to 3916 * setup_boot_cpu_capabilities() since it interacts with 3917 * can_use_gic_priorities(). 3918 */ 3919 detect_system_supports_pseudo_nmi(); 3920 3921 setup_boot_cpu_capabilities(); 3922 } 3923 3924 static void __init setup_system_capabilities(void) 3925 { 3926 /* 3927 * The system-wide safe feature register values have been finalized. 3928 * Detect, enable, and patch alternatives for the available system 3929 * cpucaps. 3930 */ 3931 update_cpu_capabilities(SCOPE_SYSTEM); 3932 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3933 apply_alternatives_all(); 3934 3935 for (int i = 0; i < ARM64_NCAPS; i++) { 3936 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3937 3938 if (!caps || !caps->desc) 3939 continue; 3940 3941 /* 3942 * Log any cpucaps with a cpumask as these aren't logged by 3943 * update_cpu_capabilities(). 3944 */ 3945 if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids) 3946 pr_info("detected: %s on CPU%*pbl\n", 3947 caps->desc, cpumask_pr_args(caps->cpus)); 3948 3949 /* Log match-all CPUs capabilities */ 3950 if (cpucap_match_all_early_cpus(caps) && 3951 cpus_have_cap(caps->capability)) 3952 pr_info("detected: %s\n", caps->desc); 3953 } 3954 3955 /* 3956 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3957 */ 3958 if (system_uses_ttbr0_pan()) 3959 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3960 3961 /* 3962 * Report Spectre mitigations status. 3963 */ 3964 spectre_print_disabled_mitigations(); 3965 } 3966 3967 void __init setup_system_features(void) 3968 { 3969 setup_system_capabilities(); 3970 3971 linear_map_maybe_split_to_ptes(); 3972 kpti_install_ng_mappings(); 3973 3974 sve_setup(); 3975 sme_setup(); 3976 3977 /* 3978 * Check for sane CTR_EL0.CWG value. 3979 */ 3980 if (!cache_type_cwg()) 3981 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3982 ARCH_DMA_MINALIGN); 3983 } 3984 3985 void __init setup_user_features(void) 3986 { 3987 user_feature_fixup(); 3988 3989 setup_elf_hwcaps(arm64_elf_hwcaps); 3990 3991 if (system_supports_32bit_el0()) { 3992 setup_elf_hwcaps(compat_elf_hwcaps); 3993 elf_hwcap_fixup(); 3994 } 3995 3996 minsigstksz_setup(); 3997 } 3998 3999 static int enable_mismatched_32bit_el0(unsigned int cpu) 4000 { 4001 /* 4002 * The first 32-bit-capable CPU we detected and so can no longer 4003 * be offlined by userspace. -1 indicates we haven't yet onlined 4004 * a 32-bit-capable CPU. 4005 */ 4006 static int lucky_winner = -1; 4007 4008 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 4009 bool cpu_32bit = false; 4010 4011 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 4012 if (!housekeeping_cpu(cpu, HK_TYPE_DOMAIN)) 4013 pr_info("Treating domain isolated CPU %u as 64-bit only\n", cpu); 4014 else 4015 cpu_32bit = true; 4016 } 4017 4018 if (cpu_32bit) { 4019 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 4020 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 4021 } 4022 4023 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 4024 return 0; 4025 4026 if (lucky_winner >= 0) 4027 return 0; 4028 4029 /* 4030 * We've detected a mismatch. We need to keep one of our CPUs with 4031 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 4032 * every CPU in the system for a 32-bit task. 4033 */ 4034 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 4035 cpu_active_mask); 4036 get_cpu_device(lucky_winner)->offline_disabled = true; 4037 setup_elf_hwcaps(compat_elf_hwcaps); 4038 elf_hwcap_fixup(); 4039 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 4040 cpu, lucky_winner); 4041 return 0; 4042 } 4043 4044 static int __init init_32bit_el0_mask(void) 4045 { 4046 if (!allow_mismatched_32bit_el0) 4047 return 0; 4048 4049 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 4050 return -ENOMEM; 4051 4052 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 4053 "arm64/mismatched_32bit_el0:online", 4054 enable_mismatched_32bit_el0, NULL); 4055 } 4056 subsys_initcall_sync(init_32bit_el0_mask); 4057 4058 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 4059 { 4060 cpu_enable_swapper_cnp(); 4061 } 4062 4063 /* 4064 * We emulate only the following system register space. 4065 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 4066 * See Table C5-6 System instruction encodings for System register accesses, 4067 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 4068 */ 4069 static inline bool __attribute_const__ is_emulated(u32 id) 4070 { 4071 return (sys_reg_Op0(id) == 0x3 && 4072 sys_reg_CRn(id) == 0x0 && 4073 sys_reg_Op1(id) == 0x0 && 4074 (sys_reg_CRm(id) == 0 || 4075 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 4076 } 4077 4078 /* 4079 * With CRm == 0, reg should be one of : 4080 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 4081 */ 4082 static inline int emulate_id_reg(u32 id, u64 *valp) 4083 { 4084 switch (id) { 4085 case SYS_MIDR_EL1: 4086 *valp = read_cpuid_id(); 4087 break; 4088 case SYS_MPIDR_EL1: 4089 *valp = SYS_MPIDR_SAFE_VAL; 4090 break; 4091 case SYS_REVIDR_EL1: 4092 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 4093 *valp = 0; 4094 break; 4095 default: 4096 return -EINVAL; 4097 } 4098 4099 return 0; 4100 } 4101 4102 static int emulate_sys_reg(u32 id, u64 *valp) 4103 { 4104 struct arm64_ftr_reg *regp; 4105 4106 if (!is_emulated(id)) 4107 return -EINVAL; 4108 4109 if (sys_reg_CRm(id) == 0) 4110 return emulate_id_reg(id, valp); 4111 4112 regp = get_arm64_ftr_reg_nowarn(id); 4113 if (regp) 4114 *valp = arm64_ftr_reg_user_value(regp); 4115 else 4116 /* 4117 * The untracked registers are either IMPLEMENTATION DEFINED 4118 * (e.g, ID_AFR0_EL1) or reserved RAZ. 4119 */ 4120 *valp = 0; 4121 return 0; 4122 } 4123 4124 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 4125 { 4126 int rc; 4127 u64 val; 4128 4129 rc = emulate_sys_reg(sys_reg, &val); 4130 if (!rc) { 4131 pt_regs_write_reg(regs, rt, val); 4132 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 4133 } 4134 return rc; 4135 } 4136 4137 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 4138 { 4139 u32 sys_reg, rt; 4140 4141 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 4142 return false; 4143 4144 /* 4145 * sys_reg values are defined as used in mrs/msr instruction. 4146 * shift the imm value to get the encoding. 4147 */ 4148 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 4149 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 4150 return do_emulate_mrs(regs, sys_reg, rt) == 0; 4151 } 4152 4153 enum mitigation_state arm64_get_meltdown_state(void) 4154 { 4155 if (__meltdown_safe) 4156 return SPECTRE_UNAFFECTED; 4157 4158 if (arm64_kernel_unmapped_at_el0()) 4159 return SPECTRE_MITIGATED; 4160 4161 return SPECTRE_VULNERABLE; 4162 } 4163 4164 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 4165 char *buf) 4166 { 4167 switch (arm64_get_meltdown_state()) { 4168 case SPECTRE_UNAFFECTED: 4169 return sprintf(buf, "Not affected\n"); 4170 4171 case SPECTRE_MITIGATED: 4172 return sprintf(buf, "Mitigation: PTI\n"); 4173 4174 default: 4175 return sprintf(buf, "Vulnerable\n"); 4176 } 4177 } 4178