1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * mtip32xx.h - Header file for the P320 SSD Block Driver 4 * Copyright (C) 2011 Micron Technology, Inc. 5 * 6 * Portions of this code were derived from works subjected to the 7 * following copyright: 8 * Copyright (C) 2009 Integrated Device Technology, Inc. 9 */ 10 11 #ifndef __MTIP32XX_H__ 12 #define __MTIP32XX_H__ 13 14 #include <linux/spinlock.h> 15 #include <linux/mutex.h> 16 #include <linux/rwsem.h> 17 #include <linux/ata.h> 18 #include <linux/interrupt.h> 19 20 /* Offset of Subsystem Device ID in pci confoguration space */ 21 #define PCI_SUBSYSTEM_DEVICEID 0x2E 22 23 /* offset of Device Control register in PCIe extended capabilites space */ 24 #define PCIE_CONFIG_EXT_DEVICE_CONTROL_OFFSET 0x48 25 26 /* check for erase mode support during secure erase */ 27 #define MTIP_SEC_ERASE_MODE 0x2 28 29 /* # of times to retry timed out/failed IOs */ 30 #define MTIP_MAX_RETRIES 2 31 32 /* Various timeout values in ms */ 33 #define MTIP_NCQ_CMD_TIMEOUT_MS 15000 34 #define MTIP_IOCTL_CMD_TIMEOUT_MS 5000 35 #define MTIP_INT_CMD_TIMEOUT_MS 5000 36 #define MTIP_QUIESCE_IO_TIMEOUT_MS (MTIP_NCQ_CMD_TIMEOUT_MS * \ 37 (MTIP_MAX_RETRIES + 1)) 38 39 /* check for timeouts every 500ms */ 40 #define MTIP_TIMEOUT_CHECK_PERIOD 500 41 42 /* ftl rebuild */ 43 #define MTIP_FTL_REBUILD_OFFSET 142 44 #define MTIP_FTL_REBUILD_MAGIC 0xED51 45 #define MTIP_FTL_REBUILD_TIMEOUT_MS 2400000 46 47 /* unaligned IO handling */ 48 #define MTIP_MAX_UNALIGNED_SLOTS 2 49 50 /* Macro to extract the tag bit number from a tag value. */ 51 #define MTIP_TAG_BIT(tag) (tag & 0x1F) 52 53 /* 54 * Macro to extract the tag index from a tag value. The index 55 * is used to access the correct s_active/Command Issue register based 56 * on the tag value. 57 */ 58 #define MTIP_TAG_INDEX(tag) (tag >> 5) 59 60 /* 61 * Maximum number of scatter gather entries 62 * a single command may have. 63 */ 64 #define MTIP_MAX_SG 504 65 66 /* 67 * Maximum number of slot groups (Command Issue & s_active registers) 68 * NOTE: This is the driver maximum; check dd->slot_groups for actual value. 69 */ 70 #define MTIP_MAX_SLOT_GROUPS 8 71 72 /* Internal command tag. */ 73 #define MTIP_TAG_INTERNAL 0 74 75 /* Micron Vendor ID & P320x SSD Device ID */ 76 #define PCI_VENDOR_ID_MICRON 0x1344 77 #define P320H_DEVICE_ID 0x5150 78 #define P320M_DEVICE_ID 0x5151 79 #define P320S_DEVICE_ID 0x5152 80 #define P325M_DEVICE_ID 0x5153 81 #define P420H_DEVICE_ID 0x5160 82 #define P420M_DEVICE_ID 0x5161 83 #define P425M_DEVICE_ID 0x5163 84 85 /* Driver name and version strings */ 86 #define MTIP_DRV_NAME "mtip32xx" 87 #define MTIP_DRV_VERSION "1.3.1" 88 89 /* Maximum number of minor device numbers per device. */ 90 #define MTIP_MAX_MINORS 16 91 92 /* Maximum number of supported command slots. */ 93 #define MTIP_MAX_COMMAND_SLOTS (MTIP_MAX_SLOT_GROUPS * 32) 94 95 /* 96 * Per-tag bitfield size in longs. 97 * Linux bit manipulation functions 98 * (i.e. test_and_set_bit, find_next_zero_bit) 99 * manipulate memory in longs, so we try to make the math work. 100 * take the slot groups and find the number of longs, rounding up. 101 * Careful! i386 and x86_64 use different size longs! 102 */ 103 #define U32_PER_LONG (sizeof(long) / sizeof(u32)) 104 #define SLOTBITS_IN_LONGS ((MTIP_MAX_SLOT_GROUPS + \ 105 (U32_PER_LONG-1))/U32_PER_LONG) 106 107 /* BAR number used to access the HBA registers. */ 108 #define MTIP_ABAR 5 109 110 #ifdef DEBUG 111 #define dbg_printk(format, arg...) \ 112 printk(pr_fmt(format), ##arg); 113 #else 114 #define dbg_printk(format, arg...) 115 #endif 116 117 #define MTIP_DFS_MAX_BUF_SIZE 1024 118 119 enum { 120 /* below are bit numbers in 'flags' defined in mtip_port */ 121 MTIP_PF_IC_ACTIVE_BIT = 0, /* pio/ioctl */ 122 MTIP_PF_EH_ACTIVE_BIT = 1, /* error handling */ 123 MTIP_PF_SE_ACTIVE_BIT = 2, /* secure erase */ 124 MTIP_PF_DM_ACTIVE_BIT = 3, /* download microcde */ 125 MTIP_PF_TO_ACTIVE_BIT = 9, /* timeout handling */ 126 MTIP_PF_PAUSE_IO = ((1 << MTIP_PF_IC_ACTIVE_BIT) | 127 (1 << MTIP_PF_EH_ACTIVE_BIT) | 128 (1 << MTIP_PF_SE_ACTIVE_BIT) | 129 (1 << MTIP_PF_DM_ACTIVE_BIT) | 130 (1 << MTIP_PF_TO_ACTIVE_BIT)), 131 MTIP_PF_HOST_CAP_64 = 10, /* cache HOST_CAP_64 */ 132 133 MTIP_PF_SVC_THD_ACTIVE_BIT = 4, 134 MTIP_PF_ISSUE_CMDS_BIT = 5, 135 MTIP_PF_REBUILD_BIT = 6, 136 MTIP_PF_SVC_THD_STOP_BIT = 8, 137 138 MTIP_PF_SVC_THD_WORK = ((1 << MTIP_PF_EH_ACTIVE_BIT) | 139 (1 << MTIP_PF_ISSUE_CMDS_BIT) | 140 (1 << MTIP_PF_REBUILD_BIT) | 141 (1 << MTIP_PF_SVC_THD_STOP_BIT) | 142 (1 << MTIP_PF_TO_ACTIVE_BIT)), 143 144 /* below are bit numbers in 'dd_flag' defined in driver_data */ 145 MTIP_DDF_SEC_LOCK_BIT = 0, 146 MTIP_DDF_REMOVE_PENDING_BIT = 1, 147 MTIP_DDF_OVER_TEMP_BIT = 2, 148 MTIP_DDF_WRITE_PROTECT_BIT = 3, 149 MTIP_DDF_CLEANUP_BIT = 5, 150 MTIP_DDF_RESUME_BIT = 6, 151 MTIP_DDF_INIT_DONE_BIT = 7, 152 MTIP_DDF_REBUILD_FAILED_BIT = 8, 153 154 MTIP_DDF_STOP_IO = ((1 << MTIP_DDF_REMOVE_PENDING_BIT) | 155 (1 << MTIP_DDF_SEC_LOCK_BIT) | 156 (1 << MTIP_DDF_OVER_TEMP_BIT) | 157 (1 << MTIP_DDF_WRITE_PROTECT_BIT) | 158 (1 << MTIP_DDF_REBUILD_FAILED_BIT)), 159 160 }; 161 162 struct smart_attr { 163 u8 attr_id; 164 __le16 flags; 165 u8 cur; 166 u8 worst; 167 __le32 data; 168 u8 res[3]; 169 } __packed; 170 171 struct mtip_work { 172 struct work_struct work; 173 void *port; 174 int cpu_binding; 175 u32 completed; 176 } ____cacheline_aligned_in_smp; 177 178 #define DEFINE_HANDLER(group) \ 179 void mtip_workq_sdbf##group(struct work_struct *work) \ 180 { \ 181 struct mtip_work *w = (struct mtip_work *) work; \ 182 mtip_workq_sdbfx(w->port, group, w->completed); \ 183 } 184 185 /* Register Frame Information Structure (FIS), host to device. */ 186 struct host_to_dev_fis { 187 /* 188 * FIS type. 189 * - 27h Register FIS, host to device. 190 * - 34h Register FIS, device to host. 191 * - 39h DMA Activate FIS, device to host. 192 * - 41h DMA Setup FIS, bi-directional. 193 * - 46h Data FIS, bi-directional. 194 * - 58h BIST Activate FIS, bi-directional. 195 * - 5Fh PIO Setup FIS, device to host. 196 * - A1h Set Device Bits FIS, device to host. 197 */ 198 unsigned char type; 199 unsigned char opts; 200 unsigned char command; 201 unsigned char features; 202 203 union { 204 unsigned char lba_low; 205 unsigned char sector; 206 }; 207 union { 208 unsigned char lba_mid; 209 unsigned char cyl_low; 210 }; 211 union { 212 unsigned char lba_hi; 213 unsigned char cyl_hi; 214 }; 215 union { 216 unsigned char device; 217 unsigned char head; 218 }; 219 220 union { 221 unsigned char lba_low_ex; 222 unsigned char sector_ex; 223 }; 224 union { 225 unsigned char lba_mid_ex; 226 unsigned char cyl_low_ex; 227 }; 228 union { 229 unsigned char lba_hi_ex; 230 unsigned char cyl_hi_ex; 231 }; 232 unsigned char features_ex; 233 234 unsigned char sect_count; 235 unsigned char sect_cnt_ex; 236 unsigned char res2; 237 unsigned char control; 238 239 unsigned int res3; 240 }; 241 242 /* Command header structure. */ 243 struct mtip_cmd_hdr { 244 /* 245 * Command options. 246 * - Bits 31:16 Number of PRD entries. 247 * - Bits 15:8 Unused in this implementation. 248 * - Bit 7 Prefetch bit, informs the drive to prefetch PRD entries. 249 * - Bit 6 Write bit, should be set when writing data to the device. 250 * - Bit 5 Unused in this implementation. 251 * - Bits 4:0 Length of the command FIS in DWords (DWord = 4 bytes). 252 */ 253 __le32 opts; 254 /* This field is unsed when using NCQ. */ 255 union { 256 __le32 byte_count; 257 __le32 status; 258 }; 259 /* 260 * Lower 32 bits of the command table address associated with this 261 * header. The command table addresses must be 128 byte aligned. 262 */ 263 __le32 ctba; 264 /* 265 * If 64 bit addressing is used this field is the upper 32 bits 266 * of the command table address associated with this command. 267 */ 268 __le32 ctbau; 269 /* Reserved and unused. */ 270 u32 res[4]; 271 }; 272 273 /* Command scatter gather structure (PRD). */ 274 struct mtip_cmd_sg { 275 /* 276 * Low 32 bits of the data buffer address. For P320 this 277 * address must be 8 byte aligned signified by bits 2:0 being 278 * set to 0. 279 */ 280 __le32 dba; 281 /* 282 * When 64 bit addressing is used this field is the upper 283 * 32 bits of the data buffer address. 284 */ 285 __le32 dba_upper; 286 /* Unused. */ 287 __le32 reserved; 288 /* 289 * Bit 31: interrupt when this data block has been transferred. 290 * Bits 30..22: reserved 291 * Bits 21..0: byte count (minus 1). For P320 the byte count must be 292 * 8 byte aligned signified by bits 2:0 being set to 1. 293 */ 294 __le32 info; 295 }; 296 struct mtip_port; 297 298 struct mtip_int_cmd; 299 300 /* Structure used to describe a command. */ 301 struct mtip_cmd { 302 void *command; /* ptr to command table entry */ 303 304 dma_addr_t command_dma; /* corresponding physical address */ 305 306 int scatter_ents; /* Number of scatter list entries used */ 307 308 int unaligned; /* command is unaligned on 4k boundary */ 309 310 union { 311 struct scatterlist sg[MTIP_MAX_SG]; /* Scatter list entries */ 312 struct mtip_int_cmd *icmd; 313 }; 314 315 int retries; /* The number of retries left for this command. */ 316 317 int direction; /* Data transfer direction */ 318 blk_status_t status; 319 }; 320 321 /* Structure used to describe a port. */ 322 struct mtip_port { 323 /* Pointer back to the driver data for this port. */ 324 struct driver_data *dd; 325 /* 326 * Used to determine if the data pointed to by the 327 * identify field is valid. 328 */ 329 unsigned long identify_valid; 330 /* Base address of the memory mapped IO for the port. */ 331 void __iomem *mmio; 332 /* Array of pointers to the memory mapped s_active registers. */ 333 void __iomem *s_active[MTIP_MAX_SLOT_GROUPS]; 334 /* Array of pointers to the memory mapped completed registers. */ 335 void __iomem *completed[MTIP_MAX_SLOT_GROUPS]; 336 /* Array of pointers to the memory mapped Command Issue registers. */ 337 void __iomem *cmd_issue[MTIP_MAX_SLOT_GROUPS]; 338 /* 339 * Pointer to the beginning of the command header memory as used 340 * by the driver. 341 */ 342 void *command_list; 343 /* 344 * Pointer to the beginning of the command header memory as used 345 * by the DMA. 346 */ 347 dma_addr_t command_list_dma; 348 /* 349 * Pointer to the beginning of the RX FIS memory as used 350 * by the driver. 351 */ 352 void *rxfis; 353 /* 354 * Pointer to the beginning of the RX FIS memory as used 355 * by the DMA. 356 */ 357 dma_addr_t rxfis_dma; 358 /* 359 * Pointer to the DMA region for RX Fis, Identify, RLE10, and SMART 360 */ 361 void *block1; 362 /* 363 * DMA address of region for RX Fis, Identify, RLE10, and SMART 364 */ 365 dma_addr_t block1_dma; 366 /* 367 * Pointer to the beginning of the identify data memory as used 368 * by the driver. 369 */ 370 u16 *identify; 371 /* 372 * Pointer to the beginning of the identify data memory as used 373 * by the DMA. 374 */ 375 dma_addr_t identify_dma; 376 /* 377 * Pointer to the beginning of a sector buffer that is used 378 * by the driver when issuing internal commands. 379 */ 380 u16 *sector_buffer; 381 /* 382 * Pointer to the beginning of a sector buffer that is used 383 * by the DMA when the driver issues internal commands. 384 */ 385 dma_addr_t sector_buffer_dma; 386 387 u16 *log_buf; 388 dma_addr_t log_buf_dma; 389 390 u8 *smart_buf; 391 dma_addr_t smart_buf_dma; 392 393 /* 394 * used to queue commands when an internal command is in progress 395 * or error handling is active 396 */ 397 unsigned long cmds_to_issue[SLOTBITS_IN_LONGS]; 398 /* Used by mtip_service_thread to wait for an event */ 399 wait_queue_head_t svc_wait; 400 /* 401 * indicates the state of the port. Also, helps the service thread 402 * to determine its action on wake up. 403 */ 404 unsigned long flags; 405 /* 406 * Timer used to complete commands that have been active for too long. 407 */ 408 unsigned long ic_pause_timer; 409 410 /* Counter to control queue depth of unaligned IOs */ 411 atomic_t cmd_slot_unal; 412 413 /* Spinlock for working around command-issue bug. */ 414 spinlock_t cmd_issue_lock[MTIP_MAX_SLOT_GROUPS]; 415 }; 416 417 /* 418 * Driver private data structure. 419 * 420 * One structure is allocated per probed device. 421 */ 422 struct driver_data { 423 void __iomem *mmio; /* Base address of the HBA registers. */ 424 425 int major; /* Major device number. */ 426 427 int instance; /* Instance number. First device probed is 0, ... */ 428 429 struct gendisk *disk; /* Pointer to our gendisk structure. */ 430 431 struct pci_dev *pdev; /* Pointer to the PCI device structure. */ 432 433 struct request_queue *queue; /* Our request queue. */ 434 435 struct blk_mq_tag_set tags; /* blk_mq tags */ 436 struct mutex ioctl_mutex; 437 438 struct mtip_port *port; /* Pointer to the port data structure. */ 439 440 unsigned product_type; /* magic value declaring the product type */ 441 442 unsigned slot_groups; /* number of slot groups the product supports */ 443 444 unsigned long index; /* Index to determine the disk name */ 445 446 unsigned long dd_flag; /* NOTE: use atomic bit operations on this */ 447 448 struct task_struct *mtip_svc_handler; /* task_struct of svc thd */ 449 450 struct dentry *dfs_node; 451 452 bool sr; 453 454 int numa_node; /* NUMA support */ 455 456 char workq_name[32]; 457 458 struct workqueue_struct *isr_workq; 459 460 atomic_t irq_workers_active; 461 462 struct mtip_work work[MTIP_MAX_SLOT_GROUPS]; 463 464 int isr_binding; 465 466 int unal_qdepth; /* qdepth of unaligned IO queue */ 467 }; 468 469 #endif 470