1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine
4 *
5 * Copyright (C) 2012 Texas Instruments
6 *
7 */
8 #include <linux/bitmap.h>
9 #include <linux/if_vlan.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/seq_file.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/stat.h>
19 #include <linux/sysfs.h>
20 #include <linux/etherdevice.h>
21
22 #include "cpsw_ale.h"
23
24 #define BITMASK(bits) (BIT(bits) - 1)
25
26 /* ALE Registers */
27 #define ALE_IDVER 0x00
28 #define ALE_STATUS 0x04
29 #define ALE_CONTROL 0x08
30 #define ALE_PRESCALE 0x10
31 #define ALE_AGING_TIMER 0x14
32 #define ALE_UNKNOWNVLAN 0x18
33 #define ALE_TABLE_CONTROL 0x20
34 #define ALE_TABLE 0x34
35 #define ALE_PORTCTL 0x40
36
37 /* ALE NetCP NU switch specific Registers */
38 #define ALE_UNKNOWNVLAN_MEMBER 0x90
39 #define ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD 0x94
40 #define ALE_UNKNOWNVLAN_REG_MCAST_FLOOD 0x98
41 #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS 0x9C
42 #define ALE_VLAN_MASK_MUX(reg) (0xc0 + (0x4 * (reg)))
43
44 #define ALE_POLICER_PORT_OUI 0x100
45 #define ALE_POLICER_DA_SA 0x104
46 #define ALE_POLICER_VLAN 0x108
47 #define ALE_POLICER_ETHERTYPE_IPSA 0x10c
48 #define ALE_POLICER_IPDA 0x110
49 #define ALE_POLICER_PIR 0x118
50 #define ALE_POLICER_CIR 0x11c
51 #define ALE_POLICER_TBL_CTL 0x120
52 #define ALE_POLICER_CTL 0x124
53 #define ALE_POLICER_TEST_CTL 0x128
54 #define ALE_POLICER_HIT_STATUS 0x12c
55 #define ALE_THREAD_DEF 0x134
56 #define ALE_THREAD_CTL 0x138
57 #define ALE_THREAD_VAL 0x13c
58
59 #define ALE_POLICER_TBL_WRITE_ENABLE BIT(31)
60 #define ALE_POLICER_TBL_INDEX_MASK GENMASK(4, 0)
61
62 #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134
63
64 /* ALE_AGING_TIMER */
65 #define ALE_AGING_TIMER_MASK GENMASK(23, 0)
66
67 #define ALE_RATE_LIMIT_MIN_PPS 1000
68
69 /**
70 * struct ale_entry_fld - The ALE tbl entry field description
71 * @start_bit: field start bit
72 * @num_bits: field bit length
73 * @flags: field flags
74 */
75 struct ale_entry_fld {
76 u8 start_bit;
77 u8 num_bits;
78 u8 flags;
79 };
80
81 enum {
82 CPSW_ALE_F_STATUS_REG = BIT(0), /* Status register present */
83 CPSW_ALE_F_HW_AUTOAGING = BIT(1), /* HW auto aging */
84
85 CPSW_ALE_F_COUNT
86 };
87
88 /**
89 * struct cpsw_ale_dev_id - The ALE version/SoC specific configuration
90 * @dev_id: ALE version/SoC id
91 * @features: features supported by ALE
92 * @tbl_entries: number of ALE entries
93 * @reg_fields: pointer to array of register field configuration
94 * @num_fields: number of fields in the reg_fields array
95 * @nu_switch_ale: NU Switch ALE
96 * @vlan_entry_tbl: ALE vlan entry fields description tbl
97 */
98 struct cpsw_ale_dev_id {
99 const char *dev_id;
100 u32 features;
101 u32 tbl_entries;
102 const struct reg_field *reg_fields;
103 int num_fields;
104 bool nu_switch_ale;
105 const struct ale_entry_fld *vlan_entry_tbl;
106 };
107
108 #define ALE_TABLE_WRITE BIT(31)
109
110 #define ALE_TYPE_FREE 0
111 #define ALE_TYPE_ADDR 1
112 #define ALE_TYPE_VLAN 2
113 #define ALE_TYPE_VLAN_ADDR 3
114
115 #define ALE_UCAST_PERSISTANT 0
116 #define ALE_UCAST_UNTOUCHED 1
117 #define ALE_UCAST_OUI 2
118 #define ALE_UCAST_TOUCHED 3
119
120 #define ALE_TABLE_SIZE_MULTIPLIER 1024
121 #define ALE_POLICER_SIZE_MULTIPLIER 8
122
cpsw_ale_get_field(u32 * ale_entry,u32 start,u32 bits)123 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
124 {
125 int idx, idx2, index;
126 u32 hi_val = 0;
127
128 idx = start / 32;
129 idx2 = (start + bits - 1) / 32;
130 /* Check if bits to be fetched exceed a word */
131 if (idx != idx2) {
132 index = 2 - idx2; /* flip */
133 hi_val = ale_entry[index] << ((idx2 * 32) - start);
134 }
135 start -= idx * 32;
136 idx = 2 - idx; /* flip */
137 return (hi_val + (ale_entry[idx] >> start)) & BITMASK(bits);
138 }
139
cpsw_ale_set_field(u32 * ale_entry,u32 start,u32 bits,u32 value)140 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
141 u32 value)
142 {
143 int idx, idx2, index;
144
145 value &= BITMASK(bits);
146 idx = start / 32;
147 idx2 = (start + bits - 1) / 32;
148 /* Check if bits to be set exceed a word */
149 if (idx != idx2) {
150 index = 2 - idx2; /* flip */
151 ale_entry[index] &= ~(BITMASK(bits + start - (idx2 * 32)));
152 ale_entry[index] |= (value >> ((idx2 * 32) - start));
153 }
154 start -= idx * 32;
155 idx = 2 - idx; /* flip */
156 ale_entry[idx] &= ~(BITMASK(bits) << start);
157 ale_entry[idx] |= (value << start);
158 }
159
160 #define DEFINE_ALE_FIELD_GET(name, start, bits) \
161 static inline int cpsw_ale_get_##name(u32 *ale_entry) \
162 { \
163 return cpsw_ale_get_field(ale_entry, start, bits); \
164 }
165
166 #define DEFINE_ALE_FIELD_SET(name, start, bits) \
167 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
168 { \
169 cpsw_ale_set_field(ale_entry, start, bits, value); \
170 }
171
172 #define DEFINE_ALE_FIELD(name, start, bits) \
173 DEFINE_ALE_FIELD_GET(name, start, bits) \
174 DEFINE_ALE_FIELD_SET(name, start, bits)
175
176 #define DEFINE_ALE_FIELD1_GET(name, start) \
177 static inline int cpsw_ale_get_##name(u32 *ale_entry, u32 bits) \
178 { \
179 return cpsw_ale_get_field(ale_entry, start, bits); \
180 }
181
182 #define DEFINE_ALE_FIELD1_SET(name, start) \
183 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value, \
184 u32 bits) \
185 { \
186 cpsw_ale_set_field(ale_entry, start, bits, value); \
187 }
188
189 #define DEFINE_ALE_FIELD1(name, start) \
190 DEFINE_ALE_FIELD1_GET(name, start) \
191 DEFINE_ALE_FIELD1_SET(name, start)
192
193 enum {
194 ALE_ENT_VID_MEMBER_LIST = 0,
195 ALE_ENT_VID_UNREG_MCAST_MSK,
196 ALE_ENT_VID_REG_MCAST_MSK,
197 ALE_ENT_VID_FORCE_UNTAGGED_MSK,
198 ALE_ENT_VID_UNREG_MCAST_IDX,
199 ALE_ENT_VID_REG_MCAST_IDX,
200 ALE_ENT_VID_LAST,
201 };
202
203 #define ALE_FLD_ALLOWED BIT(0)
204 #define ALE_FLD_SIZE_PORT_MASK_BITS BIT(1)
205 #define ALE_FLD_SIZE_PORT_NUM_BITS BIT(2)
206
207 #define ALE_ENTRY_FLD(id, start, bits) \
208 [id] = { \
209 .start_bit = start, \
210 .num_bits = bits, \
211 .flags = ALE_FLD_ALLOWED, \
212 }
213
214 #define ALE_ENTRY_FLD_DYN_MSK_SIZE(id, start) \
215 [id] = { \
216 .start_bit = start, \
217 .num_bits = 0, \
218 .flags = ALE_FLD_ALLOWED | \
219 ALE_FLD_SIZE_PORT_MASK_BITS, \
220 }
221
222 /* dm814x, am3/am4/am5, k2hk */
223 static const struct ale_entry_fld vlan_entry_cpsw[ALE_ENT_VID_LAST] = {
224 ALE_ENTRY_FLD(ALE_ENT_VID_MEMBER_LIST, 0, 3),
225 ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_MSK, 8, 3),
226 ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_MSK, 16, 3),
227 ALE_ENTRY_FLD(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24, 3),
228 };
229
230 /* k2e/k2l, k3 am65/j721e cpsw2g */
231 static const struct ale_entry_fld vlan_entry_nu[ALE_ENT_VID_LAST] = {
232 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_MEMBER_LIST, 0),
233 ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_IDX, 20, 3),
234 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24),
235 ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_IDX, 44, 3),
236 };
237
238 /* K3 j721e/j7200 cpsw9g/5g, am64x cpsw3g */
239 static const struct ale_entry_fld vlan_entry_k3_cpswxg[] = {
240 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_MEMBER_LIST, 0),
241 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_UNREG_MCAST_MSK, 12),
242 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24),
243 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_REG_MCAST_MSK, 36),
244 };
245
246 DEFINE_ALE_FIELD(entry_type, 60, 2)
247 DEFINE_ALE_FIELD(vlan_id, 48, 12)
248 DEFINE_ALE_FIELD_SET(mcast_state, 62, 2)
249 DEFINE_ALE_FIELD1(port_mask, 66)
250 DEFINE_ALE_FIELD(super, 65, 1)
251 DEFINE_ALE_FIELD(ucast_type, 62, 2)
252 DEFINE_ALE_FIELD1_SET(port_num, 66)
253 DEFINE_ALE_FIELD_SET(blocked, 65, 1)
254 DEFINE_ALE_FIELD_SET(secure, 64, 1)
255 DEFINE_ALE_FIELD_GET(mcast, 40, 1)
256
257 #define NU_VLAN_UNREG_MCAST_IDX 1
258
cpsw_ale_entry_get_fld(struct cpsw_ale * ale,u32 * ale_entry,const struct ale_entry_fld * entry_tbl,int fld_id)259 static int cpsw_ale_entry_get_fld(struct cpsw_ale *ale,
260 u32 *ale_entry,
261 const struct ale_entry_fld *entry_tbl,
262 int fld_id)
263 {
264 const struct ale_entry_fld *entry_fld;
265 u32 bits;
266
267 if (!ale || !ale_entry)
268 return -EINVAL;
269
270 entry_fld = &entry_tbl[fld_id];
271 if (!(entry_fld->flags & ALE_FLD_ALLOWED)) {
272 dev_err(ale->params.dev, "get: wrong ale fld id %d\n", fld_id);
273 return -ENOENT;
274 }
275
276 bits = entry_fld->num_bits;
277 if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS)
278 bits = ale->port_mask_bits;
279
280 return cpsw_ale_get_field(ale_entry, entry_fld->start_bit, bits);
281 }
282
cpsw_ale_entry_set_fld(struct cpsw_ale * ale,u32 * ale_entry,const struct ale_entry_fld * entry_tbl,int fld_id,u32 value)283 static void cpsw_ale_entry_set_fld(struct cpsw_ale *ale,
284 u32 *ale_entry,
285 const struct ale_entry_fld *entry_tbl,
286 int fld_id,
287 u32 value)
288 {
289 const struct ale_entry_fld *entry_fld;
290 u32 bits;
291
292 if (!ale || !ale_entry)
293 return;
294
295 entry_fld = &entry_tbl[fld_id];
296 if (!(entry_fld->flags & ALE_FLD_ALLOWED)) {
297 dev_err(ale->params.dev, "set: wrong ale fld id %d\n", fld_id);
298 return;
299 }
300
301 bits = entry_fld->num_bits;
302 if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS)
303 bits = ale->port_mask_bits;
304
305 cpsw_ale_set_field(ale_entry, entry_fld->start_bit, bits, value);
306 }
307
cpsw_ale_vlan_get_fld(struct cpsw_ale * ale,u32 * ale_entry,int fld_id)308 static int cpsw_ale_vlan_get_fld(struct cpsw_ale *ale,
309 u32 *ale_entry,
310 int fld_id)
311 {
312 return cpsw_ale_entry_get_fld(ale, ale_entry,
313 ale->vlan_entry_tbl, fld_id);
314 }
315
cpsw_ale_vlan_set_fld(struct cpsw_ale * ale,u32 * ale_entry,int fld_id,u32 value)316 static void cpsw_ale_vlan_set_fld(struct cpsw_ale *ale,
317 u32 *ale_entry,
318 int fld_id,
319 u32 value)
320 {
321 cpsw_ale_entry_set_fld(ale, ale_entry,
322 ale->vlan_entry_tbl, fld_id, value);
323 }
324
325 /* The MAC address field in the ALE entry cannot be macroized as above */
cpsw_ale_get_addr(u32 * ale_entry,u8 * addr)326 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
327 {
328 int i;
329
330 for (i = 0; i < 6; i++)
331 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
332 }
333
cpsw_ale_set_addr(u32 * ale_entry,const u8 * addr)334 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
335 {
336 int i;
337
338 for (i = 0; i < 6; i++)
339 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
340 }
341
cpsw_ale_read(struct cpsw_ale * ale,int idx,u32 * ale_entry)342 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry)
343 {
344 int i;
345
346 WARN_ON(idx > ale->params.ale_entries);
347
348 writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL);
349
350 for (i = 0; i < ALE_ENTRY_WORDS; i++)
351 ale_entry[i] = readl_relaxed(ale->params.ale_regs +
352 ALE_TABLE + 4 * i);
353
354 return idx;
355 }
356
cpsw_ale_write(struct cpsw_ale * ale,int idx,u32 * ale_entry)357 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry)
358 {
359 int i;
360
361 WARN_ON(idx > ale->params.ale_entries);
362
363 for (i = 0; i < ALE_ENTRY_WORDS; i++)
364 writel_relaxed(ale_entry[i], ale->params.ale_regs +
365 ALE_TABLE + 4 * i);
366
367 writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs +
368 ALE_TABLE_CONTROL);
369
370 return idx;
371 }
372
cpsw_ale_match_addr(struct cpsw_ale * ale,const u8 * addr,u16 vid)373 static int cpsw_ale_match_addr(struct cpsw_ale *ale, const u8 *addr, u16 vid)
374 {
375 u32 ale_entry[ALE_ENTRY_WORDS];
376 int type, idx;
377
378 for (idx = 0; idx < ale->params.ale_entries; idx++) {
379 u8 entry_addr[6];
380
381 cpsw_ale_read(ale, idx, ale_entry);
382 type = cpsw_ale_get_entry_type(ale_entry);
383 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
384 continue;
385 if (cpsw_ale_get_vlan_id(ale_entry) != vid)
386 continue;
387 cpsw_ale_get_addr(ale_entry, entry_addr);
388 if (ether_addr_equal(entry_addr, addr))
389 return idx;
390 }
391 return -ENOENT;
392 }
393
cpsw_ale_match_vlan(struct cpsw_ale * ale,u16 vid)394 static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid)
395 {
396 u32 ale_entry[ALE_ENTRY_WORDS];
397 int type, idx;
398
399 for (idx = 0; idx < ale->params.ale_entries; idx++) {
400 cpsw_ale_read(ale, idx, ale_entry);
401 type = cpsw_ale_get_entry_type(ale_entry);
402 if (type != ALE_TYPE_VLAN)
403 continue;
404 if (cpsw_ale_get_vlan_id(ale_entry) == vid)
405 return idx;
406 }
407 return -ENOENT;
408 }
409
cpsw_ale_match_free(struct cpsw_ale * ale)410 static int cpsw_ale_match_free(struct cpsw_ale *ale)
411 {
412 u32 ale_entry[ALE_ENTRY_WORDS];
413 int type, idx;
414
415 for (idx = 0; idx < ale->params.ale_entries; idx++) {
416 cpsw_ale_read(ale, idx, ale_entry);
417 type = cpsw_ale_get_entry_type(ale_entry);
418 if (type == ALE_TYPE_FREE)
419 return idx;
420 }
421 return -ENOENT;
422 }
423
cpsw_ale_find_ageable(struct cpsw_ale * ale)424 static int cpsw_ale_find_ageable(struct cpsw_ale *ale)
425 {
426 u32 ale_entry[ALE_ENTRY_WORDS];
427 int type, idx;
428
429 for (idx = 0; idx < ale->params.ale_entries; idx++) {
430 cpsw_ale_read(ale, idx, ale_entry);
431 type = cpsw_ale_get_entry_type(ale_entry);
432 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
433 continue;
434 if (cpsw_ale_get_mcast(ale_entry))
435 continue;
436 type = cpsw_ale_get_ucast_type(ale_entry);
437 if (type != ALE_UCAST_PERSISTANT &&
438 type != ALE_UCAST_OUI)
439 return idx;
440 }
441 return -ENOENT;
442 }
443
cpsw_ale_flush_mcast(struct cpsw_ale * ale,u32 * ale_entry,int port_mask)444 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry,
445 int port_mask)
446 {
447 int mask;
448
449 mask = cpsw_ale_get_port_mask(ale_entry,
450 ale->port_mask_bits);
451 if ((mask & port_mask) == 0)
452 return; /* ports dont intersect, not interested */
453 mask &= (~port_mask | ALE_PORT_HOST);
454
455 if (mask == 0x0 || mask == ALE_PORT_HOST)
456 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
457 else
458 cpsw_ale_set_port_mask(ale_entry, mask,
459 ale->port_mask_bits);
460 }
461
cpsw_ale_flush_multicast(struct cpsw_ale * ale,int port_mask,int vid)462 int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid)
463 {
464 u32 ale_entry[ALE_ENTRY_WORDS];
465 int ret, idx;
466
467 for (idx = 0; idx < ale->params.ale_entries; idx++) {
468 cpsw_ale_read(ale, idx, ale_entry);
469 ret = cpsw_ale_get_entry_type(ale_entry);
470 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
471 continue;
472
473 /* if vid passed is -1 then remove all multicast entry from
474 * the table irrespective of vlan id, if a valid vlan id is
475 * passed then remove only multicast added to that vlan id.
476 * if vlan id doesn't match then move on to next entry.
477 */
478 if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid)
479 continue;
480
481 if (cpsw_ale_get_mcast(ale_entry)) {
482 u8 addr[6];
483
484 if (cpsw_ale_get_super(ale_entry))
485 continue;
486
487 cpsw_ale_get_addr(ale_entry, addr);
488 if (!is_broadcast_ether_addr(addr))
489 cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
490 }
491
492 cpsw_ale_write(ale, idx, ale_entry);
493 }
494 return 0;
495 }
496
cpsw_ale_set_vlan_entry_type(u32 * ale_entry,int flags,u16 vid)497 static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry,
498 int flags, u16 vid)
499 {
500 if (flags & ALE_VLAN) {
501 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
502 cpsw_ale_set_vlan_id(ale_entry, vid);
503 } else {
504 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
505 }
506 }
507
cpsw_ale_add_ucast(struct cpsw_ale * ale,const u8 * addr,int port,int flags,u16 vid)508 int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
509 int flags, u16 vid)
510 {
511 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
512 int idx;
513
514 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
515
516 cpsw_ale_set_addr(ale_entry, addr);
517 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
518 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
519 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
520 cpsw_ale_set_port_num(ale_entry, port, ale->port_num_bits);
521
522 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
523 if (idx < 0)
524 idx = cpsw_ale_match_free(ale);
525 if (idx < 0)
526 idx = cpsw_ale_find_ageable(ale);
527 if (idx < 0)
528 return -ENOMEM;
529
530 cpsw_ale_write(ale, idx, ale_entry);
531 return 0;
532 }
533
cpsw_ale_del_ucast(struct cpsw_ale * ale,const u8 * addr,int port,int flags,u16 vid)534 int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
535 int flags, u16 vid)
536 {
537 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
538 int idx;
539
540 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
541 if (idx < 0)
542 return -ENOENT;
543
544 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
545 cpsw_ale_write(ale, idx, ale_entry);
546 return 0;
547 }
548
cpsw_ale_add_mcast(struct cpsw_ale * ale,const u8 * addr,int port_mask,int flags,u16 vid,int mcast_state)549 int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
550 int flags, u16 vid, int mcast_state)
551 {
552 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
553 int idx, mask;
554
555 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
556 if (idx >= 0)
557 cpsw_ale_read(ale, idx, ale_entry);
558
559 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
560
561 cpsw_ale_set_addr(ale_entry, addr);
562 cpsw_ale_set_super(ale_entry, (flags & ALE_SUPER) ? 1 : 0);
563 cpsw_ale_set_mcast_state(ale_entry, mcast_state);
564
565 mask = cpsw_ale_get_port_mask(ale_entry,
566 ale->port_mask_bits);
567 port_mask |= mask;
568 cpsw_ale_set_port_mask(ale_entry, port_mask,
569 ale->port_mask_bits);
570
571 if (idx < 0)
572 idx = cpsw_ale_match_free(ale);
573 if (idx < 0)
574 idx = cpsw_ale_find_ageable(ale);
575 if (idx < 0)
576 return -ENOMEM;
577
578 cpsw_ale_write(ale, idx, ale_entry);
579 return 0;
580 }
581
cpsw_ale_del_mcast(struct cpsw_ale * ale,const u8 * addr,int port_mask,int flags,u16 vid)582 int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
583 int flags, u16 vid)
584 {
585 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
586 int mcast_members = 0;
587 int idx;
588
589 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
590 if (idx < 0)
591 return -ENOENT;
592
593 cpsw_ale_read(ale, idx, ale_entry);
594
595 if (port_mask) {
596 mcast_members = cpsw_ale_get_port_mask(ale_entry,
597 ale->port_mask_bits);
598 mcast_members &= ~port_mask;
599 }
600
601 if (mcast_members)
602 cpsw_ale_set_port_mask(ale_entry, mcast_members,
603 ale->port_mask_bits);
604 else
605 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
606
607 cpsw_ale_write(ale, idx, ale_entry);
608 return 0;
609 }
610
611 /* ALE NetCP NU switch specific vlan functions */
cpsw_ale_set_vlan_mcast(struct cpsw_ale * ale,u32 * ale_entry,int reg_mcast,int unreg_mcast)612 static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry,
613 int reg_mcast, int unreg_mcast)
614 {
615 int idx;
616
617 /* Set VLAN registered multicast flood mask */
618 idx = cpsw_ale_vlan_get_fld(ale, ale_entry,
619 ALE_ENT_VID_REG_MCAST_IDX);
620 writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
621
622 /* Set VLAN unregistered multicast flood mask */
623 idx = cpsw_ale_vlan_get_fld(ale, ale_entry,
624 ALE_ENT_VID_UNREG_MCAST_IDX);
625 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
626 }
627
cpsw_ale_set_vlan_untag(struct cpsw_ale * ale,u32 * ale_entry,u16 vid,int untag_mask)628 static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry,
629 u16 vid, int untag_mask)
630 {
631 cpsw_ale_vlan_set_fld(ale, ale_entry,
632 ALE_ENT_VID_FORCE_UNTAGGED_MSK,
633 untag_mask);
634 if (untag_mask & ALE_PORT_HOST)
635 bitmap_set(ale->p0_untag_vid_mask, vid, 1);
636 else
637 bitmap_clear(ale->p0_untag_vid_mask, vid, 1);
638 }
639
cpsw_ale_add_vlan(struct cpsw_ale * ale,u16 vid,int port_mask,int untag,int reg_mcast,int unreg_mcast)640 int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag,
641 int reg_mcast, int unreg_mcast)
642 {
643 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
644 int idx;
645
646 idx = cpsw_ale_match_vlan(ale, vid);
647 if (idx >= 0)
648 cpsw_ale_read(ale, idx, ale_entry);
649
650 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN);
651 cpsw_ale_set_vlan_id(ale_entry, vid);
652 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
653
654 if (!ale->params.nu_switch_ale) {
655 cpsw_ale_vlan_set_fld(ale, ale_entry,
656 ALE_ENT_VID_REG_MCAST_MSK, reg_mcast);
657 cpsw_ale_vlan_set_fld(ale, ale_entry,
658 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast);
659 } else {
660 cpsw_ale_vlan_set_fld(ale, ale_entry,
661 ALE_ENT_VID_UNREG_MCAST_IDX,
662 NU_VLAN_UNREG_MCAST_IDX);
663 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast);
664 }
665
666 cpsw_ale_vlan_set_fld(ale, ale_entry,
667 ALE_ENT_VID_MEMBER_LIST, port_mask);
668
669 if (idx < 0)
670 idx = cpsw_ale_match_free(ale);
671 if (idx < 0)
672 idx = cpsw_ale_find_ageable(ale);
673 if (idx < 0)
674 return -ENOMEM;
675
676 cpsw_ale_write(ale, idx, ale_entry);
677 return 0;
678 }
679
cpsw_ale_vlan_del_modify_int(struct cpsw_ale * ale,u32 * ale_entry,u16 vid,int port_mask)680 static void cpsw_ale_vlan_del_modify_int(struct cpsw_ale *ale, u32 *ale_entry,
681 u16 vid, int port_mask)
682 {
683 int reg_mcast, unreg_mcast;
684 int members, untag;
685
686 members = cpsw_ale_vlan_get_fld(ale, ale_entry,
687 ALE_ENT_VID_MEMBER_LIST);
688 members &= ~port_mask;
689 if (!members) {
690 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0);
691 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
692 return;
693 }
694
695 untag = cpsw_ale_vlan_get_fld(ale, ale_entry,
696 ALE_ENT_VID_FORCE_UNTAGGED_MSK);
697 reg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry,
698 ALE_ENT_VID_REG_MCAST_MSK);
699 unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry,
700 ALE_ENT_VID_UNREG_MCAST_MSK);
701 untag &= members;
702 reg_mcast &= members;
703 unreg_mcast &= members;
704
705 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
706
707 if (!ale->params.nu_switch_ale) {
708 cpsw_ale_vlan_set_fld(ale, ale_entry,
709 ALE_ENT_VID_REG_MCAST_MSK, reg_mcast);
710 cpsw_ale_vlan_set_fld(ale, ale_entry,
711 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast);
712 } else {
713 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast,
714 unreg_mcast);
715 }
716 cpsw_ale_vlan_set_fld(ale, ale_entry,
717 ALE_ENT_VID_MEMBER_LIST, members);
718 }
719
cpsw_ale_vlan_del_modify(struct cpsw_ale * ale,u16 vid,int port_mask)720 int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask)
721 {
722 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
723 int idx;
724
725 idx = cpsw_ale_match_vlan(ale, vid);
726 if (idx < 0)
727 return -ENOENT;
728
729 cpsw_ale_read(ale, idx, ale_entry);
730
731 cpsw_ale_vlan_del_modify_int(ale, ale_entry, vid, port_mask);
732 cpsw_ale_write(ale, idx, ale_entry);
733
734 return 0;
735 }
736
cpsw_ale_del_vlan(struct cpsw_ale * ale,u16 vid,int port_mask)737 int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask)
738 {
739 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
740 int members, idx;
741
742 idx = cpsw_ale_match_vlan(ale, vid);
743 if (idx < 0)
744 return -ENOENT;
745
746 cpsw_ale_read(ale, idx, ale_entry);
747
748 /* if !port_mask - force remove VLAN (legacy).
749 * Check if there are other VLAN members ports
750 * if no - remove VLAN.
751 * if yes it means same VLAN was added to >1 port in multi port mode, so
752 * remove port_mask ports from VLAN ALE entry excluding Host port.
753 */
754 members = cpsw_ale_vlan_get_fld(ale, ale_entry, ALE_ENT_VID_MEMBER_LIST);
755 members &= ~port_mask;
756
757 if (!port_mask || !members) {
758 /* last port or force remove - remove VLAN */
759 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0);
760 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
761 } else {
762 port_mask &= ~ALE_PORT_HOST;
763 cpsw_ale_vlan_del_modify_int(ale, ale_entry, vid, port_mask);
764 }
765
766 cpsw_ale_write(ale, idx, ale_entry);
767
768 return 0;
769 }
770
cpsw_ale_vlan_add_modify(struct cpsw_ale * ale,u16 vid,int port_mask,int untag_mask,int reg_mask,int unreg_mask)771 int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
772 int untag_mask, int reg_mask, int unreg_mask)
773 {
774 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
775 int reg_mcast_members, unreg_mcast_members;
776 int vlan_members, untag_members;
777 int idx, ret = 0;
778
779 idx = cpsw_ale_match_vlan(ale, vid);
780 if (idx >= 0)
781 cpsw_ale_read(ale, idx, ale_entry);
782
783 vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
784 ALE_ENT_VID_MEMBER_LIST);
785 reg_mcast_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
786 ALE_ENT_VID_REG_MCAST_MSK);
787 unreg_mcast_members =
788 cpsw_ale_vlan_get_fld(ale, ale_entry,
789 ALE_ENT_VID_UNREG_MCAST_MSK);
790 untag_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
791 ALE_ENT_VID_FORCE_UNTAGGED_MSK);
792
793 vlan_members |= port_mask;
794 untag_members = (untag_members & ~port_mask) | untag_mask;
795 reg_mcast_members = (reg_mcast_members & ~port_mask) | reg_mask;
796 unreg_mcast_members = (unreg_mcast_members & ~port_mask) | unreg_mask;
797
798 ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members,
799 reg_mcast_members, unreg_mcast_members);
800 if (ret) {
801 dev_err(ale->params.dev, "Unable to add vlan\n");
802 return ret;
803 }
804 dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members,
805 untag_mask);
806
807 return ret;
808 }
809
cpsw_ale_set_unreg_mcast(struct cpsw_ale * ale,int unreg_mcast_mask,bool add)810 void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
811 bool add)
812 {
813 u32 ale_entry[ALE_ENTRY_WORDS];
814 int unreg_members = 0;
815 int type, idx;
816
817 for (idx = 0; idx < ale->params.ale_entries; idx++) {
818 cpsw_ale_read(ale, idx, ale_entry);
819 type = cpsw_ale_get_entry_type(ale_entry);
820 if (type != ALE_TYPE_VLAN)
821 continue;
822
823 unreg_members =
824 cpsw_ale_vlan_get_fld(ale, ale_entry,
825 ALE_ENT_VID_UNREG_MCAST_MSK);
826 if (add)
827 unreg_members |= unreg_mcast_mask;
828 else
829 unreg_members &= ~unreg_mcast_mask;
830 cpsw_ale_vlan_set_fld(ale, ale_entry,
831 ALE_ENT_VID_UNREG_MCAST_MSK,
832 unreg_members);
833 cpsw_ale_write(ale, idx, ale_entry);
834 }
835 }
836
cpsw_ale_vlan_set_unreg_mcast(struct cpsw_ale * ale,u32 * ale_entry,int allmulti)837 static void cpsw_ale_vlan_set_unreg_mcast(struct cpsw_ale *ale, u32 *ale_entry,
838 int allmulti)
839 {
840 int unreg_mcast;
841
842 unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry,
843 ALE_ENT_VID_UNREG_MCAST_MSK);
844 if (allmulti)
845 unreg_mcast |= ALE_PORT_HOST;
846 else
847 unreg_mcast &= ~ALE_PORT_HOST;
848
849 cpsw_ale_vlan_set_fld(ale, ale_entry,
850 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast);
851 }
852
853 static void
cpsw_ale_vlan_set_unreg_mcast_idx(struct cpsw_ale * ale,u32 * ale_entry,int allmulti)854 cpsw_ale_vlan_set_unreg_mcast_idx(struct cpsw_ale *ale, u32 *ale_entry,
855 int allmulti)
856 {
857 int unreg_mcast;
858 int idx;
859
860 idx = cpsw_ale_vlan_get_fld(ale, ale_entry,
861 ALE_ENT_VID_UNREG_MCAST_IDX);
862
863 unreg_mcast = readl(ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
864
865 if (allmulti)
866 unreg_mcast |= ALE_PORT_HOST;
867 else
868 unreg_mcast &= ~ALE_PORT_HOST;
869
870 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
871 }
872
cpsw_ale_set_allmulti(struct cpsw_ale * ale,int allmulti,int port)873 void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port)
874 {
875 u32 ale_entry[ALE_ENTRY_WORDS];
876 int type, idx;
877
878 for (idx = 0; idx < ale->params.ale_entries; idx++) {
879 int vlan_members;
880
881 cpsw_ale_read(ale, idx, ale_entry);
882 type = cpsw_ale_get_entry_type(ale_entry);
883 if (type != ALE_TYPE_VLAN)
884 continue;
885
886 vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
887 ALE_ENT_VID_MEMBER_LIST);
888
889 if (port != -1 && !(vlan_members & BIT(port)))
890 continue;
891
892 if (!ale->params.nu_switch_ale)
893 cpsw_ale_vlan_set_unreg_mcast(ale, ale_entry, allmulti);
894 else
895 cpsw_ale_vlan_set_unreg_mcast_idx(ale, ale_entry,
896 allmulti);
897
898 cpsw_ale_write(ale, idx, ale_entry);
899 }
900 }
901
902 struct ale_control_info {
903 const char *name;
904 int offset, port_offset;
905 int shift, port_shift;
906 int bits;
907 };
908
909 static struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = {
910 [ALE_ENABLE] = {
911 .name = "enable",
912 .offset = ALE_CONTROL,
913 .port_offset = 0,
914 .shift = 31,
915 .port_shift = 0,
916 .bits = 1,
917 },
918 [ALE_CLEAR] = {
919 .name = "clear",
920 .offset = ALE_CONTROL,
921 .port_offset = 0,
922 .shift = 30,
923 .port_shift = 0,
924 .bits = 1,
925 },
926 [ALE_AGEOUT] = {
927 .name = "ageout",
928 .offset = ALE_CONTROL,
929 .port_offset = 0,
930 .shift = 29,
931 .port_shift = 0,
932 .bits = 1,
933 },
934 [ALE_P0_UNI_FLOOD] = {
935 .name = "port0_unicast_flood",
936 .offset = ALE_CONTROL,
937 .port_offset = 0,
938 .shift = 8,
939 .port_shift = 0,
940 .bits = 1,
941 },
942 [ALE_VLAN_NOLEARN] = {
943 .name = "vlan_nolearn",
944 .offset = ALE_CONTROL,
945 .port_offset = 0,
946 .shift = 7,
947 .port_shift = 0,
948 .bits = 1,
949 },
950 [ALE_NO_PORT_VLAN] = {
951 .name = "no_port_vlan",
952 .offset = ALE_CONTROL,
953 .port_offset = 0,
954 .shift = 6,
955 .port_shift = 0,
956 .bits = 1,
957 },
958 [ALE_OUI_DENY] = {
959 .name = "oui_deny",
960 .offset = ALE_CONTROL,
961 .port_offset = 0,
962 .shift = 5,
963 .port_shift = 0,
964 .bits = 1,
965 },
966 [ALE_BYPASS] = {
967 .name = "bypass",
968 .offset = ALE_CONTROL,
969 .port_offset = 0,
970 .shift = 4,
971 .port_shift = 0,
972 .bits = 1,
973 },
974 [ALE_RATE_LIMIT_TX] = {
975 .name = "rate_limit_tx",
976 .offset = ALE_CONTROL,
977 .port_offset = 0,
978 .shift = 3,
979 .port_shift = 0,
980 .bits = 1,
981 },
982 [ALE_VLAN_AWARE] = {
983 .name = "vlan_aware",
984 .offset = ALE_CONTROL,
985 .port_offset = 0,
986 .shift = 2,
987 .port_shift = 0,
988 .bits = 1,
989 },
990 [ALE_AUTH_ENABLE] = {
991 .name = "auth_enable",
992 .offset = ALE_CONTROL,
993 .port_offset = 0,
994 .shift = 1,
995 .port_shift = 0,
996 .bits = 1,
997 },
998 [ALE_RATE_LIMIT] = {
999 .name = "rate_limit",
1000 .offset = ALE_CONTROL,
1001 .port_offset = 0,
1002 .shift = 0,
1003 .port_shift = 0,
1004 .bits = 1,
1005 },
1006 [ALE_PORT_STATE] = {
1007 .name = "port_state",
1008 .offset = ALE_PORTCTL,
1009 .port_offset = 4,
1010 .shift = 0,
1011 .port_shift = 0,
1012 .bits = 2,
1013 },
1014 [ALE_PORT_DROP_UNTAGGED] = {
1015 .name = "drop_untagged",
1016 .offset = ALE_PORTCTL,
1017 .port_offset = 4,
1018 .shift = 2,
1019 .port_shift = 0,
1020 .bits = 1,
1021 },
1022 [ALE_PORT_DROP_UNKNOWN_VLAN] = {
1023 .name = "drop_unknown",
1024 .offset = ALE_PORTCTL,
1025 .port_offset = 4,
1026 .shift = 3,
1027 .port_shift = 0,
1028 .bits = 1,
1029 },
1030 [ALE_PORT_NOLEARN] = {
1031 .name = "nolearn",
1032 .offset = ALE_PORTCTL,
1033 .port_offset = 4,
1034 .shift = 4,
1035 .port_shift = 0,
1036 .bits = 1,
1037 },
1038 [ALE_PORT_NO_SA_UPDATE] = {
1039 .name = "no_source_update",
1040 .offset = ALE_PORTCTL,
1041 .port_offset = 4,
1042 .shift = 5,
1043 .port_shift = 0,
1044 .bits = 1,
1045 },
1046 [ALE_PORT_MACONLY] = {
1047 .name = "mac_only_port_mode",
1048 .offset = ALE_PORTCTL,
1049 .port_offset = 4,
1050 .shift = 11,
1051 .port_shift = 0,
1052 .bits = 1,
1053 },
1054 [ALE_PORT_MACONLY_CAF] = {
1055 .name = "mac_only_port_caf",
1056 .offset = ALE_PORTCTL,
1057 .port_offset = 4,
1058 .shift = 13,
1059 .port_shift = 0,
1060 .bits = 1,
1061 },
1062 [ALE_PORT_MCAST_LIMIT] = {
1063 .name = "mcast_limit",
1064 .offset = ALE_PORTCTL,
1065 .port_offset = 4,
1066 .shift = 16,
1067 .port_shift = 0,
1068 .bits = 8,
1069 },
1070 [ALE_PORT_BCAST_LIMIT] = {
1071 .name = "bcast_limit",
1072 .offset = ALE_PORTCTL,
1073 .port_offset = 4,
1074 .shift = 24,
1075 .port_shift = 0,
1076 .bits = 8,
1077 },
1078 [ALE_PORT_UNKNOWN_VLAN_MEMBER] = {
1079 .name = "unknown_vlan_member",
1080 .offset = ALE_UNKNOWNVLAN,
1081 .port_offset = 0,
1082 .shift = 0,
1083 .port_shift = 0,
1084 .bits = 6,
1085 },
1086 [ALE_PORT_UNKNOWN_MCAST_FLOOD] = {
1087 .name = "unknown_mcast_flood",
1088 .offset = ALE_UNKNOWNVLAN,
1089 .port_offset = 0,
1090 .shift = 8,
1091 .port_shift = 0,
1092 .bits = 6,
1093 },
1094 [ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = {
1095 .name = "unknown_reg_flood",
1096 .offset = ALE_UNKNOWNVLAN,
1097 .port_offset = 0,
1098 .shift = 16,
1099 .port_shift = 0,
1100 .bits = 6,
1101 },
1102 [ALE_PORT_UNTAGGED_EGRESS] = {
1103 .name = "untagged_egress",
1104 .offset = ALE_UNKNOWNVLAN,
1105 .port_offset = 0,
1106 .shift = 24,
1107 .port_shift = 0,
1108 .bits = 6,
1109 },
1110 [ALE_DEFAULT_THREAD_ID] = {
1111 .name = "default_thread_id",
1112 .offset = AM65_CPSW_ALE_THREAD_DEF_REG,
1113 .port_offset = 0,
1114 .shift = 0,
1115 .port_shift = 0,
1116 .bits = 6,
1117 },
1118 [ALE_DEFAULT_THREAD_ENABLE] = {
1119 .name = "default_thread_id_enable",
1120 .offset = AM65_CPSW_ALE_THREAD_DEF_REG,
1121 .port_offset = 0,
1122 .shift = 15,
1123 .port_shift = 0,
1124 .bits = 1,
1125 },
1126 };
1127
cpsw_ale_control_set(struct cpsw_ale * ale,int port,int control,int value)1128 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
1129 int value)
1130 {
1131 const struct ale_control_info *info;
1132 int offset, shift;
1133 u32 tmp, mask;
1134
1135 if (control < 0 || control >= ARRAY_SIZE(ale_controls))
1136 return -EINVAL;
1137
1138 info = &ale_controls[control];
1139 if (info->port_offset == 0 && info->port_shift == 0)
1140 port = 0; /* global, port is a dont care */
1141
1142 if (port < 0 || port >= ale->params.ale_ports)
1143 return -EINVAL;
1144
1145 mask = BITMASK(info->bits);
1146 if (value & ~mask)
1147 return -EINVAL;
1148
1149 offset = info->offset + (port * info->port_offset);
1150 shift = info->shift + (port * info->port_shift);
1151
1152 tmp = readl_relaxed(ale->params.ale_regs + offset);
1153 tmp = (tmp & ~(mask << shift)) | (value << shift);
1154 writel_relaxed(tmp, ale->params.ale_regs + offset);
1155
1156 return 0;
1157 }
1158
cpsw_ale_control_get(struct cpsw_ale * ale,int port,int control)1159 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
1160 {
1161 const struct ale_control_info *info;
1162 int offset, shift;
1163 u32 tmp;
1164
1165 if (control < 0 || control >= ARRAY_SIZE(ale_controls))
1166 return -EINVAL;
1167
1168 info = &ale_controls[control];
1169 if (info->port_offset == 0 && info->port_shift == 0)
1170 port = 0; /* global, port is a dont care */
1171
1172 if (port < 0 || port >= ale->params.ale_ports)
1173 return -EINVAL;
1174
1175 offset = info->offset + (port * info->port_offset);
1176 shift = info->shift + (port * info->port_shift);
1177
1178 tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift;
1179 return tmp & BITMASK(info->bits);
1180 }
1181
cpsw_ale_rx_ratelimit_mc(struct cpsw_ale * ale,int port,unsigned int ratelimit_pps)1182 int cpsw_ale_rx_ratelimit_mc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps)
1183
1184 {
1185 int val = ratelimit_pps / ALE_RATE_LIMIT_MIN_PPS;
1186 u32 remainder = ratelimit_pps % ALE_RATE_LIMIT_MIN_PPS;
1187
1188 if (ratelimit_pps && !val) {
1189 dev_err(ale->params.dev, "ALE MC port:%d ratelimit min value 1000pps\n", port);
1190 return -EINVAL;
1191 }
1192
1193 if (remainder)
1194 dev_info(ale->params.dev, "ALE port:%d MC ratelimit set to %dpps (requested %d)\n",
1195 port, ratelimit_pps - remainder, ratelimit_pps);
1196
1197 cpsw_ale_control_set(ale, port, ALE_PORT_MCAST_LIMIT, val);
1198
1199 dev_dbg(ale->params.dev, "ALE port:%d MC ratelimit set %d\n",
1200 port, val * ALE_RATE_LIMIT_MIN_PPS);
1201 return 0;
1202 }
1203
cpsw_ale_rx_ratelimit_bc(struct cpsw_ale * ale,int port,unsigned int ratelimit_pps)1204 int cpsw_ale_rx_ratelimit_bc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps)
1205
1206 {
1207 int val = ratelimit_pps / ALE_RATE_LIMIT_MIN_PPS;
1208 u32 remainder = ratelimit_pps % ALE_RATE_LIMIT_MIN_PPS;
1209
1210 if (ratelimit_pps && !val) {
1211 dev_err(ale->params.dev, "ALE port:%d BC ratelimit min value 1000pps\n", port);
1212 return -EINVAL;
1213 }
1214
1215 if (remainder)
1216 dev_info(ale->params.dev, "ALE port:%d BC ratelimit set to %dpps (requested %d)\n",
1217 port, ratelimit_pps - remainder, ratelimit_pps);
1218
1219 cpsw_ale_control_set(ale, port, ALE_PORT_BCAST_LIMIT, val);
1220
1221 dev_dbg(ale->params.dev, "ALE port:%d BC ratelimit set %d\n",
1222 port, val * ALE_RATE_LIMIT_MIN_PPS);
1223 return 0;
1224 }
1225
cpsw_ale_timer(struct timer_list * t)1226 static void cpsw_ale_timer(struct timer_list *t)
1227 {
1228 struct cpsw_ale *ale = timer_container_of(ale, t, timer);
1229
1230 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
1231
1232 if (ale->ageout) {
1233 ale->timer.expires = jiffies + ale->ageout;
1234 add_timer(&ale->timer);
1235 }
1236 }
1237
cpsw_ale_hw_aging_timer_start(struct cpsw_ale * ale)1238 static void cpsw_ale_hw_aging_timer_start(struct cpsw_ale *ale)
1239 {
1240 u32 aging_timer;
1241
1242 aging_timer = ale->params.bus_freq / 1000000;
1243 aging_timer *= ale->params.ale_ageout;
1244
1245 if (aging_timer & ~ALE_AGING_TIMER_MASK) {
1246 aging_timer = ALE_AGING_TIMER_MASK;
1247 dev_warn(ale->params.dev,
1248 "ALE aging timer overflow, set to max\n");
1249 }
1250
1251 writel(aging_timer, ale->params.ale_regs + ALE_AGING_TIMER);
1252 }
1253
cpsw_ale_hw_aging_timer_stop(struct cpsw_ale * ale)1254 static void cpsw_ale_hw_aging_timer_stop(struct cpsw_ale *ale)
1255 {
1256 writel(0, ale->params.ale_regs + ALE_AGING_TIMER);
1257 }
1258
cpsw_ale_aging_start(struct cpsw_ale * ale)1259 static void cpsw_ale_aging_start(struct cpsw_ale *ale)
1260 {
1261 if (!ale->params.ale_ageout)
1262 return;
1263
1264 if (ale->features & CPSW_ALE_F_HW_AUTOAGING) {
1265 cpsw_ale_hw_aging_timer_start(ale);
1266 return;
1267 }
1268
1269 timer_setup(&ale->timer, cpsw_ale_timer, 0);
1270 ale->timer.expires = jiffies + ale->ageout;
1271 add_timer(&ale->timer);
1272 }
1273
cpsw_ale_aging_stop(struct cpsw_ale * ale)1274 static void cpsw_ale_aging_stop(struct cpsw_ale *ale)
1275 {
1276 if (!ale->params.ale_ageout)
1277 return;
1278
1279 if (ale->features & CPSW_ALE_F_HW_AUTOAGING) {
1280 cpsw_ale_hw_aging_timer_stop(ale);
1281 return;
1282 }
1283
1284 timer_delete_sync(&ale->timer);
1285 }
1286
cpsw_ale_start(struct cpsw_ale * ale)1287 void cpsw_ale_start(struct cpsw_ale *ale)
1288 {
1289 unsigned long ale_prescale;
1290
1291 /* configure Broadcast and Multicast Rate Limit
1292 * number_of_packets = (Fclk / ALE_PRESCALE) * port.BCAST/MCAST_LIMIT
1293 * ALE_PRESCALE width is 19bit and min value 0x10
1294 * port.BCAST/MCAST_LIMIT is 8bit
1295 *
1296 * For multi port configuration support the ALE_PRESCALE is configured to 1ms interval,
1297 * which allows to configure port.BCAST/MCAST_LIMIT per port and achieve:
1298 * min number_of_packets = 1000 when port.BCAST/MCAST_LIMIT = 1
1299 * max number_of_packets = 1000 * 255 = 255000 when port.BCAST/MCAST_LIMIT = 0xFF
1300 */
1301 ale_prescale = ale->params.bus_freq / ALE_RATE_LIMIT_MIN_PPS;
1302 writel((u32)ale_prescale, ale->params.ale_regs + ALE_PRESCALE);
1303
1304 /* Allow MC/BC rate limiting globally.
1305 * The actual Rate Limit cfg enabled per-port by port.BCAST/MCAST_LIMIT
1306 */
1307 cpsw_ale_control_set(ale, 0, ALE_RATE_LIMIT, 1);
1308
1309 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1);
1310 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1311
1312 cpsw_ale_aging_start(ale);
1313 }
1314
cpsw_ale_stop(struct cpsw_ale * ale)1315 void cpsw_ale_stop(struct cpsw_ale *ale)
1316 {
1317 cpsw_ale_aging_stop(ale);
1318 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1319 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
1320 }
1321
1322 static const struct reg_field ale_fields_cpsw[] = {
1323 /* CPSW_ALE_IDVER_REG */
1324 [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7),
1325 [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 15),
1326 };
1327
1328 static const struct reg_field ale_fields_cpsw_nu[] = {
1329 /* CPSW_ALE_IDVER_REG */
1330 [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7),
1331 [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 10),
1332 /* CPSW_ALE_STATUS_REG */
1333 [ALE_ENTRIES] = REG_FIELD(ALE_STATUS, 0, 7),
1334 [ALE_POLICERS] = REG_FIELD(ALE_STATUS, 8, 15),
1335 /* CPSW_ALE_POLICER_PORT_OUI_REG */
1336 [POL_PORT_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 31, 31),
1337 [POL_TRUNK_ID] = REG_FIELD(ALE_POLICER_PORT_OUI, 30, 30),
1338 [POL_PORT_NUM] = REG_FIELD(ALE_POLICER_PORT_OUI, 25, 25),
1339 [POL_PRI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 19, 19),
1340 [POL_PRI_VAL] = REG_FIELD(ALE_POLICER_PORT_OUI, 16, 18),
1341 [POL_OUI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 15, 15),
1342 [POL_OUI_INDEX] = REG_FIELD(ALE_POLICER_PORT_OUI, 0, 5),
1343
1344 /* CPSW_ALE_POLICER_DA_SA_REG */
1345 [POL_DST_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 31, 31),
1346 [POL_DST_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 16, 21),
1347 [POL_SRC_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 15, 15),
1348 [POL_SRC_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 0, 5),
1349
1350 /* CPSW_ALE_POLICER_VLAN_REG */
1351 [POL_OVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 31, 31),
1352 [POL_OVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 16, 21),
1353 [POL_IVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 15, 15),
1354 [POL_IVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 0, 5),
1355
1356 /* CPSW_ALE_POLICER_ETHERTYPE_IPSA_REG */
1357 [POL_ETHERTYPE_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 31, 31),
1358 [POL_ETHERTYPE_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 16, 21),
1359 [POL_IPSRC_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 15, 15),
1360 [POL_IPSRC_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 0, 5),
1361
1362 /* CPSW_ALE_POLICER_IPDA_REG */
1363 [POL_IPDST_MEN] = REG_FIELD(ALE_POLICER_IPDA, 31, 31),
1364 [POL_IPDST_INDEX] = REG_FIELD(ALE_POLICER_IPDA, 16, 21),
1365
1366 /* CPSW_ALE_POLICER_TBL_CTL_REG */
1367 /**
1368 * REG_FIELDS not defined for this as fields cannot be correctly
1369 * used independently
1370 */
1371
1372 /* CPSW_ALE_POLICER_CTL_REG */
1373 [POL_EN] = REG_FIELD(ALE_POLICER_CTL, 31, 31),
1374 [POL_RED_DROP_EN] = REG_FIELD(ALE_POLICER_CTL, 29, 29),
1375 [POL_YELLOW_DROP_EN] = REG_FIELD(ALE_POLICER_CTL, 28, 28),
1376 [POL_YELLOW_THRESH] = REG_FIELD(ALE_POLICER_CTL, 24, 26),
1377 [POL_POL_MATCH_MODE] = REG_FIELD(ALE_POLICER_CTL, 22, 23),
1378 [POL_PRIORITY_THREAD_EN] = REG_FIELD(ALE_POLICER_CTL, 21, 21),
1379 [POL_MAC_ONLY_DEF_DIS] = REG_FIELD(ALE_POLICER_CTL, 20, 20),
1380
1381 /* CPSW_ALE_POLICER_TEST_CTL_REG */
1382 [POL_TEST_CLR] = REG_FIELD(ALE_POLICER_TEST_CTL, 31, 31),
1383 [POL_TEST_CLR_RED] = REG_FIELD(ALE_POLICER_TEST_CTL, 30, 30),
1384 [POL_TEST_CLR_YELLOW] = REG_FIELD(ALE_POLICER_TEST_CTL, 29, 29),
1385 [POL_TEST_CLR_SELECTED] = REG_FIELD(ALE_POLICER_TEST_CTL, 28, 28),
1386 [POL_TEST_ENTRY] = REG_FIELD(ALE_POLICER_TEST_CTL, 0, 4),
1387
1388 /* CPSW_ALE_POLICER_HIT_STATUS_REG */
1389 [POL_STATUS_HIT] = REG_FIELD(ALE_POLICER_HIT_STATUS, 31, 31),
1390 [POL_STATUS_HIT_RED] = REG_FIELD(ALE_POLICER_HIT_STATUS, 30, 30),
1391 [POL_STATUS_HIT_YELLOW] = REG_FIELD(ALE_POLICER_HIT_STATUS, 29, 29),
1392
1393 /* CPSW_ALE_THREAD_DEF_REG */
1394 [ALE_DEFAULT_THREAD_EN] = REG_FIELD(ALE_THREAD_DEF, 15, 15),
1395 [ALE_DEFAULT_THREAD_VAL] = REG_FIELD(ALE_THREAD_DEF, 0, 5),
1396
1397 /* CPSW_ALE_THREAD_CTL_REG */
1398 [ALE_THREAD_CLASS_INDEX] = REG_FIELD(ALE_THREAD_CTL, 0, 4),
1399
1400 /* CPSW_ALE_THREAD_VAL_REG */
1401 [ALE_THREAD_ENABLE] = REG_FIELD(ALE_THREAD_VAL, 15, 15),
1402 [ALE_THREAD_VALUE] = REG_FIELD(ALE_THREAD_VAL, 0, 5),
1403 };
1404
1405 static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = {
1406 {
1407 /* am3/4/5, dra7. dm814x, 66ak2hk-gbe */
1408 .dev_id = "cpsw",
1409 .tbl_entries = 1024,
1410 .reg_fields = ale_fields_cpsw,
1411 .num_fields = ARRAY_SIZE(ale_fields_cpsw),
1412 .vlan_entry_tbl = vlan_entry_cpsw,
1413 },
1414 {
1415 /* 66ak2h_xgbe */
1416 .dev_id = "66ak2h-xgbe",
1417 .tbl_entries = 2048,
1418 .reg_fields = ale_fields_cpsw,
1419 .num_fields = ARRAY_SIZE(ale_fields_cpsw),
1420 .vlan_entry_tbl = vlan_entry_cpsw,
1421 },
1422 {
1423 .dev_id = "66ak2el",
1424 .features = CPSW_ALE_F_STATUS_REG,
1425 .reg_fields = ale_fields_cpsw_nu,
1426 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu),
1427 .nu_switch_ale = true,
1428 .vlan_entry_tbl = vlan_entry_nu,
1429 },
1430 {
1431 .dev_id = "66ak2g",
1432 .features = CPSW_ALE_F_STATUS_REG,
1433 .tbl_entries = 64,
1434 .reg_fields = ale_fields_cpsw_nu,
1435 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu),
1436 .nu_switch_ale = true,
1437 .vlan_entry_tbl = vlan_entry_nu,
1438 },
1439 {
1440 .dev_id = "am65x-cpsw2g",
1441 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING,
1442 .tbl_entries = 64,
1443 .reg_fields = ale_fields_cpsw_nu,
1444 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu),
1445 .nu_switch_ale = true,
1446 .vlan_entry_tbl = vlan_entry_nu,
1447 },
1448 {
1449 .dev_id = "j721e-cpswxg",
1450 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING,
1451 .reg_fields = ale_fields_cpsw_nu,
1452 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu),
1453 .vlan_entry_tbl = vlan_entry_k3_cpswxg,
1454 },
1455 {
1456 .dev_id = "am64-cpswxg",
1457 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING,
1458 .reg_fields = ale_fields_cpsw_nu,
1459 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu),
1460 .vlan_entry_tbl = vlan_entry_k3_cpswxg,
1461 .tbl_entries = 512,
1462 },
1463 { },
1464 };
1465
1466 static const struct
cpsw_ale_match_id(const struct cpsw_ale_dev_id * id,const char * dev_id)1467 cpsw_ale_dev_id *cpsw_ale_match_id(const struct cpsw_ale_dev_id *id,
1468 const char *dev_id)
1469 {
1470 if (!dev_id)
1471 return NULL;
1472
1473 while (id->dev_id) {
1474 if (strcmp(dev_id, id->dev_id) == 0)
1475 return id;
1476 id++;
1477 }
1478 return NULL;
1479 }
1480
1481 static const struct regmap_config ale_regmap_cfg = {
1482 .reg_bits = 32,
1483 .val_bits = 32,
1484 .reg_stride = 4,
1485 .name = "cpsw-ale",
1486 };
1487
cpsw_ale_regfield_init(struct cpsw_ale * ale)1488 static int cpsw_ale_regfield_init(struct cpsw_ale *ale)
1489 {
1490 const struct reg_field *reg_fields = ale->params.reg_fields;
1491 struct device *dev = ale->params.dev;
1492 struct regmap *regmap = ale->regmap;
1493 int i;
1494
1495 for (i = 0; i < ale->params.num_fields; i++) {
1496 ale->fields[i] = devm_regmap_field_alloc(dev, regmap,
1497 reg_fields[i]);
1498 if (IS_ERR(ale->fields[i])) {
1499 dev_err(dev, "Unable to allocate regmap field %d\n", i);
1500 return PTR_ERR(ale->fields[i]);
1501 }
1502 }
1503
1504 return 0;
1505 }
1506
cpsw_ale_create(struct cpsw_ale_params * params)1507 struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
1508 {
1509 u32 ale_entries, rev_major, rev_minor, policers;
1510 const struct cpsw_ale_dev_id *ale_dev_id;
1511 struct cpsw_ale *ale;
1512 int ret;
1513
1514 ale_dev_id = cpsw_ale_match_id(cpsw_ale_id_match, params->dev_id);
1515 if (!ale_dev_id)
1516 return ERR_PTR(-EINVAL);
1517
1518 params->ale_entries = ale_dev_id->tbl_entries;
1519 params->nu_switch_ale = ale_dev_id->nu_switch_ale;
1520 params->reg_fields = ale_dev_id->reg_fields;
1521 params->num_fields = ale_dev_id->num_fields;
1522
1523 ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL);
1524 if (!ale)
1525 return ERR_PTR(-ENOMEM);
1526 ale->regmap = devm_regmap_init_mmio(params->dev, params->ale_regs,
1527 &ale_regmap_cfg);
1528 if (IS_ERR(ale->regmap)) {
1529 dev_err(params->dev, "Couldn't create CPSW ALE regmap\n");
1530 return ERR_PTR(-ENOMEM);
1531 }
1532
1533 ale->params = *params;
1534 ret = cpsw_ale_regfield_init(ale);
1535 if (ret)
1536 return ERR_PTR(ret);
1537
1538 ale->p0_untag_vid_mask = devm_bitmap_zalloc(params->dev, VLAN_N_VID,
1539 GFP_KERNEL);
1540 if (!ale->p0_untag_vid_mask)
1541 return ERR_PTR(-ENOMEM);
1542
1543 ale->ageout = ale->params.ale_ageout * HZ;
1544 ale->features = ale_dev_id->features;
1545 ale->vlan_entry_tbl = ale_dev_id->vlan_entry_tbl;
1546
1547 regmap_field_read(ale->fields[MINOR_VER], &rev_minor);
1548 regmap_field_read(ale->fields[MAJOR_VER], &rev_major);
1549 ale->version = rev_major << 8 | rev_minor;
1550 dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n",
1551 rev_major, rev_minor);
1552
1553 if (ale->features & CPSW_ALE_F_STATUS_REG &&
1554 !ale->params.ale_entries) {
1555 regmap_field_read(ale->fields[ALE_ENTRIES], &ale_entries);
1556 /* ALE available on newer NetCP switches has introduced
1557 * a register, ALE_STATUS, to indicate the size of ALE
1558 * table which shows the size as a multiple of 1024 entries.
1559 * For these, params.ale_entries will be set to zero. So
1560 * read the register and update the value of ale_entries.
1561 * return error if ale_entries is zero in ALE_STATUS.
1562 */
1563 if (!ale_entries)
1564 return ERR_PTR(-EINVAL);
1565
1566 ale_entries *= ALE_TABLE_SIZE_MULTIPLIER;
1567 ale->params.ale_entries = ale_entries;
1568 }
1569
1570 if (ale->features & CPSW_ALE_F_STATUS_REG &&
1571 !ale->params.num_policers) {
1572 regmap_field_read(ale->fields[ALE_POLICERS], &policers);
1573 if (!policers)
1574 return ERR_PTR(-EINVAL);
1575
1576 policers *= ALE_POLICER_SIZE_MULTIPLIER;
1577 ale->params.num_policers = policers;
1578 }
1579
1580 dev_info(ale->params.dev,
1581 "ALE Table size %ld, Policers %ld\n", ale->params.ale_entries,
1582 ale->params.num_policers);
1583
1584 /* set default bits for existing h/w */
1585 ale->port_mask_bits = ale->params.ale_ports;
1586 ale->port_num_bits = order_base_2(ale->params.ale_ports);
1587 ale->vlan_field_bits = ale->params.ale_ports;
1588
1589 /* Set defaults override for ALE on NetCP NU switch and for version
1590 * 1R3
1591 */
1592 if (ale->params.nu_switch_ale) {
1593 /* Separate registers for unknown vlan configuration.
1594 * Also there are N bits, where N is number of ale
1595 * ports and shift value should be 0
1596 */
1597 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].bits =
1598 ale->params.ale_ports;
1599 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].offset =
1600 ALE_UNKNOWNVLAN_MEMBER;
1601 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].bits =
1602 ale->params.ale_ports;
1603 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].shift = 0;
1604 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].offset =
1605 ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD;
1606 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].bits =
1607 ale->params.ale_ports;
1608 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].shift = 0;
1609 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].offset =
1610 ALE_UNKNOWNVLAN_REG_MCAST_FLOOD;
1611 ale_controls[ALE_PORT_UNTAGGED_EGRESS].bits =
1612 ale->params.ale_ports;
1613 ale_controls[ALE_PORT_UNTAGGED_EGRESS].shift = 0;
1614 ale_controls[ALE_PORT_UNTAGGED_EGRESS].offset =
1615 ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS;
1616 }
1617
1618 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1619 return ale;
1620 }
1621
cpsw_ale_dump(struct cpsw_ale * ale,u32 * data)1622 void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data)
1623 {
1624 int i;
1625
1626 for (i = 0; i < ale->params.ale_entries; i++) {
1627 cpsw_ale_read(ale, i, data);
1628 data += ALE_ENTRY_WORDS;
1629 }
1630 }
1631
cpsw_ale_restore(struct cpsw_ale * ale,u32 * data)1632 void cpsw_ale_restore(struct cpsw_ale *ale, u32 *data)
1633 {
1634 int i;
1635
1636 for (i = 0; i < ale->params.ale_entries; i++) {
1637 cpsw_ale_write(ale, i, data);
1638 data += ALE_ENTRY_WORDS;
1639 }
1640 }
1641
cpsw_ale_get_num_entries(struct cpsw_ale * ale)1642 u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale)
1643 {
1644 return ale ? ale->params.ale_entries : 0;
1645 }
1646
1647 /* Reads the specified policer index into ALE POLICER registers */
cpsw_ale_policer_read_idx(struct cpsw_ale * ale,u32 idx)1648 static void cpsw_ale_policer_read_idx(struct cpsw_ale *ale, u32 idx)
1649 {
1650 idx &= ALE_POLICER_TBL_INDEX_MASK;
1651 writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL);
1652 }
1653
1654 /* Writes the ALE POLICER registers into the specified policer index */
cpsw_ale_policer_write_idx(struct cpsw_ale * ale,u32 idx)1655 static void cpsw_ale_policer_write_idx(struct cpsw_ale *ale, u32 idx)
1656 {
1657 idx &= ALE_POLICER_TBL_INDEX_MASK;
1658 idx |= ALE_POLICER_TBL_WRITE_ENABLE;
1659 writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL);
1660 }
1661
1662 /* enables/disables the custom thread value for the specified policer index */
cpsw_ale_policer_thread_idx_enable(struct cpsw_ale * ale,u32 idx,u32 thread_id,bool enable)1663 static void cpsw_ale_policer_thread_idx_enable(struct cpsw_ale *ale, u32 idx,
1664 u32 thread_id, bool enable)
1665 {
1666 regmap_field_write(ale->fields[ALE_THREAD_CLASS_INDEX], idx);
1667 regmap_field_write(ale->fields[ALE_THREAD_VALUE], thread_id);
1668 regmap_field_write(ale->fields[ALE_THREAD_ENABLE], enable ? 1 : 0);
1669 }
1670
1671 /* Disable all policer entries and thread mappings */
cpsw_ale_policer_reset(struct cpsw_ale * ale)1672 static void cpsw_ale_policer_reset(struct cpsw_ale *ale)
1673 {
1674 int i;
1675
1676 for (i = 0; i < ale->params.num_policers ; i++) {
1677 cpsw_ale_policer_read_idx(ale, i);
1678 regmap_field_write(ale->fields[POL_PORT_MEN], 0);
1679 regmap_field_write(ale->fields[POL_PRI_MEN], 0);
1680 regmap_field_write(ale->fields[POL_OUI_MEN], 0);
1681 regmap_field_write(ale->fields[POL_DST_MEN], 0);
1682 regmap_field_write(ale->fields[POL_SRC_MEN], 0);
1683 regmap_field_write(ale->fields[POL_OVLAN_MEN], 0);
1684 regmap_field_write(ale->fields[POL_IVLAN_MEN], 0);
1685 regmap_field_write(ale->fields[POL_ETHERTYPE_MEN], 0);
1686 regmap_field_write(ale->fields[POL_IPSRC_MEN], 0);
1687 regmap_field_write(ale->fields[POL_IPDST_MEN], 0);
1688 regmap_field_write(ale->fields[POL_EN], 0);
1689 regmap_field_write(ale->fields[POL_RED_DROP_EN], 0);
1690 regmap_field_write(ale->fields[POL_YELLOW_DROP_EN], 0);
1691 regmap_field_write(ale->fields[POL_PRIORITY_THREAD_EN], 0);
1692
1693 cpsw_ale_policer_thread_idx_enable(ale, i, 0, 0);
1694 }
1695 }
1696
1697 /* Default classifier is to map 8 user priorities to N receive channels */
cpsw_ale_classifier_setup_default(struct cpsw_ale * ale,int num_rx_ch)1698 void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch)
1699 {
1700 int pri, idx;
1701
1702 /* Reference:
1703 * IEEE802.1Q-2014, Standard for Local and metropolitan area networks
1704 * Table I-2 - Traffic type acronyms
1705 * Table I-3 - Defining traffic types
1706 * Section I.4 Traffic types and priority values, states:
1707 * "0 is thus used both for default priority and for Best Effort, and
1708 * Background is associated with a priority value of 1. This means
1709 * that the value 1 effectively communicates a lower priority than 0."
1710 *
1711 * In the table below, Priority Code Point (PCP) 0 is assigned
1712 * to a higher priority thread than PCP 1 wherever possible.
1713 * The table maps which thread the PCP traffic needs to be
1714 * sent to for a given number of threads (RX channels). Upper threads
1715 * have higher priority.
1716 * e.g. if number of threads is 8 then user priority 0 will map to
1717 * pri_thread_map[8-1][0] i.e. thread 1
1718 */
1719
1720 int pri_thread_map[8][8] = { /* BK,BE,EE,CA,VI,VO,IC,NC */
1721 { 0, 0, 0, 0, 0, 0, 0, 0, },
1722 { 0, 0, 0, 0, 1, 1, 1, 1, },
1723 { 0, 0, 0, 0, 1, 1, 2, 2, },
1724 { 0, 0, 1, 1, 2, 2, 3, 3, },
1725 { 0, 0, 1, 1, 2, 2, 3, 4, },
1726 { 1, 0, 2, 2, 3, 3, 4, 5, },
1727 { 1, 0, 2, 3, 4, 4, 5, 6, },
1728 { 1, 0, 2, 3, 4, 5, 6, 7 } };
1729
1730 cpsw_ale_policer_reset(ale);
1731
1732 /* use first 8 classifiers to map 8 (DSCP/PCP) priorities to channels */
1733 for (pri = 0; pri < 8; pri++) {
1734 idx = pri;
1735
1736 /* Classifier 'idx' match on priority 'pri' */
1737 cpsw_ale_policer_read_idx(ale, idx);
1738 regmap_field_write(ale->fields[POL_PRI_VAL], pri);
1739 regmap_field_write(ale->fields[POL_PRI_MEN], 1);
1740 cpsw_ale_policer_write_idx(ale, idx);
1741
1742 /* Map Classifier 'idx' to thread provided by the map */
1743 cpsw_ale_policer_thread_idx_enable(ale, idx,
1744 pri_thread_map[num_rx_ch - 1][pri],
1745 1);
1746 }
1747 }
1748