1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef _CORESIGHT_PRIV_H
7 #define _CORESIGHT_PRIV_H
8
9 #include <linux/amba/bus.h>
10 #include <linux/bitops.h>
11 #include <linux/io.h>
12 #include <linux/coresight.h>
13 #include <linux/pm_runtime.h>
14
15 extern struct mutex coresight_mutex;
16 extern const struct device_type coresight_dev_type[];
17
18 /*
19 * Coresight management registers (0xf00-0xfcc)
20 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
21 * Trace registers in PFTv1.1
22 */
23 #define CORESIGHT_ITCTRL 0xf00
24 #define CORESIGHT_CLAIMSET 0xfa0
25 #define CORESIGHT_CLAIMCLR 0xfa4
26 #define CORESIGHT_LAR 0xfb0
27 #define CORESIGHT_LSR 0xfb4
28 #define CORESIGHT_DEVARCH 0xfbc
29 #define CORESIGHT_AUTHSTATUS 0xfb8
30 #define CORESIGHT_DEVID 0xfc8
31 #define CORESIGHT_DEVTYPE 0xfcc
32
33
34 /*
35 * Coresight device CLAIM protocol.
36 * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
37 */
38 #define CORESIGHT_CLAIM_MASK GENMASK(1, 0)
39 #define CORESIGHT_CLAIM_FREE 0
40 #define CORESIGHT_CLAIM_EXTERNAL 1
41 #define CORESIGHT_CLAIM_SELF_HOSTED 2
42 #define CORESIGHT_CLAIM_INVALID 3
43
44 #define TIMEOUT_US 100
45 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
46
47 #define ETM_MODE_EXCL_KERN BIT(30)
48 #define ETM_MODE_EXCL_USER BIT(31)
49 #define ETM_MODE_EXCL_HOST BIT(32)
50 #define ETM_MODE_EXCL_GUEST BIT(33)
51
52 struct cs_pair_attribute {
53 struct device_attribute attr;
54 u32 lo_off;
55 u32 hi_off;
56 };
57
58 struct cs_off_attribute {
59 struct device_attribute attr;
60 u32 off;
61 };
62
63 ssize_t coresight_simple_show32(struct device *_dev, struct device_attribute *attr, char *buf);
64 ssize_t coresight_simple_show_pair(struct device *_dev, struct device_attribute *attr, char *buf);
65
66 #define coresight_simple_reg32(name, offset) \
67 (&((struct cs_off_attribute[]) { \
68 { \
69 __ATTR(name, 0444, coresight_simple_show32, NULL), \
70 offset \
71 } \
72 })[0].attr.attr)
73
74 #define coresight_simple_reg64(name, lo_off, hi_off) \
75 (&((struct cs_pair_attribute[]) { \
76 { \
77 __ATTR(name, 0444, coresight_simple_show_pair, NULL), \
78 lo_off, hi_off \
79 } \
80 })[0].attr.attr)
81
82 extern const u32 coresight_barrier_pkt[4];
83 #define CORESIGHT_BARRIER_PKT_SIZE (sizeof(coresight_barrier_pkt))
84
85 enum etm_addr_type {
86 ETM_ADDR_TYPE_NONE,
87 ETM_ADDR_TYPE_SINGLE,
88 ETM_ADDR_TYPE_RANGE,
89 ETM_ADDR_TYPE_START,
90 ETM_ADDR_TYPE_STOP,
91 };
92
93 /**
94 * struct cs_buffer - keep track of a recording session' specifics
95 * @cur: index of the current buffer
96 * @nr_pages: max number of pages granted to us
97 * @pid: PID this cs_buffer belongs to
98 * @offset: offset within the current buffer
99 * @data_size: how much we collected in this run
100 * @snapshot: is this run in snapshot mode
101 * @data_pages: a handle the ring buffer
102 */
103 struct cs_buffers {
104 unsigned int cur;
105 unsigned int nr_pages;
106 pid_t pid;
107 unsigned long offset;
108 local_t data_size;
109 bool snapshot;
110 void **data_pages;
111 };
112
coresight_insert_barrier_packet(void * buf)113 static inline void coresight_insert_barrier_packet(void *buf)
114 {
115 if (buf)
116 memcpy(buf, coresight_barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
117 }
118
CS_LOCK(void __iomem * addr)119 static inline void CS_LOCK(void __iomem *addr)
120 {
121 do {
122 /* Wait for things to settle */
123 mb();
124 writel_relaxed(0x0, addr + CORESIGHT_LAR);
125 } while (0);
126 }
127
CS_UNLOCK(void __iomem * addr)128 static inline void CS_UNLOCK(void __iomem *addr)
129 {
130 do {
131 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
132 /* Make sure everyone has seen this */
133 mb();
134 } while (0);
135 }
136
137 void coresight_disable_path(struct coresight_path *path);
138 int coresight_enable_path(struct coresight_path *path, enum cs_mode mode);
139 struct coresight_device *coresight_get_sink(struct coresight_path *path);
140 struct coresight_device *coresight_get_sink_by_id(u32 id);
141 struct coresight_device *
142 coresight_find_default_sink(struct coresight_device *csdev);
143 struct coresight_path *coresight_build_path(struct coresight_device *csdev,
144 struct coresight_device *sink);
145 void coresight_release_path(struct coresight_path *path);
146 int coresight_add_sysfs_link(struct coresight_sysfs_link *info);
147 void coresight_remove_sysfs_link(struct coresight_sysfs_link *info);
148 int coresight_create_conns_sysfs_group(struct coresight_device *csdev);
149 void coresight_remove_conns_sysfs_group(struct coresight_device *csdev);
150 int coresight_make_links(struct coresight_device *orig,
151 struct coresight_connection *conn,
152 struct coresight_device *target);
153 void coresight_remove_links(struct coresight_device *orig,
154 struct coresight_connection *conn);
155 u32 coresight_get_sink_id(struct coresight_device *csdev);
156 void coresight_path_assign_trace_id(struct coresight_path *path,
157 enum cs_mode mode);
158
159 #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
160 int etm_readl_cp14(u32 off, unsigned int *val);
161 int etm_writel_cp14(u32 off, u32 val);
162 #else
etm_readl_cp14(u32 off,unsigned int * val)163 static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
etm_writel_cp14(u32 off,u32 val)164 static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
165 #endif
166
167 struct cti_assoc_op {
168 void (*add)(struct coresight_device *csdev);
169 void (*remove)(struct coresight_device *csdev);
170 };
171
172 void coresight_set_cti_ops(const struct cti_assoc_op *cti_op);
173 void coresight_remove_cti_ops(void);
174
175 /*
176 * Macros and inline functions to handle CoreSight UCI data and driver
177 * private data in AMBA ID table entries, and extract data values.
178 */
179
180 /* coresight AMBA ID, no UCI, no driver data: id table entry */
181 #define CS_AMBA_ID(pid) \
182 { \
183 .id = pid, \
184 .mask = 0x000fffff, \
185 }
186
187 /* coresight AMBA ID, UCI with driver data only: id table entry. */
188 #define CS_AMBA_ID_DATA(pid, dval) \
189 { \
190 .id = pid, \
191 .mask = 0x000fffff, \
192 .data = (void *)&(struct amba_cs_uci_id) \
193 { \
194 .data = (void *)dval, \
195 } \
196 }
197
198 /* coresight AMBA ID, full UCI structure: id table entry. */
199 #define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \
200 { \
201 .id = pid, \
202 .mask = m, \
203 .data = (void *)uci_ptr \
204 }
205 #define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci)
206 /*
207 * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the
208 * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that
209 * as a match value for blanket matching all devices in the given CoreSight
210 * device type and architecture.
211 */
212 #define PIDR2_JEDEC BIT(3)
213 #define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16)
214 /*
215 * Match all PIDs in a given CoreSight device type and architecture, defined
216 * by the uci.
217 */
218 #define CS_AMBA_MATCH_ALL_UCI(uci) \
219 __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)
220
221 /* extract the data value from a UCI structure given amba_id pointer. */
coresight_get_uci_data(const struct amba_id * id)222 static inline void *coresight_get_uci_data(const struct amba_id *id)
223 {
224 struct amba_cs_uci_id *uci_id = id->data;
225
226 if (!uci_id)
227 return NULL;
228
229 return uci_id->data;
230 }
231
coresight_get_uci_data_from_amba(const struct amba_id * table,u32 pid)232 static inline void *coresight_get_uci_data_from_amba(const struct amba_id *table, u32 pid)
233 {
234 while (table->mask) {
235 if ((pid & table->mask) == table->id)
236 return coresight_get_uci_data(table);
237 table++;
238 };
239 return NULL;
240 }
241
242 void coresight_release_platform_data(struct coresight_device *csdev,
243 struct device *dev,
244 struct coresight_platform_data *pdata);
245 struct coresight_device *
246 coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode);
247 void coresight_add_helper(struct coresight_device *csdev,
248 struct coresight_device *helper);
249
250 void coresight_set_percpu_sink(int cpu, struct coresight_device *csdev);
251 struct coresight_device *coresight_get_percpu_sink(int cpu);
252 void coresight_disable_source(struct coresight_device *csdev, void *data);
253 void coresight_pause_source(struct coresight_device *csdev);
254 int coresight_resume_source(struct coresight_device *csdev);
255
256 #endif
257