1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Texas Instruments DSPS platforms "glue layer" 4 * 5 * Copyright (C) 2012, by Texas Instruments 6 * 7 * Based on the am35x "glue layer" code. 8 * 9 * This file is part of the Inventra Controller Driver for Linux. 10 * 11 * musb_dsps.c will be a common file for all the TI DSPS platforms 12 * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x. 13 * For now only ti81x is using this and in future davinci.c, am35x.c 14 * da8xx.c would be merged to this file after testing. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/irq.h> 19 #include <linux/err.h> 20 #include <linux/platform_device.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/module.h> 24 #include <linux/usb/usb_phy_generic.h> 25 #include <linux/platform_data/usb-omap.h> 26 #include <linux/sizes.h> 27 #include <linux/string_choices.h> 28 29 #include <linux/of.h> 30 #include <linux/of_address.h> 31 #include <linux/usb/of.h> 32 33 #include <linux/debugfs.h> 34 35 #include "musb_core.h" 36 37 static const struct of_device_id musb_dsps_of_match[]; 38 39 /* 40 * DSPS musb wrapper register offset. 41 * FIXME: This should be expanded to have all the wrapper registers from TI DSPS 42 * musb ips. 43 */ 44 struct dsps_musb_wrapper { 45 u16 revision; 46 u16 control; 47 u16 status; 48 u16 epintr_set; 49 u16 epintr_clear; 50 u16 epintr_status; 51 u16 coreintr_set; 52 u16 coreintr_clear; 53 u16 coreintr_status; 54 u16 phy_utmi; 55 u16 mode; 56 u16 tx_mode; 57 u16 rx_mode; 58 59 /* bit positions for control */ 60 unsigned reset:5; 61 62 /* bit positions for interrupt */ 63 unsigned usb_shift:5; 64 u32 usb_mask; 65 u32 usb_bitmap; 66 unsigned drvvbus:5; 67 68 unsigned txep_shift:5; 69 u32 txep_mask; 70 u32 txep_bitmap; 71 72 unsigned rxep_shift:5; 73 u32 rxep_mask; 74 u32 rxep_bitmap; 75 76 /* bit positions for phy_utmi */ 77 unsigned otg_disable:5; 78 79 /* bit positions for mode */ 80 unsigned iddig:5; 81 unsigned iddig_mux:5; 82 /* miscellaneous stuff */ 83 unsigned poll_timeout; 84 }; 85 86 /* 87 * register shadow for suspend 88 */ 89 struct dsps_context { 90 u32 control; 91 u32 epintr; 92 u32 coreintr; 93 u32 phy_utmi; 94 u32 mode; 95 u32 tx_mode; 96 u32 rx_mode; 97 }; 98 99 /* 100 * DSPS glue structure. 101 */ 102 struct dsps_glue { 103 struct device *dev; 104 struct platform_device *musb; /* child musb pdev */ 105 const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */ 106 int vbus_irq; /* optional vbus irq */ 107 unsigned long last_timer; /* last timer data for each instance */ 108 bool sw_babble_enabled; 109 void __iomem *usbss_base; 110 111 struct dsps_context context; 112 struct debugfs_regset32 regset; 113 struct dentry *dbgfs_root; 114 }; 115 116 static const struct debugfs_reg32 dsps_musb_regs[] = { 117 { "revision", 0x00 }, 118 { "control", 0x14 }, 119 { "status", 0x18 }, 120 { "eoi", 0x24 }, 121 { "intr0_stat", 0x30 }, 122 { "intr1_stat", 0x34 }, 123 { "intr0_set", 0x38 }, 124 { "intr1_set", 0x3c }, 125 { "txmode", 0x70 }, 126 { "rxmode", 0x74 }, 127 { "autoreq", 0xd0 }, 128 { "srpfixtime", 0xd4 }, 129 { "tdown", 0xd8 }, 130 { "phy_utmi", 0xe0 }, 131 { "mode", 0xe8 }, 132 }; 133 134 static void dsps_mod_timer(struct dsps_glue *glue, int wait_ms) 135 { 136 struct musb *musb = platform_get_drvdata(glue->musb); 137 int wait; 138 139 if (wait_ms < 0) 140 wait = msecs_to_jiffies(glue->wrp->poll_timeout); 141 else 142 wait = msecs_to_jiffies(wait_ms); 143 144 mod_timer(&musb->dev_timer, jiffies + wait); 145 } 146 147 /* 148 * If no vbus irq from the PMIC is configured, we need to poll VBUS status. 149 */ 150 static void dsps_mod_timer_optional(struct dsps_glue *glue) 151 { 152 if (glue->vbus_irq) 153 return; 154 155 dsps_mod_timer(glue, -1); 156 } 157 158 /* USBSS / USB AM335x */ 159 #define USBSS_IRQ_STATUS 0x28 160 #define USBSS_IRQ_ENABLER 0x2c 161 #define USBSS_IRQ_CLEARR 0x30 162 163 #define USBSS_IRQ_PD_COMP (1 << 2) 164 165 /* 166 * dsps_musb_enable - enable interrupts 167 */ 168 static void dsps_musb_enable(struct musb *musb) 169 { 170 struct device *dev = musb->controller; 171 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 172 const struct dsps_musb_wrapper *wrp = glue->wrp; 173 void __iomem *reg_base = musb->ctrl_base; 174 u32 epmask, coremask; 175 176 /* Workaround: setup IRQs through both register sets. */ 177 epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) | 178 ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift); 179 coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF); 180 181 musb_writel(reg_base, wrp->epintr_set, epmask); 182 musb_writel(reg_base, wrp->coreintr_set, coremask); 183 /* 184 * start polling for runtime PM active and idle, 185 * and for ID change in dual-role idle mode. 186 */ 187 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE) 188 dsps_mod_timer(glue, -1); 189 } 190 191 /* 192 * dsps_musb_disable - disable HDRC and flush interrupts 193 */ 194 static void dsps_musb_disable(struct musb *musb) 195 { 196 struct device *dev = musb->controller; 197 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 198 const struct dsps_musb_wrapper *wrp = glue->wrp; 199 void __iomem *reg_base = musb->ctrl_base; 200 201 musb_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap); 202 musb_writel(reg_base, wrp->epintr_clear, 203 wrp->txep_bitmap | wrp->rxep_bitmap); 204 timer_delete_sync(&musb->dev_timer); 205 } 206 207 /* Caller must take musb->lock */ 208 static int dsps_check_status(struct musb *musb, void *unused) 209 { 210 void __iomem *mregs = musb->mregs; 211 struct device *dev = musb->controller; 212 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 213 const struct dsps_musb_wrapper *wrp = glue->wrp; 214 u8 devctl; 215 int skip_session = 0; 216 217 if (glue->vbus_irq) 218 timer_delete(&musb->dev_timer); 219 220 /* 221 * We poll because DSPS IP's won't expose several OTG-critical 222 * status change events (from the transceiver) otherwise. 223 */ 224 devctl = musb_readb(mregs, MUSB_DEVCTL); 225 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, 226 usb_otg_state_string(musb->xceiv->otg->state)); 227 228 switch (musb->xceiv->otg->state) { 229 case OTG_STATE_A_WAIT_VRISE: 230 if (musb->port_mode == MUSB_HOST) { 231 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; 232 dsps_mod_timer_optional(glue); 233 break; 234 } 235 fallthrough; 236 237 case OTG_STATE_A_WAIT_BCON: 238 /* keep VBUS on for host-only mode */ 239 if (musb->port_mode == MUSB_HOST) { 240 dsps_mod_timer_optional(glue); 241 break; 242 } 243 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 244 skip_session = 1; 245 fallthrough; 246 247 case OTG_STATE_A_IDLE: 248 case OTG_STATE_B_IDLE: 249 if (!glue->vbus_irq) { 250 if (devctl & MUSB_DEVCTL_BDEVICE) { 251 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 252 MUSB_DEV_MODE(musb); 253 } else { 254 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 255 MUSB_HST_MODE(musb); 256 } 257 258 if (musb->port_mode == MUSB_PERIPHERAL) 259 skip_session = 1; 260 261 if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session) 262 musb_writeb(mregs, MUSB_DEVCTL, 263 MUSB_DEVCTL_SESSION); 264 } 265 dsps_mod_timer_optional(glue); 266 break; 267 case OTG_STATE_A_WAIT_VFALL: 268 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 269 musb_writel(musb->ctrl_base, wrp->coreintr_set, 270 MUSB_INTR_VBUSERROR << wrp->usb_shift); 271 break; 272 default: 273 break; 274 } 275 276 return 0; 277 } 278 279 static void otg_timer(struct timer_list *t) 280 { 281 struct musb *musb = timer_container_of(musb, t, dev_timer); 282 struct device *dev = musb->controller; 283 unsigned long flags; 284 int err; 285 286 err = pm_runtime_get(dev); 287 if ((err != -EINPROGRESS) && err < 0) { 288 dev_err(dev, "Poll could not pm_runtime_get: %i\n", err); 289 pm_runtime_put_noidle(dev); 290 291 return; 292 } 293 294 spin_lock_irqsave(&musb->lock, flags); 295 err = musb_queue_resume_work(musb, dsps_check_status, NULL); 296 if (err < 0) 297 dev_err(dev, "%s resume work: %i\n", __func__, err); 298 spin_unlock_irqrestore(&musb->lock, flags); 299 pm_runtime_put_autosuspend(dev); 300 } 301 302 static void dsps_musb_clear_ep_rxintr(struct musb *musb, int epnum) 303 { 304 u32 epintr; 305 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent); 306 const struct dsps_musb_wrapper *wrp = glue->wrp; 307 308 /* musb->lock might already been held */ 309 epintr = (1 << epnum) << wrp->rxep_shift; 310 musb_writel(musb->ctrl_base, wrp->epintr_status, epintr); 311 } 312 313 static irqreturn_t dsps_interrupt(int irq, void *hci) 314 { 315 struct musb *musb = hci; 316 void __iomem *reg_base = musb->ctrl_base; 317 struct device *dev = musb->controller; 318 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 319 const struct dsps_musb_wrapper *wrp = glue->wrp; 320 unsigned long flags; 321 irqreturn_t ret = IRQ_NONE; 322 u32 epintr, usbintr; 323 324 spin_lock_irqsave(&musb->lock, flags); 325 326 /* Get endpoint interrupts */ 327 epintr = musb_readl(reg_base, wrp->epintr_status); 328 musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift; 329 musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift; 330 331 if (epintr) 332 musb_writel(reg_base, wrp->epintr_status, epintr); 333 334 /* Get usb core interrupts */ 335 usbintr = musb_readl(reg_base, wrp->coreintr_status); 336 if (!usbintr && !epintr) 337 goto out; 338 339 musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift; 340 if (usbintr) 341 musb_writel(reg_base, wrp->coreintr_status, usbintr); 342 343 dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", 344 usbintr, epintr); 345 346 if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) { 347 int drvvbus = musb_readl(reg_base, wrp->status); 348 void __iomem *mregs = musb->mregs; 349 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 350 int err; 351 352 err = musb->int_usb & MUSB_INTR_VBUSERROR; 353 if (err) { 354 /* 355 * The Mentor core doesn't debounce VBUS as needed 356 * to cope with device connect current spikes. This 357 * means it's not uncommon for bus-powered devices 358 * to get VBUS errors during enumeration. 359 * 360 * This is a workaround, but newer RTL from Mentor 361 * seems to allow a better one: "re"-starting sessions 362 * without waiting for VBUS to stop registering in 363 * devctl. 364 */ 365 musb->int_usb &= ~MUSB_INTR_VBUSERROR; 366 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; 367 dsps_mod_timer_optional(glue); 368 WARNING("VBUS error workaround (delay coming)\n"); 369 } else if (drvvbus) { 370 MUSB_HST_MODE(musb); 371 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 372 dsps_mod_timer_optional(glue); 373 } else { 374 musb->is_active = 0; 375 MUSB_DEV_MODE(musb); 376 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 377 } 378 379 /* NOTE: this must complete power-on within 100 ms. */ 380 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", 381 str_on_off(drvvbus), 382 usb_otg_state_string(musb->xceiv->otg->state), 383 err ? " ERROR" : "", 384 devctl); 385 ret = IRQ_HANDLED; 386 } 387 388 if (musb->int_tx || musb->int_rx || musb->int_usb) 389 ret |= musb_interrupt(musb); 390 391 /* Poll for ID change and connect */ 392 switch (musb->xceiv->otg->state) { 393 case OTG_STATE_B_IDLE: 394 case OTG_STATE_A_WAIT_BCON: 395 dsps_mod_timer_optional(glue); 396 break; 397 default: 398 break; 399 } 400 401 out: 402 spin_unlock_irqrestore(&musb->lock, flags); 403 404 return ret; 405 } 406 407 static int dsps_musb_dbg_init(struct musb *musb, struct dsps_glue *glue) 408 { 409 struct dentry *root; 410 char buf[128]; 411 412 sprintf(buf, "%s.dsps", dev_name(musb->controller)); 413 root = debugfs_create_dir(buf, usb_debug_root); 414 glue->dbgfs_root = root; 415 416 glue->regset.regs = dsps_musb_regs; 417 glue->regset.nregs = ARRAY_SIZE(dsps_musb_regs); 418 glue->regset.base = musb->ctrl_base; 419 420 debugfs_create_regset32("regdump", S_IRUGO, root, &glue->regset); 421 return 0; 422 } 423 424 static int dsps_musb_init(struct musb *musb) 425 { 426 struct device *dev = musb->controller; 427 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 428 struct platform_device *parent = to_platform_device(dev->parent); 429 const struct dsps_musb_wrapper *wrp = glue->wrp; 430 void __iomem *reg_base; 431 struct resource *r; 432 u32 rev, val; 433 int ret; 434 435 r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control"); 436 reg_base = devm_ioremap_resource(dev, r); 437 if (IS_ERR(reg_base)) 438 return PTR_ERR(reg_base); 439 musb->ctrl_base = reg_base; 440 441 /* NOP driver needs change if supporting dual instance */ 442 musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent, "phys", 0); 443 if (IS_ERR(musb->xceiv)) 444 return PTR_ERR(musb->xceiv); 445 446 musb->phy = devm_phy_get(dev->parent, "usb2-phy"); 447 448 /* Returns zero if e.g. not clocked */ 449 rev = musb_readl(reg_base, wrp->revision); 450 if (!rev) 451 return -ENODEV; 452 453 if (IS_ERR(musb->phy)) { 454 musb->phy = NULL; 455 } else { 456 ret = phy_init(musb->phy); 457 if (ret < 0) 458 return ret; 459 ret = phy_power_on(musb->phy); 460 if (ret) { 461 phy_exit(musb->phy); 462 return ret; 463 } 464 } 465 466 timer_setup(&musb->dev_timer, otg_timer, 0); 467 468 /* Reset the musb */ 469 musb_writel(reg_base, wrp->control, (1 << wrp->reset)); 470 471 musb->isr = dsps_interrupt; 472 473 /* reset the otgdisable bit, needed for host mode to work */ 474 val = musb_readl(reg_base, wrp->phy_utmi); 475 val &= ~(1 << wrp->otg_disable); 476 musb_writel(musb->ctrl_base, wrp->phy_utmi, val); 477 478 /* 479 * Check whether the dsps version has babble control enabled. 480 * In latest silicon revision the babble control logic is enabled. 481 * If MUSB_BABBLE_CTL returns 0x4 then we have the babble control 482 * logic enabled. 483 */ 484 val = musb_readb(musb->mregs, MUSB_BABBLE_CTL); 485 if (val & MUSB_BABBLE_RCV_DISABLE) { 486 glue->sw_babble_enabled = true; 487 val |= MUSB_BABBLE_SW_SESSION_CTRL; 488 musb_writeb(musb->mregs, MUSB_BABBLE_CTL, val); 489 } 490 491 dsps_mod_timer(glue, -1); 492 493 return dsps_musb_dbg_init(musb, glue); 494 } 495 496 static int dsps_musb_exit(struct musb *musb) 497 { 498 struct device *dev = musb->controller; 499 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 500 501 timer_delete_sync(&musb->dev_timer); 502 phy_power_off(musb->phy); 503 phy_exit(musb->phy); 504 debugfs_remove_recursive(glue->dbgfs_root); 505 506 return 0; 507 } 508 509 static int dsps_musb_set_mode(struct musb *musb, u8 mode) 510 { 511 struct device *dev = musb->controller; 512 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 513 const struct dsps_musb_wrapper *wrp = glue->wrp; 514 void __iomem *ctrl_base = musb->ctrl_base; 515 u32 reg; 516 517 reg = musb_readl(ctrl_base, wrp->mode); 518 519 switch (mode) { 520 case MUSB_HOST: 521 reg &= ~(1 << wrp->iddig); 522 523 /* 524 * if we're setting mode to host-only or device-only, we're 525 * going to ignore whatever the PHY sends us and just force 526 * ID pin status by SW 527 */ 528 reg |= (1 << wrp->iddig_mux); 529 530 musb_writel(ctrl_base, wrp->mode, reg); 531 musb_writel(ctrl_base, wrp->phy_utmi, 0x02); 532 break; 533 case MUSB_PERIPHERAL: 534 reg |= (1 << wrp->iddig); 535 536 /* 537 * if we're setting mode to host-only or device-only, we're 538 * going to ignore whatever the PHY sends us and just force 539 * ID pin status by SW 540 */ 541 reg |= (1 << wrp->iddig_mux); 542 543 musb_writel(ctrl_base, wrp->mode, reg); 544 break; 545 case MUSB_OTG: 546 musb_writel(ctrl_base, wrp->phy_utmi, 0x02); 547 break; 548 default: 549 dev_err(glue->dev, "unsupported mode %d\n", mode); 550 return -EINVAL; 551 } 552 553 return 0; 554 } 555 556 static bool dsps_sw_babble_control(struct musb *musb) 557 { 558 u8 babble_ctl; 559 bool session_restart = false; 560 561 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL); 562 dev_dbg(musb->controller, "babble: MUSB_BABBLE_CTL value %x\n", 563 babble_ctl); 564 /* 565 * check line monitor flag to check whether babble is 566 * due to noise 567 */ 568 dev_dbg(musb->controller, "STUCK_J is %s\n", 569 babble_ctl & MUSB_BABBLE_STUCK_J ? "set" : "reset"); 570 571 if (babble_ctl & MUSB_BABBLE_STUCK_J) { 572 int timeout = 10; 573 574 /* 575 * babble is due to noise, then set transmit idle (d7 bit) 576 * to resume normal operation 577 */ 578 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL); 579 babble_ctl |= MUSB_BABBLE_FORCE_TXIDLE; 580 musb_writeb(musb->mregs, MUSB_BABBLE_CTL, babble_ctl); 581 582 /* wait till line monitor flag cleared */ 583 dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n"); 584 do { 585 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL); 586 udelay(1); 587 } while ((babble_ctl & MUSB_BABBLE_STUCK_J) && timeout--); 588 589 /* check whether stuck_at_j bit cleared */ 590 if (babble_ctl & MUSB_BABBLE_STUCK_J) { 591 /* 592 * real babble condition has occurred 593 * restart the controller to start the 594 * session again 595 */ 596 dev_dbg(musb->controller, "J not cleared, misc (%x)\n", 597 babble_ctl); 598 session_restart = true; 599 } 600 } else { 601 session_restart = true; 602 } 603 604 return session_restart; 605 } 606 607 static int dsps_musb_recover(struct musb *musb) 608 { 609 struct device *dev = musb->controller; 610 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 611 int session_restart = 0; 612 613 if (glue->sw_babble_enabled) 614 session_restart = dsps_sw_babble_control(musb); 615 else 616 session_restart = 1; 617 618 return session_restart ? 0 : -EPIPE; 619 } 620 621 static int dsps_musb_vbus_status(struct musb *musb) 622 { 623 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 624 625 return (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS; 626 } 627 628 static void dsps_musb_set_vbus(struct musb *musb, int is_on) 629 { 630 u8 devctl; 631 632 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 633 634 if (is_on) { 635 devctl |= MUSB_DEVCTL_SESSION; 636 } else { 637 musb_root_disconnect(musb); 638 devctl &= ~MUSB_DEVCTL_SESSION; 639 } 640 641 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 642 } 643 644 /* Similar to am35x, dm81xx support only 32-bit read operation */ 645 static void dsps_read_fifo32(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 646 { 647 void __iomem *fifo = hw_ep->fifo; 648 649 if (len >= 4) { 650 ioread32_rep(fifo, dst, len >> 2); 651 dst += len & ~0x03; 652 len &= 0x03; 653 } 654 655 /* Read any remaining 1 to 3 bytes */ 656 if (len > 0) { 657 u32 val = musb_readl(fifo, 0); 658 memcpy(dst, &val, len); 659 } 660 } 661 662 #ifdef CONFIG_USB_TI_CPPI41_DMA 663 static void dsps_dma_controller_callback(struct dma_controller *c) 664 { 665 struct musb *musb = c->musb; 666 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent); 667 void __iomem *usbss_base = glue->usbss_base; 668 u32 status; 669 670 status = musb_readl(usbss_base, USBSS_IRQ_STATUS); 671 if (status & USBSS_IRQ_PD_COMP) 672 musb_writel(usbss_base, USBSS_IRQ_STATUS, USBSS_IRQ_PD_COMP); 673 } 674 675 static struct dma_controller * 676 dsps_dma_controller_create(struct musb *musb, void __iomem *base) 677 { 678 struct dma_controller *controller; 679 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent); 680 void __iomem *usbss_base = glue->usbss_base; 681 682 controller = cppi41_dma_controller_create(musb, base); 683 if (IS_ERR_OR_NULL(controller)) 684 return controller; 685 686 musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP); 687 controller->dma_callback = dsps_dma_controller_callback; 688 689 return controller; 690 } 691 692 #ifdef CONFIG_PM_SLEEP 693 static void dsps_dma_controller_suspend(struct dsps_glue *glue) 694 { 695 void __iomem *usbss_base = glue->usbss_base; 696 697 musb_writel(usbss_base, USBSS_IRQ_CLEARR, USBSS_IRQ_PD_COMP); 698 } 699 700 static void dsps_dma_controller_resume(struct dsps_glue *glue) 701 { 702 void __iomem *usbss_base = glue->usbss_base; 703 704 musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP); 705 } 706 #endif 707 #else /* CONFIG_USB_TI_CPPI41_DMA */ 708 #ifdef CONFIG_PM_SLEEP 709 static void dsps_dma_controller_suspend(struct dsps_glue *glue) {} 710 static void dsps_dma_controller_resume(struct dsps_glue *glue) {} 711 #endif 712 #endif /* CONFIG_USB_TI_CPPI41_DMA */ 713 714 static struct musb_platform_ops dsps_ops = { 715 .quirks = MUSB_DMA_CPPI41 | MUSB_INDEXED_EP, 716 .init = dsps_musb_init, 717 .exit = dsps_musb_exit, 718 719 #ifdef CONFIG_USB_TI_CPPI41_DMA 720 .dma_init = dsps_dma_controller_create, 721 .dma_exit = cppi41_dma_controller_destroy, 722 #endif 723 .enable = dsps_musb_enable, 724 .disable = dsps_musb_disable, 725 726 .set_mode = dsps_musb_set_mode, 727 .recover = dsps_musb_recover, 728 .vbus_status = dsps_musb_vbus_status, 729 .set_vbus = dsps_musb_set_vbus, 730 .clear_ep_rxintr = dsps_musb_clear_ep_rxintr, 731 }; 732 733 static u64 musb_dmamask = DMA_BIT_MASK(32); 734 735 static int get_int_prop(struct device_node *dn, const char *s) 736 { 737 int ret; 738 u32 val; 739 740 ret = of_property_read_u32(dn, s, &val); 741 if (ret) 742 return 0; 743 return val; 744 } 745 746 static int dsps_create_musb_pdev(struct dsps_glue *glue, 747 struct platform_device *parent) 748 { 749 struct musb_hdrc_platform_data pdata; 750 struct resource resources[2]; 751 struct resource *res; 752 struct device *dev = &parent->dev; 753 struct musb_hdrc_config *config; 754 struct platform_device *musb; 755 struct device_node *dn = parent->dev.of_node; 756 int ret, val; 757 758 memset(resources, 0, sizeof(resources)); 759 res = platform_get_resource_byname(parent, IORESOURCE_MEM, "mc"); 760 if (!res) { 761 dev_err(dev, "failed to get memory.\n"); 762 return -EINVAL; 763 } 764 resources[0] = *res; 765 766 ret = platform_get_irq_byname(parent, "mc"); 767 if (ret < 0) 768 return ret; 769 770 resources[1].start = ret; 771 resources[1].end = ret; 772 resources[1].flags = IORESOURCE_IRQ | irq_get_trigger_type(ret); 773 resources[1].name = "mc"; 774 775 /* allocate the child platform device */ 776 musb = platform_device_alloc("musb-hdrc", 777 (resources[0].start & 0xFFF) == 0x400 ? 0 : 1); 778 if (!musb) { 779 dev_err(dev, "failed to allocate musb device\n"); 780 return -ENOMEM; 781 } 782 783 musb->dev.parent = dev; 784 musb->dev.dma_mask = &musb_dmamask; 785 musb->dev.coherent_dma_mask = musb_dmamask; 786 device_set_of_node_from_dev(&musb->dev, &parent->dev); 787 788 glue->musb = musb; 789 790 ret = platform_device_add_resources(musb, resources, 791 ARRAY_SIZE(resources)); 792 if (ret) { 793 dev_err(dev, "failed to add resources\n"); 794 goto err; 795 } 796 797 config = devm_kzalloc(&parent->dev, sizeof(*config), GFP_KERNEL); 798 if (!config) { 799 ret = -ENOMEM; 800 goto err; 801 } 802 pdata.config = config; 803 pdata.platform_ops = &dsps_ops; 804 805 config->num_eps = get_int_prop(dn, "mentor,num-eps"); 806 config->ram_bits = get_int_prop(dn, "mentor,ram-bits"); 807 config->host_port_deassert_reset_at_resume = 1; 808 pdata.mode = musb_get_mode(dev); 809 /* DT keeps this entry in mA, musb expects it as per USB spec */ 810 pdata.power = get_int_prop(dn, "mentor,power") / 2; 811 812 ret = of_property_read_u32(dn, "mentor,multipoint", &val); 813 if (!ret && val) 814 config->multipoint = true; 815 816 config->maximum_speed = usb_get_maximum_speed(&parent->dev); 817 switch (config->maximum_speed) { 818 case USB_SPEED_LOW: 819 case USB_SPEED_FULL: 820 break; 821 case USB_SPEED_SUPER: 822 dev_warn(dev, "ignore incorrect maximum_speed " 823 "(super-speed) setting in dts"); 824 fallthrough; 825 default: 826 config->maximum_speed = USB_SPEED_HIGH; 827 } 828 829 ret = platform_device_add_data(musb, &pdata, sizeof(pdata)); 830 if (ret) { 831 dev_err(dev, "failed to add platform_data\n"); 832 goto err; 833 } 834 835 ret = platform_device_add(musb); 836 if (ret) { 837 dev_err(dev, "failed to register musb device\n"); 838 goto err; 839 } 840 return 0; 841 842 err: 843 platform_device_put(musb); 844 return ret; 845 } 846 847 static irqreturn_t dsps_vbus_threaded_irq(int irq, void *priv) 848 { 849 struct dsps_glue *glue = priv; 850 struct musb *musb = platform_get_drvdata(glue->musb); 851 852 if (!musb) 853 return IRQ_NONE; 854 855 dev_dbg(glue->dev, "VBUS interrupt\n"); 856 dsps_mod_timer(glue, 0); 857 858 return IRQ_HANDLED; 859 } 860 861 static int dsps_setup_optional_vbus_irq(struct platform_device *pdev, 862 struct dsps_glue *glue) 863 { 864 int error; 865 866 glue->vbus_irq = platform_get_irq_byname_optional(pdev, "vbus"); 867 if (glue->vbus_irq == -EPROBE_DEFER) 868 return -EPROBE_DEFER; 869 870 if (glue->vbus_irq <= 0) { 871 glue->vbus_irq = 0; 872 return 0; 873 } 874 875 error = devm_request_threaded_irq(glue->dev, glue->vbus_irq, 876 NULL, dsps_vbus_threaded_irq, 877 IRQF_SHARED, 878 "vbus", glue); 879 if (error) { 880 glue->vbus_irq = 0; 881 return error; 882 } 883 dev_dbg(glue->dev, "VBUS irq %i configured\n", glue->vbus_irq); 884 885 return 0; 886 } 887 888 static int dsps_probe(struct platform_device *pdev) 889 { 890 const struct of_device_id *match; 891 const struct dsps_musb_wrapper *wrp; 892 struct dsps_glue *glue; 893 int ret; 894 895 if (!strcmp(pdev->name, "musb-hdrc")) 896 return -ENODEV; 897 898 match = of_match_node(musb_dsps_of_match, pdev->dev.of_node); 899 if (!match) { 900 dev_err(&pdev->dev, "fail to get matching of_match struct\n"); 901 return -EINVAL; 902 } 903 wrp = match->data; 904 905 if (of_device_is_compatible(pdev->dev.of_node, "ti,musb-dm816")) 906 dsps_ops.read_fifo = dsps_read_fifo32; 907 908 /* allocate glue */ 909 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 910 if (!glue) 911 return -ENOMEM; 912 913 glue->dev = &pdev->dev; 914 glue->wrp = wrp; 915 glue->usbss_base = of_iomap(pdev->dev.parent->of_node, 0); 916 if (!glue->usbss_base) 917 return -ENXIO; 918 919 platform_set_drvdata(pdev, glue); 920 pm_runtime_enable(&pdev->dev); 921 ret = dsps_create_musb_pdev(glue, pdev); 922 if (ret) 923 goto err; 924 925 if (usb_get_dr_mode(&pdev->dev) == USB_DR_MODE_PERIPHERAL) { 926 ret = dsps_setup_optional_vbus_irq(pdev, glue); 927 if (ret) 928 goto unregister_pdev; 929 } 930 931 return 0; 932 933 unregister_pdev: 934 platform_device_unregister(glue->musb); 935 err: 936 pm_runtime_disable(&pdev->dev); 937 iounmap(glue->usbss_base); 938 return ret; 939 } 940 941 static void dsps_remove(struct platform_device *pdev) 942 { 943 struct dsps_glue *glue = platform_get_drvdata(pdev); 944 945 platform_device_unregister(glue->musb); 946 947 pm_runtime_disable(&pdev->dev); 948 iounmap(glue->usbss_base); 949 } 950 951 static const struct dsps_musb_wrapper am33xx_driver_data = { 952 .revision = 0x00, 953 .control = 0x14, 954 .status = 0x18, 955 .epintr_set = 0x38, 956 .epintr_clear = 0x40, 957 .epintr_status = 0x30, 958 .coreintr_set = 0x3c, 959 .coreintr_clear = 0x44, 960 .coreintr_status = 0x34, 961 .phy_utmi = 0xe0, 962 .mode = 0xe8, 963 .tx_mode = 0x70, 964 .rx_mode = 0x74, 965 .reset = 0, 966 .otg_disable = 21, 967 .iddig = 8, 968 .iddig_mux = 7, 969 .usb_shift = 0, 970 .usb_mask = 0x1ff, 971 .usb_bitmap = (0x1ff << 0), 972 .drvvbus = 8, 973 .txep_shift = 0, 974 .txep_mask = 0xffff, 975 .txep_bitmap = (0xffff << 0), 976 .rxep_shift = 16, 977 .rxep_mask = 0xfffe, 978 .rxep_bitmap = (0xfffe << 16), 979 .poll_timeout = 2000, /* ms */ 980 }; 981 982 static const struct of_device_id musb_dsps_of_match[] = { 983 { .compatible = "ti,musb-am33xx", 984 .data = &am33xx_driver_data, }, 985 { .compatible = "ti,musb-dm816", 986 .data = &am33xx_driver_data, }, 987 { }, 988 }; 989 MODULE_DEVICE_TABLE(of, musb_dsps_of_match); 990 991 #ifdef CONFIG_PM_SLEEP 992 static int dsps_suspend(struct device *dev) 993 { 994 struct dsps_glue *glue = dev_get_drvdata(dev); 995 const struct dsps_musb_wrapper *wrp = glue->wrp; 996 struct musb *musb = platform_get_drvdata(glue->musb); 997 void __iomem *mbase; 998 int ret; 999 1000 if (!musb) 1001 /* This can happen if the musb device is in -EPROBE_DEFER */ 1002 return 0; 1003 1004 ret = pm_runtime_get_sync(dev); 1005 if (ret < 0) { 1006 pm_runtime_put_noidle(dev); 1007 return ret; 1008 } 1009 1010 timer_delete_sync(&musb->dev_timer); 1011 1012 mbase = musb->ctrl_base; 1013 glue->context.control = musb_readl(mbase, wrp->control); 1014 glue->context.epintr = musb_readl(mbase, wrp->epintr_set); 1015 glue->context.coreintr = musb_readl(mbase, wrp->coreintr_set); 1016 glue->context.phy_utmi = musb_readl(mbase, wrp->phy_utmi); 1017 glue->context.mode = musb_readl(mbase, wrp->mode); 1018 glue->context.tx_mode = musb_readl(mbase, wrp->tx_mode); 1019 glue->context.rx_mode = musb_readl(mbase, wrp->rx_mode); 1020 1021 dsps_dma_controller_suspend(glue); 1022 1023 return 0; 1024 } 1025 1026 static int dsps_resume(struct device *dev) 1027 { 1028 struct dsps_glue *glue = dev_get_drvdata(dev); 1029 const struct dsps_musb_wrapper *wrp = glue->wrp; 1030 struct musb *musb = platform_get_drvdata(glue->musb); 1031 void __iomem *mbase; 1032 1033 if (!musb) 1034 return 0; 1035 1036 dsps_dma_controller_resume(glue); 1037 1038 mbase = musb->ctrl_base; 1039 musb_writel(mbase, wrp->control, glue->context.control); 1040 musb_writel(mbase, wrp->epintr_set, glue->context.epintr); 1041 musb_writel(mbase, wrp->coreintr_set, glue->context.coreintr); 1042 musb_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi); 1043 musb_writel(mbase, wrp->mode, glue->context.mode); 1044 musb_writel(mbase, wrp->tx_mode, glue->context.tx_mode); 1045 musb_writel(mbase, wrp->rx_mode, glue->context.rx_mode); 1046 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE && 1047 musb->port_mode == MUSB_OTG) 1048 dsps_mod_timer(glue, -1); 1049 1050 pm_runtime_put(dev); 1051 1052 return 0; 1053 } 1054 #endif 1055 1056 static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume); 1057 1058 static struct platform_driver dsps_usbss_driver = { 1059 .probe = dsps_probe, 1060 .remove = dsps_remove, 1061 .driver = { 1062 .name = "musb-dsps", 1063 .pm = &dsps_pm_ops, 1064 .of_match_table = musb_dsps_of_match, 1065 }, 1066 }; 1067 1068 MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer"); 1069 MODULE_AUTHOR("Ravi B <ravibabu@ti.com>"); 1070 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>"); 1071 MODULE_LICENSE("GPL v2"); 1072 1073 module_platform_driver(dsps_usbss_driver); 1074