1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5677-spi.c -- RT5677 ALSA SoC audio codec driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Oder Chiou <oder_chiou@realtek.com> 7 */ 8 9 #include <linux/cleanup.h> 10 #include <linux/module.h> 11 #include <linux/input.h> 12 #include <linux/spi/spi.h> 13 #include <linux/device.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/slab.h> 19 #include <linux/sched.h> 20 #include <linux/uaccess.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/pm_qos.h> 23 #include <linux/sysfs.h> 24 #include <linux/clk.h> 25 #include <linux/firmware.h> 26 #include <linux/acpi.h> 27 28 #include <sound/soc.h> 29 30 #include "rt5677.h" 31 #include "rt5677-spi.h" 32 33 #define DRV_NAME "rt5677spi" 34 35 #define RT5677_SPI_BURST_LEN 240 36 #define RT5677_SPI_HEADER 5 37 #define RT5677_SPI_FREQ 6000000 38 39 /* The AddressPhase and DataPhase of SPI commands are MSB first on the wire. 40 * DataPhase word size of 16-bit commands is 2 bytes. 41 * DataPhase word size of 32-bit commands is 4 bytes. 42 * DataPhase word size of burst commands is 8 bytes. 43 * The DSP CPU is little-endian. 44 */ 45 #define RT5677_SPI_WRITE_BURST 0x5 46 #define RT5677_SPI_READ_BURST 0x4 47 #define RT5677_SPI_WRITE_32 0x3 48 #define RT5677_SPI_READ_32 0x2 49 #define RT5677_SPI_WRITE_16 0x1 50 #define RT5677_SPI_READ_16 0x0 51 52 #define RT5677_BUF_BYTES_TOTAL 0x20000 53 #define RT5677_MIC_BUF_ADDR 0x60030000 54 #define RT5677_MODEL_ADDR 0x5FFC9800 55 #define RT5677_MIC_BUF_BYTES ((u32)(RT5677_BUF_BYTES_TOTAL - \ 56 sizeof(u32))) 57 #define RT5677_MIC_BUF_FIRST_READ_SIZE 0x10000 58 59 static struct spi_device *g_spi; 60 static DEFINE_MUTEX(spi_mutex); 61 62 struct rt5677_dsp { 63 struct device *dev; 64 struct delayed_work copy_work; 65 struct mutex dma_lock; 66 struct snd_pcm_substream *substream; 67 size_t dma_offset; /* zero-based offset into runtime->dma_area */ 68 size_t avail_bytes; /* number of new bytes since last period */ 69 u32 mic_read_offset; /* zero-based offset into DSP's mic buffer */ 70 bool new_hotword; /* a new hotword is fired */ 71 }; 72 73 static const struct snd_pcm_hardware rt5677_spi_pcm_hardware = { 74 .info = SNDRV_PCM_INFO_MMAP | 75 SNDRV_PCM_INFO_MMAP_VALID | 76 SNDRV_PCM_INFO_INTERLEAVED, 77 .formats = SNDRV_PCM_FMTBIT_S16_LE, 78 .period_bytes_min = PAGE_SIZE, 79 .period_bytes_max = RT5677_BUF_BYTES_TOTAL / 8, 80 .periods_min = 8, 81 .periods_max = 8, 82 .channels_min = 1, 83 .channels_max = 1, 84 .buffer_bytes_max = RT5677_BUF_BYTES_TOTAL, 85 }; 86 87 static struct snd_soc_dai_driver rt5677_spi_dai = { 88 /* The DAI name "rt5677-dsp-cpu-dai" is not used. The actual DAI name 89 * registered with ASoC is the name of the device "spi-RT5677AA:00", 90 * because we only have one DAI. See snd_soc_register_dais(). 91 */ 92 .name = "rt5677-dsp-cpu-dai", 93 .id = 0, 94 .capture = { 95 .stream_name = "DSP Capture", 96 .channels_min = 1, 97 .channels_max = 1, 98 .rates = SNDRV_PCM_RATE_16000, 99 .formats = SNDRV_PCM_FMTBIT_S16_LE, 100 }, 101 }; 102 103 /* PCM for streaming audio from the DSP buffer */ 104 static int rt5677_spi_pcm_open( 105 struct snd_soc_component *component, 106 struct snd_pcm_substream *substream) 107 { 108 snd_soc_set_runtime_hwparams(substream, &rt5677_spi_pcm_hardware); 109 return 0; 110 } 111 112 static int rt5677_spi_pcm_close( 113 struct snd_soc_component *component, 114 struct snd_pcm_substream *substream) 115 { 116 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 117 struct snd_soc_component *codec_component = 118 snd_soc_rtdcom_lookup(rtd, "rt5677"); 119 struct rt5677_priv *rt5677 = 120 snd_soc_component_get_drvdata(codec_component); 121 struct rt5677_dsp *rt5677_dsp = 122 snd_soc_component_get_drvdata(component); 123 124 cancel_delayed_work_sync(&rt5677_dsp->copy_work); 125 rt5677->set_dsp_vad(codec_component, false); 126 return 0; 127 } 128 129 static int rt5677_spi_hw_params( 130 struct snd_soc_component *component, 131 struct snd_pcm_substream *substream, 132 struct snd_pcm_hw_params *hw_params) 133 { 134 struct rt5677_dsp *rt5677_dsp = 135 snd_soc_component_get_drvdata(component); 136 137 guard(mutex)(&rt5677_dsp->dma_lock); 138 rt5677_dsp->substream = substream; 139 140 return 0; 141 } 142 143 static int rt5677_spi_hw_free( 144 struct snd_soc_component *component, 145 struct snd_pcm_substream *substream) 146 { 147 struct rt5677_dsp *rt5677_dsp = 148 snd_soc_component_get_drvdata(component); 149 150 guard(mutex)(&rt5677_dsp->dma_lock); 151 rt5677_dsp->substream = NULL; 152 153 return 0; 154 } 155 156 static int rt5677_spi_prepare( 157 struct snd_soc_component *component, 158 struct snd_pcm_substream *substream) 159 { 160 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 161 struct snd_soc_component *rt5677_component = 162 snd_soc_rtdcom_lookup(rtd, "rt5677"); 163 struct rt5677_priv *rt5677 = 164 snd_soc_component_get_drvdata(rt5677_component); 165 struct rt5677_dsp *rt5677_dsp = 166 snd_soc_component_get_drvdata(component); 167 168 rt5677->set_dsp_vad(rt5677_component, true); 169 rt5677_dsp->dma_offset = 0; 170 rt5677_dsp->avail_bytes = 0; 171 return 0; 172 } 173 174 static snd_pcm_uframes_t rt5677_spi_pcm_pointer( 175 struct snd_soc_component *component, 176 struct snd_pcm_substream *substream) 177 { 178 struct snd_pcm_runtime *runtime = substream->runtime; 179 struct rt5677_dsp *rt5677_dsp = 180 snd_soc_component_get_drvdata(component); 181 182 return bytes_to_frames(runtime, rt5677_dsp->dma_offset); 183 } 184 185 static int rt5677_spi_mic_write_offset(u32 *mic_write_offset) 186 { 187 int ret; 188 /* Grab the first 4 bytes that hold the write pointer on the 189 * dsp, and check to make sure that it points somewhere inside the 190 * buffer. 191 */ 192 ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR, mic_write_offset, 193 sizeof(u32)); 194 if (ret) 195 return ret; 196 /* Adjust the offset so that it's zero-based */ 197 *mic_write_offset = *mic_write_offset - sizeof(u32); 198 return *mic_write_offset < RT5677_MIC_BUF_BYTES ? 0 : -EFAULT; 199 } 200 201 /* 202 * Copy one contiguous block of audio samples from the DSP mic buffer to the 203 * dma_area of the pcm runtime. The receiving buffer may wrap around. 204 * @begin: start offset of the block to copy, in bytes. 205 * @end: offset of the first byte after the block to copy, must be greater 206 * than or equal to begin. 207 * 208 * Return: Zero if successful, or a negative error code on failure. 209 */ 210 static int rt5677_spi_copy_block(struct rt5677_dsp *rt5677_dsp, 211 u32 begin, u32 end) 212 { 213 struct snd_pcm_runtime *runtime = rt5677_dsp->substream->runtime; 214 size_t bytes_per_frame = frames_to_bytes(runtime, 1); 215 size_t first_chunk_len, second_chunk_len; 216 int ret; 217 218 if (begin > end || runtime->dma_bytes < 2 * bytes_per_frame) { 219 dev_err(rt5677_dsp->dev, 220 "Invalid copy from (%u, %u), dma_area size %zu\n", 221 begin, end, runtime->dma_bytes); 222 return -EINVAL; 223 } 224 225 /* The block to copy is empty */ 226 if (begin == end) 227 return 0; 228 229 /* If the incoming chunk is too big for the receiving buffer, only the 230 * last "receiving buffer size - one frame" bytes are copied. 231 */ 232 if (end - begin > runtime->dma_bytes - bytes_per_frame) 233 begin = end - (runtime->dma_bytes - bytes_per_frame); 234 235 /* May need to split to two chunks, calculate the size of each */ 236 first_chunk_len = end - begin; 237 second_chunk_len = 0; 238 if (rt5677_dsp->dma_offset + first_chunk_len > runtime->dma_bytes) { 239 /* Receiving buffer wrapped around */ 240 second_chunk_len = first_chunk_len; 241 first_chunk_len = runtime->dma_bytes - rt5677_dsp->dma_offset; 242 second_chunk_len -= first_chunk_len; 243 } 244 245 /* Copy first chunk */ 246 ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR + sizeof(u32) + begin, 247 runtime->dma_area + rt5677_dsp->dma_offset, 248 first_chunk_len); 249 if (ret) 250 return ret; 251 rt5677_dsp->dma_offset += first_chunk_len; 252 if (rt5677_dsp->dma_offset == runtime->dma_bytes) 253 rt5677_dsp->dma_offset = 0; 254 255 /* Copy second chunk */ 256 if (second_chunk_len) { 257 ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR + sizeof(u32) + 258 begin + first_chunk_len, runtime->dma_area, 259 second_chunk_len); 260 if (!ret) 261 rt5677_dsp->dma_offset = second_chunk_len; 262 } 263 return ret; 264 } 265 266 /* 267 * Copy a given amount of audio samples from the DSP mic buffer starting at 268 * mic_read_offset, to the dma_area of the pcm runtime. The source buffer may 269 * wrap around. mic_read_offset is updated after successful copy. 270 * @amount: amount of samples to copy, in bytes. 271 * 272 * Return: Zero if successful, or a negative error code on failure. 273 */ 274 static int rt5677_spi_copy(struct rt5677_dsp *rt5677_dsp, u32 amount) 275 { 276 int ret = 0; 277 u32 target; 278 279 if (amount == 0) 280 return ret; 281 282 target = rt5677_dsp->mic_read_offset + amount; 283 /* Copy the first chunk in DSP's mic buffer */ 284 ret |= rt5677_spi_copy_block(rt5677_dsp, rt5677_dsp->mic_read_offset, 285 min(target, RT5677_MIC_BUF_BYTES)); 286 287 if (target >= RT5677_MIC_BUF_BYTES) { 288 /* Wrap around, copy the second chunk */ 289 target -= RT5677_MIC_BUF_BYTES; 290 ret |= rt5677_spi_copy_block(rt5677_dsp, 0, target); 291 } 292 293 if (!ret) 294 rt5677_dsp->mic_read_offset = target; 295 return ret; 296 } 297 298 /* 299 * A delayed work that streams audio samples from the DSP mic buffer to the 300 * dma_area of the pcm runtime via SPI. 301 */ 302 static void rt5677_spi_copy_work(struct work_struct *work) 303 { 304 struct rt5677_dsp *rt5677_dsp = 305 container_of(work, struct rt5677_dsp, copy_work.work); 306 struct snd_pcm_runtime *runtime; 307 u32 mic_write_offset; 308 size_t new_bytes, copy_bytes, period_bytes; 309 unsigned int delay; 310 int ret = 0; 311 312 /* Ensure runtime->dma_area buffer does not go away while copying. */ 313 guard(mutex)(&rt5677_dsp->dma_lock); 314 if (!rt5677_dsp->substream) { 315 dev_err(rt5677_dsp->dev, "No pcm substream\n"); 316 return; 317 } 318 319 runtime = rt5677_dsp->substream->runtime; 320 321 if (rt5677_spi_mic_write_offset(&mic_write_offset)) { 322 dev_err(rt5677_dsp->dev, "No mic_write_offset\n"); 323 return; 324 } 325 326 /* If this is the first time that we've asked for streaming data after 327 * a hotword is fired, we should start reading from the previous 2 328 * seconds of audio from wherever the mic_write_offset is currently. 329 */ 330 if (rt5677_dsp->new_hotword) { 331 rt5677_dsp->new_hotword = false; 332 /* See if buffer wraparound happens */ 333 if (mic_write_offset < RT5677_MIC_BUF_FIRST_READ_SIZE) 334 rt5677_dsp->mic_read_offset = RT5677_MIC_BUF_BYTES - 335 (RT5677_MIC_BUF_FIRST_READ_SIZE - 336 mic_write_offset); 337 else 338 rt5677_dsp->mic_read_offset = mic_write_offset - 339 RT5677_MIC_BUF_FIRST_READ_SIZE; 340 } 341 342 /* Calculate the amount of new samples in bytes */ 343 if (rt5677_dsp->mic_read_offset <= mic_write_offset) 344 new_bytes = mic_write_offset - rt5677_dsp->mic_read_offset; 345 else 346 new_bytes = RT5677_MIC_BUF_BYTES + mic_write_offset 347 - rt5677_dsp->mic_read_offset; 348 349 /* Copy all new samples from DSP mic buffer, one period at a time */ 350 period_bytes = snd_pcm_lib_period_bytes(rt5677_dsp->substream); 351 while (new_bytes) { 352 copy_bytes = min(new_bytes, period_bytes 353 - rt5677_dsp->avail_bytes); 354 ret = rt5677_spi_copy(rt5677_dsp, copy_bytes); 355 if (ret) { 356 dev_err(rt5677_dsp->dev, "Copy failed %d\n", ret); 357 return; 358 } 359 rt5677_dsp->avail_bytes += copy_bytes; 360 if (rt5677_dsp->avail_bytes >= period_bytes) { 361 snd_pcm_period_elapsed(rt5677_dsp->substream); 362 rt5677_dsp->avail_bytes = 0; 363 } 364 new_bytes -= copy_bytes; 365 } 366 367 delay = bytes_to_frames(runtime, period_bytes) / runtime->rate; 368 schedule_delayed_work(&rt5677_dsp->copy_work, secs_to_jiffies(delay)); 369 } 370 371 static int rt5677_spi_pcm_new(struct snd_soc_component *component, 372 struct snd_soc_pcm_runtime *rtd) 373 { 374 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_VMALLOC, 375 NULL, 0, 0); 376 return 0; 377 } 378 379 static int rt5677_spi_pcm_probe(struct snd_soc_component *component) 380 { 381 struct rt5677_dsp *rt5677_dsp; 382 383 rt5677_dsp = devm_kzalloc(component->dev, sizeof(*rt5677_dsp), 384 GFP_KERNEL); 385 if (!rt5677_dsp) 386 return -ENOMEM; 387 rt5677_dsp->dev = &g_spi->dev; 388 mutex_init(&rt5677_dsp->dma_lock); 389 INIT_DELAYED_WORK(&rt5677_dsp->copy_work, rt5677_spi_copy_work); 390 391 snd_soc_component_set_drvdata(component, rt5677_dsp); 392 return 0; 393 } 394 395 static const struct snd_soc_component_driver rt5677_spi_dai_component = { 396 .name = DRV_NAME, 397 .probe = rt5677_spi_pcm_probe, 398 .open = rt5677_spi_pcm_open, 399 .close = rt5677_spi_pcm_close, 400 .hw_params = rt5677_spi_hw_params, 401 .hw_free = rt5677_spi_hw_free, 402 .prepare = rt5677_spi_prepare, 403 .pointer = rt5677_spi_pcm_pointer, 404 .pcm_new = rt5677_spi_pcm_new, 405 .legacy_dai_naming = 1, 406 }; 407 408 /* Select a suitable transfer command for the next transfer to ensure 409 * the transfer address is always naturally aligned while minimizing 410 * the total number of transfers required. 411 * 412 * 3 transfer commands are available: 413 * RT5677_SPI_READ/WRITE_16: Transfer 2 bytes 414 * RT5677_SPI_READ/WRITE_32: Transfer 4 bytes 415 * RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes 416 * 417 * Note: 418 * 16 Bit writes and reads are restricted to the address range 419 * 0x18020000 ~ 0x18021000 420 * 421 * For example, reading 256 bytes at 0x60030004 uses the following commands: 422 * 0x60030004 RT5677_SPI_READ_32 4 bytes 423 * 0x60030008 RT5677_SPI_READ_BURST 240 bytes 424 * 0x600300F8 RT5677_SPI_READ_BURST 8 bytes 425 * 0x60030100 RT5677_SPI_READ_32 4 bytes 426 * 427 * Input: 428 * @read: true for read commands; false for write commands 429 * @align: alignment of the next transfer address 430 * @remain: number of bytes remaining to transfer 431 * 432 * Output: 433 * @len: number of bytes to transfer with the selected command 434 * Returns the selected command 435 */ 436 static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len) 437 { 438 u8 cmd; 439 440 if (align == 4 || remain <= 4) { 441 cmd = RT5677_SPI_READ_32; 442 *len = 4; 443 } else { 444 cmd = RT5677_SPI_READ_BURST; 445 *len = (((remain - 1) >> 3) + 1) << 3; 446 *len = min_t(u32, *len, RT5677_SPI_BURST_LEN); 447 } 448 return read ? cmd : cmd + 1; 449 } 450 451 /* Copy dstlen bytes from src to dst, while reversing byte order for each word. 452 * If srclen < dstlen, zeros are padded. 453 */ 454 static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen) 455 { 456 u32 w, i, si; 457 u32 word_size = min_t(u32, dstlen, 8); 458 459 for (w = 0; w < dstlen; w += word_size) { 460 for (i = 0; i < word_size && i + w < dstlen; i++) { 461 si = w + word_size - i - 1; 462 dst[w + i] = si < srclen ? src[si] : 0; 463 } 464 } 465 } 466 467 /* Read DSP address space using SPI. addr and len have to be 4-byte aligned. */ 468 int rt5677_spi_read(u32 addr, void *rxbuf, size_t len) 469 { 470 u32 offset; 471 int status = 0; 472 struct spi_transfer t[2]; 473 struct spi_message m; 474 /* +4 bytes is for the DummyPhase following the AddressPhase */ 475 u8 header[RT5677_SPI_HEADER + 4]; 476 u8 body[RT5677_SPI_BURST_LEN]; 477 u8 spi_cmd; 478 u8 *cb = rxbuf; 479 480 if (!g_spi) 481 return -ENODEV; 482 483 if ((addr & 3) || (len & 3)) { 484 dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len); 485 return -EACCES; 486 } 487 488 memset(t, 0, sizeof(t)); 489 t[0].tx_buf = header; 490 t[0].len = sizeof(header); 491 t[0].speed_hz = RT5677_SPI_FREQ; 492 t[1].rx_buf = body; 493 t[1].speed_hz = RT5677_SPI_FREQ; 494 spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); 495 496 for (offset = 0; offset < len; offset += t[1].len) { 497 spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7, 498 len - offset, &t[1].len); 499 500 /* Construct SPI message header */ 501 header[0] = spi_cmd; 502 header[1] = ((addr + offset) & 0xff000000) >> 24; 503 header[2] = ((addr + offset) & 0x00ff0000) >> 16; 504 header[3] = ((addr + offset) & 0x0000ff00) >> 8; 505 header[4] = ((addr + offset) & 0x000000ff) >> 0; 506 507 scoped_guard(mutex, &spi_mutex) 508 status |= spi_sync(g_spi, &m); 509 510 /* Copy data back to caller buffer */ 511 rt5677_spi_reverse(cb + offset, len - offset, body, t[1].len); 512 } 513 return status; 514 } 515 EXPORT_SYMBOL_GPL(rt5677_spi_read); 516 517 /* Write DSP address space using SPI. addr has to be 4-byte aligned. 518 * If len is not 4-byte aligned, then extra zeros are written at the end 519 * as padding. 520 */ 521 int rt5677_spi_write(u32 addr, const void *txbuf, size_t len) 522 { 523 u32 offset; 524 int status = 0; 525 struct spi_transfer t; 526 struct spi_message m; 527 /* +1 byte is for the DummyPhase following the DataPhase */ 528 u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1]; 529 u8 *body = buf + RT5677_SPI_HEADER; 530 u8 spi_cmd; 531 const u8 *cb = txbuf; 532 533 if (!g_spi) 534 return -ENODEV; 535 536 if (addr & 3) { 537 dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len); 538 return -EACCES; 539 } 540 541 memset(&t, 0, sizeof(t)); 542 t.tx_buf = buf; 543 t.speed_hz = RT5677_SPI_FREQ; 544 spi_message_init_with_transfers(&m, &t, 1); 545 546 for (offset = 0; offset < len;) { 547 spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7, 548 len - offset, &t.len); 549 550 /* Construct SPI message header */ 551 buf[0] = spi_cmd; 552 buf[1] = ((addr + offset) & 0xff000000) >> 24; 553 buf[2] = ((addr + offset) & 0x00ff0000) >> 16; 554 buf[3] = ((addr + offset) & 0x0000ff00) >> 8; 555 buf[4] = ((addr + offset) & 0x000000ff) >> 0; 556 557 /* Fetch data from caller buffer */ 558 rt5677_spi_reverse(body, t.len, cb + offset, len - offset); 559 offset += t.len; 560 t.len += RT5677_SPI_HEADER + 1; 561 562 scoped_guard(mutex, &spi_mutex) 563 status |= spi_sync(g_spi, &m); 564 } 565 return status; 566 } 567 EXPORT_SYMBOL_GPL(rt5677_spi_write); 568 569 int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw) 570 { 571 return rt5677_spi_write(addr, fw->data, fw->size); 572 } 573 EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware); 574 575 void rt5677_spi_hotword_detected(void) 576 { 577 struct rt5677_dsp *rt5677_dsp; 578 579 if (!g_spi) 580 return; 581 582 rt5677_dsp = dev_get_drvdata(&g_spi->dev); 583 if (!rt5677_dsp) { 584 dev_err(&g_spi->dev, "Can't get rt5677_dsp\n"); 585 return; 586 } 587 588 scoped_guard(mutex, &rt5677_dsp->dma_lock) { 589 dev_info(rt5677_dsp->dev, "Hotword detected\n"); 590 rt5677_dsp->new_hotword = true; 591 } 592 593 schedule_delayed_work(&rt5677_dsp->copy_work, 0); 594 } 595 EXPORT_SYMBOL_GPL(rt5677_spi_hotword_detected); 596 597 static int rt5677_spi_probe(struct spi_device *spi) 598 { 599 int ret; 600 601 g_spi = spi; 602 603 ret = devm_snd_soc_register_component(&spi->dev, 604 &rt5677_spi_dai_component, 605 &rt5677_spi_dai, 1); 606 if (ret < 0) 607 dev_err(&spi->dev, "Failed to register component.\n"); 608 609 return ret; 610 } 611 612 #ifdef CONFIG_ACPI 613 static const struct acpi_device_id rt5677_spi_acpi_id[] = { 614 { "10EC5677" }, 615 { "RT5677AA" }, 616 { } 617 }; 618 MODULE_DEVICE_TABLE(acpi, rt5677_spi_acpi_id); 619 #endif 620 621 static const struct spi_device_id rt5677_spi_ids[] = { 622 { "rt5677", 0 }, 623 { }, 624 }; 625 MODULE_DEVICE_TABLE(spi, rt5677_spi_ids); 626 627 static struct spi_driver rt5677_spi_driver = { 628 .driver = { 629 .name = DRV_NAME, 630 .acpi_match_table = ACPI_PTR(rt5677_spi_acpi_id), 631 }, 632 .probe = rt5677_spi_probe, 633 .id_table = rt5677_spi_ids, 634 }; 635 module_spi_driver(rt5677_spi_driver); 636 637 MODULE_DESCRIPTION("ASoC RT5677 SPI driver"); 638 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 639 MODULE_LICENSE("GPL v2"); 640