1 // SPDX-License-Identifier: GPL-2.0-only 2 /****************************************************************************** 3 4 AudioScience HPI driver 5 Copyright (C) 1997-2011 AudioScience Inc. <support@audioscience.com> 6 7 8 Hardware Programming Interface (HPI) for AudioScience ASI6200 series adapters. 9 These PCI bus adapters are based on the TI C6711 DSP. 10 11 Exported functions: 12 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr) 13 14 #defines 15 HIDE_PCI_ASSERTS to show the PCI asserts 16 PROFILE_DSP2 get profile data from DSP2 if present (instead of DSP 1) 17 18 (C) Copyright AudioScience Inc. 1998-2003 19 *******************************************************************************/ 20 #define SOURCEFILE_NAME "hpi6000.c" 21 22 #include "hpi_internal.h" 23 #include "hpimsginit.h" 24 #include "hpidebug.h" 25 #include "hpi6000.h" 26 #include "hpidspcd.h" 27 #include "hpicmn.h" 28 29 #define HPI_HIF_BASE (0x00000200) /* start of C67xx internal RAM */ 30 #define HPI_HIF_ADDR(member) \ 31 (HPI_HIF_BASE + offsetof(struct hpi_hif_6000, member)) 32 #define HPI_HIF_ERROR_MASK 0x4000 33 34 /* HPI6000 specific error codes */ 35 #define HPI6000_ERROR_BASE 900 /* not actually used anywhere */ 36 37 /* operational/messaging errors */ 38 #define HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT 901 39 #define HPI6000_ERROR_RESP_GET_LEN 902 40 #define HPI6000_ERROR_MSG_RESP_GET_RESP_ACK 903 41 #define HPI6000_ERROR_MSG_GET_ADR 904 42 #define HPI6000_ERROR_RESP_GET_ADR 905 43 #define HPI6000_ERROR_MSG_RESP_BLOCKWRITE32 906 44 #define HPI6000_ERROR_MSG_RESP_BLOCKREAD32 907 45 46 #define HPI6000_ERROR_CONTROL_CACHE_PARAMS 909 47 48 #define HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT 911 49 #define HPI6000_ERROR_SEND_DATA_ACK 912 50 #define HPI6000_ERROR_SEND_DATA_ADR 913 51 #define HPI6000_ERROR_SEND_DATA_TIMEOUT 914 52 #define HPI6000_ERROR_SEND_DATA_CMD 915 53 #define HPI6000_ERROR_SEND_DATA_WRITE 916 54 #define HPI6000_ERROR_SEND_DATA_IDLECMD 917 55 56 #define HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT 921 57 #define HPI6000_ERROR_GET_DATA_ACK 922 58 #define HPI6000_ERROR_GET_DATA_CMD 923 59 #define HPI6000_ERROR_GET_DATA_READ 924 60 #define HPI6000_ERROR_GET_DATA_IDLECMD 925 61 62 #define HPI6000_ERROR_CONTROL_CACHE_ADDRLEN 951 63 #define HPI6000_ERROR_CONTROL_CACHE_READ 952 64 #define HPI6000_ERROR_CONTROL_CACHE_FLUSH 953 65 66 #define HPI6000_ERROR_MSG_RESP_GETRESPCMD 961 67 #define HPI6000_ERROR_MSG_RESP_IDLECMD 962 68 69 /* Initialisation/bootload errors */ 70 #define HPI6000_ERROR_UNHANDLED_SUBSYS_ID 930 71 72 /* can't access PCI2040 */ 73 #define HPI6000_ERROR_INIT_PCI2040 931 74 /* can't access DSP HPI i/f */ 75 #define HPI6000_ERROR_INIT_DSPHPI 932 76 /* can't access internal DSP memory */ 77 #define HPI6000_ERROR_INIT_DSPINTMEM 933 78 /* can't access SDRAM - test#1 */ 79 #define HPI6000_ERROR_INIT_SDRAM1 934 80 /* can't access SDRAM - test#2 */ 81 #define HPI6000_ERROR_INIT_SDRAM2 935 82 83 #define HPI6000_ERROR_INIT_VERIFY 938 84 85 #define HPI6000_ERROR_INIT_NOACK 939 86 87 #define HPI6000_ERROR_INIT_PLDTEST1 941 88 #define HPI6000_ERROR_INIT_PLDTEST2 942 89 90 /* local defines */ 91 92 #define HIDE_PCI_ASSERTS 93 #define PROFILE_DSP2 94 95 /* for PCI2040 i/f chip */ 96 /* HPI CSR registers */ 97 /* word offsets from CSR base */ 98 /* use when io addresses defined as u32 * */ 99 100 #define INTERRUPT_EVENT_SET 0 101 #define INTERRUPT_EVENT_CLEAR 1 102 #define INTERRUPT_MASK_SET 2 103 #define INTERRUPT_MASK_CLEAR 3 104 #define HPI_ERROR_REPORT 4 105 #define HPI_RESET 5 106 #define HPI_DATA_WIDTH 6 107 108 #define MAX_DSPS 2 109 /* HPI registers, spaced 8K bytes = 2K words apart */ 110 #define DSP_SPACING 0x800 111 112 #define CONTROL 0x0000 113 #define ADDRESS 0x0200 114 #define DATA_AUTOINC 0x0400 115 #define DATA 0x0600 116 117 #define TIMEOUT 500000 118 119 struct dsp_obj { 120 __iomem u32 *prHPI_control; 121 __iomem u32 *prHPI_address; 122 __iomem u32 *prHPI_data; 123 __iomem u32 *prHPI_data_auto_inc; 124 char c_dsp_rev; /*A, B */ 125 u32 control_cache_address_on_dsp; 126 u32 control_cache_length_on_dsp; 127 struct hpi_adapter_obj *pa_parent_adapter; 128 }; 129 130 struct hpi_hw_obj { 131 __iomem u32 *dw2040_HPICSR; 132 __iomem u32 *dw2040_HPIDSP; 133 134 u16 num_dsp; 135 struct dsp_obj ado[MAX_DSPS]; 136 137 u32 message_buffer_address_on_dsp; 138 u32 response_buffer_address_on_dsp; 139 u32 pCI2040HPI_error_count; 140 141 struct hpi_control_cache_single control_cache[HPI_NMIXER_CONTROLS]; 142 struct hpi_control_cache *p_cache; 143 }; 144 145 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao, 146 u16 dsp_index, u32 hpi_address, u32 *source, u32 count); 147 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao, 148 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count); 149 150 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao, 151 u32 *pos_error_code); 152 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao, 153 u16 read_or_write); 154 #define H6READ 1 155 #define H6WRITE 0 156 157 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao, 158 struct hpi_message *phm); 159 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao, 160 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr); 161 162 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, 163 struct hpi_response *phr); 164 165 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index, 166 u32 ack_value); 167 168 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao, 169 u16 dsp_index, u32 host_cmd); 170 171 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo); 172 173 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index, 174 struct hpi_message *phm, struct hpi_response *phr); 175 176 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index, 177 struct hpi_message *phm, struct hpi_response *phr); 178 179 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data); 180 181 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address); 182 183 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata, 184 u32 length); 185 186 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata, 187 u32 length); 188 189 static void subsys_create_adapter(struct hpi_message *phm, 190 struct hpi_response *phr); 191 192 static void adapter_delete(struct hpi_adapter_obj *pao, 193 struct hpi_message *phm, struct hpi_response *phr); 194 195 static void adapter_get_asserts(struct hpi_adapter_obj *pao, 196 struct hpi_message *phm, struct hpi_response *phr); 197 198 static short create_adapter_obj(struct hpi_adapter_obj *pao, 199 u32 *pos_error_code); 200 201 static void delete_adapter_obj(struct hpi_adapter_obj *pao); 202 203 /* local globals */ 204 205 static u16 gw_pci_read_asserts; /* used to count PCI2040 errors */ 206 static u16 gw_pci_write_asserts; /* used to count PCI2040 errors */ 207 208 static void subsys_message(struct hpi_message *phm, struct hpi_response *phr) 209 { 210 switch (phm->function) { 211 case HPI_SUBSYS_CREATE_ADAPTER: 212 subsys_create_adapter(phm, phr); 213 break; 214 default: 215 phr->error = HPI_ERROR_INVALID_FUNC; 216 break; 217 } 218 } 219 220 static void control_message(struct hpi_adapter_obj *pao, 221 struct hpi_message *phm, struct hpi_response *phr) 222 { 223 struct hpi_hw_obj *phw = pao->priv; 224 225 switch (phm->function) { 226 case HPI_CONTROL_GET_STATE: 227 if (pao->has_control_cache) { 228 u16 err; 229 err = hpi6000_update_control_cache(pao, phm); 230 231 if (err) { 232 if (err >= HPI_ERROR_BACKEND_BASE) { 233 phr->error = 234 HPI_ERROR_CONTROL_CACHING; 235 phr->specific_error = err; 236 } else { 237 phr->error = err; 238 } 239 break; 240 } 241 242 if (hpi_check_control_cache(phw->p_cache, phm, phr)) 243 break; 244 } 245 hw_message(pao, phm, phr); 246 break; 247 case HPI_CONTROL_SET_STATE: 248 hw_message(pao, phm, phr); 249 hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm, phr); 250 break; 251 252 case HPI_CONTROL_GET_INFO: 253 default: 254 hw_message(pao, phm, phr); 255 break; 256 } 257 } 258 259 static void adapter_message(struct hpi_adapter_obj *pao, 260 struct hpi_message *phm, struct hpi_response *phr) 261 { 262 switch (phm->function) { 263 case HPI_ADAPTER_GET_ASSERT: 264 adapter_get_asserts(pao, phm, phr); 265 break; 266 267 case HPI_ADAPTER_DELETE: 268 adapter_delete(pao, phm, phr); 269 break; 270 271 default: 272 hw_message(pao, phm, phr); 273 break; 274 } 275 } 276 277 static void outstream_message(struct hpi_adapter_obj *pao, 278 struct hpi_message *phm, struct hpi_response *phr) 279 { 280 switch (phm->function) { 281 case HPI_OSTREAM_HOSTBUFFER_ALLOC: 282 case HPI_OSTREAM_HOSTBUFFER_FREE: 283 /* Don't let these messages go to the HW function because 284 * they're called without locking the spinlock. 285 * For the HPI6000 adapters the HW would return 286 * HPI_ERROR_INVALID_FUNC anyway. 287 */ 288 phr->error = HPI_ERROR_INVALID_FUNC; 289 break; 290 default: 291 hw_message(pao, phm, phr); 292 return; 293 } 294 } 295 296 static void instream_message(struct hpi_adapter_obj *pao, 297 struct hpi_message *phm, struct hpi_response *phr) 298 { 299 300 switch (phm->function) { 301 case HPI_ISTREAM_HOSTBUFFER_ALLOC: 302 case HPI_ISTREAM_HOSTBUFFER_FREE: 303 /* Don't let these messages go to the HW function because 304 * they're called without locking the spinlock. 305 * For the HPI6000 adapters the HW would return 306 * HPI_ERROR_INVALID_FUNC anyway. 307 */ 308 phr->error = HPI_ERROR_INVALID_FUNC; 309 break; 310 default: 311 hw_message(pao, phm, phr); 312 return; 313 } 314 } 315 316 /************************************************************************/ 317 /** HPI_6000() 318 * Entry point from HPIMAN 319 * All calls to the HPI start here 320 */ 321 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr) 322 { 323 struct hpi_adapter_obj *pao = NULL; 324 325 if (phm->object != HPI_OBJ_SUBSYSTEM) { 326 pao = hpi_find_adapter(phm->adapter_index); 327 if (!pao) { 328 hpi_init_response(phr, phm->object, phm->function, 329 HPI_ERROR_BAD_ADAPTER_NUMBER); 330 HPI_DEBUG_LOG(DEBUG, "invalid adapter index: %d \n", 331 phm->adapter_index); 332 return; 333 } 334 335 /* Don't even try to communicate with crashed DSP */ 336 if (pao->dsp_crashed >= 10) { 337 hpi_init_response(phr, phm->object, phm->function, 338 HPI_ERROR_DSP_HARDWARE); 339 HPI_DEBUG_LOG(DEBUG, "adapter %d dsp crashed\n", 340 phm->adapter_index); 341 return; 342 } 343 } 344 /* Init default response including the size field */ 345 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER) 346 hpi_init_response(phr, phm->object, phm->function, 347 HPI_ERROR_PROCESSING_MESSAGE); 348 349 switch (phm->type) { 350 case HPI_TYPE_REQUEST: 351 switch (phm->object) { 352 case HPI_OBJ_SUBSYSTEM: 353 subsys_message(phm, phr); 354 break; 355 356 case HPI_OBJ_ADAPTER: 357 phr->size = 358 sizeof(struct hpi_response_header) + 359 sizeof(struct hpi_adapter_res); 360 adapter_message(pao, phm, phr); 361 break; 362 363 case HPI_OBJ_CONTROL: 364 control_message(pao, phm, phr); 365 break; 366 367 case HPI_OBJ_OSTREAM: 368 outstream_message(pao, phm, phr); 369 break; 370 371 case HPI_OBJ_ISTREAM: 372 instream_message(pao, phm, phr); 373 break; 374 375 default: 376 hw_message(pao, phm, phr); 377 break; 378 } 379 break; 380 381 default: 382 phr->error = HPI_ERROR_INVALID_TYPE; 383 break; 384 } 385 } 386 387 /************************************************************************/ 388 /* SUBSYSTEM */ 389 390 /* create an adapter object and initialise it based on resource information 391 * passed in the message 392 * NOTE - you cannot use this function AND the FindAdapters function at the 393 * same time, the application must use only one of them to get the adapters 394 */ 395 static void subsys_create_adapter(struct hpi_message *phm, 396 struct hpi_response *phr) 397 { 398 /* create temp adapter obj, because we don't know what index yet */ 399 struct hpi_adapter_obj ao; 400 struct hpi_adapter_obj *pao; 401 u32 os_error_code; 402 u16 err = 0; 403 u32 dsp_index = 0; 404 405 HPI_DEBUG_LOG(VERBOSE, "subsys_create_adapter\n"); 406 407 memset(&ao, 0, sizeof(ao)); 408 409 ao.priv = kzalloc_obj(struct hpi_hw_obj); 410 if (!ao.priv) { 411 HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n"); 412 phr->error = HPI_ERROR_MEMORY_ALLOC; 413 return; 414 } 415 416 /* create the adapter object based on the resource information */ 417 ao.pci = *phm->u.s.resource.r.pci; 418 419 err = create_adapter_obj(&ao, &os_error_code); 420 if (err) { 421 delete_adapter_obj(&ao); 422 if (err >= HPI_ERROR_BACKEND_BASE) { 423 phr->error = HPI_ERROR_DSP_BOOTLOAD; 424 phr->specific_error = err; 425 } else { 426 phr->error = err; 427 } 428 429 phr->u.s.data = os_error_code; 430 return; 431 } 432 /* need to update paParentAdapter */ 433 pao = hpi_find_adapter(ao.index); 434 if (!pao) { 435 /* We just added this adapter, why can't we find it!? */ 436 HPI_DEBUG_LOG(ERROR, "lost adapter after boot\n"); 437 phr->error = HPI_ERROR_BAD_ADAPTER; 438 return; 439 } 440 441 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) { 442 struct hpi_hw_obj *phw = pao->priv; 443 phw->ado[dsp_index].pa_parent_adapter = pao; 444 } 445 446 phr->u.s.adapter_type = ao.type; 447 phr->u.s.adapter_index = ao.index; 448 phr->error = 0; 449 } 450 451 static void adapter_delete(struct hpi_adapter_obj *pao, 452 struct hpi_message *phm, struct hpi_response *phr) 453 { 454 delete_adapter_obj(pao); 455 hpi_delete_adapter(pao); 456 phr->error = 0; 457 } 458 459 /* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */ 460 static short create_adapter_obj(struct hpi_adapter_obj *pao, 461 u32 *pos_error_code) 462 { 463 short boot_error = 0; 464 u32 dsp_index = 0; 465 u32 control_cache_size = 0; 466 u32 control_cache_count = 0; 467 struct hpi_hw_obj *phw = pao->priv; 468 469 /* The PCI2040 has the following address map */ 470 /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */ 471 /* BAR1 - 32K = HPI registers on DSP */ 472 phw->dw2040_HPICSR = pao->pci.ap_mem_base[0]; 473 phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1]; 474 HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR, 475 phw->dw2040_HPIDSP); 476 477 /* set addresses for the possible DSP HPI interfaces */ 478 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) { 479 phw->ado[dsp_index].prHPI_control = 480 phw->dw2040_HPIDSP + (CONTROL + 481 DSP_SPACING * dsp_index); 482 483 phw->ado[dsp_index].prHPI_address = 484 phw->dw2040_HPIDSP + (ADDRESS + 485 DSP_SPACING * dsp_index); 486 phw->ado[dsp_index].prHPI_data = 487 phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index); 488 489 phw->ado[dsp_index].prHPI_data_auto_inc = 490 phw->dw2040_HPIDSP + (DATA_AUTOINC + 491 DSP_SPACING * dsp_index); 492 493 HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n", 494 phw->ado[dsp_index].prHPI_control, 495 phw->ado[dsp_index].prHPI_address, 496 phw->ado[dsp_index].prHPI_data, 497 phw->ado[dsp_index].prHPI_data_auto_inc); 498 499 phw->ado[dsp_index].pa_parent_adapter = pao; 500 } 501 502 phw->pCI2040HPI_error_count = 0; 503 pao->has_control_cache = 0; 504 505 /* Set the default number of DSPs on this card */ 506 /* This is (conditionally) adjusted after bootloading */ 507 /* of the first DSP in the bootload section. */ 508 phw->num_dsp = 1; 509 510 boot_error = hpi6000_adapter_boot_load_dsp(pao, pos_error_code); 511 if (boot_error) 512 return boot_error; 513 514 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n"); 515 516 phw->message_buffer_address_on_dsp = 0L; 517 phw->response_buffer_address_on_dsp = 0L; 518 519 /* get info about the adapter by asking the adapter */ 520 /* send a HPI_ADAPTER_GET_INFO message */ 521 { 522 struct hpi_message hm; 523 struct hpi_response hr0; /* response from DSP 0 */ 524 struct hpi_response hr1; /* response from DSP 1 */ 525 u16 error = 0; 526 527 HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n"); 528 memset(&hm, 0, sizeof(hm)); 529 hm.type = HPI_TYPE_REQUEST; 530 hm.size = sizeof(struct hpi_message); 531 hm.object = HPI_OBJ_ADAPTER; 532 hm.function = HPI_ADAPTER_GET_INFO; 533 hm.adapter_index = 0; 534 memset(&hr0, 0, sizeof(hr0)); 535 memset(&hr1, 0, sizeof(hr1)); 536 hr0.size = sizeof(hr0); 537 hr1.size = sizeof(hr1); 538 539 error = hpi6000_message_response_sequence(pao, 0, &hm, &hr0); 540 if (error) { 541 HPI_DEBUG_LOG(ERROR, "message transport error %d\n", 542 error); 543 return error; 544 } 545 if (hr0.error) { 546 HPI_DEBUG_LOG(DEBUG, "message error %d\n", hr0.error); 547 return hr0.error; 548 } 549 if (phw->num_dsp == 2) { 550 error = hpi6000_message_response_sequence(pao, 1, &hm, 551 &hr1); 552 if (error) 553 return error; 554 } 555 pao->type = hr0.u.ax.info.adapter_type; 556 pao->index = hr0.u.ax.info.adapter_index; 557 } 558 559 memset(&phw->control_cache[0], 0, 560 sizeof(struct hpi_control_cache_single) * 561 HPI_NMIXER_CONTROLS); 562 /* Read the control cache length to figure out if it is turned on */ 563 control_cache_size = 564 hpi_read_word(&phw->ado[0], 565 HPI_HIF_ADDR(control_cache_size_in_bytes)); 566 if (control_cache_size) { 567 control_cache_count = 568 hpi_read_word(&phw->ado[0], 569 HPI_HIF_ADDR(control_cache_count)); 570 571 phw->p_cache = 572 hpi_alloc_control_cache(control_cache_count, 573 control_cache_size, (unsigned char *) 574 &phw->control_cache[0] 575 ); 576 if (phw->p_cache) 577 pao->has_control_cache = 1; 578 } 579 580 HPI_DEBUG_LOG(DEBUG, "get adapter info ASI%04X index %d\n", pao->type, 581 pao->index); 582 583 if (phw->p_cache) 584 phw->p_cache->adap_idx = pao->index; 585 586 return hpi_add_adapter(pao); 587 } 588 589 static void delete_adapter_obj(struct hpi_adapter_obj *pao) 590 { 591 struct hpi_hw_obj *phw = pao->priv; 592 593 if (pao->has_control_cache) 594 hpi_free_control_cache(phw->p_cache); 595 596 /* reset DSPs on adapter */ 597 iowrite32(0x0003000F, phw->dw2040_HPICSR + HPI_RESET); 598 599 kfree(phw); 600 } 601 602 /************************************************************************/ 603 /* ADAPTER */ 604 605 static void adapter_get_asserts(struct hpi_adapter_obj *pao, 606 struct hpi_message *phm, struct hpi_response *phr) 607 { 608 #ifndef HIDE_PCI_ASSERTS 609 /* if we have PCI2040 asserts then collect them */ 610 if ((gw_pci_read_asserts > 0) || (gw_pci_write_asserts > 0)) { 611 phr->u.ax.assert.p1 = 612 gw_pci_read_asserts * 100 + gw_pci_write_asserts; 613 phr->u.ax.assert.p2 = 0; 614 phr->u.ax.assert.count = 1; /* assert count */ 615 phr->u.ax.assert.dsp_index = -1; /* "dsp index" */ 616 strscpy(phr->u.ax.assert.sz_message, "PCI2040 error"); 617 phr->u.ax.assert.dsp_msg_addr = 0; 618 gw_pci_read_asserts = 0; 619 gw_pci_write_asserts = 0; 620 phr->error = 0; 621 } else 622 #endif 623 hw_message(pao, phm, phr); /*get DSP asserts */ 624 625 return; 626 } 627 628 /************************************************************************/ 629 /* LOW-LEVEL */ 630 631 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao, 632 u32 *pos_error_code) 633 { 634 struct hpi_hw_obj *phw = pao->priv; 635 short error; 636 u32 timeout; 637 u32 read = 0; 638 u32 i = 0; 639 u32 data = 0; 640 u32 j = 0; 641 u32 test_addr = 0x80000000; 642 u32 test_data = 0x00000001; 643 u32 dw2040_reset = 0; 644 u32 dsp_index = 0; 645 u32 endian = 0; 646 u32 adapter_info = 0; 647 u32 delay = 0; 648 649 struct dsp_code dsp_code; 650 u16 boot_load_family = 0; 651 652 /* NOTE don't use wAdapterType in this routine. It is not setup yet */ 653 654 switch (pao->pci.pci_dev->subsystem_device) { 655 case 0x5100: 656 case 0x5110: /* ASI5100 revB or higher with C6711D */ 657 case 0x5200: /* ASI5200 PCIe version of ASI5100 */ 658 case 0x6100: 659 case 0x6200: 660 boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200); 661 break; 662 default: 663 return HPI6000_ERROR_UNHANDLED_SUBSYS_ID; 664 } 665 666 /* reset all DSPs, indicate two DSPs are present 667 * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode 668 */ 669 endian = 0; 670 dw2040_reset = 0x0003000F; 671 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); 672 673 /* read back register to make sure PCI2040 chip is functioning 674 * note that bits 4..15 are read-only and so should always return zero, 675 * even though we wrote 1 to them 676 */ 677 hpios_delay_micro_seconds(1000); 678 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET); 679 680 if (delay != dw2040_reset) { 681 HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset, 682 delay); 683 return HPI6000_ERROR_INIT_PCI2040; 684 } 685 686 /* Indicate that DSP#0,1 is a C6X */ 687 iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH); 688 /* set Bit30 and 29 - which will prevent Target aborts from being 689 * issued upon HPI or GP error 690 */ 691 iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET); 692 693 /* isolate DSP HAD8 line from PCI2040 so that 694 * Little endian can be set by pullup 695 */ 696 dw2040_reset = dw2040_reset & (~(endian << 3)); 697 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); 698 699 phw->ado[0].c_dsp_rev = 'B'; /* revB */ 700 phw->ado[1].c_dsp_rev = 'B'; /* revB */ 701 702 /*Take both DSPs out of reset, setting HAD8 to the correct Endian */ 703 dw2040_reset = dw2040_reset & (~0x00000001); /* start DSP 0 */ 704 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); 705 dw2040_reset = dw2040_reset & (~0x00000002); /* start DSP 1 */ 706 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); 707 708 /* set HAD8 back to PCI2040, now that DSP set to little endian mode */ 709 dw2040_reset = dw2040_reset & (~0x00000008); 710 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); 711 /*delay to allow DSP to get going */ 712 hpios_delay_micro_seconds(100); 713 714 /* loop through all DSPs, downloading DSP code */ 715 for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) { 716 struct dsp_obj *pdo = &phw->ado[dsp_index]; 717 718 /* configure DSP so that we download code into the SRAM */ 719 /* set control reg for little endian, HWOB=1 */ 720 iowrite32(0x00010001, pdo->prHPI_control); 721 722 /* test access to the HPI address register (HPIA) */ 723 test_data = 0x00000001; 724 for (j = 0; j < 32; j++) { 725 iowrite32(test_data, pdo->prHPI_address); 726 data = ioread32(pdo->prHPI_address); 727 if (data != test_data) { 728 HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n", 729 test_data, data, dsp_index); 730 return HPI6000_ERROR_INIT_DSPHPI; 731 } 732 test_data = test_data << 1; 733 } 734 735 /* if C6713 the setup PLL to generate 225MHz from 25MHz. 736 * Since the PLLDIV1 read is sometimes wrong, even on a C6713, 737 * we're going to do this unconditionally 738 */ 739 /* PLLDIV1 should have a value of 8000 after reset */ 740 /* 741 if (HpiReadWord(pdo,0x01B7C118) == 0x8000) 742 */ 743 { 744 /* C6713 datasheet says we cannot program PLL from HPI, 745 * and indeed if we try to set the PLL multiply from the 746 * HPI, the PLL does not seem to lock, 747 * so we enable the PLL and use the default of x 7 748 */ 749 /* bypass PLL */ 750 hpi_write_word(pdo, 0x01B7C100, 0x0000); 751 hpios_delay_micro_seconds(100); 752 753 /* ** use default of PLL x7 ** */ 754 /* EMIF = 225/3=75MHz */ 755 hpi_write_word(pdo, 0x01B7C120, 0x8002); 756 hpios_delay_micro_seconds(100); 757 758 /* peri = 225/2 */ 759 hpi_write_word(pdo, 0x01B7C11C, 0x8001); 760 hpios_delay_micro_seconds(100); 761 762 /* cpu = 225/1 */ 763 hpi_write_word(pdo, 0x01B7C118, 0x8000); 764 765 /* ~2ms delay */ 766 hpios_delay_micro_seconds(2000); 767 768 /* PLL not bypassed */ 769 hpi_write_word(pdo, 0x01B7C100, 0x0001); 770 /* ~2ms delay */ 771 hpios_delay_micro_seconds(2000); 772 } 773 774 /* test r/w to internal DSP memory 775 * C6711 has L2 cache mapped to 0x0 when reset 776 * 777 * revB - because of bug 3.0.1 last HPI read 778 * (before HPI address issued) must be non-autoinc 779 */ 780 /* test each bit in the 32bit word */ 781 for (i = 0; i < 100; i++) { 782 test_addr = 0x00000000; 783 test_data = 0x00000001; 784 for (j = 0; j < 32; j++) { 785 hpi_write_word(pdo, test_addr + i, test_data); 786 data = hpi_read_word(pdo, test_addr + i); 787 if (data != test_data) { 788 HPI_DEBUG_LOG(ERROR, 789 "DSP mem %x %x %x %x\n", 790 test_addr + i, test_data, 791 data, dsp_index); 792 793 return HPI6000_ERROR_INIT_DSPINTMEM; 794 } 795 test_data = test_data << 1; 796 } 797 } 798 799 /* memory map of ASI6200 800 00000000-0000FFFF 16Kx32 internal program 801 01800000-019FFFFF Internal peripheral 802 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz 803 90000000-9000FFFF CE1 Async peripherals: 804 805 EMIF config 806 ------------ 807 Global EMIF control 808 0 - 809 1 - 810 2 - 811 3 CLK2EN = 1 CLKOUT2 enabled 812 4 CLK1EN = 0 CLKOUT1 disabled 813 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT 814 6 - 815 7 NOHOLD = 1 external HOLD disabled 816 8 HOLDA = 0 HOLDA output is low 817 9 HOLD = 0 HOLD input is low 818 10 ARDY = 1 ARDY input is high 819 11 BUSREQ = 0 BUSREQ output is low 820 12,13 Reserved = 1 821 */ 822 hpi_write_word(pdo, 0x01800000, 0x34A8); 823 824 /* EMIF CE0 setup - 2Mx32 Sync DRAM 825 31..28 Wr setup 826 27..22 Wr strobe 827 21..20 Wr hold 828 19..16 Rd setup 829 15..14 - 830 13..8 Rd strobe 831 7..4 MTYPE 0011 Sync DRAM 32bits 832 3 Wr hold MSB 833 2..0 Rd hold 834 */ 835 hpi_write_word(pdo, 0x01800008, 0x00000030); 836 837 /* EMIF SDRAM Extension 838 31-21 0 839 20 WR2RD = 0 840 19-18 WR2DEAC = 1 841 17 WR2WR = 0 842 16-15 R2WDQM = 2 843 14-12 RD2WR = 4 844 11-10 RD2DEAC = 1 845 9 RD2RD = 1 846 8-7 THZP = 10b 847 6-5 TWR = 2-1 = 01b (tWR = 10ns) 848 4 TRRD = 0b = 2 ECLK (tRRD = 14ns) 849 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK) 850 1 CAS latency = 3 ECLK 851 (for Micron 2M32-7 operating at 100Mhz) 852 */ 853 854 /* need to use this else DSP code crashes */ 855 hpi_write_word(pdo, 0x01800020, 0x001BDF29); 856 857 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank) 858 31 - - 859 30 SDBSZ 1 4 bank 860 29..28 SDRSZ 00 11 row address pins 861 27..26 SDCSZ 01 8 column address pins 862 25 RFEN 1 refersh enabled 863 24 INIT 1 init SDRAM 864 23..20 TRCD 0001 865 19..16 TRP 0001 866 15..12 TRC 0110 867 11..0 - - 868 */ 869 /* need to use this else DSP code crashes */ 870 hpi_write_word(pdo, 0x01800018, 0x47117000); 871 872 /* EMIF SDRAM Refresh Timing */ 873 hpi_write_word(pdo, 0x0180001C, 0x00000410); 874 875 /*MIF CE1 setup - Async peripherals 876 @100MHz bus speed, each cycle is 10ns, 877 31..28 Wr setup = 1 878 27..22 Wr strobe = 3 30ns 879 21..20 Wr hold = 1 880 19..16 Rd setup =1 881 15..14 Ta = 2 882 13..8 Rd strobe = 3 30ns 883 7..4 MTYPE 0010 Async 32bits 884 3 Wr hold MSB =0 885 2..0 Rd hold = 1 886 */ 887 { 888 u32 cE1 = 889 (1L << 28) | (3L << 22) | (1L << 20) | (1L << 890 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L; 891 hpi_write_word(pdo, 0x01800004, cE1); 892 } 893 894 /* delay a little to allow SDRAM and DSP to "get going" */ 895 hpios_delay_micro_seconds(1000); 896 897 /* test access to SDRAM */ 898 { 899 test_addr = 0x80000000; 900 test_data = 0x00000001; 901 /* test each bit in the 32bit word */ 902 for (j = 0; j < 32; j++) { 903 hpi_write_word(pdo, test_addr, test_data); 904 data = hpi_read_word(pdo, test_addr); 905 if (data != test_data) { 906 HPI_DEBUG_LOG(ERROR, 907 "DSP dram %x %x %x %x\n", 908 test_addr, test_data, data, 909 dsp_index); 910 911 return HPI6000_ERROR_INIT_SDRAM1; 912 } 913 test_data = test_data << 1; 914 } 915 /* test every Nth address in the DRAM */ 916 #define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */ 917 #define DRAM_INC 1024 918 test_addr = 0x80000000; 919 test_data = 0x0; 920 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) { 921 hpi_write_word(pdo, test_addr + i, test_data); 922 test_data++; 923 } 924 test_addr = 0x80000000; 925 test_data = 0x0; 926 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) { 927 data = hpi_read_word(pdo, test_addr + i); 928 if (data != test_data) { 929 HPI_DEBUG_LOG(ERROR, 930 "DSP dram %x %x %x %x\n", 931 test_addr + i, test_data, 932 data, dsp_index); 933 return HPI6000_ERROR_INIT_SDRAM2; 934 } 935 test_data++; 936 } 937 938 } 939 940 /* write the DSP code down into the DSPs memory */ 941 error = hpi_dsp_code_open(boot_load_family, pao->pci.pci_dev, 942 &dsp_code, pos_error_code); 943 944 if (error) 945 return error; 946 947 while (1) { 948 u32 length; 949 u32 address; 950 u32 type; 951 u32 *pcode; 952 953 error = hpi_dsp_code_read_word(&dsp_code, &length); 954 if (error) 955 break; 956 if (length == 0xFFFFFFFF) 957 break; /* end of code */ 958 959 error = hpi_dsp_code_read_word(&dsp_code, &address); 960 if (error) 961 break; 962 error = hpi_dsp_code_read_word(&dsp_code, &type); 963 if (error) 964 break; 965 error = hpi_dsp_code_read_block(length, &dsp_code, 966 &pcode); 967 if (error) 968 break; 969 error = hpi6000_dsp_block_write32(pao, (u16)dsp_index, 970 address, pcode, length); 971 if (error) 972 break; 973 } 974 975 if (error) { 976 hpi_dsp_code_close(&dsp_code); 977 return error; 978 } 979 /* verify that code was written correctly */ 980 /* this time through, assume no errors in DSP code file/array */ 981 hpi_dsp_code_rewind(&dsp_code); 982 while (1) { 983 u32 length; 984 u32 address; 985 u32 type; 986 u32 *pcode; 987 988 hpi_dsp_code_read_word(&dsp_code, &length); 989 if (length == 0xFFFFFFFF) 990 break; /* end of code */ 991 992 hpi_dsp_code_read_word(&dsp_code, &address); 993 hpi_dsp_code_read_word(&dsp_code, &type); 994 hpi_dsp_code_read_block(length, &dsp_code, &pcode); 995 996 for (i = 0; i < length; i++) { 997 data = hpi_read_word(pdo, address); 998 if (data != *pcode) { 999 error = HPI6000_ERROR_INIT_VERIFY; 1000 HPI_DEBUG_LOG(ERROR, 1001 "DSP verify %x %x %x %x\n", 1002 address, *pcode, data, 1003 dsp_index); 1004 break; 1005 } 1006 pcode++; 1007 address += 4; 1008 } 1009 if (error) 1010 break; 1011 } 1012 hpi_dsp_code_close(&dsp_code); 1013 if (error) 1014 return error; 1015 1016 /* zero out the hostmailbox */ 1017 { 1018 u32 address = HPI_HIF_ADDR(host_cmd); 1019 for (i = 0; i < 4; i++) { 1020 hpi_write_word(pdo, address, 0); 1021 address += 4; 1022 } 1023 } 1024 /* write the DSP number into the hostmailbox */ 1025 /* structure before starting the DSP */ 1026 hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index); 1027 1028 /* write the DSP adapter Info into the */ 1029 /* hostmailbox before starting the DSP */ 1030 if (dsp_index > 0) 1031 hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info), 1032 adapter_info); 1033 1034 /* step 3. Start code by sending interrupt */ 1035 iowrite32(0x00030003, pdo->prHPI_control); 1036 hpios_delay_micro_seconds(10000); 1037 1038 /* wait for a non-zero value in hostcmd - 1039 * indicating initialization is complete 1040 * 1041 * Init could take a while if DSP checks SDRAM memory 1042 * Was 200000. Increased to 2000000 for ASI8801 so we 1043 * don't get 938 errors. 1044 */ 1045 timeout = 2000000; 1046 while (timeout) { 1047 do { 1048 read = hpi_read_word(pdo, 1049 HPI_HIF_ADDR(host_cmd)); 1050 } while (--timeout 1051 && hpi6000_check_PCI2040_error_flag(pao, 1052 H6READ)); 1053 1054 if (read) 1055 break; 1056 /* The following is a workaround for bug #94: 1057 * Bluescreen on install and subsequent boots on a 1058 * DELL PowerEdge 600SC PC with 1.8GHz P4 and 1059 * ServerWorks chipset. Without this delay the system 1060 * locks up with a bluescreen (NOT GPF or pagefault). 1061 */ 1062 else 1063 hpios_delay_micro_seconds(10000); 1064 } 1065 if (timeout == 0) 1066 return HPI6000_ERROR_INIT_NOACK; 1067 1068 /* read the DSP adapter Info from the */ 1069 /* hostmailbox structure after starting the DSP */ 1070 if (dsp_index == 0) { 1071 /*u32 dwTestData=0; */ 1072 u32 mask = 0; 1073 1074 adapter_info = 1075 hpi_read_word(pdo, 1076 HPI_HIF_ADDR(adapter_info)); 1077 if (HPI_ADAPTER_FAMILY_ASI 1078 (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER 1079 (adapter_info)) == 1080 HPI_ADAPTER_FAMILY_ASI(0x6200)) 1081 /* all 6200 cards have this many DSPs */ 1082 phw->num_dsp = 2; 1083 1084 /* test that the PLD is programmed */ 1085 /* and we can read/write 24bits */ 1086 #define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */ 1087 1088 switch (boot_load_family) { 1089 case HPI_ADAPTER_FAMILY_ASI(0x6200): 1090 /* ASI6100/6200 has 24bit path to FPGA */ 1091 mask = 0xFFFFFF00L; 1092 /* ASI5100 uses AX6 code, */ 1093 /* but has no PLD r/w register to test */ 1094 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev-> 1095 subsystem_device) == 1096 HPI_ADAPTER_FAMILY_ASI(0x5100)) 1097 mask = 0x00000000L; 1098 /* ASI5200 uses AX6 code, */ 1099 /* but has no PLD r/w register to test */ 1100 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev-> 1101 subsystem_device) == 1102 HPI_ADAPTER_FAMILY_ASI(0x5200)) 1103 mask = 0x00000000L; 1104 break; 1105 case HPI_ADAPTER_FAMILY_ASI(0x8800): 1106 /* ASI8800 has 16bit path to FPGA */ 1107 mask = 0xFFFF0000L; 1108 break; 1109 } 1110 test_data = 0xAAAAAA00L & mask; 1111 /* write to 24 bit Debug register (D31-D8) */ 1112 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data); 1113 read = hpi_read_word(pdo, 1114 PLD_BASE_ADDRESS + 4L) & mask; 1115 if (read != test_data) { 1116 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data, 1117 read); 1118 return HPI6000_ERROR_INIT_PLDTEST1; 1119 } 1120 test_data = 0x55555500L & mask; 1121 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data); 1122 read = hpi_read_word(pdo, 1123 PLD_BASE_ADDRESS + 4L) & mask; 1124 if (read != test_data) { 1125 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data, 1126 read); 1127 return HPI6000_ERROR_INIT_PLDTEST2; 1128 } 1129 } 1130 } /* for numDSP */ 1131 return 0; 1132 } 1133 1134 #define PCI_TIMEOUT 100 1135 1136 static int hpi_set_address(struct dsp_obj *pdo, u32 address) 1137 { 1138 u32 timeout = PCI_TIMEOUT; 1139 1140 do { 1141 iowrite32(address, pdo->prHPI_address); 1142 } while (hpi6000_check_PCI2040_error_flag(pdo->pa_parent_adapter, 1143 H6WRITE) 1144 && --timeout); 1145 1146 if (timeout) 1147 return 0; 1148 1149 return 1; 1150 } 1151 1152 /* write one word to the HPI port */ 1153 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data) 1154 { 1155 if (hpi_set_address(pdo, address)) 1156 return; 1157 iowrite32(data, pdo->prHPI_data); 1158 } 1159 1160 /* read one word from the HPI port */ 1161 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address) 1162 { 1163 u32 data = 0; 1164 1165 if (hpi_set_address(pdo, address)) 1166 return 0; /*? No way to return error */ 1167 1168 /* take care of errata in revB DSP (2.0.1) */ 1169 data = ioread32(pdo->prHPI_data); 1170 return data; 1171 } 1172 1173 /* write a block of 32bit words to the DSP HPI port using auto-inc mode */ 1174 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata, 1175 u32 length) 1176 { 1177 u16 length16 = length - 1; 1178 1179 if (length == 0) 1180 return; 1181 1182 if (hpi_set_address(pdo, address)) 1183 return; 1184 1185 iowrite32_rep(pdo->prHPI_data_auto_inc, pdata, length16); 1186 1187 /* take care of errata in revB DSP (2.0.1) */ 1188 /* must end with non auto-inc */ 1189 iowrite32(*(pdata + length - 1), pdo->prHPI_data); 1190 } 1191 1192 /** read a block of 32bit words from the DSP HPI port using auto-inc mode 1193 */ 1194 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata, 1195 u32 length) 1196 { 1197 u16 length16 = length - 1; 1198 1199 if (length == 0) 1200 return; 1201 1202 if (hpi_set_address(pdo, address)) 1203 return; 1204 1205 ioread32_rep(pdo->prHPI_data_auto_inc, pdata, length16); 1206 1207 /* take care of errata in revB DSP (2.0.1) */ 1208 /* must end with non auto-inc */ 1209 *(pdata + length - 1) = ioread32(pdo->prHPI_data); 1210 } 1211 1212 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao, 1213 u16 dsp_index, u32 hpi_address, u32 *source, u32 count) 1214 { 1215 struct hpi_hw_obj *phw = pao->priv; 1216 struct dsp_obj *pdo = &phw->ado[dsp_index]; 1217 u32 time_out = PCI_TIMEOUT; 1218 int c6711_burst_size = 128; 1219 u32 local_hpi_address = hpi_address; 1220 int local_count = count; 1221 int xfer_size; 1222 u32 *pdata = source; 1223 1224 while (local_count) { 1225 if (local_count > c6711_burst_size) 1226 xfer_size = c6711_burst_size; 1227 else 1228 xfer_size = local_count; 1229 1230 time_out = PCI_TIMEOUT; 1231 do { 1232 hpi_write_block(pdo, local_hpi_address, pdata, 1233 xfer_size); 1234 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) 1235 && --time_out); 1236 1237 if (!time_out) 1238 break; 1239 pdata += xfer_size; 1240 local_hpi_address += sizeof(u32) * xfer_size; 1241 local_count -= xfer_size; 1242 } 1243 1244 if (time_out) 1245 return 0; 1246 else 1247 return 1; 1248 } 1249 1250 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao, 1251 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count) 1252 { 1253 struct hpi_hw_obj *phw = pao->priv; 1254 struct dsp_obj *pdo = &phw->ado[dsp_index]; 1255 u32 time_out = PCI_TIMEOUT; 1256 int c6711_burst_size = 16; 1257 u32 local_hpi_address = hpi_address; 1258 int local_count = count; 1259 int xfer_size; 1260 u32 *pdata = dest; 1261 1262 while (local_count) { 1263 if (local_count > c6711_burst_size) 1264 xfer_size = c6711_burst_size; 1265 else 1266 xfer_size = local_count; 1267 1268 time_out = PCI_TIMEOUT; 1269 do { 1270 hpi_read_block(pdo, local_hpi_address, pdata, 1271 xfer_size); 1272 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) 1273 && --time_out); 1274 if (!time_out) 1275 break; 1276 1277 pdata += xfer_size; 1278 local_hpi_address += sizeof(u32) * xfer_size; 1279 local_count -= xfer_size; 1280 } 1281 1282 if (time_out) 1283 return 0; 1284 else 1285 return 1; 1286 } 1287 1288 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao, 1289 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr) 1290 { 1291 struct hpi_hw_obj *phw = pao->priv; 1292 struct dsp_obj *pdo = &phw->ado[dsp_index]; 1293 u32 timeout; 1294 u16 ack; 1295 u32 address; 1296 u32 length; 1297 u32 *p_data; 1298 u16 error = 0; 1299 1300 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE); 1301 if (ack & HPI_HIF_ERROR_MASK) { 1302 pao->dsp_crashed++; 1303 return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT; 1304 } 1305 pao->dsp_crashed = 0; 1306 1307 /* get the message address and size */ 1308 if (phw->message_buffer_address_on_dsp == 0) { 1309 timeout = TIMEOUT; 1310 do { 1311 address = 1312 hpi_read_word(pdo, 1313 HPI_HIF_ADDR(message_buffer_address)); 1314 phw->message_buffer_address_on_dsp = address; 1315 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) 1316 && --timeout); 1317 if (!timeout) 1318 return HPI6000_ERROR_MSG_GET_ADR; 1319 } else 1320 address = phw->message_buffer_address_on_dsp; 1321 1322 length = phm->size; 1323 1324 /* send the message */ 1325 p_data = (u32 *)phm; 1326 if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data, 1327 (u16)length / 4)) 1328 return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32; 1329 1330 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_RESP)) 1331 return HPI6000_ERROR_MSG_RESP_GETRESPCMD; 1332 hpi6000_send_dsp_interrupt(pdo); 1333 1334 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_RESP); 1335 if (ack & HPI_HIF_ERROR_MASK) 1336 return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK; 1337 1338 /* get the response address */ 1339 if (phw->response_buffer_address_on_dsp == 0) { 1340 timeout = TIMEOUT; 1341 do { 1342 address = 1343 hpi_read_word(pdo, 1344 HPI_HIF_ADDR(response_buffer_address)); 1345 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) 1346 && --timeout); 1347 phw->response_buffer_address_on_dsp = address; 1348 1349 if (!timeout) 1350 return HPI6000_ERROR_RESP_GET_ADR; 1351 } else 1352 address = phw->response_buffer_address_on_dsp; 1353 1354 /* read the length of the response back from the DSP */ 1355 timeout = TIMEOUT; 1356 do { 1357 length = hpi_read_word(pdo, HPI_HIF_ADDR(length)); 1358 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); 1359 if (!timeout) 1360 return HPI6000_ERROR_RESP_GET_LEN; 1361 1362 if (length > phr->size) 1363 return HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL; 1364 1365 /* get the response */ 1366 p_data = (u32 *)phr; 1367 if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data, 1368 (u16)length / 4)) 1369 return HPI6000_ERROR_MSG_RESP_BLOCKREAD32; 1370 1371 /* set i/f back to idle */ 1372 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE)) 1373 return HPI6000_ERROR_MSG_RESP_IDLECMD; 1374 hpi6000_send_dsp_interrupt(pdo); 1375 1376 error = hpi_validate_response(phm, phr); 1377 return error; 1378 } 1379 1380 /* have to set up the below defines to match stuff in the MAP file */ 1381 1382 #define MSG_ADDRESS (HPI_HIF_BASE+0x18) 1383 #define MSG_LENGTH 11 1384 #define RESP_ADDRESS (HPI_HIF_BASE+0x44) 1385 #define RESP_LENGTH 16 1386 #define QUEUE_START (HPI_HIF_BASE+0x88) 1387 #define QUEUE_SIZE 0x8000 1388 1389 static short hpi6000_send_data_check_adr(u32 address, u32 length_in_dwords) 1390 { 1391 /*#define CHECKING // comment this line in to enable checking */ 1392 #ifdef CHECKING 1393 if (address < (u32)MSG_ADDRESS) 1394 return 0; 1395 if (address > (u32)(QUEUE_START + QUEUE_SIZE)) 1396 return 0; 1397 if ((address + (length_in_dwords << 2)) > 1398 (u32)(QUEUE_START + QUEUE_SIZE)) 1399 return 0; 1400 #else 1401 (void)address; 1402 (void)length_in_dwords; 1403 return 1; 1404 #endif 1405 } 1406 1407 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index, 1408 struct hpi_message *phm, struct hpi_response *phr) 1409 { 1410 struct hpi_hw_obj *phw = pao->priv; 1411 struct dsp_obj *pdo = &phw->ado[dsp_index]; 1412 u32 data_sent = 0; 1413 u16 ack; 1414 u32 length, address; 1415 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data; 1416 u16 time_out = 8; 1417 1418 (void)phr; 1419 1420 /* round dwDataSize down to nearest 4 bytes */ 1421 while ((data_sent < (phm->u.d.u.data.data_size & ~3L)) 1422 && --time_out) { 1423 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE); 1424 if (ack & HPI_HIF_ERROR_MASK) 1425 return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT; 1426 1427 if (hpi6000_send_host_command(pao, dsp_index, 1428 HPI_HIF_SEND_DATA)) 1429 return HPI6000_ERROR_SEND_DATA_CMD; 1430 1431 hpi6000_send_dsp_interrupt(pdo); 1432 1433 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_SEND_DATA); 1434 1435 if (ack & HPI_HIF_ERROR_MASK) 1436 return HPI6000_ERROR_SEND_DATA_ACK; 1437 1438 do { 1439 /* get the address and size */ 1440 address = hpi_read_word(pdo, HPI_HIF_ADDR(address)); 1441 /* DSP returns number of DWORDS */ 1442 length = hpi_read_word(pdo, HPI_HIF_ADDR(length)); 1443 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)); 1444 1445 if (!hpi6000_send_data_check_adr(address, length)) 1446 return HPI6000_ERROR_SEND_DATA_ADR; 1447 1448 /* send the data. break data into 512 DWORD blocks (2K bytes) 1449 * and send using block write. 2Kbytes is the max as this is the 1450 * memory window given to the HPI data register by the PCI2040 1451 */ 1452 1453 { 1454 u32 len = length; 1455 u32 blk_len = 512; 1456 while (len) { 1457 if (len < blk_len) 1458 blk_len = len; 1459 if (hpi6000_dsp_block_write32(pao, dsp_index, 1460 address, p_data, blk_len)) 1461 return HPI6000_ERROR_SEND_DATA_WRITE; 1462 address += blk_len * 4; 1463 p_data += blk_len; 1464 len -= blk_len; 1465 } 1466 } 1467 1468 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE)) 1469 return HPI6000_ERROR_SEND_DATA_IDLECMD; 1470 1471 hpi6000_send_dsp_interrupt(pdo); 1472 1473 data_sent += length * 4; 1474 } 1475 if (!time_out) 1476 return HPI6000_ERROR_SEND_DATA_TIMEOUT; 1477 return 0; 1478 } 1479 1480 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index, 1481 struct hpi_message *phm, struct hpi_response *phr) 1482 { 1483 struct hpi_hw_obj *phw = pao->priv; 1484 struct dsp_obj *pdo = &phw->ado[dsp_index]; 1485 u32 data_got = 0; 1486 u16 ack; 1487 u32 length, address; 1488 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data; 1489 1490 (void)phr; /* this parameter not used! */ 1491 1492 /* round dwDataSize down to nearest 4 bytes */ 1493 while (data_got < (phm->u.d.u.data.data_size & ~3L)) { 1494 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE); 1495 if (ack & HPI_HIF_ERROR_MASK) 1496 return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT; 1497 1498 if (hpi6000_send_host_command(pao, dsp_index, 1499 HPI_HIF_GET_DATA)) 1500 return HPI6000_ERROR_GET_DATA_CMD; 1501 hpi6000_send_dsp_interrupt(pdo); 1502 1503 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_DATA); 1504 1505 if (ack & HPI_HIF_ERROR_MASK) 1506 return HPI6000_ERROR_GET_DATA_ACK; 1507 1508 /* get the address and size */ 1509 do { 1510 address = hpi_read_word(pdo, HPI_HIF_ADDR(address)); 1511 length = hpi_read_word(pdo, HPI_HIF_ADDR(length)); 1512 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)); 1513 1514 /* read the data */ 1515 { 1516 u32 len = length; 1517 u32 blk_len = 512; 1518 while (len) { 1519 if (len < blk_len) 1520 blk_len = len; 1521 if (hpi6000_dsp_block_read32(pao, dsp_index, 1522 address, p_data, blk_len)) 1523 return HPI6000_ERROR_GET_DATA_READ; 1524 address += blk_len * 4; 1525 p_data += blk_len; 1526 len -= blk_len; 1527 } 1528 } 1529 1530 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE)) 1531 return HPI6000_ERROR_GET_DATA_IDLECMD; 1532 hpi6000_send_dsp_interrupt(pdo); 1533 1534 data_got += length * 4; 1535 } 1536 return 0; 1537 } 1538 1539 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo) 1540 { 1541 iowrite32(0x00030003, pdo->prHPI_control); /* DSPINT */ 1542 } 1543 1544 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao, 1545 u16 dsp_index, u32 host_cmd) 1546 { 1547 struct hpi_hw_obj *phw = pao->priv; 1548 struct dsp_obj *pdo = &phw->ado[dsp_index]; 1549 u32 timeout = TIMEOUT; 1550 1551 /* set command */ 1552 do { 1553 hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd); 1554 /* flush the FIFO */ 1555 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd)); 1556 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout); 1557 1558 /* reset the interrupt bit */ 1559 iowrite32(0x00040004, pdo->prHPI_control); 1560 1561 if (timeout) 1562 return 0; 1563 else 1564 return 1; 1565 } 1566 1567 /* if the PCI2040 has recorded an HPI timeout, reset the error and return 1 */ 1568 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao, 1569 u16 read_or_write) 1570 { 1571 u32 hPI_error; 1572 1573 struct hpi_hw_obj *phw = pao->priv; 1574 1575 /* read the error bits from the PCI2040 */ 1576 hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT); 1577 if (hPI_error) { 1578 /* reset the error flag */ 1579 iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT); 1580 phw->pCI2040HPI_error_count++; 1581 if (read_or_write == 1) 1582 gw_pci_read_asserts++; /************* inc global */ 1583 else 1584 gw_pci_write_asserts++; 1585 return 1; 1586 } else 1587 return 0; 1588 } 1589 1590 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index, 1591 u32 ack_value) 1592 { 1593 struct hpi_hw_obj *phw = pao->priv; 1594 struct dsp_obj *pdo = &phw->ado[dsp_index]; 1595 u32 ack = 0L; 1596 u32 timeout; 1597 u32 hPIC = 0L; 1598 1599 /* wait for host interrupt to signal ack is ready */ 1600 timeout = TIMEOUT; 1601 while (--timeout) { 1602 hPIC = ioread32(pdo->prHPI_control); 1603 if (hPIC & 0x04) /* 0x04 = HINT from DSP */ 1604 break; 1605 } 1606 if (timeout == 0) 1607 return HPI_HIF_ERROR_MASK; 1608 1609 /* wait for dwAckValue */ 1610 timeout = TIMEOUT; 1611 while (--timeout) { 1612 /* read the ack mailbox */ 1613 ack = hpi_read_word(pdo, HPI_HIF_ADDR(dsp_ack)); 1614 if (ack == ack_value) 1615 break; 1616 if ((ack & HPI_HIF_ERROR_MASK) 1617 && !hpi6000_check_PCI2040_error_flag(pao, H6READ)) 1618 break; 1619 /*for (i=0;i<1000;i++) */ 1620 /* dwPause=i+1; */ 1621 } 1622 if (ack & HPI_HIF_ERROR_MASK) 1623 /* indicates bad read from DSP - 1624 typically 0xffffff is read for some reason */ 1625 ack = HPI_HIF_ERROR_MASK; 1626 1627 if (timeout == 0) 1628 ack = HPI_HIF_ERROR_MASK; 1629 return (short)ack; 1630 } 1631 1632 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao, 1633 struct hpi_message *phm) 1634 { 1635 const u16 dsp_index = 0; 1636 struct hpi_hw_obj *phw = pao->priv; 1637 struct dsp_obj *pdo = &phw->ado[dsp_index]; 1638 u32 timeout; 1639 u32 cache_dirty_flag; 1640 u16 err; 1641 1642 hpios_dsplock_lock(pao); 1643 1644 timeout = TIMEOUT; 1645 do { 1646 cache_dirty_flag = 1647 hpi_read_word((struct dsp_obj *)pdo, 1648 HPI_HIF_ADDR(control_cache_is_dirty)); 1649 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); 1650 if (!timeout) { 1651 err = HPI6000_ERROR_CONTROL_CACHE_PARAMS; 1652 goto unlock; 1653 } 1654 1655 if (cache_dirty_flag) { 1656 /* read the cached controls */ 1657 u32 address; 1658 u32 length; 1659 1660 timeout = TIMEOUT; 1661 if (pdo->control_cache_address_on_dsp == 0) { 1662 do { 1663 address = 1664 hpi_read_word((struct dsp_obj *)pdo, 1665 HPI_HIF_ADDR(control_cache_address)); 1666 1667 length = hpi_read_word((struct dsp_obj *)pdo, 1668 HPI_HIF_ADDR 1669 (control_cache_size_in_bytes)); 1670 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) 1671 && --timeout); 1672 if (!timeout) { 1673 err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN; 1674 goto unlock; 1675 } 1676 pdo->control_cache_address_on_dsp = address; 1677 pdo->control_cache_length_on_dsp = length; 1678 } else { 1679 address = pdo->control_cache_address_on_dsp; 1680 length = pdo->control_cache_length_on_dsp; 1681 } 1682 1683 if (hpi6000_dsp_block_read32(pao, dsp_index, address, 1684 (u32 *)&phw->control_cache[0], 1685 length / sizeof(u32))) { 1686 err = HPI6000_ERROR_CONTROL_CACHE_READ; 1687 goto unlock; 1688 } 1689 do { 1690 hpi_write_word((struct dsp_obj *)pdo, 1691 HPI_HIF_ADDR(control_cache_is_dirty), 0); 1692 /* flush the FIFO */ 1693 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd)); 1694 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) 1695 && --timeout); 1696 if (!timeout) { 1697 err = HPI6000_ERROR_CONTROL_CACHE_FLUSH; 1698 goto unlock; 1699 } 1700 1701 } 1702 err = 0; 1703 1704 unlock: 1705 hpios_dsplock_unlock(pao); 1706 return err; 1707 } 1708 1709 /** Get dsp index for multi DSP adapters only */ 1710 static u16 get_dsp_index(struct hpi_adapter_obj *pao, struct hpi_message *phm) 1711 { 1712 u16 ret = 0; 1713 switch (phm->object) { 1714 case HPI_OBJ_ISTREAM: 1715 if (phm->obj_index < 2) 1716 ret = 1; 1717 break; 1718 case HPI_OBJ_PROFILE: 1719 ret = phm->obj_index; 1720 break; 1721 default: 1722 break; 1723 } 1724 return ret; 1725 } 1726 1727 /** Complete transaction with DSP 1728 1729 Send message, get response, send or get stream data if any. 1730 */ 1731 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, 1732 struct hpi_response *phr) 1733 { 1734 u16 error = 0; 1735 u16 dsp_index = 0; 1736 struct hpi_hw_obj *phw = pao->priv; 1737 u16 num_dsp = phw->num_dsp; 1738 1739 if (num_dsp < 2) 1740 dsp_index = 0; 1741 else { 1742 dsp_index = get_dsp_index(pao, phm); 1743 1744 /* is this checked on the DSP anyway? */ 1745 if ((phm->function == HPI_ISTREAM_GROUP_ADD) 1746 || (phm->function == HPI_OSTREAM_GROUP_ADD)) { 1747 struct hpi_message hm; 1748 u16 add_index; 1749 hm.obj_index = phm->u.d.u.stream.stream_index; 1750 hm.object = phm->u.d.u.stream.object_type; 1751 add_index = get_dsp_index(pao, &hm); 1752 if (add_index != dsp_index) { 1753 phr->error = HPI_ERROR_NO_INTERDSP_GROUPS; 1754 return; 1755 } 1756 } 1757 } 1758 1759 hpios_dsplock_lock(pao); 1760 error = hpi6000_message_response_sequence(pao, dsp_index, phm, phr); 1761 1762 if (error) /* something failed in the HPI/DSP interface */ 1763 goto err; 1764 1765 if (phr->error) /* something failed in the DSP */ 1766 goto out; 1767 1768 switch (phm->function) { 1769 case HPI_OSTREAM_WRITE: 1770 case HPI_ISTREAM_ANC_WRITE: 1771 error = hpi6000_send_data(pao, dsp_index, phm, phr); 1772 break; 1773 case HPI_ISTREAM_READ: 1774 case HPI_OSTREAM_ANC_READ: 1775 error = hpi6000_get_data(pao, dsp_index, phm, phr); 1776 break; 1777 case HPI_ADAPTER_GET_ASSERT: 1778 phr->u.ax.assert.dsp_index = 0; /* dsp 0 default */ 1779 if (num_dsp == 2) { 1780 if (!phr->u.ax.assert.count) { 1781 /* no assert from dsp 0, check dsp 1 */ 1782 error = hpi6000_message_response_sequence(pao, 1783 1, phm, phr); 1784 phr->u.ax.assert.dsp_index = 1; 1785 } 1786 } 1787 } 1788 1789 err: 1790 if (error) { 1791 if (error >= HPI_ERROR_BACKEND_BASE) { 1792 phr->error = HPI_ERROR_DSP_COMMUNICATION; 1793 phr->specific_error = error; 1794 } else { 1795 phr->error = error; 1796 } 1797 1798 /* just the header of the response is valid */ 1799 phr->size = sizeof(struct hpi_response_header); 1800 } 1801 out: 1802 hpios_dsplock_unlock(pao); 1803 return; 1804 } 1805