1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/atomic.h> 4 #include <linux/bits.h> 5 #include <linux/bitfield.h> 6 #include <linux/bug.h> 7 #include <linux/container_of.h> 8 #include <linux/dev_printk.h> 9 #include <linux/dpll.h> 10 #include <linux/err.h> 11 #include <linux/kthread.h> 12 #include <linux/math64.h> 13 #include <linux/mod_devicetable.h> 14 #include <linux/module.h> 15 #include <linux/netlink.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/slab.h> 19 #include <linux/sprintf.h> 20 21 #include "core.h" 22 #include "dpll.h" 23 #include "prop.h" 24 #include "regs.h" 25 26 #define ZL3073X_DPLL_REF_NONE ZL3073X_NUM_REFS 27 #define ZL3073X_DPLL_REF_IS_VALID(_ref) ((_ref) != ZL3073X_DPLL_REF_NONE) 28 29 /** 30 * struct zl3073x_dpll_pin - DPLL pin 31 * @list: this DPLL pin list entry 32 * @dpll: DPLL the pin is registered to 33 * @dpll_pin: pointer to registered dpll_pin 34 * @tracker: tracking object for the acquired reference 35 * @fwnode: firmware node handle 36 * @label: package label 37 * @dir: pin direction 38 * @id: pin id 39 * @prio: pin priority <0, 14> 40 * @esync_control: embedded sync is controllable 41 * @phase_gran: phase adjustment granularity 42 * @operstate: last saved operational state 43 * @phase_offset: last saved pin phase offset 44 * @freq_offset: last saved fractional frequency offset 45 * @measured_freq: last saved measured frequency 46 */ 47 struct zl3073x_dpll_pin { 48 struct list_head list; 49 struct zl3073x_dpll *dpll; 50 struct dpll_pin *dpll_pin; 51 dpll_tracker tracker; 52 struct fwnode_handle *fwnode; 53 char label[8]; 54 enum dpll_pin_direction dir; 55 u8 id; 56 u8 prio; 57 bool esync_control; 58 s32 phase_gran; 59 enum dpll_pin_operstate operstate; 60 s64 phase_offset; 61 atomic64_t freq_offset; 62 u32 measured_freq; 63 }; 64 65 /* 66 * Supported esync ranges for input and for output per output pair type 67 */ 68 static const struct dpll_pin_frequency esync_freq_ranges[] = { 69 DPLL_PIN_FREQUENCY_RANGE(0, 1), 70 }; 71 72 /** 73 * zl3073x_dpll_is_input_pin - check if the pin is input one 74 * @pin: pin to check 75 * 76 * Return: true if pin is input, false if pin is output. 77 */ 78 static bool 79 zl3073x_dpll_is_input_pin(struct zl3073x_dpll_pin *pin) 80 { 81 return pin->dir == DPLL_PIN_DIRECTION_INPUT; 82 } 83 84 /** 85 * zl3073x_dpll_is_p_pin - check if the pin is P-pin 86 * @pin: pin to check 87 * 88 * Return: true if the pin is P-pin, false if it is N-pin 89 */ 90 static bool 91 zl3073x_dpll_is_p_pin(struct zl3073x_dpll_pin *pin) 92 { 93 return zl3073x_is_p_pin(pin->id); 94 } 95 96 static int 97 zl3073x_dpll_pin_direction_get(const struct dpll_pin *dpll_pin, void *pin_priv, 98 const struct dpll_device *dpll, void *dpll_priv, 99 enum dpll_pin_direction *direction, 100 struct netlink_ext_ack *extack) 101 { 102 struct zl3073x_dpll_pin *pin = pin_priv; 103 104 *direction = pin->dir; 105 106 return 0; 107 } 108 109 static struct zl3073x_dpll_pin * 110 zl3073x_dpll_pin_get_by_ref(struct zl3073x_dpll *zldpll, u8 ref_id) 111 { 112 struct zl3073x_dpll_pin *pin; 113 114 list_for_each_entry(pin, &zldpll->pins, list) { 115 if (zl3073x_dpll_is_input_pin(pin) && 116 zl3073x_input_pin_ref_get(pin->id) == ref_id) 117 return pin; 118 } 119 120 return NULL; 121 } 122 123 static int 124 zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin, 125 void *pin_priv, 126 const struct dpll_device *dpll, 127 void *dpll_priv, 128 struct dpll_pin_esync *esync, 129 struct netlink_ext_ack *extack) 130 { 131 struct zl3073x_dpll *zldpll = dpll_priv; 132 struct zl3073x_dev *zldev = zldpll->dev; 133 struct zl3073x_dpll_pin *pin = pin_priv; 134 const struct zl3073x_ref *ref; 135 u8 ref_id; 136 137 ref_id = zl3073x_input_pin_ref_get(pin->id); 138 ref = zl3073x_ref_state_get(zldev, ref_id); 139 140 if (!pin->esync_control || zl3073x_ref_freq_get(ref) <= 1) 141 return -EOPNOTSUPP; 142 143 esync->range = esync_freq_ranges; 144 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 145 146 switch (zl3073x_ref_sync_mode_get(ref)) { 147 case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75: 148 esync->freq = ref->esync_n_div == ZL_REF_ESYNC_DIV_1HZ ? 1 : 0; 149 esync->pulse = 25; 150 break; 151 default: 152 esync->freq = 0; 153 esync->pulse = 0; 154 break; 155 } 156 157 return 0; 158 } 159 160 static int 161 zl3073x_dpll_input_pin_esync_set(const struct dpll_pin *dpll_pin, 162 void *pin_priv, 163 const struct dpll_device *dpll, 164 void *dpll_priv, u64 freq, 165 struct netlink_ext_ack *extack) 166 { 167 struct zl3073x_dpll *zldpll = dpll_priv; 168 struct zl3073x_dev *zldev = zldpll->dev; 169 struct zl3073x_dpll_pin *pin = pin_priv; 170 struct zl3073x_ref ref; 171 u8 ref_id, sync_mode; 172 173 ref_id = zl3073x_input_pin_ref_get(pin->id); 174 ref = *zl3073x_ref_state_get(zldev, ref_id); 175 176 /* Use freq == 0 to disable esync */ 177 if (!freq) 178 sync_mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF; 179 else 180 sync_mode = ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75; 181 182 zl3073x_ref_sync_mode_set(&ref, sync_mode); 183 184 if (freq) { 185 /* 1 Hz is only supported frequency now */ 186 ref.esync_n_div = ZL_REF_ESYNC_DIV_1HZ; 187 } 188 189 /* Update reference configuration */ 190 return zl3073x_ref_state_set(zldev, ref_id, &ref); 191 } 192 193 static int 194 zl3073x_dpll_input_pin_ref_sync_get(const struct dpll_pin *dpll_pin, 195 void *pin_priv, 196 const struct dpll_pin *ref_sync_pin, 197 void *ref_sync_pin_priv, 198 enum dpll_pin_state *state, 199 struct netlink_ext_ack *extack) 200 { 201 struct zl3073x_dpll_pin *sync_pin = ref_sync_pin_priv; 202 struct zl3073x_dpll_pin *pin = pin_priv; 203 struct zl3073x_dpll *zldpll = pin->dpll; 204 struct zl3073x_dev *zldev = zldpll->dev; 205 const struct zl3073x_ref *ref; 206 u8 ref_id, mode, pair; 207 208 ref_id = zl3073x_input_pin_ref_get(pin->id); 209 ref = zl3073x_ref_state_get(zldev, ref_id); 210 mode = zl3073x_ref_sync_mode_get(ref); 211 pair = zl3073x_ref_sync_pair_get(ref); 212 213 if (mode == ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR && 214 pair == zl3073x_input_pin_ref_get(sync_pin->id)) 215 *state = DPLL_PIN_STATE_CONNECTED; 216 else 217 *state = DPLL_PIN_STATE_DISCONNECTED; 218 219 return 0; 220 } 221 222 static int 223 zl3073x_dpll_input_pin_ref_sync_set(const struct dpll_pin *dpll_pin, 224 void *pin_priv, 225 const struct dpll_pin *ref_sync_pin, 226 void *ref_sync_pin_priv, 227 const enum dpll_pin_state state, 228 struct netlink_ext_ack *extack) 229 { 230 struct zl3073x_dpll_pin *sync_pin = ref_sync_pin_priv; 231 struct zl3073x_dpll_pin *pin = pin_priv; 232 struct zl3073x_dpll *zldpll = pin->dpll; 233 struct zl3073x_dev *zldev = zldpll->dev; 234 u8 mode, ref_id, sync_ref_id; 235 struct zl3073x_chan chan; 236 struct zl3073x_ref ref; 237 int rc; 238 239 ref_id = zl3073x_input_pin_ref_get(pin->id); 240 sync_ref_id = zl3073x_input_pin_ref_get(sync_pin->id); 241 ref = *zl3073x_ref_state_get(zldev, ref_id); 242 243 if (state == DPLL_PIN_STATE_CONNECTED) { 244 const struct zl3073x_ref *sync_ref; 245 u32 ref_freq, sync_freq; 246 247 sync_ref = zl3073x_ref_state_get(zldev, sync_ref_id); 248 ref_freq = zl3073x_ref_freq_get(&ref); 249 sync_freq = zl3073x_ref_freq_get(sync_ref); 250 251 /* Sync signal must be 8 kHz or less and clock reference 252 * must be 1 kHz or more and higher than the sync signal. 253 */ 254 if (sync_freq > 8000) { 255 NL_SET_ERR_MSG(extack, 256 "sync frequency must be 8 kHz or less"); 257 return -EINVAL; 258 } 259 if (ref_freq < 1000) { 260 NL_SET_ERR_MSG(extack, 261 "clock frequency must be 1 kHz or more"); 262 return -EINVAL; 263 } 264 if (ref_freq <= sync_freq) { 265 NL_SET_ERR_MSG(extack, 266 "clock frequency must be higher than sync frequency"); 267 return -EINVAL; 268 } 269 270 zl3073x_ref_sync_pair_set(&ref, sync_ref_id); 271 mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR; 272 } else { 273 mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF; 274 } 275 276 zl3073x_ref_sync_mode_set(&ref, mode); 277 278 rc = zl3073x_ref_state_set(zldev, ref_id, &ref); 279 if (rc) 280 return rc; 281 282 /* Exclude sync source from automatic reference selection by setting 283 * its priority to NONE. On disconnect the priority is left as NONE 284 * and the user must explicitly make the pin selectable again. 285 */ 286 if (state == DPLL_PIN_STATE_CONNECTED) { 287 chan = *zl3073x_chan_state_get(zldev, zldpll->id); 288 zl3073x_chan_ref_prio_set(&chan, sync_ref_id, 289 ZL_DPLL_REF_PRIO_NONE); 290 return zl3073x_chan_state_set(zldev, zldpll->id, &chan); 291 } 292 293 return 0; 294 } 295 296 static int 297 zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv, 298 const struct dpll_device *dpll, void *dpll_priv, 299 struct dpll_ffo_param *ffo, 300 struct netlink_ext_ack *extack) 301 { 302 struct zl3073x_dpll_pin *pin = pin_priv; 303 304 if (pin->operstate != DPLL_PIN_OPERSTATE_ACTIVE) 305 return -ENODATA; 306 307 ffo->ffo = atomic64_read(&pin->freq_offset); 308 309 return 0; 310 } 311 312 static int 313 zl3073x_dpll_input_pin_measured_freq_get(const struct dpll_pin *dpll_pin, 314 void *pin_priv, 315 const struct dpll_device *dpll, 316 void *dpll_priv, u64 *measured_freq, 317 struct netlink_ext_ack *extack) 318 { 319 struct zl3073x_dpll_pin *pin = pin_priv; 320 321 *measured_freq = pin->measured_freq; 322 *measured_freq *= DPLL_PIN_MEASURED_FREQUENCY_DIVIDER; 323 324 return 0; 325 } 326 327 static int 328 zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin *dpll_pin, 329 void *pin_priv, 330 const struct dpll_device *dpll, 331 void *dpll_priv, u64 *frequency, 332 struct netlink_ext_ack *extack) 333 { 334 struct zl3073x_dpll *zldpll = dpll_priv; 335 struct zl3073x_dpll_pin *pin = pin_priv; 336 u8 ref_id; 337 338 ref_id = zl3073x_input_pin_ref_get(pin->id); 339 *frequency = zl3073x_dev_ref_freq_get(zldpll->dev, ref_id); 340 341 return 0; 342 } 343 344 static int 345 zl3073x_dpll_input_pin_frequency_set(const struct dpll_pin *dpll_pin, 346 void *pin_priv, 347 const struct dpll_device *dpll, 348 void *dpll_priv, u64 frequency, 349 struct netlink_ext_ack *extack) 350 { 351 struct zl3073x_dpll *zldpll = dpll_priv; 352 struct zl3073x_dev *zldev = zldpll->dev; 353 struct zl3073x_dpll_pin *pin = pin_priv; 354 struct zl3073x_ref ref; 355 u8 ref_id; 356 357 /* Get reference state */ 358 ref_id = zl3073x_input_pin_ref_get(pin->id); 359 ref = *zl3073x_ref_state_get(zldev, ref_id); 360 361 /* Update frequency */ 362 zl3073x_ref_freq_set(&ref, frequency); 363 364 /* Commit reference state */ 365 return zl3073x_ref_state_set(zldev, ref_id, &ref); 366 } 367 368 /** 369 * zl3073x_dpll_connected_ref_get - get currently connected reference 370 * @zldpll: pointer to zl3073x_dpll 371 * 372 * Looks for currently connected reference the DPLL is locked to. 373 * 374 * Return: reference index if locked, ZL3073X_DPLL_REF_NONE otherwise 375 */ 376 static u8 377 zl3073x_dpll_connected_ref_get(struct zl3073x_dpll *zldpll) 378 { 379 const struct zl3073x_chan *chan = zl3073x_chan_state_get(zldpll->dev, 380 zldpll->id); 381 u8 state; 382 383 /* A reference is connected only when the DPLL is locked to it */ 384 state = zl3073x_chan_refsel_state_get(chan); 385 if (state == ZL_DPLL_REFSEL_STATUS_STATE_LOCK) 386 return zl3073x_chan_refsel_ref_get(chan); 387 388 return ZL3073X_DPLL_REF_NONE; 389 } 390 391 static int 392 zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin *dpll_pin, 393 void *pin_priv, 394 const struct dpll_device *dpll, 395 void *dpll_priv, s64 *phase_offset, 396 struct netlink_ext_ack *extack) 397 { 398 struct zl3073x_dpll *zldpll = dpll_priv; 399 struct zl3073x_dev *zldev = zldpll->dev; 400 struct zl3073x_dpll_pin *pin = pin_priv; 401 const struct zl3073x_ref *ref; 402 u8 conn_id, ref_id; 403 s64 ref_phase; 404 405 /* Get currently connected reference */ 406 conn_id = zl3073x_dpll_connected_ref_get(zldpll); 407 408 /* Report phase offset only for currently connected pin if the phase 409 * monitor feature is disabled and only if the input pin signal is 410 * present. 411 */ 412 ref_id = zl3073x_input_pin_ref_get(pin->id); 413 ref = zl3073x_ref_state_get(zldev, ref_id); 414 if ((!zldpll->phase_monitor && ref_id != conn_id) || 415 !zl3073x_ref_is_status_ok(ref)) { 416 *phase_offset = 0; 417 return 0; 418 } 419 420 ref_phase = pin->phase_offset; 421 422 /* The DPLL being locked to a higher freq than the current ref 423 * the phase offset is modded to the period of the signal 424 * the dpll is locked to. 425 */ 426 if (ZL3073X_DPLL_REF_IS_VALID(conn_id) && conn_id != ref_id) { 427 u32 conn_freq, ref_freq; 428 429 /* Get frequency of connected and given ref */ 430 conn_freq = zl3073x_dev_ref_freq_get(zldev, conn_id); 431 ref_freq = zl3073x_ref_freq_get(ref); 432 433 if (conn_freq > ref_freq) { 434 s64 conn_period, div_factor; 435 436 conn_period = div_s64(PSEC_PER_SEC, conn_freq); 437 div_factor = div64_s64(ref_phase, conn_period); 438 ref_phase -= conn_period * div_factor; 439 } 440 } 441 442 *phase_offset = ref_phase * DPLL_PHASE_OFFSET_DIVIDER; 443 444 return 0; 445 } 446 447 static int 448 zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 449 void *pin_priv, 450 const struct dpll_device *dpll, 451 void *dpll_priv, 452 s32 *phase_adjust, 453 struct netlink_ext_ack *extack) 454 { 455 struct zl3073x_dpll *zldpll = dpll_priv; 456 struct zl3073x_dev *zldev = zldpll->dev; 457 struct zl3073x_dpll_pin *pin = pin_priv; 458 const struct zl3073x_ref *ref; 459 s64 phase_comp; 460 u8 ref_id; 461 462 /* Read reference configuration */ 463 ref_id = zl3073x_input_pin_ref_get(pin->id); 464 ref = zl3073x_ref_state_get(zldev, ref_id); 465 466 /* Perform sign extension based on register width */ 467 if (zl3073x_dev_is_ref_phase_comp_32bit(zldev)) 468 phase_comp = sign_extend64(ref->phase_comp, 31); 469 else 470 phase_comp = sign_extend64(ref->phase_comp, 47); 471 472 /* Reverse two's complement negation applied during set and convert 473 * to 32bit signed int 474 */ 475 *phase_adjust = (s32)-phase_comp; 476 477 return 0; 478 } 479 480 static int 481 zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 482 void *pin_priv, 483 const struct dpll_device *dpll, 484 void *dpll_priv, 485 s32 phase_adjust, 486 struct netlink_ext_ack *extack) 487 { 488 struct zl3073x_dpll *zldpll = dpll_priv; 489 struct zl3073x_dev *zldev = zldpll->dev; 490 struct zl3073x_dpll_pin *pin = pin_priv; 491 struct zl3073x_ref ref; 492 u8 ref_id; 493 494 /* Read reference configuration */ 495 ref_id = zl3073x_input_pin_ref_get(pin->id); 496 ref = *zl3073x_ref_state_get(zldev, ref_id); 497 498 /* The value in the register is stored as two's complement negation 499 * of requested value. 500 */ 501 ref.phase_comp = -phase_adjust; 502 503 /* Update reference configuration */ 504 return zl3073x_ref_state_set(zldev, ref_id, &ref); 505 } 506 507 /** 508 * zl3073x_dpll_ref_operstate_get - get operational state for input pin 509 * @pin: pointer to pin 510 * @operstate: place to store operational state 511 * 512 * Returns the actual hardware state of the pin: whether it is actively 513 * used by the DPLL, has no signal, failed qualification, or is simply 514 * not in use. 515 * 516 * Return: 0 on success, <0 on error 517 */ 518 static int 519 zl3073x_dpll_ref_operstate_get(struct zl3073x_dpll_pin *pin, 520 enum dpll_pin_operstate *operstate) 521 { 522 struct zl3073x_dpll *zldpll = pin->dpll; 523 struct zl3073x_dev *zldev = zldpll->dev; 524 const struct zl3073x_ref *ref; 525 u8 ref_id; 526 527 ref_id = zl3073x_input_pin_ref_get(pin->id); 528 529 /* Check if this pin is the currently locked reference */ 530 if (ref_id == zl3073x_dpll_connected_ref_get(zldpll)) { 531 *operstate = DPLL_PIN_OPERSTATE_ACTIVE; 532 return 0; 533 } 534 535 /* Check reference monitor status */ 536 ref = zl3073x_ref_state_get(zldev, ref_id); 537 if (ref->mon_status & ZL_REF_MON_STATUS_LOS) 538 *operstate = DPLL_PIN_OPERSTATE_NO_SIGNAL; 539 else if (!zl3073x_ref_is_status_ok(ref)) 540 *operstate = DPLL_PIN_OPERSTATE_QUAL_FAILED; 541 else 542 *operstate = DPLL_PIN_OPERSTATE_STANDBY; 543 544 return 0; 545 } 546 547 static int 548 zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 549 void *pin_priv, 550 const struct dpll_device *dpll, 551 void *dpll_priv, 552 enum dpll_pin_state *state, 553 struct netlink_ext_ack *extack) 554 { 555 struct zl3073x_dpll *zldpll = dpll_priv; 556 struct zl3073x_dpll_pin *pin = pin_priv; 557 const struct zl3073x_chan *chan; 558 u8 mode, ref; 559 560 chan = zl3073x_chan_state_get(zldpll->dev, zldpll->id); 561 ref = zl3073x_input_pin_ref_get(pin->id); 562 mode = zl3073x_chan_mode_get(chan); 563 564 switch (mode) { 565 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 566 if (ref == zl3073x_chan_ref_get(chan)) 567 *state = DPLL_PIN_STATE_CONNECTED; 568 else 569 *state = DPLL_PIN_STATE_DISCONNECTED; 570 break; 571 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 572 if (zl3073x_chan_ref_is_selectable(chan, ref)) 573 *state = DPLL_PIN_STATE_SELECTABLE; 574 else 575 *state = DPLL_PIN_STATE_DISCONNECTED; 576 break; 577 default: 578 *state = DPLL_PIN_STATE_DISCONNECTED; 579 break; 580 } 581 582 return 0; 583 } 584 585 static int 586 zl3073x_dpll_input_pin_operstate_on_dpll_get(const struct dpll_pin *dpll_pin, 587 void *pin_priv, 588 const struct dpll_device *dpll, 589 void *dpll_priv, 590 enum dpll_pin_operstate *operstate, 591 struct netlink_ext_ack *extack) 592 { 593 struct zl3073x_dpll_pin *pin = pin_priv; 594 595 return zl3073x_dpll_ref_operstate_get(pin, operstate); 596 } 597 598 static int 599 zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin *dpll_pin, 600 void *pin_priv, 601 const struct dpll_device *dpll, 602 void *dpll_priv, 603 enum dpll_pin_state state, 604 struct netlink_ext_ack *extack) 605 { 606 struct zl3073x_dpll *zldpll = dpll_priv; 607 struct zl3073x_dpll_pin *pin = pin_priv; 608 struct zl3073x_chan chan; 609 u8 mode, ref; 610 int rc; 611 612 chan = *zl3073x_chan_state_get(zldpll->dev, zldpll->id); 613 ref = zl3073x_input_pin_ref_get(pin->id); 614 mode = zl3073x_chan_mode_get(&chan); 615 616 switch (mode) { 617 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 618 if (state == DPLL_PIN_STATE_CONNECTED) { 619 /* Choose the pin as new selected reference */ 620 zl3073x_chan_ref_set(&chan, ref); 621 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 622 /* Choose new mode based on lock status */ 623 switch (zldpll->lock_status) { 624 case DPLL_LOCK_STATUS_LOCKED_HO_ACQ: 625 case DPLL_LOCK_STATUS_HOLDOVER: 626 mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; 627 break; 628 default: 629 mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN; 630 break; 631 } 632 zl3073x_chan_mode_set(&chan, mode); 633 } else { 634 goto invalid_state; 635 } 636 break; 637 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 638 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 639 if (state == DPLL_PIN_STATE_CONNECTED) { 640 /* Choose the pin as new selected reference */ 641 zl3073x_chan_ref_set(&chan, ref); 642 /* Switch to reflock mode */ 643 zl3073x_chan_mode_set(&chan, 644 ZL_DPLL_MODE_REFSEL_MODE_REFLOCK); 645 } else if (state != DPLL_PIN_STATE_DISCONNECTED) { 646 goto invalid_state; 647 } 648 break; 649 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 650 if (state == DPLL_PIN_STATE_SELECTABLE) { 651 if (zl3073x_chan_ref_is_selectable(&chan, ref)) 652 return 0; /* Pin is already selectable */ 653 654 /* Restore pin priority in HW */ 655 zl3073x_chan_ref_prio_set(&chan, ref, pin->prio); 656 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 657 if (!zl3073x_chan_ref_is_selectable(&chan, ref)) 658 return 0; /* Pin is already disconnected */ 659 660 /* Set pin priority to none in HW */ 661 zl3073x_chan_ref_prio_set(&chan, ref, 662 ZL_DPLL_REF_PRIO_NONE); 663 } else { 664 goto invalid_state; 665 } 666 break; 667 default: 668 /* In other modes we cannot change input reference */ 669 NL_SET_ERR_MSG(extack, 670 "Pin state cannot be changed in current mode"); 671 return -EOPNOTSUPP; 672 } 673 674 /* Commit DPLL channel changes */ 675 rc = zl3073x_chan_state_set(zldpll->dev, zldpll->id, &chan); 676 if (rc) 677 return rc; 678 679 return 0; 680 invalid_state: 681 NL_SET_ERR_MSG_MOD(extack, "Invalid pin state for this device mode"); 682 return -EINVAL; 683 } 684 685 static int 686 zl3073x_dpll_input_pin_prio_get(const struct dpll_pin *dpll_pin, void *pin_priv, 687 const struct dpll_device *dpll, void *dpll_priv, 688 u32 *prio, struct netlink_ext_ack *extack) 689 { 690 struct zl3073x_dpll_pin *pin = pin_priv; 691 692 *prio = pin->prio; 693 694 return 0; 695 } 696 697 static int 698 zl3073x_dpll_input_pin_prio_set(const struct dpll_pin *dpll_pin, void *pin_priv, 699 const struct dpll_device *dpll, void *dpll_priv, 700 u32 prio, struct netlink_ext_ack *extack) 701 { 702 struct zl3073x_dpll *zldpll = dpll_priv; 703 struct zl3073x_dpll_pin *pin = pin_priv; 704 struct zl3073x_chan chan; 705 u8 ref; 706 int rc; 707 708 if (prio > ZL_DPLL_REF_PRIO_MAX) 709 return -EINVAL; 710 711 /* If the pin is selectable then update HW registers */ 712 chan = *zl3073x_chan_state_get(zldpll->dev, zldpll->id); 713 ref = zl3073x_input_pin_ref_get(pin->id); 714 if (zl3073x_chan_ref_is_selectable(&chan, ref)) { 715 zl3073x_chan_ref_prio_set(&chan, ref, prio); 716 rc = zl3073x_chan_state_set(zldpll->dev, zldpll->id, &chan); 717 if (rc) 718 return rc; 719 } 720 721 /* Save priority */ 722 pin->prio = prio; 723 724 return 0; 725 } 726 727 static int 728 zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin, 729 void *pin_priv, 730 const struct dpll_device *dpll, 731 void *dpll_priv, 732 struct dpll_pin_esync *esync, 733 struct netlink_ext_ack *extack) 734 { 735 struct zl3073x_dpll *zldpll = dpll_priv; 736 struct zl3073x_dev *zldev = zldpll->dev; 737 struct zl3073x_dpll_pin *pin = pin_priv; 738 const struct zl3073x_synth *synth; 739 const struct zl3073x_out *out; 740 u32 synth_freq, out_freq; 741 u8 out_id; 742 743 out_id = zl3073x_output_pin_out_get(pin->id); 744 out = zl3073x_out_state_get(zldev, out_id); 745 746 /* If N-division is enabled, esync is not supported. The register used 747 * for N-division is also used for the esync divider so both cannot 748 * be used. 749 */ 750 if (zl3073x_out_is_ndiv(out)) 751 return -EOPNOTSUPP; 752 753 /* Get attached synth frequency */ 754 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(out)); 755 synth_freq = zl3073x_synth_freq_get(synth); 756 out_freq = synth_freq / out->div; 757 758 if (!pin->esync_control || out_freq <= 1) 759 return -EOPNOTSUPP; 760 761 esync->range = esync_freq_ranges; 762 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 763 764 if (zl3073x_out_clock_type_get(out) != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) { 765 /* No need to read esync data if it is not enabled */ 766 esync->freq = 0; 767 esync->pulse = 0; 768 769 return 0; 770 } 771 772 /* Compute esync frequency */ 773 esync->freq = out_freq / out->esync_n_period; 774 775 /* By comparing the esync_pulse_width to the half of the pulse width 776 * the esync pulse percentage can be determined. 777 * Note that half pulse width is in units of half synth cycles, which 778 * is why it reduces down to be output_div. 779 */ 780 esync->pulse = (50 * out->esync_n_width) / out->div; 781 782 return 0; 783 } 784 785 static int 786 zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin, 787 void *pin_priv, 788 const struct dpll_device *dpll, 789 void *dpll_priv, u64 freq, 790 struct netlink_ext_ack *extack) 791 { 792 struct zl3073x_dpll *zldpll = dpll_priv; 793 struct zl3073x_dev *zldev = zldpll->dev; 794 struct zl3073x_dpll_pin *pin = pin_priv; 795 const struct zl3073x_synth *synth; 796 struct zl3073x_out out; 797 u32 synth_freq; 798 u8 out_id; 799 800 out_id = zl3073x_output_pin_out_get(pin->id); 801 out = *zl3073x_out_state_get(zldev, out_id); 802 803 /* If N-division is enabled, esync is not supported. The register used 804 * for N-division is also used for the esync divider so both cannot 805 * be used. 806 */ 807 if (zl3073x_out_is_ndiv(&out)) 808 return -EOPNOTSUPP; 809 810 /* Update clock type in output mode */ 811 if (freq) 812 zl3073x_out_clock_type_set(&out, 813 ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC); 814 else 815 zl3073x_out_clock_type_set(&out, 816 ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL); 817 818 /* If esync is being disabled just write mailbox and finish */ 819 if (!freq) 820 goto write_mailbox; 821 822 /* Get attached synth frequency */ 823 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(&out)); 824 synth_freq = zl3073x_synth_freq_get(synth); 825 826 /* Compute and update esync period */ 827 out.esync_n_period = synth_freq / (u32)freq / out.div; 828 829 /* Half of the period in units of 1/2 synth cycle can be represented by 830 * the output_div. To get the supported esync pulse width of 25% of the 831 * period the output_div can just be divided by 2. Note that this 832 * assumes that output_div is even, otherwise some resolution will be 833 * lost. 834 */ 835 out.esync_n_width = out.div / 2; 836 837 write_mailbox: 838 /* Commit output configuration */ 839 return zl3073x_out_state_set(zldev, out_id, &out); 840 } 841 842 static int 843 zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin *dpll_pin, 844 void *pin_priv, 845 const struct dpll_device *dpll, 846 void *dpll_priv, u64 *frequency, 847 struct netlink_ext_ack *extack) 848 { 849 struct zl3073x_dpll *zldpll = dpll_priv; 850 struct zl3073x_dpll_pin *pin = pin_priv; 851 852 *frequency = zl3073x_dev_output_pin_freq_get(zldpll->dev, pin->id); 853 854 return 0; 855 } 856 857 static int 858 zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin, 859 void *pin_priv, 860 const struct dpll_device *dpll, 861 void *dpll_priv, u64 frequency, 862 struct netlink_ext_ack *extack) 863 { 864 struct zl3073x_dpll *zldpll = dpll_priv; 865 struct zl3073x_dev *zldev = zldpll->dev; 866 struct zl3073x_dpll_pin *pin = pin_priv; 867 const struct zl3073x_synth *synth; 868 u32 new_div, synth_freq; 869 struct zl3073x_out out; 870 u8 out_id; 871 872 out_id = zl3073x_output_pin_out_get(pin->id); 873 out = *zl3073x_out_state_get(zldev, out_id); 874 875 /* Get attached synth frequency and compute new divisor */ 876 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(&out)); 877 synth_freq = zl3073x_synth_freq_get(synth); 878 new_div = synth_freq / (u32)frequency; 879 880 /* Check signal format */ 881 if (!zl3073x_out_is_ndiv(&out)) { 882 /* For non N-divided signal formats the frequency is computed 883 * as division of synth frequency and output divisor. 884 */ 885 out.div = new_div; 886 887 /* For 50/50 duty cycle the divisor is equal to width */ 888 out.width = new_div; 889 890 /* Commit output configuration */ 891 return zl3073x_out_state_set(zldev, out_id, &out); 892 } 893 894 if (zl3073x_dpll_is_p_pin(pin)) { 895 /* We are going to change output frequency for P-pin but 896 * if the requested frequency is less than current N-pin 897 * frequency then indicate a failure as we are not able 898 * to compute N-pin divisor to keep its frequency unchanged. 899 * 900 * Update divisor for N-pin to keep N-pin frequency. 901 */ 902 out.esync_n_period = (out.esync_n_period * out.div) / new_div; 903 if (!out.esync_n_period) 904 return -EINVAL; 905 906 /* Update the output divisor */ 907 out.div = new_div; 908 909 /* For 50/50 duty cycle the divisor is equal to width */ 910 out.width = out.div; 911 } else { 912 /* We are going to change frequency of N-pin but if 913 * the requested freq is greater or equal than freq of P-pin 914 * in the output pair we cannot compute divisor for the N-pin. 915 * In this case indicate a failure. 916 * 917 * Update divisor for N-pin 918 */ 919 out.esync_n_period = div64_u64(synth_freq, frequency * out.div); 920 if (!out.esync_n_period) 921 return -EINVAL; 922 } 923 924 /* For 50/50 duty cycle the divisor is equal to width */ 925 out.esync_n_width = out.esync_n_period; 926 927 /* Commit output configuration */ 928 return zl3073x_out_state_set(zldev, out_id, &out); 929 } 930 931 static int 932 zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 933 void *pin_priv, 934 const struct dpll_device *dpll, 935 void *dpll_priv, 936 s32 *phase_adjust, 937 struct netlink_ext_ack *extack) 938 { 939 struct zl3073x_dpll *zldpll = dpll_priv; 940 struct zl3073x_dev *zldev = zldpll->dev; 941 struct zl3073x_dpll_pin *pin = pin_priv; 942 const struct zl3073x_out *out; 943 u8 out_id; 944 945 out_id = zl3073x_output_pin_out_get(pin->id); 946 out = zl3073x_out_state_get(zldev, out_id); 947 948 /* The value in the register is expressed in half synth clock cycles. */ 949 *phase_adjust = out->phase_comp * pin->phase_gran; 950 951 return 0; 952 } 953 954 static int 955 zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 956 void *pin_priv, 957 const struct dpll_device *dpll, 958 void *dpll_priv, 959 s32 phase_adjust, 960 struct netlink_ext_ack *extack) 961 { 962 struct zl3073x_dpll *zldpll = dpll_priv; 963 struct zl3073x_dev *zldev = zldpll->dev; 964 struct zl3073x_dpll_pin *pin = pin_priv; 965 struct zl3073x_out out; 966 u8 out_id; 967 968 out_id = zl3073x_output_pin_out_get(pin->id); 969 out = *zl3073x_out_state_get(zldev, out_id); 970 971 /* The value in the register is expressed in half synth clock cycles. */ 972 out.phase_comp = phase_adjust / pin->phase_gran; 973 974 /* Update output configuration from mailbox */ 975 return zl3073x_out_state_set(zldev, out_id, &out); 976 } 977 978 static int 979 zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 980 void *pin_priv, 981 const struct dpll_device *dpll, 982 void *dpll_priv, 983 enum dpll_pin_state *state, 984 struct netlink_ext_ack *extack) 985 { 986 /* If the output pin is registered then it is always connected */ 987 *state = DPLL_PIN_STATE_CONNECTED; 988 989 return 0; 990 } 991 992 static int 993 zl3073x_dpll_temp_get(const struct dpll_device *dpll, void *dpll_priv, 994 s32 *temp, struct netlink_ext_ack *extack) 995 { 996 struct zl3073x_dpll *zldpll = dpll_priv; 997 struct zl3073x_dev *zldev = zldpll->dev; 998 u16 val; 999 int rc; 1000 1001 rc = zl3073x_read_u16(zldev, ZL_REG_DIE_TEMP_STATUS, &val); 1002 if (rc) 1003 return rc; 1004 1005 /* Register value is in units of 0.1 C, convert to millidegrees */ 1006 *temp = (s16)val * 100; 1007 1008 return 0; 1009 } 1010 1011 static int 1012 zl3073x_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv, 1013 enum dpll_lock_status *status, 1014 enum dpll_lock_status_error *status_error, 1015 struct netlink_ext_ack *extack) 1016 { 1017 struct zl3073x_dpll *zldpll = dpll_priv; 1018 const struct zl3073x_chan *chan; 1019 1020 chan = zl3073x_chan_state_get(zldpll->dev, zldpll->id); 1021 1022 switch (zl3073x_chan_mode_get(chan)) { 1023 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1024 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1025 /* In FREERUN and NCO modes the DPLL is always unlocked */ 1026 *status = DPLL_LOCK_STATUS_UNLOCKED; 1027 1028 return 0; 1029 default: 1030 break; 1031 } 1032 1033 switch (zl3073x_chan_lock_state_get(chan)) { 1034 case ZL_DPLL_MON_STATUS_STATE_LOCK: 1035 if (zl3073x_chan_is_ho_ready(chan)) 1036 *status = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 1037 else 1038 *status = DPLL_LOCK_STATUS_LOCKED; 1039 break; 1040 case ZL_DPLL_MON_STATUS_STATE_HOLDOVER: 1041 case ZL_DPLL_MON_STATUS_STATE_ACQUIRING: 1042 *status = DPLL_LOCK_STATUS_HOLDOVER; 1043 break; 1044 default: 1045 dev_warn(zldpll->dev->dev, 1046 "Unknown DPLL monitor status: 0x%02x\n", 1047 chan->mon_status); 1048 *status = DPLL_LOCK_STATUS_UNLOCKED; 1049 break; 1050 } 1051 1052 return 0; 1053 } 1054 1055 static int 1056 zl3073x_dpll_supported_modes_get(const struct dpll_device *dpll, 1057 void *dpll_priv, unsigned long *modes, 1058 struct netlink_ext_ack *extack) 1059 { 1060 struct zl3073x_dpll *zldpll = dpll_priv; 1061 const struct zl3073x_chan *chan; 1062 1063 chan = zl3073x_chan_state_get(zldpll->dev, zldpll->id); 1064 1065 /* We support switching between automatic and manual mode, except in 1066 * a case where the DPLL channel is configured to run in NCO mode. 1067 * In this case, report only the manual mode to which the NCO is mapped 1068 * as the only supported one. 1069 */ 1070 if (zl3073x_chan_mode_get(chan) != ZL_DPLL_MODE_REFSEL_MODE_NCO) 1071 __set_bit(DPLL_MODE_AUTOMATIC, modes); 1072 1073 __set_bit(DPLL_MODE_MANUAL, modes); 1074 1075 return 0; 1076 } 1077 1078 static int 1079 zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv, 1080 enum dpll_mode *mode, struct netlink_ext_ack *extack) 1081 { 1082 struct zl3073x_dpll *zldpll = dpll_priv; 1083 const struct zl3073x_chan *chan; 1084 1085 chan = zl3073x_chan_state_get(zldpll->dev, zldpll->id); 1086 1087 switch (zl3073x_chan_mode_get(chan)) { 1088 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1089 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 1090 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1091 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 1092 /* Use MANUAL for device FREERUN, HOLDOVER, NCO and 1093 * REFLOCK modes 1094 */ 1095 *mode = DPLL_MODE_MANUAL; 1096 break; 1097 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 1098 /* Use AUTO for device AUTO mode */ 1099 *mode = DPLL_MODE_AUTOMATIC; 1100 break; 1101 default: 1102 return -EINVAL; 1103 } 1104 1105 return 0; 1106 } 1107 1108 static int 1109 zl3073x_dpll_phase_offset_avg_factor_get(const struct dpll_device *dpll, 1110 void *dpll_priv, u32 *factor, 1111 struct netlink_ext_ack *extack) 1112 { 1113 struct zl3073x_dpll *zldpll = dpll_priv; 1114 1115 *factor = zl3073x_dev_phase_avg_factor_get(zldpll->dev); 1116 1117 return 0; 1118 } 1119 1120 static int 1121 zl3073x_dpll_phase_offset_avg_factor_set(const struct dpll_device *dpll, 1122 void *dpll_priv, u32 factor, 1123 struct netlink_ext_ack *extack) 1124 { 1125 struct zl3073x_dpll *item, *zldpll = dpll_priv; 1126 int rc; 1127 1128 if (factor > 15) { 1129 NL_SET_ERR_MSG_FMT(extack, 1130 "Phase offset average factor has to be from range <0,15>"); 1131 return -EINVAL; 1132 } 1133 1134 rc = zl3073x_dev_phase_avg_factor_set(zldpll->dev, factor); 1135 if (rc) { 1136 NL_SET_ERR_MSG_FMT(extack, 1137 "Failed to set phase offset averaging factor"); 1138 return rc; 1139 } 1140 1141 /* The averaging factor is common for all DPLL channels so after change 1142 * we have to send a notification for other DPLL devices. 1143 */ 1144 list_for_each_entry(item, &zldpll->dev->dplls, list) { 1145 struct dpll_device *dpll_dev = READ_ONCE(item->dpll_dev); 1146 1147 if (item != zldpll && dpll_dev) 1148 __dpll_device_change_ntf(dpll_dev); 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int 1155 zl3073x_dpll_mode_set(const struct dpll_device *dpll, void *dpll_priv, 1156 enum dpll_mode mode, struct netlink_ext_ack *extack) 1157 { 1158 struct zl3073x_dpll *zldpll = dpll_priv; 1159 struct zl3073x_chan chan; 1160 u8 hw_mode, ref; 1161 int rc; 1162 1163 chan = *zl3073x_chan_state_get(zldpll->dev, zldpll->id); 1164 ref = zl3073x_chan_refsel_ref_get(&chan); 1165 1166 if (mode == DPLL_MODE_MANUAL) { 1167 /* We are switching from automatic to manual mode: 1168 * - if we have a valid reference selected during auto mode then 1169 * we will switch to forced reference lock mode and use this 1170 * reference for selection 1171 * - if NO valid reference is selected, we will switch to forced 1172 * holdover mode or freerun mode, depending on the current 1173 * lock status 1174 */ 1175 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1176 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK; 1177 else if (zldpll->lock_status == DPLL_LOCK_STATUS_UNLOCKED) 1178 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN; 1179 else 1180 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; 1181 } else { 1182 /* We are switching from manual to automatic mode: 1183 * - if there is a valid reference selected then ensure that 1184 * it is selectable after switch to automatic mode 1185 * - switch to automatic mode 1186 */ 1187 if (ZL3073X_DPLL_REF_IS_VALID(ref) && 1188 !zl3073x_chan_ref_is_selectable(&chan, ref)) { 1189 struct zl3073x_dpll_pin *pin; 1190 1191 pin = zl3073x_dpll_pin_get_by_ref(zldpll, ref); 1192 if (pin) { 1193 /* Restore pin priority in HW */ 1194 zl3073x_chan_ref_prio_set(&chan, ref, 1195 pin->prio); 1196 } 1197 } 1198 1199 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_AUTO; 1200 } 1201 1202 zl3073x_chan_mode_set(&chan, hw_mode); 1203 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1204 zl3073x_chan_ref_set(&chan, ref); 1205 1206 rc = zl3073x_chan_state_set(zldpll->dev, zldpll->id, &chan); 1207 if (rc) { 1208 NL_SET_ERR_MSG_MOD(extack, 1209 "failed to set reference selection mode"); 1210 return rc; 1211 } 1212 1213 return 0; 1214 } 1215 1216 static int 1217 zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device *dpll, 1218 void *dpll_priv, 1219 enum dpll_feature_state *state, 1220 struct netlink_ext_ack *extack) 1221 { 1222 struct zl3073x_dpll *zldpll = dpll_priv; 1223 1224 if (zldpll->phase_monitor) 1225 *state = DPLL_FEATURE_STATE_ENABLE; 1226 else 1227 *state = DPLL_FEATURE_STATE_DISABLE; 1228 1229 return 0; 1230 } 1231 1232 static int 1233 zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device *dpll, 1234 void *dpll_priv, 1235 enum dpll_feature_state state, 1236 struct netlink_ext_ack *extack) 1237 { 1238 struct zl3073x_dpll *zldpll = dpll_priv; 1239 1240 zldpll->phase_monitor = (state == DPLL_FEATURE_STATE_ENABLE); 1241 1242 return 0; 1243 } 1244 1245 static int 1246 zl3073x_dpll_freq_monitor_get(const struct dpll_device *dpll, 1247 void *dpll_priv, 1248 enum dpll_feature_state *state, 1249 struct netlink_ext_ack *extack) 1250 { 1251 struct zl3073x_dpll *zldpll = dpll_priv; 1252 1253 if (zldpll->dev->freq_monitor) 1254 *state = DPLL_FEATURE_STATE_ENABLE; 1255 else 1256 *state = DPLL_FEATURE_STATE_DISABLE; 1257 1258 return 0; 1259 } 1260 1261 static int 1262 zl3073x_dpll_freq_monitor_set(const struct dpll_device *dpll, 1263 void *dpll_priv, 1264 enum dpll_feature_state state, 1265 struct netlink_ext_ack *extack) 1266 { 1267 struct zl3073x_dpll *item, *zldpll = dpll_priv; 1268 1269 zldpll->dev->freq_monitor = (state == DPLL_FEATURE_STATE_ENABLE); 1270 1271 /* The frequency monitoring is common for all DPLL channels so after 1272 * change we have to send a notification for other DPLL devices. 1273 */ 1274 list_for_each_entry(item, &zldpll->dev->dplls, list) { 1275 struct dpll_device *dpll_dev = READ_ONCE(item->dpll_dev); 1276 1277 if (item != zldpll && dpll_dev) 1278 __dpll_device_change_ntf(dpll_dev); 1279 } 1280 1281 return 0; 1282 } 1283 1284 static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops = { 1285 .supported_ffo = BIT(DPLL_FFO_PIN_DEVICE), 1286 .direction_get = zl3073x_dpll_pin_direction_get, 1287 .esync_get = zl3073x_dpll_input_pin_esync_get, 1288 .esync_set = zl3073x_dpll_input_pin_esync_set, 1289 .ffo_get = zl3073x_dpll_input_pin_ffo_get, 1290 .frequency_get = zl3073x_dpll_input_pin_frequency_get, 1291 .frequency_set = zl3073x_dpll_input_pin_frequency_set, 1292 .measured_freq_get = zl3073x_dpll_input_pin_measured_freq_get, 1293 .operstate_on_dpll_get = zl3073x_dpll_input_pin_operstate_on_dpll_get, 1294 .phase_offset_get = zl3073x_dpll_input_pin_phase_offset_get, 1295 .phase_adjust_get = zl3073x_dpll_input_pin_phase_adjust_get, 1296 .phase_adjust_set = zl3073x_dpll_input_pin_phase_adjust_set, 1297 .prio_get = zl3073x_dpll_input_pin_prio_get, 1298 .prio_set = zl3073x_dpll_input_pin_prio_set, 1299 .ref_sync_get = zl3073x_dpll_input_pin_ref_sync_get, 1300 .ref_sync_set = zl3073x_dpll_input_pin_ref_sync_set, 1301 .state_on_dpll_get = zl3073x_dpll_input_pin_state_on_dpll_get, 1302 .state_on_dpll_set = zl3073x_dpll_input_pin_state_on_dpll_set, 1303 }; 1304 1305 static const struct dpll_pin_ops zl3073x_dpll_output_pin_ops = { 1306 .direction_get = zl3073x_dpll_pin_direction_get, 1307 .esync_get = zl3073x_dpll_output_pin_esync_get, 1308 .esync_set = zl3073x_dpll_output_pin_esync_set, 1309 .frequency_get = zl3073x_dpll_output_pin_frequency_get, 1310 .frequency_set = zl3073x_dpll_output_pin_frequency_set, 1311 .phase_adjust_get = zl3073x_dpll_output_pin_phase_adjust_get, 1312 .phase_adjust_set = zl3073x_dpll_output_pin_phase_adjust_set, 1313 .state_on_dpll_get = zl3073x_dpll_output_pin_state_on_dpll_get, 1314 }; 1315 1316 static const struct dpll_device_ops zl3073x_dpll_device_ops = { 1317 .lock_status_get = zl3073x_dpll_lock_status_get, 1318 .mode_get = zl3073x_dpll_mode_get, 1319 .mode_set = zl3073x_dpll_mode_set, 1320 .phase_offset_avg_factor_get = zl3073x_dpll_phase_offset_avg_factor_get, 1321 .phase_offset_avg_factor_set = zl3073x_dpll_phase_offset_avg_factor_set, 1322 .phase_offset_monitor_get = zl3073x_dpll_phase_offset_monitor_get, 1323 .phase_offset_monitor_set = zl3073x_dpll_phase_offset_monitor_set, 1324 .freq_monitor_get = zl3073x_dpll_freq_monitor_get, 1325 .freq_monitor_set = zl3073x_dpll_freq_monitor_set, 1326 .supported_modes_get = zl3073x_dpll_supported_modes_get, 1327 }; 1328 1329 /** 1330 * zl3073x_dpll_pin_alloc - allocate DPLL pin 1331 * @zldpll: pointer to zl3073x_dpll 1332 * @dir: pin direction 1333 * @id: pin id 1334 * 1335 * Allocates and initializes zl3073x_dpll_pin structure for given 1336 * pin id and direction. 1337 * 1338 * Return: pointer to allocated structure on success, error pointer on error 1339 */ 1340 static struct zl3073x_dpll_pin * 1341 zl3073x_dpll_pin_alloc(struct zl3073x_dpll *zldpll, enum dpll_pin_direction dir, 1342 u8 id) 1343 { 1344 struct zl3073x_dpll_pin *pin; 1345 1346 pin = kzalloc_obj(*pin); 1347 if (!pin) 1348 return ERR_PTR(-ENOMEM); 1349 1350 pin->dpll = zldpll; 1351 pin->dir = dir; 1352 pin->id = id; 1353 1354 return pin; 1355 } 1356 1357 /** 1358 * zl3073x_dpll_pin_free - deallocate DPLL pin 1359 * @pin: pin to free 1360 * 1361 * Deallocates DPLL pin previously allocated by @zl3073x_dpll_pin_alloc. 1362 */ 1363 static void 1364 zl3073x_dpll_pin_free(struct zl3073x_dpll_pin *pin) 1365 { 1366 WARN(pin->dpll_pin, "DPLL pin is still registered\n"); 1367 1368 kfree(pin); 1369 } 1370 1371 /** 1372 * zl3073x_dpll_pin_register - register DPLL pin 1373 * @pin: pointer to DPLL pin 1374 * @index: absolute pin index for registration 1375 * 1376 * Registers given DPLL pin into DPLL sub-system. 1377 * 1378 * Return: 0 on success, <0 on error 1379 */ 1380 static int 1381 zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index) 1382 { 1383 struct zl3073x_dpll *zldpll = pin->dpll; 1384 struct zl3073x_pin_props *props; 1385 const struct dpll_pin_ops *ops; 1386 int rc; 1387 1388 /* Get pin properties */ 1389 props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id); 1390 if (IS_ERR(props)) 1391 return PTR_ERR(props); 1392 1393 /* Save package label, fwnode, esync capability and phase adjust 1394 * granularity. 1395 */ 1396 strscpy(pin->label, props->package_label); 1397 pin->fwnode = fwnode_handle_get(props->fwnode); 1398 pin->esync_control = props->esync_control; 1399 pin->phase_gran = props->dpll_props.phase_gran; 1400 1401 if (zl3073x_dpll_is_input_pin(pin)) { 1402 const struct zl3073x_chan *chan; 1403 u8 ref; 1404 1405 chan = zl3073x_chan_state_get(zldpll->dev, zldpll->id); 1406 ref = zl3073x_input_pin_ref_get(pin->id); 1407 pin->prio = zl3073x_chan_ref_prio_get(chan, ref); 1408 1409 if (pin->prio == ZL_DPLL_REF_PRIO_NONE) 1410 /* Clamp prio to max value */ 1411 pin->prio = ZL_DPLL_REF_PRIO_MAX; 1412 } 1413 1414 /* Create or get existing DPLL pin */ 1415 pin->dpll_pin = dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE, 1416 &props->dpll_props, &pin->tracker); 1417 if (IS_ERR(pin->dpll_pin)) { 1418 rc = PTR_ERR(pin->dpll_pin); 1419 goto err_pin_get; 1420 } 1421 dpll_pin_fwnode_set(pin->dpll_pin, props->fwnode); 1422 1423 if (zl3073x_dpll_is_input_pin(pin)) 1424 ops = &zl3073x_dpll_input_pin_ops; 1425 else 1426 ops = &zl3073x_dpll_output_pin_ops; 1427 1428 /* Register the pin */ 1429 rc = dpll_pin_register(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1430 if (rc) 1431 goto err_register; 1432 1433 /* Free pin properties */ 1434 zl3073x_pin_props_put(props); 1435 1436 return 0; 1437 1438 err_register: 1439 dpll_pin_put(pin->dpll_pin, &pin->tracker); 1440 err_pin_get: 1441 pin->dpll_pin = NULL; 1442 fwnode_handle_put(pin->fwnode); 1443 pin->fwnode = NULL; 1444 zl3073x_pin_props_put(props); 1445 1446 return rc; 1447 } 1448 1449 /** 1450 * zl3073x_dpll_pin_unregister - unregister DPLL pin 1451 * @pin: pointer to DPLL pin 1452 * 1453 * Unregisters pin previously registered by @zl3073x_dpll_pin_register. 1454 */ 1455 static void 1456 zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *pin) 1457 { 1458 struct zl3073x_dpll *zldpll = pin->dpll; 1459 const struct dpll_pin_ops *ops; 1460 1461 WARN(!pin->dpll_pin, "DPLL pin is not registered\n"); 1462 1463 if (zl3073x_dpll_is_input_pin(pin)) 1464 ops = &zl3073x_dpll_input_pin_ops; 1465 else 1466 ops = &zl3073x_dpll_output_pin_ops; 1467 1468 /* Unregister the pin */ 1469 dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1470 1471 dpll_pin_put(pin->dpll_pin, &pin->tracker); 1472 pin->dpll_pin = NULL; 1473 1474 fwnode_handle_put(pin->fwnode); 1475 pin->fwnode = NULL; 1476 } 1477 1478 /** 1479 * zl3073x_dpll_pins_unregister - unregister all registered DPLL pins 1480 * @zldpll: pointer to zl3073x_dpll structure 1481 * 1482 * Enumerates all DPLL pins registered to given DPLL device and 1483 * unregisters them. 1484 */ 1485 static void 1486 zl3073x_dpll_pins_unregister(struct zl3073x_dpll *zldpll) 1487 { 1488 struct zl3073x_dpll_pin *pin, *next; 1489 1490 list_for_each_entry_safe(pin, next, &zldpll->pins, list) { 1491 zl3073x_dpll_pin_unregister(pin); 1492 list_del(&pin->list); 1493 zl3073x_dpll_pin_free(pin); 1494 } 1495 } 1496 1497 /** 1498 * zl3073x_dpll_pin_is_registrable - check if the pin is registrable 1499 * @zldpll: pointer to zl3073x_dpll structure 1500 * @dir: pin direction 1501 * @index: pin index 1502 * 1503 * Checks if the given pin can be registered to given DPLL. For both 1504 * directions the pin can be registered if it is enabled. In case of 1505 * differential signal type only P-pin is reported as registrable. 1506 * And additionally for the output pin, the pin can be registered only 1507 * if it is connected to synthesizer that is driven by given DPLL. 1508 * 1509 * Return: true if the pin is registrable, false if not 1510 */ 1511 static bool 1512 zl3073x_dpll_pin_is_registrable(struct zl3073x_dpll *zldpll, 1513 enum dpll_pin_direction dir, u8 index) 1514 { 1515 struct zl3073x_dev *zldev = zldpll->dev; 1516 const struct zl3073x_chan *chan; 1517 bool is_diff, is_enabled; 1518 const char *name; 1519 1520 chan = zl3073x_chan_state_get(zldev, zldpll->id); 1521 1522 if (dir == DPLL_PIN_DIRECTION_INPUT) { 1523 u8 ref_id = zl3073x_input_pin_ref_get(index); 1524 const struct zl3073x_ref *ref; 1525 1526 /* Skip the pin if the DPLL is running in NCO mode */ 1527 if (zl3073x_chan_mode_get(chan) == ZL_DPLL_MODE_REFSEL_MODE_NCO) 1528 return false; 1529 1530 name = "REF"; 1531 ref = zl3073x_ref_state_get(zldev, ref_id); 1532 is_diff = zl3073x_ref_is_diff(ref); 1533 is_enabled = zl3073x_ref_is_enabled(ref); 1534 } else { 1535 /* Output P&N pair shares single HW output */ 1536 u8 out = zl3073x_output_pin_out_get(index); 1537 1538 /* Skip the pin if it is connected to different DPLL channel */ 1539 if (zl3073x_dev_out_dpll_get(zldev, out) != zldpll->id) { 1540 dev_dbg(zldev->dev, 1541 "OUT%u is driven by different DPLL\n", out); 1542 1543 return false; 1544 } 1545 1546 name = "OUT"; 1547 is_diff = zl3073x_dev_out_is_diff(zldev, out); 1548 is_enabled = zl3073x_dev_output_pin_is_enabled(zldev, index); 1549 } 1550 1551 /* Skip N-pin if the corresponding input/output is differential */ 1552 if (is_diff && zl3073x_is_n_pin(index)) { 1553 dev_dbg(zldev->dev, "%s%u is differential, skipping N-pin\n", 1554 name, index / 2); 1555 1556 return false; 1557 } 1558 1559 /* Skip the pin if it is disabled */ 1560 if (!is_enabled) { 1561 dev_dbg(zldev->dev, "%s%u%c is disabled\n", name, index / 2, 1562 zl3073x_is_p_pin(index) ? 'P' : 'N'); 1563 1564 return false; 1565 } 1566 1567 return true; 1568 } 1569 1570 /** 1571 * zl3073x_dpll_pins_register - register all registerable DPLL pins 1572 * @zldpll: pointer to zl3073x_dpll structure 1573 * 1574 * Enumerates all possible input/output pins and registers all of them 1575 * that are registrable. 1576 * 1577 * Return: 0 on success, <0 on error 1578 */ 1579 static int 1580 zl3073x_dpll_pins_register(struct zl3073x_dpll *zldpll) 1581 { 1582 struct zl3073x_dpll_pin *pin; 1583 enum dpll_pin_direction dir; 1584 u8 id, index; 1585 int rc; 1586 1587 /* Process input pins */ 1588 for (index = 0; index < ZL3073X_NUM_PINS; index++) { 1589 /* First input pins and then output pins */ 1590 if (index < ZL3073X_NUM_INPUT_PINS) { 1591 id = index; 1592 dir = DPLL_PIN_DIRECTION_INPUT; 1593 } else { 1594 id = index - ZL3073X_NUM_INPUT_PINS; 1595 dir = DPLL_PIN_DIRECTION_OUTPUT; 1596 } 1597 1598 /* Check if the pin registrable to this DPLL */ 1599 if (!zl3073x_dpll_pin_is_registrable(zldpll, dir, id)) 1600 continue; 1601 1602 pin = zl3073x_dpll_pin_alloc(zldpll, dir, id); 1603 if (IS_ERR(pin)) { 1604 rc = PTR_ERR(pin); 1605 goto error; 1606 } 1607 1608 rc = zl3073x_dpll_pin_register(pin, index); 1609 if (rc) { 1610 zl3073x_dpll_pin_free(pin); 1611 goto error; 1612 } 1613 1614 list_add(&pin->list, &zldpll->pins); 1615 } 1616 1617 return 0; 1618 1619 error: 1620 zl3073x_dpll_pins_unregister(zldpll); 1621 1622 return rc; 1623 } 1624 1625 /** 1626 * zl3073x_dpll_device_register - register DPLL device 1627 * @zldpll: pointer to zl3073x_dpll structure 1628 * 1629 * Registers given DPLL device into DPLL sub-system. 1630 * 1631 * Return: 0 on success, <0 on error 1632 */ 1633 static int 1634 zl3073x_dpll_device_register(struct zl3073x_dpll *zldpll) 1635 { 1636 struct zl3073x_dev *zldev = zldpll->dev; 1637 int rc; 1638 1639 zldpll->ops = zl3073x_dpll_device_ops; 1640 if (zldev->info->flags & ZL3073X_FLAG_DIE_TEMP) 1641 zldpll->ops.temp_get = zl3073x_dpll_temp_get; 1642 1643 zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id, 1644 THIS_MODULE, &zldpll->tracker); 1645 if (IS_ERR(zldpll->dpll_dev)) { 1646 rc = PTR_ERR(zldpll->dpll_dev); 1647 zldpll->dpll_dev = NULL; 1648 1649 return rc; 1650 } 1651 1652 rc = dpll_device_register(zldpll->dpll_dev, 1653 zl3073x_prop_dpll_type_get(zldev, zldpll->id), 1654 &zldpll->ops, zldpll); 1655 if (rc) { 1656 dpll_device_put(zldpll->dpll_dev, &zldpll->tracker); 1657 zldpll->dpll_dev = NULL; 1658 } 1659 1660 return rc; 1661 } 1662 1663 /** 1664 * zl3073x_dpll_device_unregister - unregister DPLL device 1665 * @zldpll: pointer to zl3073x_dpll structure 1666 * 1667 * Unregisters given DPLL device from DPLL sub-system previously registered 1668 * by @zl3073x_dpll_device_register. 1669 */ 1670 static void 1671 zl3073x_dpll_device_unregister(struct zl3073x_dpll *zldpll) 1672 { 1673 struct dpll_device *dpll_dev = READ_ONCE(zldpll->dpll_dev); 1674 1675 WARN(!dpll_dev, "DPLL device is not registered\n"); 1676 1677 WRITE_ONCE(zldpll->dpll_dev, NULL); 1678 dpll_device_unregister(dpll_dev, &zldpll->ops, zldpll); 1679 dpll_device_put(dpll_dev, &zldpll->tracker); 1680 } 1681 1682 /** 1683 * zl3073x_dpll_pin_phase_offset_check - check for pin phase offset change 1684 * @pin: pin to check 1685 * 1686 * Check for the change of DPLL to connected pin phase offset change. 1687 * 1688 * Return: true on phase offset change, false otherwise 1689 */ 1690 static bool 1691 zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dpll_pin *pin) 1692 { 1693 struct zl3073x_dpll *zldpll = pin->dpll; 1694 struct zl3073x_dev *zldev = zldpll->dev; 1695 unsigned int reg; 1696 s64 phase_offset; 1697 u8 ref_id; 1698 int rc; 1699 1700 /* No phase offset if the ref monitor reports signal errors */ 1701 ref_id = zl3073x_input_pin_ref_get(pin->id); 1702 if (!zl3073x_dev_ref_is_status_ok(zldev, ref_id)) 1703 return false; 1704 1705 /* Select register to read phase offset value depending on pin and 1706 * phase monitor state: 1707 * 1) For connected pin use dpll_phase_err_data register 1708 * 2) For other pins use appropriate ref_phase register if the phase 1709 * monitor feature is enabled. 1710 */ 1711 if (pin->operstate == DPLL_PIN_OPERSTATE_ACTIVE) 1712 reg = ZL_REG_DPLL_PHASE_ERR_DATA(zldpll->id); 1713 else if (zldpll->phase_monitor) 1714 reg = ZL_REG_REF_PHASE(ref_id); 1715 else 1716 return false; 1717 1718 /* Read measured phase offset value */ 1719 rc = zl3073x_read_u48(zldev, reg, &phase_offset); 1720 if (rc) { 1721 dev_err(zldev->dev, "Failed to read ref phase offset: %pe\n", 1722 ERR_PTR(rc)); 1723 1724 return false; 1725 } 1726 1727 /* Convert to ps */ 1728 phase_offset = div_s64(sign_extend64(phase_offset, 47), 100); 1729 1730 /* Compare with previous value */ 1731 if (phase_offset != pin->phase_offset) { 1732 dev_dbg(zldev->dev, "%s phase offset changed: %lld -> %lld\n", 1733 pin->label, pin->phase_offset, phase_offset); 1734 pin->phase_offset = phase_offset; 1735 1736 return true; 1737 } 1738 1739 return false; 1740 } 1741 1742 /** 1743 * zl3073x_dpll_pin_ffo_check - check for FFO change on active pin 1744 * @pin: pin to check 1745 * 1746 * Return: true on change, false otherwise 1747 */ 1748 static bool 1749 zl3073x_dpll_pin_ffo_check(struct zl3073x_dpll_pin *pin) 1750 { 1751 struct zl3073x_dpll *zldpll = pin->dpll; 1752 struct zl3073x_dev *zldev = zldpll->dev; 1753 const struct zl3073x_chan *chan; 1754 s64 ffo; 1755 1756 if (pin->operstate != DPLL_PIN_OPERSTATE_ACTIVE) 1757 return false; 1758 1759 chan = zl3073x_chan_state_get(zldpll->dev, zldpll->id); 1760 ffo = mul_s64_u64_shr(zl3073x_chan_df_offset_get(chan), 1761 244140625, 36); 1762 1763 if (atomic64_xchg(&pin->freq_offset, ffo) != ffo) { 1764 dev_dbg(zldev->dev, "%s freq offset changed to: %lld\n", 1765 pin->label, ffo); 1766 return true; 1767 } 1768 1769 return false; 1770 } 1771 1772 /** 1773 * zl3073x_dpll_pin_measured_freq_check - check for pin measured frequency 1774 * change 1775 * @pin: pin to check 1776 * 1777 * Check for the given pin's measured frequency change. 1778 * 1779 * Return: true on measured frequency change, false otherwise 1780 */ 1781 static bool 1782 zl3073x_dpll_pin_measured_freq_check(struct zl3073x_dpll_pin *pin) 1783 { 1784 struct zl3073x_dpll *zldpll = pin->dpll; 1785 struct zl3073x_dev *zldev = zldpll->dev; 1786 const struct zl3073x_ref *ref; 1787 u8 ref_id; 1788 u32 freq; 1789 1790 if (!zldpll->dev->freq_monitor) 1791 return false; 1792 1793 ref_id = zl3073x_input_pin_ref_get(pin->id); 1794 ref = zl3073x_ref_state_get(zldev, ref_id); 1795 1796 freq = zl3073x_ref_meas_freq_get(ref); 1797 if (pin->measured_freq != freq) { 1798 dev_dbg(zldev->dev, "%s measured freq changed: %u -> %u\n", 1799 pin->label, pin->measured_freq, freq); 1800 pin->measured_freq = freq; 1801 1802 return true; 1803 } 1804 1805 return false; 1806 } 1807 1808 /** 1809 * zl3073x_dpll_changes_check - check for changes and send notifications 1810 * @zldpll: pointer to zl3073x_dpll structure 1811 * 1812 * Checks for changes on given DPLL device and its registered DPLL pins 1813 * and sends notifications about them. 1814 * 1815 * This function is periodically called from @zl3073x_dev_periodic_work. 1816 */ 1817 void 1818 zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll) 1819 { 1820 struct zl3073x_dev *zldev = zldpll->dev; 1821 enum dpll_lock_status lock_status; 1822 struct device *dev = zldev->dev; 1823 struct zl3073x_dpll_pin *pin; 1824 int rc; 1825 1826 zldpll->check_count++; 1827 1828 /* Get current lock status for the DPLL */ 1829 rc = zl3073x_dpll_lock_status_get(zldpll->dpll_dev, zldpll, 1830 &lock_status, NULL, NULL); 1831 if (rc) { 1832 dev_err(dev, "Failed to get DPLL%u lock status: %pe\n", 1833 zldpll->id, ERR_PTR(rc)); 1834 return; 1835 } 1836 1837 /* If lock status was changed then notify DPLL core */ 1838 if (zldpll->lock_status != lock_status) { 1839 zldpll->lock_status = lock_status; 1840 dpll_device_change_ntf(zldpll->dpll_dev); 1841 } 1842 1843 /* Update phase offset latch registers for this DPLL if the phase 1844 * offset monitor feature is enabled. 1845 */ 1846 if (zldpll->phase_monitor) { 1847 rc = zl3073x_ref_phase_offsets_update(zldev, zldpll->id); 1848 if (rc) { 1849 dev_err(zldev->dev, 1850 "Failed to update phase offsets: %pe\n", 1851 ERR_PTR(rc)); 1852 return; 1853 } 1854 } 1855 1856 list_for_each_entry(pin, &zldpll->pins, list) { 1857 enum dpll_pin_operstate operstate; 1858 bool pin_changed = false; 1859 1860 /* Output pins change checks are not necessary because output 1861 * states are constant. 1862 */ 1863 if (!zl3073x_dpll_is_input_pin(pin)) 1864 continue; 1865 1866 rc = zl3073x_dpll_ref_operstate_get(pin, &operstate); 1867 if (rc) { 1868 dev_err(dev, 1869 "Failed to get %s on DPLL%u oper state: %pe\n", 1870 pin->label, zldpll->id, ERR_PTR(rc)); 1871 return; 1872 } 1873 1874 if (operstate != pin->operstate) { 1875 dev_dbg(dev, "%s oper state changed: %u->%u\n", 1876 pin->label, pin->operstate, operstate); 1877 pin->operstate = operstate; 1878 pin_changed = true; 1879 } 1880 1881 /* Check for phase offset, ffo, and measured freq change 1882 * once per second. 1883 */ 1884 if (zldpll->check_count % 2 == 0) { 1885 if (zl3073x_dpll_pin_phase_offset_check(pin)) 1886 pin_changed = true; 1887 1888 if (zl3073x_dpll_pin_ffo_check(pin)) 1889 pin_changed = true; 1890 1891 if (zl3073x_dpll_pin_measured_freq_check(pin)) 1892 pin_changed = true; 1893 } 1894 1895 if (pin_changed) 1896 dpll_pin_change_ntf(pin->dpll_pin); 1897 } 1898 } 1899 1900 /** 1901 * zl3073x_dpll_init_fine_phase_adjust - do initial fine phase adjustments 1902 * @zldev: pointer to zl3073x device 1903 * 1904 * Performs initial fine phase adjustments needed per datasheet. 1905 * 1906 * Return: 0 on success, <0 on error 1907 */ 1908 int 1909 zl3073x_dpll_init_fine_phase_adjust(struct zl3073x_dev *zldev) 1910 { 1911 int rc; 1912 1913 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_MASK, 0x1f); 1914 if (rc) 1915 return rc; 1916 1917 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_INTVL, 0x01); 1918 if (rc) 1919 return rc; 1920 1921 rc = zl3073x_write_u16(zldev, ZL_REG_SYNTH_PHASE_SHIFT_DATA, 0xffff); 1922 if (rc) 1923 return rc; 1924 1925 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_CTRL, 0x01); 1926 if (rc) 1927 return rc; 1928 1929 return rc; 1930 } 1931 1932 /** 1933 * zl3073x_dpll_alloc - allocate DPLL device 1934 * @zldev: pointer to zl3073x device 1935 * @ch: DPLL channel number 1936 * 1937 * Allocates DPLL device structure for given DPLL channel. 1938 * 1939 * Return: pointer to DPLL device on success, error pointer on error 1940 */ 1941 struct zl3073x_dpll * 1942 zl3073x_dpll_alloc(struct zl3073x_dev *zldev, u8 ch) 1943 { 1944 struct zl3073x_dpll *zldpll; 1945 1946 zldpll = kzalloc_obj(*zldpll); 1947 if (!zldpll) 1948 return ERR_PTR(-ENOMEM); 1949 1950 zldpll->dev = zldev; 1951 zldpll->id = ch; 1952 INIT_LIST_HEAD(&zldpll->pins); 1953 1954 return zldpll; 1955 } 1956 1957 /** 1958 * zl3073x_dpll_free - free DPLL device 1959 * @zldpll: pointer to zl3073x_dpll structure 1960 * 1961 * Deallocates given DPLL device previously allocated by @zl3073x_dpll_alloc. 1962 */ 1963 void 1964 zl3073x_dpll_free(struct zl3073x_dpll *zldpll) 1965 { 1966 WARN(zldpll->dpll_dev, "DPLL device is still registered\n"); 1967 1968 kfree(zldpll); 1969 } 1970 1971 /** 1972 * zl3073x_dpll_ref_sync_pair_register - register ref_sync pairs for a pin 1973 * @pin: pointer to zl3073x_dpll_pin structure 1974 * 1975 * Iterates 'ref-sync-sources' phandles in the pin's firmware node and 1976 * registers each declared pairing. 1977 * 1978 * Return: 0 on success, <0 on error 1979 */ 1980 static int 1981 zl3073x_dpll_ref_sync_pair_register(struct zl3073x_dpll_pin *pin) 1982 { 1983 struct zl3073x_dev *zldev = pin->dpll->dev; 1984 struct fwnode_handle *fwnode; 1985 struct dpll_pin *sync_pin; 1986 dpll_tracker tracker; 1987 int n, rc; 1988 1989 for (n = 0; ; n++) { 1990 /* Get n'th ref-sync source */ 1991 fwnode = fwnode_find_reference(pin->fwnode, "ref-sync-sources", 1992 n); 1993 if (IS_ERR(fwnode)) { 1994 rc = PTR_ERR(fwnode); 1995 break; 1996 } 1997 1998 /* Find associated dpll pin */ 1999 sync_pin = fwnode_dpll_pin_find(fwnode, &tracker); 2000 fwnode_handle_put(fwnode); 2001 if (!sync_pin) { 2002 dev_warn(zldev->dev, "%s: ref-sync source %d not found", 2003 pin->label, n); 2004 continue; 2005 } 2006 2007 /* Register new ref-sync pair */ 2008 rc = dpll_pin_ref_sync_pair_add(pin->dpll_pin, sync_pin); 2009 dpll_pin_put(sync_pin, &tracker); 2010 2011 /* -EBUSY means pairing already exists from another DPLL's 2012 * registration. 2013 */ 2014 if (rc && rc != -EBUSY) { 2015 dev_err(zldev->dev, 2016 "%s: failed to add ref-sync source %d: %pe", 2017 pin->label, n, ERR_PTR(rc)); 2018 break; 2019 } 2020 } 2021 2022 return rc != -ENOENT ? rc : 0; 2023 } 2024 2025 /** 2026 * zl3073x_dpll_ref_sync_pairs_register - register ref_sync pairs for a DPLL 2027 * @zldpll: pointer to zl3073x_dpll structure 2028 * 2029 * Iterates all registered input pins of the given DPLL and establishes 2030 * ref_sync pairings declared by 'ref-sync-sources' phandles in the 2031 * device tree. 2032 * 2033 * Return: 0 on success, <0 on error 2034 */ 2035 static int 2036 zl3073x_dpll_ref_sync_pairs_register(struct zl3073x_dpll *zldpll) 2037 { 2038 struct zl3073x_dpll_pin *pin; 2039 int rc; 2040 2041 list_for_each_entry(pin, &zldpll->pins, list) { 2042 if (!zl3073x_dpll_is_input_pin(pin) || !pin->fwnode) 2043 continue; 2044 2045 rc = zl3073x_dpll_ref_sync_pair_register(pin); 2046 if (rc) 2047 return rc; 2048 } 2049 2050 return 0; 2051 } 2052 2053 /** 2054 * zl3073x_dpll_register - register DPLL device and all its pins 2055 * @zldpll: pointer to zl3073x_dpll structure 2056 * 2057 * Registers given DPLL device and all its pins into DPLL sub-system. 2058 * 2059 * Return: 0 on success, <0 on error 2060 */ 2061 int 2062 zl3073x_dpll_register(struct zl3073x_dpll *zldpll) 2063 { 2064 int rc; 2065 2066 rc = zl3073x_dpll_device_register(zldpll); 2067 if (rc) 2068 return rc; 2069 2070 rc = zl3073x_dpll_pins_register(zldpll); 2071 if (rc) { 2072 zl3073x_dpll_device_unregister(zldpll); 2073 return rc; 2074 } 2075 2076 rc = zl3073x_dpll_ref_sync_pairs_register(zldpll); 2077 if (rc) { 2078 zl3073x_dpll_pins_unregister(zldpll); 2079 zl3073x_dpll_device_unregister(zldpll); 2080 return rc; 2081 } 2082 2083 return 0; 2084 } 2085 2086 /** 2087 * zl3073x_dpll_unregister - unregister DPLL device and its pins 2088 * @zldpll: pointer to zl3073x_dpll structure 2089 * 2090 * Unregisters given DPLL device and all its pins from DPLL sub-system 2091 * previously registered by @zl3073x_dpll_register. 2092 */ 2093 void 2094 zl3073x_dpll_unregister(struct zl3073x_dpll *zldpll) 2095 { 2096 /* Unregister all pins and dpll */ 2097 zl3073x_dpll_pins_unregister(zldpll); 2098 zl3073x_dpll_device_unregister(zldpll); 2099 } 2100