1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 8 #ifndef __QCOM_CLK_ALPHA_PLL_H__ 9 #define __QCOM_CLK_ALPHA_PLL_H__ 10 11 #include <linux/clk-provider.h> 12 #include "clk-regmap.h" 13 14 /* Alpha PLL types */ 15 enum { 16 CLK_ALPHA_PLL_TYPE_DEFAULT, 17 CLK_ALPHA_PLL_TYPE_HUAYRA, 18 CLK_ALPHA_PLL_TYPE_HUAYRA_APSS, 19 CLK_ALPHA_PLL_TYPE_HUAYRA_2290, 20 CLK_ALPHA_PLL_TYPE_BRAMMO, 21 CLK_ALPHA_PLL_TYPE_FABIA, 22 CLK_ALPHA_PLL_TYPE_TRION, 23 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, 24 CLK_ALPHA_PLL_TYPE_AGERA, 25 CLK_ALPHA_PLL_TYPE_ZONDA, 26 CLK_ALPHA_PLL_TYPE_REGERA = CLK_ALPHA_PLL_TYPE_ZONDA, 27 CLK_ALPHA_PLL_TYPE_ZONDA_OLE, 28 CLK_ALPHA_PLL_TYPE_LUCID_EVO, 29 CLK_ALPHA_PLL_TYPE_LUCID_OLE, 30 CLK_ALPHA_PLL_TYPE_PONGO_ELU, 31 CLK_ALPHA_PLL_TYPE_PONGO_EKO_T = CLK_ALPHA_PLL_TYPE_PONGO_ELU, 32 CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, 33 CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T = CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, 34 CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T = CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, 35 CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, 36 CLK_ALPHA_PLL_TYPE_RIVIAN_ELU, 37 CLK_ALPHA_PLL_TYPE_RIVIAN_EKO_T = CLK_ALPHA_PLL_TYPE_RIVIAN_ELU, 38 CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, 39 CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, 40 CLK_ALPHA_PLL_TYPE_STROMER, 41 CLK_ALPHA_PLL_TYPE_STROMER_PLUS, 42 CLK_ALPHA_PLL_TYPE_NSS_HUAYRA, 43 CLK_ALPHA_PLL_TYPE_MAX, 44 }; 45 46 enum { 47 PLL_OFF_L_VAL, 48 PLL_OFF_CAL_L_VAL, 49 PLL_OFF_ALPHA_VAL, 50 PLL_OFF_ALPHA_VAL_U, 51 PLL_OFF_USER_CTL, 52 PLL_OFF_USER_CTL_U, 53 PLL_OFF_USER_CTL_U1, 54 PLL_OFF_CONFIG_CTL, 55 PLL_OFF_CONFIG_CTL_U, 56 PLL_OFF_CONFIG_CTL_U1, 57 PLL_OFF_CONFIG_CTL_U2, 58 PLL_OFF_TEST_CTL, 59 PLL_OFF_TEST_CTL_U, 60 PLL_OFF_TEST_CTL_U1, 61 PLL_OFF_TEST_CTL_U2, 62 PLL_OFF_TEST_CTL_U3, 63 PLL_OFF_STATE, 64 PLL_OFF_STATUS, 65 PLL_OFF_OPMODE, 66 PLL_OFF_FRAC, 67 PLL_OFF_CAL_VAL, 68 PLL_OFF_MAX_REGS 69 }; 70 71 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 72 73 struct pll_vco { 74 unsigned long min_freq; 75 unsigned long max_freq; 76 u32 val; 77 }; 78 79 #define VCO(a, b, c) { \ 80 .val = a,\ 81 .min_freq = b,\ 82 .max_freq = c,\ 83 } 84 85 /** 86 * struct clk_alpha_pll - phase locked loop (PLL) 87 * @offset: base address of registers 88 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 89 * @config: array of pll settings 90 * @vco_table: array of VCO settings 91 * @num_vco: number of VCO settings in @vco_table 92 * @flags: bitmask to indicate features supported by the hardware 93 * @clkr: regmap clock handle 94 */ 95 struct clk_alpha_pll { 96 u32 offset; 97 const u8 *regs; 98 99 const struct alpha_pll_config *config; 100 const struct pll_vco *vco_table; 101 size_t num_vco; 102 #define SUPPORTS_OFFLINE_REQ BIT(0) 103 #define SUPPORTS_FSM_MODE BIT(2) 104 #define SUPPORTS_DYNAMIC_UPDATE BIT(3) 105 #define SUPPORTS_FSM_LEGACY_MODE BIT(4) 106 u8 flags; 107 108 struct clk_regmap clkr; 109 }; 110 111 /** 112 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 113 * @offset: base address of registers 114 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 115 * @width: width of post-divider 116 * @post_div_shift: shift to differentiate between odd & even post-divider 117 * @post_div_table: table with PLL odd and even post-divider settings 118 * @num_post_div: Number of PLL post-divider settings 119 * 120 * @clkr: regmap clock handle 121 */ 122 struct clk_alpha_pll_postdiv { 123 u32 offset; 124 u8 width; 125 const u8 *regs; 126 127 struct clk_regmap clkr; 128 int post_div_shift; 129 const struct clk_div_table *post_div_table; 130 size_t num_post_div; 131 }; 132 133 struct alpha_pll_config { 134 u32 l; 135 u32 cal_l; 136 u32 alpha; 137 u32 alpha_hi; 138 u32 config_ctl_val; 139 u32 config_ctl_hi_val; 140 u32 config_ctl_hi1_val; 141 u32 config_ctl_hi2_val; 142 u32 user_ctl_val; 143 u32 user_ctl_hi_val; 144 u32 user_ctl_hi1_val; 145 u32 test_ctl_val; 146 u32 test_ctl_mask; 147 u32 test_ctl_hi_val; 148 u32 test_ctl_hi_mask; 149 u32 test_ctl_hi1_val; 150 u32 test_ctl_hi2_val; 151 u32 test_ctl_hi3_val; 152 u32 main_output_mask; 153 u32 aux_output_mask; 154 u32 aux2_output_mask; 155 u32 early_output_mask; 156 u32 alpha_en_mask; 157 u32 alpha_mode_mask; 158 u32 pre_div_val; 159 u32 pre_div_mask; 160 u32 post_div_val; 161 u32 post_div_mask; 162 u32 vco_val; 163 u32 vco_mask; 164 u32 status_val; 165 u32 status_mask; 166 u32 lock_det; 167 }; 168 169 extern const struct clk_ops clk_alpha_pll_ops; 170 extern const struct clk_ops clk_alpha_pll_fixed_ops; 171 extern const struct clk_ops clk_alpha_pll_hwfsm_ops; 172 extern const struct clk_ops clk_alpha_pll_postdiv_ops; 173 extern const struct clk_ops clk_alpha_pll_huayra_ops; 174 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 175 extern const struct clk_ops clk_alpha_pll_stromer_ops; 176 extern const struct clk_ops clk_alpha_pll_stromer_plus_ops; 177 178 extern const struct clk_ops clk_alpha_pll_fabia_ops; 179 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; 180 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; 181 182 extern const struct clk_ops clk_alpha_pll_trion_ops; 183 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops; 184 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops; 185 186 extern const struct clk_ops clk_alpha_pll_lucid_ops; 187 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops 188 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; 189 extern const struct clk_ops clk_alpha_pll_agera_ops; 190 191 extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops; 192 extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops; 193 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; 194 195 extern const struct clk_ops clk_alpha_pll_zonda_ops; 196 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops 197 #define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops 198 199 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; 200 #define clk_alpha_pll_taycan_elu_ops clk_alpha_pll_lucid_evo_ops 201 #define clk_alpha_pll_taycan_eko_t_ops clk_alpha_pll_lucid_evo_ops 202 #define clk_alpha_pll_taycan_eha_t_ops clk_alpha_pll_lucid_evo_ops 203 extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; 204 #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops 205 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; 206 #define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops 207 #define clk_alpha_pll_fixed_taycan_elu_ops clk_alpha_pll_fixed_lucid_evo_ops 208 #define clk_alpha_pll_fixed_taycan_eko_t_ops clk_alpha_pll_fixed_lucid_evo_ops 209 #define clk_alpha_pll_fixed_taycan_eha_t_ops clk_alpha_pll_fixed_lucid_evo_ops 210 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; 211 #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops 212 #define clk_alpha_pll_postdiv_taycan_elu_ops clk_alpha_pll_postdiv_lucid_evo_ops 213 #define clk_alpha_pll_postdiv_taycan_eko_t_ops clk_alpha_pll_postdiv_lucid_evo_ops 214 #define clk_alpha_pll_postdiv_taycan_eha_t_ops clk_alpha_pll_postdiv_lucid_evo_ops 215 216 extern const struct clk_ops clk_alpha_pll_pongo_elu_ops; 217 #define clk_alpha_pll_pongo_eko_t_ops clk_alpha_pll_pongo_elu_ops 218 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; 219 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops 220 #define clk_alpha_pll_rivian_elu_ops clk_alpha_pll_rivian_evo_ops 221 #define clk_alpha_pll_rivian_eko_t_ops clk_alpha_pll_rivian_evo_ops 222 223 extern const struct clk_ops clk_alpha_pll_regera_ops; 224 extern const struct clk_ops clk_alpha_pll_slew_ops; 225 226 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 227 const struct alpha_pll_config *config); 228 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 229 const struct alpha_pll_config *config); 230 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 231 const struct alpha_pll_config *config); 232 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 233 const struct alpha_pll_config *config); 234 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 235 const struct alpha_pll_config *config); 236 #define clk_lucid_pll_configure(pll, regmap, config) \ 237 clk_trion_pll_configure(pll, regmap, config) 238 239 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 240 const struct alpha_pll_config *config); 241 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 242 const struct alpha_pll_config *config); 243 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 244 const struct alpha_pll_config *config); 245 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 246 const struct alpha_pll_config *config); 247 void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 248 const struct alpha_pll_config *config); 249 #define clk_taycan_elu_pll_configure(pll, regmap, config) \ 250 clk_lucid_evo_pll_configure(pll, regmap, config) 251 #define clk_taycan_eko_t_pll_configure(pll, regmap, config) \ 252 clk_lucid_evo_pll_configure(pll, regmap, config) 253 #define clk_taycan_eha_t_pll_configure(pll, regmap, config) \ 254 clk_lucid_evo_pll_configure(pll, regmap, config) 255 256 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 257 const struct alpha_pll_config *config); 258 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 259 const struct alpha_pll_config *config); 260 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 261 const struct alpha_pll_config *config); 262 void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap); 263 264 #endif 265