1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/i2c.h> 11 #include <linux/kernel.h> 12 #include <linux/math64.h> 13 #include <linux/media-bus-format.h> 14 #include <linux/minmax.h> 15 #include <linux/module.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/slab.h> 19 #include <linux/units.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_drv.h> 23 #include <drm/drm_mipi_dsi.h> 24 #include <drm/drm_of.h> 25 #include <video/mipi_display.h> 26 #include <video/videomode.h> 27 28 /* Global (16-bit addressable) */ 29 #define TC358768_CHIPID 0x0000 30 #define TC358768_SYSCTL 0x0002 31 #define TC358768_CONFCTL 0x0004 32 #define TC358768_VSDLY 0x0006 33 #define TC358768_DATAFMT 0x0008 34 #define TC358768_GPIOEN 0x000E 35 #define TC358768_GPIODIR 0x0010 36 #define TC358768_GPIOIN 0x0012 37 #define TC358768_GPIOOUT 0x0014 38 #define TC358768_PLLCTL0 0x0016 39 #define TC358768_PLLCTL1 0x0018 40 #define TC358768_CMDBYTE 0x0022 41 #define TC358768_PP_MISC 0x0032 42 #define TC358768_DSITX_DT 0x0050 43 #define TC358768_FIFOSTATUS 0x00F8 44 45 /* Debug (16-bit addressable) */ 46 #define TC358768_VBUFCTRL 0x00E0 47 #define TC358768_VBUFCTRL_VBUF_EN BIT(15) 48 #define TC358768_VBUFCTRL_TX_EN BIT(14) 49 #define TC358768_VBUFCTRL_MASK BIT(13) 50 #define TC358768_DBG_WIDTH 0x00E2 51 #define TC358768_DBG_VBLANK 0x00E4 52 #define TC358768_DBG_DATA 0x00E8 53 54 /* TX PHY (32-bit addressable) */ 55 #define TC358768_CLW_DPHYCONTTX 0x0100 56 #define TC358768_D0W_DPHYCONTTX 0x0104 57 #define TC358768_D1W_DPHYCONTTX 0x0108 58 #define TC358768_D2W_DPHYCONTTX 0x010C 59 #define TC358768_D3W_DPHYCONTTX 0x0110 60 #define TC358768_CLW_CNTRL 0x0140 61 #define TC358768_D0W_CNTRL 0x0144 62 #define TC358768_D1W_CNTRL 0x0148 63 #define TC358768_D2W_CNTRL 0x014C 64 #define TC358768_D3W_CNTRL 0x0150 65 66 /* TX PPI (32-bit addressable) */ 67 #define TC358768_STARTCNTRL 0x0204 68 #define TC358768_DSITXSTATUS 0x0208 69 #define TC358768_LINEINITCNT 0x0210 70 #define TC358768_LPTXTIMECNT 0x0214 71 #define TC358768_TCLK_HEADERCNT 0x0218 72 #define TC358768_TCLK_TRAILCNT 0x021C 73 #define TC358768_THS_HEADERCNT 0x0220 74 #define TC358768_TWAKEUP 0x0224 75 #define TC358768_TCLK_POSTCNT 0x0228 76 #define TC358768_THS_TRAILCNT 0x022C 77 #define TC358768_HSTXVREGCNT 0x0230 78 #define TC358768_HSTXVREGEN 0x0234 79 #define TC358768_TXOPTIONCNTRL 0x0238 80 #define TC358768_BTACNTRL1 0x023C 81 82 /* TX CTRL (32-bit addressable) */ 83 #define TC358768_DSI_CONTROL 0x040C 84 #define TC358768_DSI_STATUS 0x0410 85 #define TC358768_DSI_INT 0x0414 86 #define TC358768_DSI_INT_ENA 0x0418 87 #define TC358768_DSICMD_RDFIFO 0x0430 88 #define TC358768_DSI_ACKERR 0x0434 89 #define TC358768_DSI_ACKERR_INTENA 0x0438 90 #define TC358768_DSI_ACKERR_HALT 0x043c 91 #define TC358768_DSI_RXERR 0x0440 92 #define TC358768_DSI_RXERR_INTENA 0x0444 93 #define TC358768_DSI_RXERR_HALT 0x0448 94 #define TC358768_DSI_ERR 0x044C 95 #define TC358768_DSI_ERR_INTENA 0x0450 96 #define TC358768_DSI_ERR_HALT 0x0454 97 #define TC358768_DSI_CONFW 0x0500 98 #define TC358768_DSI_LPCMD 0x0500 99 #define TC358768_DSI_RESET 0x0504 100 #define TC358768_DSI_INT_CLR 0x050C 101 #define TC358768_DSI_START 0x0518 102 103 /* DSITX CTRL (16-bit addressable) */ 104 #define TC358768_DSICMD_TX 0x0600 105 #define TC358768_DSICMD_TYPE 0x0602 106 #define TC358768_DSICMD_WC 0x0604 107 #define TC358768_DSICMD_WD0 0x0610 108 #define TC358768_DSICMD_WD1 0x0612 109 #define TC358768_DSICMD_WD2 0x0614 110 #define TC358768_DSICMD_WD3 0x0616 111 #define TC358768_DSI_EVENT 0x0620 112 #define TC358768_DSI_VSW 0x0622 113 #define TC358768_DSI_VBPR 0x0624 114 #define TC358768_DSI_VACT 0x0626 115 #define TC358768_DSI_HSW 0x0628 116 #define TC358768_DSI_HBPR 0x062A 117 #define TC358768_DSI_HACT 0x062C 118 119 /* TC358768_DSI_CONTROL (0x040C) register */ 120 #define TC358768_DSI_CONTROL_DSI_MODE BIT(15) 121 #define TC358768_DSI_CONTROL_TXMD BIT(7) 122 #define TC358768_DSI_CONTROL_HSCKMD BIT(5) 123 #define TC358768_DSI_CONTROL_EOTDIS BIT(0) 124 125 /* TC358768_DSI_CONFW (0x0500) register */ 126 #define TC358768_DSI_CONFW_MODE_SET (5 << 29) 127 #define TC358768_DSI_CONFW_MODE_CLR (6 << 29) 128 #define TC358768_DSI_CONFW_ADDR(x) ((x) << 24) 129 130 /* TC358768_DSICMD_TX (0x0600) register */ 131 #define TC358768_DSI_CMDTX_DC_START BIT(0) 132 133 static const char * const tc358768_supplies[] = { 134 "vddc", "vddmipi", "vddio" 135 }; 136 137 struct tc358768_dsi_output { 138 struct mipi_dsi_device *dev; 139 struct drm_bridge *bridge; 140 }; 141 142 struct tc358768_priv { 143 struct device *dev; 144 struct regmap *regmap; 145 struct gpio_desc *reset_gpio; 146 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)]; 147 struct clk *refclk; 148 int enabled; 149 int error; 150 151 struct mipi_dsi_host dsi_host; 152 struct drm_bridge bridge; 153 struct tc358768_dsi_output output; 154 155 u32 pd_lines; /* number of Parallel Port Input Data Lines */ 156 u32 dsi_lanes; /* number of DSI Lanes */ 157 u32 dsi_bpp; /* number of Bits Per Pixel over DSI */ 158 159 /* Parameters for PLL programming */ 160 u32 fbd; /* PLL feedback divider */ 161 u32 prd; /* PLL input divider */ 162 u32 frs; /* PLL Freqency range for HSCK (post divider) */ 163 164 u32 dsiclk; /* pll_clk / 2 */ 165 u32 pclk; /* incoming pclk rate */ 166 }; 167 168 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host 169 *host) 170 { 171 return container_of(host, struct tc358768_priv, dsi_host); 172 } 173 174 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge 175 *bridge) 176 { 177 return container_of(bridge, struct tc358768_priv, bridge); 178 } 179 180 static int tc358768_clear_error(struct tc358768_priv *priv) 181 { 182 int ret = priv->error; 183 184 priv->error = 0; 185 return ret; 186 } 187 188 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val) 189 { 190 /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ 191 int tmpval = val; 192 size_t count = 2; 193 194 if (priv->error) 195 return; 196 197 /* 16-bit register? */ 198 if (reg < 0x100 || reg >= 0x600) 199 count = 1; 200 201 priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count); 202 } 203 204 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val) 205 { 206 size_t count = 2; 207 208 if (priv->error) 209 return; 210 211 /* 16-bit register? */ 212 if (reg < 0x100 || reg >= 0x600) { 213 *val = 0; 214 count = 1; 215 } 216 217 priv->error = regmap_bulk_read(priv->regmap, reg, val, count); 218 } 219 220 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask, 221 u32 val) 222 { 223 u32 tmp, orig; 224 225 tc358768_read(priv, reg, &orig); 226 227 if (priv->error) 228 return; 229 230 tmp = orig & ~mask; 231 tmp |= val & mask; 232 if (tmp != orig) 233 tc358768_write(priv, reg, tmp); 234 } 235 236 static void tc358768_confw_update_bits(struct tc358768_priv *priv, u16 reg, 237 u16 mask, u16 val) 238 { 239 u8 confw_addr; 240 u32 confw_val; 241 242 switch (reg) { 243 case TC358768_DSI_CONTROL: 244 confw_addr = 0x3; 245 break; 246 default: 247 priv->error = -EINVAL; 248 return; 249 } 250 251 if (mask != val) { 252 confw_val = TC358768_DSI_CONFW_MODE_CLR | 253 TC358768_DSI_CONFW_ADDR(confw_addr) | 254 mask; 255 tc358768_write(priv, TC358768_DSI_CONFW, confw_val); 256 } 257 258 if (val & mask) { 259 confw_val = TC358768_DSI_CONFW_MODE_SET | 260 TC358768_DSI_CONFW_ADDR(confw_addr) | 261 (val & mask); 262 tc358768_write(priv, TC358768_DSI_CONFW, confw_val); 263 } 264 } 265 266 static void tc358768_dsicmd_tx(struct tc358768_priv *priv) 267 { 268 u32 val; 269 270 /* start transfer */ 271 tc358768_write(priv, TC358768_DSICMD_TX, TC358768_DSI_CMDTX_DC_START); 272 if (priv->error) 273 return; 274 275 /* wait transfer completion */ 276 priv->error = regmap_read_poll_timeout(priv->regmap, TC358768_DSICMD_TX, val, 277 (val & TC358768_DSI_CMDTX_DC_START) == 0, 278 100, 100000); 279 } 280 281 static int tc358768_sw_reset(struct tc358768_priv *priv) 282 { 283 /* Assert Reset */ 284 tc358768_write(priv, TC358768_SYSCTL, 1); 285 /* Release Reset, Exit Sleep */ 286 tc358768_write(priv, TC358768_SYSCTL, 0); 287 288 return tc358768_clear_error(priv); 289 } 290 291 static void tc358768_hw_enable(struct tc358768_priv *priv) 292 { 293 int ret; 294 295 if (priv->enabled) 296 return; 297 298 ret = clk_prepare_enable(priv->refclk); 299 if (ret < 0) 300 dev_err(priv->dev, "error enabling refclk (%d)\n", ret); 301 302 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 303 if (ret < 0) 304 dev_err(priv->dev, "error enabling regulators (%d)\n", ret); 305 306 if (priv->reset_gpio) 307 usleep_range(200, 300); 308 309 /* 310 * The RESX is active low (GPIO_ACTIVE_LOW). 311 * DEASSERT (value = 0) the reset_gpio to enable the chip 312 */ 313 gpiod_set_value_cansleep(priv->reset_gpio, 0); 314 315 /* wait for encoder clocks to stabilize */ 316 usleep_range(1000, 2000); 317 318 priv->enabled = true; 319 } 320 321 static void tc358768_hw_disable(struct tc358768_priv *priv) 322 { 323 int ret; 324 325 if (!priv->enabled) 326 return; 327 328 /* 329 * The RESX is active low (GPIO_ACTIVE_LOW). 330 * ASSERT (value = 1) the reset_gpio to disable the chip 331 */ 332 gpiod_set_value_cansleep(priv->reset_gpio, 1); 333 334 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 335 priv->supplies); 336 if (ret < 0) 337 dev_err(priv->dev, "error disabling regulators (%d)\n", ret); 338 339 clk_disable_unprepare(priv->refclk); 340 341 priv->enabled = false; 342 } 343 344 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk) 345 { 346 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp); 347 } 348 349 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk) 350 { 351 return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes); 352 } 353 354 static int tc358768_calc_pll(struct tc358768_priv *priv, 355 const struct drm_display_mode *mode, 356 bool verify_only) 357 { 358 static const u32 frs_limits[] = { 359 1000000000, 360 500000000, 361 250000000, 362 125000000, 363 62500000 364 }; 365 unsigned long refclk; 366 u32 prd, target_pll, i, max_pll, min_pll; 367 u32 frs, best_diff, best_pll, best_prd, best_fbd; 368 369 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000); 370 371 /* pll_clk = RefClk * FBD / PRD * (1 / (2^FRS)) */ 372 373 for (i = 0; i < ARRAY_SIZE(frs_limits); i++) 374 if (target_pll >= frs_limits[i]) 375 break; 376 377 if (i == ARRAY_SIZE(frs_limits) || i == 0) 378 return -EINVAL; 379 380 frs = i - 1; 381 max_pll = frs_limits[i - 1]; 382 min_pll = frs_limits[i]; 383 384 refclk = clk_get_rate(priv->refclk); 385 386 best_diff = UINT_MAX; 387 best_pll = 0; 388 best_prd = 0; 389 best_fbd = 0; 390 391 for (prd = 1; prd <= 16; ++prd) { 392 u32 divisor = prd * (1 << frs); 393 u32 fbd; 394 395 for (fbd = 1; fbd <= 512; ++fbd) { 396 u32 pll, diff, pll_in; 397 398 pll = (u32)div_u64((u64)refclk * fbd, divisor); 399 400 if (pll >= max_pll || pll < min_pll) 401 continue; 402 403 pll_in = (u32)div_u64((u64)refclk, prd); 404 if (pll_in < 4000000) 405 continue; 406 407 diff = max(pll, target_pll) - min(pll, target_pll); 408 409 if (diff < best_diff) { 410 best_diff = diff; 411 best_pll = pll; 412 best_prd = prd; 413 best_fbd = fbd; 414 415 if (best_diff == 0) 416 goto found; 417 } 418 } 419 } 420 421 if (best_diff == UINT_MAX) { 422 dev_err(priv->dev, "could not find suitable PLL setup\n"); 423 return -EINVAL; 424 } 425 426 found: 427 if (verify_only) 428 return 0; 429 430 priv->fbd = best_fbd; 431 priv->prd = best_prd; 432 priv->frs = frs; 433 priv->dsiclk = best_pll / 2; 434 priv->pclk = mode->clock * 1000; 435 436 return 0; 437 } 438 439 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host, 440 struct mipi_dsi_device *dev) 441 { 442 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 443 struct drm_bridge *bridge; 444 struct device_node *ep; 445 int ret; 446 447 if (dev->lanes > 4) { 448 dev_err(priv->dev, "unsupported number of data lanes(%u)\n", 449 dev->lanes); 450 return -EINVAL; 451 } 452 453 /* 454 * tc358768 supports both Video and Pulse mode, but the driver only 455 * implements Video (event) mode currently 456 */ 457 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) { 458 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n"); 459 return -ENOTSUPP; 460 } 461 462 /* 463 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only 464 * RGB888 is verified. 465 */ 466 if (dev->format != MIPI_DSI_FMT_RGB888) { 467 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n"); 468 return -ENOTSUPP; 469 } 470 471 bridge = of_drm_get_bridge_by_endpoint(host->dev->of_node, 1, 0); 472 if (IS_ERR(bridge)) 473 return PTR_ERR(bridge); 474 475 bridge->type = DRM_MODE_CONNECTOR_DSI; 476 bridge->pre_enable_prev_first = true; 477 478 priv->output.dev = dev; 479 priv->output.bridge = bridge; 480 481 priv->dsi_lanes = dev->lanes; 482 priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format); 483 484 /* get input ep (port0/endpoint0) */ 485 ret = -EINVAL; 486 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0); 487 if (ep) { 488 ret = of_property_read_u32(ep, "bus-width", &priv->pd_lines); 489 if (ret) 490 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines); 491 492 of_node_put(ep); 493 } 494 495 if (ret) 496 priv->pd_lines = priv->dsi_bpp; 497 498 drm_bridge_add(&priv->bridge); 499 500 return 0; 501 } 502 503 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host, 504 struct mipi_dsi_device *dev) 505 { 506 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 507 508 drm_bridge_remove(&priv->bridge); 509 drm_bridge_put(priv->output.bridge); 510 511 return 0; 512 } 513 514 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host, 515 const struct mipi_dsi_msg *msg) 516 { 517 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 518 struct mipi_dsi_packet packet; 519 int ret; 520 521 if (!priv->enabled) { 522 dev_err(priv->dev, "Bridge is not enabled\n"); 523 return -ENODEV; 524 } 525 526 if (msg->rx_len) { 527 dev_warn(priv->dev, "MIPI rx is not supported\n"); 528 return -ENOTSUPP; 529 } 530 531 if (msg->tx_len > 1024) { 532 dev_warn(priv->dev, "Maximum 1024 byte MIPI tx is supported\n"); 533 return -EINVAL; 534 } 535 536 if (msg->tx_len > 8) { 537 u32 confctl; 538 539 tc358768_read(priv, TC358768_CONFCTL, &confctl); 540 541 if (confctl & BIT(6)) { 542 dev_warn(priv->dev, 543 "Video is currently active. Unable to transmit long command\n"); 544 return -EBUSY; 545 } 546 } 547 548 ret = mipi_dsi_create_packet(&packet, msg); 549 if (ret) 550 return ret; 551 552 if (mipi_dsi_packet_format_is_short(msg->type)) { 553 tc358768_write(priv, TC358768_DSICMD_TYPE, 554 (0x10 << 8) | (packet.header[0] & 0x3f)); 555 tc358768_write(priv, TC358768_DSICMD_WC, 0); 556 tc358768_write(priv, TC358768_DSICMD_WD0, 557 (packet.header[2] << 8) | packet.header[1]); 558 tc358768_dsicmd_tx(priv); 559 } else if (packet.payload_length <= 8) { 560 tc358768_write(priv, TC358768_DSICMD_TYPE, 561 (0x40 << 8) | (packet.header[0] & 0x3f)); 562 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length); 563 564 for (int i = 0; i < packet.payload_length; i += 2) { 565 u16 val = packet.payload[i]; 566 567 if (i + 1 < packet.payload_length) 568 val |= packet.payload[i + 1] << 8; 569 tc358768_write(priv, TC358768_DSICMD_WD0 + i, val); 570 } 571 572 tc358768_dsicmd_tx(priv); 573 } else { 574 unsigned long tx_sleep_us; 575 size_t len; 576 577 /* For packets over 8 bytes we need to use the video buffer */ 578 tc358768_write(priv, TC358768_DATAFMT, BIT(0)); /* txdt_en */ 579 tc358768_write(priv, TC358768_DSITX_DT, packet.header[0] & 0x3f); 580 tc358768_write(priv, TC358768_CMDBYTE, packet.payload_length); 581 tc358768_write(priv, TC358768_VBUFCTRL, TC358768_VBUFCTRL_VBUF_EN); 582 583 /* 584 * Write the payload in 2-byte chunks, and pad with zeroes to 585 * align to 4 bytes. 586 */ 587 len = ALIGN(packet.payload_length, 4); 588 589 for (int i = 0; i < len; i += 2) { 590 u16 val = 0; 591 592 if (i < packet.payload_length) 593 val |= packet.payload[i]; 594 if (i + 1 < packet.payload_length) 595 val |= packet.payload[i + 1] << 8; 596 597 tc358768_write(priv, TC358768_DBG_DATA, val); 598 } 599 600 /* Start transmission */ 601 tc358768_write(priv, TC358768_VBUFCTRL, 602 TC358768_VBUFCTRL_VBUF_EN | 603 TC358768_VBUFCTRL_TX_EN | 604 TC358768_VBUFCTRL_MASK); 605 606 /* 607 * The TC358768 spec says to wait until the transmission has 608 * been finished, estimating the sleep time based on the payload 609 * and clock rates. We use a simple safe estimate of 2us per 610 * byte (LP mode transmission). 611 */ 612 tx_sleep_us = packet.payload_length * 2; 613 usleep_range(tx_sleep_us, tx_sleep_us * 2); 614 615 tc358768_write(priv, TC358768_VBUFCTRL, TC358768_VBUFCTRL_MASK); 616 tc358768_write(priv, TC358768_VBUFCTRL, 0); /* Stop transmission */ 617 } 618 619 ret = tc358768_clear_error(priv); 620 if (ret) 621 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 622 else 623 ret = packet.size; 624 625 return ret; 626 } 627 628 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = { 629 .attach = tc358768_dsi_host_attach, 630 .detach = tc358768_dsi_host_detach, 631 .transfer = tc358768_dsi_host_transfer, 632 }; 633 634 static int tc358768_bridge_attach(struct drm_bridge *bridge, 635 struct drm_encoder *encoder, 636 enum drm_bridge_attach_flags flags) 637 { 638 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 639 640 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) { 641 dev_err(priv->dev, "needs atomic updates support\n"); 642 return -ENOTSUPP; 643 } 644 645 return drm_bridge_attach(encoder, priv->output.bridge, bridge, 646 flags); 647 } 648 649 static enum drm_mode_status 650 tc358768_bridge_mode_valid(struct drm_bridge *bridge, 651 const struct drm_display_info *info, 652 const struct drm_display_mode *mode) 653 { 654 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 655 656 if (tc358768_calc_pll(priv, mode, true)) 657 return MODE_CLOCK_RANGE; 658 659 return MODE_OK; 660 } 661 662 static void tc358768_bridge_atomic_disable(struct drm_bridge *bridge, 663 struct drm_atomic_commit *state) 664 { 665 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 666 int ret; 667 668 /* set FrmStop */ 669 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15)); 670 671 /* wait at least for one frame */ 672 msleep(50); 673 674 /* clear PP_en */ 675 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0); 676 677 /* set RstPtr */ 678 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14)); 679 680 ret = tc358768_clear_error(priv); 681 if (ret) 682 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 683 } 684 685 static void tc358768_bridge_atomic_post_disable(struct drm_bridge *bridge, 686 struct drm_atomic_commit *state) 687 { 688 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 689 690 tc358768_hw_disable(priv); 691 } 692 693 static int tc358768_setup_pll(struct tc358768_priv *priv, 694 const struct drm_display_mode *mode) 695 { 696 u32 fbd, prd, frs; 697 int ret; 698 699 ret = tc358768_calc_pll(priv, mode, false); 700 if (ret) { 701 dev_err(priv->dev, "PLL calculation failed: %d\n", ret); 702 return ret; 703 } 704 705 fbd = priv->fbd; 706 prd = priv->prd; 707 frs = priv->frs; 708 709 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n", 710 clk_get_rate(priv->refclk), fbd, prd, frs); 711 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n", 712 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); 713 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n", 714 tc358768_pll_to_pclk(priv, priv->dsiclk * 2), 715 mode->clock * 1000); 716 717 /* PRD[15:12] FBD[8:0] */ 718 tc358768_write(priv, TC358768_PLLCTL0, ((prd - 1) << 12) | (fbd - 1)); 719 720 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ 721 tc358768_write(priv, TC358768_PLLCTL1, 722 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0)); 723 724 /* wait for lock */ 725 usleep_range(1000, 2000); 726 727 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */ 728 tc358768_write(priv, TC358768_PLLCTL1, 729 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0)); 730 731 return tc358768_clear_error(priv); 732 } 733 734 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps) 735 { 736 return DIV_ROUND_UP(ns * 1000, period_ps); 737 } 738 739 static u32 tc358768_ps_to_ns(u32 ps) 740 { 741 return ps / 1000; 742 } 743 744 static u32 tc358768_dpi_to_ns(u32 val, u32 pclk) 745 { 746 return (u32)div_u64((u64)val * NANO, pclk); 747 } 748 749 /* Convert value in DPI pixel clock units to DSI byte count */ 750 static u32 tc358768_dpi_to_dsi_bytes(struct tc358768_priv *priv, u32 val) 751 { 752 u64 m = (u64)val * priv->dsiclk / 4 * priv->dsi_lanes; 753 u64 n = priv->pclk; 754 755 return (u32)div_u64(m + n - 1, n); 756 } 757 758 static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val) 759 { 760 u64 m = (u64)val * NANO; 761 u64 n = priv->dsiclk / 4 * priv->dsi_lanes; 762 763 return (u32)div_u64(m, n); 764 } 765 766 static void tc358768_bridge_atomic_pre_enable(struct drm_bridge *bridge, 767 struct drm_atomic_commit *state) 768 { 769 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 770 struct mipi_dsi_device *dsi_dev = priv->output.dev; 771 u32 val, mask, val2, lptxcnt, hact; 772 s32 raw_val; 773 struct drm_crtc_state *crtc_state; 774 struct drm_connector_state *conn_state; 775 struct drm_connector *connector; 776 const struct drm_display_mode *mode; 777 u32 hsbyteclk_ps, dsiclk_ps, ui_ps; 778 u32 dsiclk, hsbyteclk; 779 int ret, i; 780 struct videomode vm; 781 struct device *dev = priv->dev; 782 /* In pixelclock units */ 783 u32 dpi_htot, dpi_data_start; 784 /* In byte units */ 785 u32 dsi_dpi_htot, dsi_dpi_data_start; 786 u32 dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp; 787 const u32 dsi_hss = 4; /* HSS is a short packet (4 bytes) */ 788 /* In hsbyteclk units */ 789 u32 dsi_vsdly; 790 const u32 internal_dly = 40; 791 792 tc358768_hw_enable(priv); 793 794 ret = tc358768_sw_reset(priv); 795 if (ret) { 796 dev_err(dev, "Software reset failed: %d\n", ret); 797 tc358768_hw_disable(priv); 798 return; 799 } 800 801 /* Release RstPtr so that the video buffer can be used for DSI commands */ 802 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), 0); 803 804 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 805 conn_state = drm_atomic_get_new_connector_state(state, connector); 806 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 807 mode = &crtc_state->adjusted_mode; 808 ret = tc358768_setup_pll(priv, mode); 809 if (ret) { 810 dev_err(dev, "PLL setup failed: %d\n", ret); 811 tc358768_hw_disable(priv); 812 return; 813 } 814 815 drm_display_mode_to_videomode(mode, &vm); 816 817 dsiclk = priv->dsiclk; 818 hsbyteclk = dsiclk / 4; 819 820 switch (dsi_dev->format) { 821 case MIPI_DSI_FMT_RGB888: 822 hact = vm.hactive * 3; 823 break; 824 case MIPI_DSI_FMT_RGB666: 825 hact = vm.hactive * 3; 826 break; 827 828 case MIPI_DSI_FMT_RGB666_PACKED: 829 hact = vm.hactive * 18 / 8; 830 break; 831 832 case MIPI_DSI_FMT_RGB565: 833 hact = vm.hactive * 2; 834 break; 835 default: 836 dev_err(dev, "Invalid data format (%u)\n", 837 dsi_dev->format); 838 tc358768_hw_disable(priv); 839 return; 840 } 841 842 /* 843 * There are three important things to make TC358768 work correctly, 844 * which are not trivial to manage: 845 * 846 * 1. Keep the DPI line-time and the DSI line-time as close to each 847 * other as possible. 848 * 2. TC358768 goes to LP mode after each line's active area. The DSI 849 * HFP period has to be long enough for entering and exiting LP mode. 850 * But it is not clear how to calculate this. 851 * 3. VSDly (video start delay) has to be long enough to ensure that the 852 * DSI TX does not start transmitting until we have started receiving 853 * pixel data from the DPI input. It is not clear how to calculate 854 * this either. 855 */ 856 857 dpi_htot = vm.hactive + vm.hfront_porch + vm.hsync_len + vm.hback_porch; 858 dpi_data_start = vm.hsync_len + vm.hback_porch; 859 860 dev_dbg(dev, "dpi horiz timing (pclk): %u + %u + %u + %u = %u\n", 861 vm.hsync_len, vm.hback_porch, vm.hactive, vm.hfront_porch, 862 dpi_htot); 863 864 dev_dbg(dev, "dpi horiz timing (ns): %u + %u + %u + %u = %u\n", 865 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), 866 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), 867 tc358768_dpi_to_ns(vm.hactive, vm.pixelclock), 868 tc358768_dpi_to_ns(vm.hfront_porch, vm.pixelclock), 869 tc358768_dpi_to_ns(dpi_htot, vm.pixelclock)); 870 871 dev_dbg(dev, "dpi data start (ns): %u + %u = %u\n", 872 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), 873 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), 874 tc358768_dpi_to_ns(dpi_data_start, vm.pixelclock)); 875 876 dsi_dpi_htot = tc358768_dpi_to_dsi_bytes(priv, dpi_htot); 877 dsi_dpi_data_start = tc358768_dpi_to_dsi_bytes(priv, dpi_data_start); 878 879 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 880 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, vm.hsync_len); 881 dsi_hbp = tc358768_dpi_to_dsi_bytes(priv, vm.hback_porch); 882 } else { 883 /* HBP is included in HSW in event mode */ 884 dsi_hbp = 0; 885 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, 886 vm.hsync_len + 887 vm.hback_porch); 888 889 /* 890 * The pixel packet includes the actual pixel data, and: 891 * DSI packet header = 4 bytes 892 * DCS code = 1 byte 893 * DSI packet footer = 2 bytes 894 */ 895 dsi_hact = hact + 4 + 1 + 2; 896 897 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; 898 899 /* 900 * Here we should check if HFP is long enough for entering LP 901 * and exiting LP, but it's not clear how to calculate that. 902 * Instead, this is a naive algorithm that just adjusts the HFP 903 * and HSW so that HFP is (at least) roughly 2/3 of the total 904 * blanking time. 905 */ 906 if (dsi_hfp < (dsi_hfp + dsi_hsw + dsi_hss) * 2 / 3) { 907 u32 old_hfp = dsi_hfp; 908 u32 old_hsw = dsi_hsw; 909 u32 tot = dsi_hfp + dsi_hsw + dsi_hss; 910 911 dsi_hsw = tot / 3; 912 913 /* 914 * Seems like sometimes HSW has to be divisible by num-lanes, but 915 * not always... 916 */ 917 dsi_hsw = roundup(dsi_hsw, priv->dsi_lanes); 918 919 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; 920 921 dev_dbg(dev, 922 "hfp too short, adjusting dsi hfp and dsi hsw from %u, %u to %u, %u\n", 923 old_hfp, old_hsw, dsi_hfp, dsi_hsw); 924 } 925 926 dev_dbg(dev, 927 "dsi horiz timing (bytes): %u, %u + %u + %u + %u = %u\n", 928 dsi_hss, dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp, 929 dsi_hss + dsi_hsw + dsi_hbp + dsi_hact + dsi_hfp); 930 931 dev_dbg(dev, "dsi horiz timing (ns): %u + %u + %u + %u + %u = %u\n", 932 tc358768_dsi_bytes_to_ns(priv, dsi_hss), 933 tc358768_dsi_bytes_to_ns(priv, dsi_hsw), 934 tc358768_dsi_bytes_to_ns(priv, dsi_hbp), 935 tc358768_dsi_bytes_to_ns(priv, dsi_hact), 936 tc358768_dsi_bytes_to_ns(priv, dsi_hfp), 937 tc358768_dsi_bytes_to_ns(priv, dsi_hss + dsi_hsw + 938 dsi_hbp + dsi_hact + dsi_hfp)); 939 } 940 941 /* VSDly calculation */ 942 943 /* Start with the HW internal delay */ 944 dsi_vsdly = internal_dly; 945 946 /* Convert to byte units as the other variables are in byte units */ 947 dsi_vsdly *= priv->dsi_lanes; 948 949 /* Do we need more delay, in addition to the internal? */ 950 if (dsi_dpi_data_start > dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp) { 951 dsi_vsdly = dsi_dpi_data_start - dsi_hss - dsi_hsw - dsi_hbp; 952 dsi_vsdly = roundup(dsi_vsdly, priv->dsi_lanes); 953 } 954 955 dev_dbg(dev, "dsi data start (bytes) %u + %u + %u + %u = %u\n", 956 dsi_vsdly, dsi_hss, dsi_hsw, dsi_hbp, 957 dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp); 958 959 dev_dbg(dev, "dsi data start (ns) %u + %u + %u + %u = %u\n", 960 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly), 961 tc358768_dsi_bytes_to_ns(priv, dsi_hss), 962 tc358768_dsi_bytes_to_ns(priv, dsi_hsw), 963 tc358768_dsi_bytes_to_ns(priv, dsi_hbp), 964 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp)); 965 966 /* Convert back to hsbyteclk */ 967 dsi_vsdly /= priv->dsi_lanes; 968 969 /* 970 * The docs say that there is an internal delay of 40 cycles. 971 * However, we get underflows if we follow that rule. If we 972 * instead ignore the internal delay, things work. So either 973 * the docs are wrong or the calculations are wrong. 974 * 975 * As a temporary fix, add the internal delay here, to counter 976 * the subtraction when writing the register. 977 */ 978 dsi_vsdly += internal_dly; 979 980 /* Clamp to the register max */ 981 if (dsi_vsdly - internal_dly > 0x3ff) { 982 dev_warn(dev, "VSDly too high, underflows likely\n"); 983 dsi_vsdly = 0x3ff + internal_dly; 984 } 985 986 /* VSDly[9:0] */ 987 tc358768_write(priv, TC358768_VSDLY, dsi_vsdly - internal_dly); 988 989 /* Enable D-PHY (HiZ->LP11) */ 990 tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000); 991 /* Enable lanes */ 992 for (i = 0; i < dsi_dev->lanes; i++) 993 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); 994 995 /* DSI Timings */ 996 hsbyteclk_ps = (u32)div_u64(PICO, hsbyteclk); 997 dsiclk_ps = (u32)div_u64(PICO, dsiclk); 998 ui_ps = dsiclk_ps / 2; 999 dev_dbg(dev, "dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", dsiclk_ps, 1000 ui_ps, hsbyteclk_ps); 1001 1002 /* LP11 > 100us for D-PHY Rx Init */ 1003 val = tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1; 1004 dev_dbg(dev, "LINEINITCNT: %u\n", val); 1005 tc358768_write(priv, TC358768_LINEINITCNT, val); 1006 1007 /* LPTimeCnt > 50ns */ 1008 val = tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1; 1009 lptxcnt = val; 1010 dev_dbg(dev, "LPTXTIMECNT: %u\n", val); 1011 tc358768_write(priv, TC358768_LPTXTIMECNT, val); 1012 1013 /* 38ns < TCLK_PREPARE < 95ns */ 1014 val = tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1; 1015 dev_dbg(dev, "TCLK_PREPARECNT %u\n", val); 1016 /* TCLK_PREPARE + TCLK_ZERO > 300ns */ 1017 val2 = tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps), 1018 hsbyteclk_ps) - 2; 1019 dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2); 1020 val |= val2 << 8; 1021 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); 1022 1023 /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */ 1024 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), hsbyteclk_ps) - 5; 1025 val = clamp(raw_val, 0, 127); 1026 dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val); 1027 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); 1028 1029 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ 1030 val = 50 + tc358768_ps_to_ns(4 * ui_ps); 1031 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1; 1032 dev_dbg(dev, "THS_PREPARECNT %u\n", val); 1033 /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ 1034 raw_val = tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), hsbyteclk_ps) - 10; 1035 val2 = clamp(raw_val, 0, 127); 1036 dev_dbg(dev, "THS_ZEROCNT %u\n", val2); 1037 val |= val2 << 8; 1038 tc358768_write(priv, TC358768_THS_HEADERCNT, val); 1039 1040 /* TWAKEUP > 1ms in lptxcnt steps */ 1041 val = tc358768_ns_to_cnt(1020000, hsbyteclk_ps); 1042 val = val / (lptxcnt + 1) - 1; 1043 dev_dbg(dev, "TWAKEUP: %u\n", val); 1044 tc358768_write(priv, TC358768_TWAKEUP, val); 1045 1046 /* TCLK_POSTCNT > 60ns + 52*UI */ 1047 val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps), 1048 hsbyteclk_ps) - 3; 1049 dev_dbg(dev, "TCLK_POSTCNT: %u\n", val); 1050 tc358768_write(priv, TC358768_TCLK_POSTCNT, val); 1051 1052 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ 1053 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps), 1054 hsbyteclk_ps) - 4; 1055 val = clamp(raw_val, 0, 15); 1056 dev_dbg(dev, "THS_TRAILCNT: %u\n", val); 1057 tc358768_write(priv, TC358768_THS_TRAILCNT, val); 1058 1059 val = BIT(0); 1060 for (i = 0; i < dsi_dev->lanes; i++) 1061 val |= BIT(i + 1); 1062 tc358768_write(priv, TC358768_HSTXVREGEN, val); 1063 1064 tc358768_write(priv, TC358768_TXOPTIONCNTRL, 1065 (dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); 1066 1067 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ 1068 val = tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4); 1069 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1; 1070 dev_dbg(dev, "TXTAGOCNT: %u\n", val); 1071 val2 = tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps), 1072 hsbyteclk_ps) - 2; 1073 dev_dbg(dev, "RXTASURECNT: %u\n", val2); 1074 val = val << 16 | val2; 1075 tc358768_write(priv, TC358768_BTACNTRL1, val); 1076 1077 /* START[0] */ 1078 tc358768_write(priv, TC358768_STARTCNTRL, 1); 1079 1080 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 1081 /* Set pulse mode */ 1082 tc358768_write(priv, TC358768_DSI_EVENT, 0); 1083 1084 /* vact */ 1085 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); 1086 1087 /* vsw */ 1088 tc358768_write(priv, TC358768_DSI_VSW, vm.vsync_len); 1089 1090 /* vbp */ 1091 tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch); 1092 } else { 1093 /* Set event mode */ 1094 tc358768_write(priv, TC358768_DSI_EVENT, 1); 1095 1096 /* vact */ 1097 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); 1098 1099 /* vsw (+ vbp) */ 1100 tc358768_write(priv, TC358768_DSI_VSW, 1101 vm.vsync_len + vm.vback_porch); 1102 1103 /* vbp (not used in event mode) */ 1104 tc358768_write(priv, TC358768_DSI_VBPR, 0); 1105 } 1106 1107 /* hsw (bytes) */ 1108 tc358768_write(priv, TC358768_DSI_HSW, dsi_hsw); 1109 1110 /* hbp (bytes) */ 1111 tc358768_write(priv, TC358768_DSI_HBPR, dsi_hbp); 1112 1113 /* hact (bytes) */ 1114 tc358768_write(priv, TC358768_DSI_HACT, hact); 1115 1116 /* VSYNC polarity */ 1117 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), 1118 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0); 1119 1120 /* HSYNC polarity */ 1121 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), 1122 (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0); 1123 1124 /* Start DSI Tx */ 1125 tc358768_write(priv, TC358768_DSI_START, 0x1); 1126 1127 /* Configure DSI_Control register */ 1128 val = (dsi_dev->lanes - 1) << 1; 1129 1130 if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM)) 1131 val |= TC358768_DSI_CONTROL_TXMD; 1132 1133 if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 1134 val |= TC358768_DSI_CONTROL_HSCKMD; 1135 1136 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 1137 val |= TC358768_DSI_CONTROL_EOTDIS; 1138 1139 mask = TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | 1140 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; 1141 1142 tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, mask, val); 1143 1144 tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, 1145 TC358768_DSI_CONTROL_DSI_MODE, 0); 1146 1147 ret = tc358768_clear_error(priv); 1148 if (ret) 1149 dev_err(dev, "Bridge pre_enable failed: %d\n", ret); 1150 } 1151 1152 static void tc358768_config_video_format(struct tc358768_priv *priv) 1153 { 1154 struct mipi_dsi_device *dsi_dev = priv->output.dev; 1155 u32 val, data_type; 1156 1157 /* Data Format Control Register */ 1158 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ 1159 switch (dsi_dev->format) { 1160 case MIPI_DSI_FMT_RGB888: 1161 val |= (0x3 << 4); 1162 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 1163 break; 1164 case MIPI_DSI_FMT_RGB666: 1165 val |= (0x4 << 4); 1166 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 1167 break; 1168 case MIPI_DSI_FMT_RGB666_PACKED: 1169 val |= (0x4 << 4) | BIT(3); 1170 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 1171 break; 1172 case MIPI_DSI_FMT_RGB565: 1173 val |= (0x5 << 4); 1174 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 1175 break; 1176 default: 1177 dev_err(priv->dev, "Invalid data format (%u)\n", dsi_dev->format); 1178 return; 1179 } 1180 1181 tc358768_write(priv, TC358768_DATAFMT, val); 1182 tc358768_write(priv, TC358768_DSITX_DT, data_type); 1183 } 1184 1185 static void tc358768_bridge_atomic_enable(struct drm_bridge *bridge, 1186 struct drm_atomic_commit *state) 1187 { 1188 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 1189 int ret; 1190 1191 if (!priv->enabled) { 1192 dev_err(priv->dev, "Bridge is not enabled\n"); 1193 return; 1194 } 1195 1196 /* Configure video format registers */ 1197 tc358768_config_video_format(priv); 1198 1199 /* Enable HS mode for video TX */ 1200 tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, 1201 TC358768_DSI_CONTROL_TXMD, 1202 TC358768_DSI_CONTROL_TXMD); 1203 1204 /* clear FrmStop and RstPtr */ 1205 tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0); 1206 1207 /* set PP_en */ 1208 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6)); 1209 1210 ret = tc358768_clear_error(priv); 1211 if (ret) 1212 dev_err(priv->dev, "Bridge enable failed: %d\n", ret); 1213 } 1214 1215 #define MAX_INPUT_SEL_FORMATS 1 1216 1217 static u32 * 1218 tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 1219 struct drm_bridge_state *bridge_state, 1220 struct drm_crtc_state *crtc_state, 1221 struct drm_connector_state *conn_state, 1222 u32 output_fmt, 1223 unsigned int *num_input_fmts) 1224 { 1225 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 1226 u32 *input_fmts; 1227 1228 *num_input_fmts = 0; 1229 1230 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 1231 GFP_KERNEL); 1232 if (!input_fmts) 1233 return NULL; 1234 1235 switch (priv->pd_lines) { 1236 case 16: 1237 input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16; 1238 break; 1239 case 18: 1240 input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18; 1241 break; 1242 default: 1243 case 24: 1244 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 1245 break; 1246 } 1247 1248 *num_input_fmts = MAX_INPUT_SEL_FORMATS; 1249 1250 return input_fmts; 1251 } 1252 1253 static int tc358768_bridge_atomic_check(struct drm_bridge *bridge, 1254 struct drm_bridge_state *bridge_state, 1255 struct drm_crtc_state *crtc_state, 1256 struct drm_connector_state *conn_state) 1257 { 1258 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 1259 1260 /* Default to positive sync */ 1261 1262 if (!(adjusted_mode->flags & 1263 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 1264 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; 1265 1266 if (!(adjusted_mode->flags & 1267 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 1268 adjusted_mode->flags |= DRM_MODE_FLAG_PVSYNC; 1269 1270 bridge_state->input_bus_cfg.flags = bridge->timings->input_bus_flags; 1271 1272 return 0; 1273 } 1274 1275 static const struct drm_bridge_funcs tc358768_bridge_funcs = { 1276 .attach = tc358768_bridge_attach, 1277 .mode_valid = tc358768_bridge_mode_valid, 1278 .atomic_check = tc358768_bridge_atomic_check, 1279 .atomic_pre_enable = tc358768_bridge_atomic_pre_enable, 1280 .atomic_enable = tc358768_bridge_atomic_enable, 1281 .atomic_disable = tc358768_bridge_atomic_disable, 1282 .atomic_post_disable = tc358768_bridge_atomic_post_disable, 1283 1284 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1285 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1286 .atomic_create_state = drm_atomic_helper_bridge_create_state, 1287 .atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts, 1288 }; 1289 1290 static const struct drm_bridge_timings default_tc358768_timings = { 1291 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 1292 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE 1293 | DRM_BUS_FLAG_DE_HIGH, 1294 }; 1295 1296 static bool tc358768_is_reserved_reg(unsigned int reg) 1297 { 1298 switch (reg) { 1299 case 0x114 ... 0x13f: 1300 case 0x200: 1301 case 0x20c: 1302 case 0x400 ... 0x408: 1303 case 0x41c ... 0x42f: 1304 return true; 1305 default: 1306 return false; 1307 } 1308 } 1309 1310 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg) 1311 { 1312 if (tc358768_is_reserved_reg(reg)) 1313 return false; 1314 1315 switch (reg) { 1316 case TC358768_CHIPID: 1317 case TC358768_FIFOSTATUS: 1318 case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2): 1319 case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2): 1320 case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2): 1321 return false; 1322 default: 1323 return true; 1324 } 1325 } 1326 1327 static bool tc358768_readable_reg(struct device *dev, unsigned int reg) 1328 { 1329 if (tc358768_is_reserved_reg(reg)) 1330 return false; 1331 1332 switch (reg) { 1333 case TC358768_STARTCNTRL: 1334 case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2): 1335 case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2): 1336 case TC358768_DSI_START ... (TC358768_DSI_START + 2): 1337 case TC358768_DBG_DATA: 1338 return false; 1339 default: 1340 return true; 1341 } 1342 } 1343 1344 static const struct regmap_config tc358768_regmap_config = { 1345 .name = "tc358768", 1346 .reg_bits = 16, 1347 .val_bits = 16, 1348 .max_register = TC358768_DSI_HACT, 1349 .cache_type = REGCACHE_NONE, 1350 .writeable_reg = tc358768_writeable_reg, 1351 .readable_reg = tc358768_readable_reg, 1352 .reg_format_endian = REGMAP_ENDIAN_BIG, 1353 .val_format_endian = REGMAP_ENDIAN_BIG, 1354 }; 1355 1356 static const struct i2c_device_id tc358768_i2c_ids[] = { 1357 { .name = "tc358768" }, 1358 { .name = "tc358778" }, 1359 { } 1360 }; 1361 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids); 1362 1363 static const struct of_device_id tc358768_of_ids[] = { 1364 { .compatible = "toshiba,tc358768", }, 1365 { .compatible = "toshiba,tc358778", }, 1366 { } 1367 }; 1368 MODULE_DEVICE_TABLE(of, tc358768_of_ids); 1369 1370 static int tc358768_get_regulators(struct tc358768_priv *priv) 1371 { 1372 int i, ret; 1373 1374 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i) 1375 priv->supplies[i].supply = tc358768_supplies[i]; 1376 1377 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies), 1378 priv->supplies); 1379 if (ret < 0) 1380 dev_err(priv->dev, "failed to get regulators: %d\n", ret); 1381 1382 return ret; 1383 } 1384 1385 static int tc358768_i2c_probe(struct i2c_client *client) 1386 { 1387 struct tc358768_priv *priv; 1388 struct device *dev = &client->dev; 1389 struct device_node *np = dev->of_node; 1390 int ret; 1391 1392 if (!np) 1393 return -ENODEV; 1394 1395 priv = devm_drm_bridge_alloc(dev, struct tc358768_priv, bridge, 1396 &tc358768_bridge_funcs); 1397 if (IS_ERR(priv)) 1398 return PTR_ERR(priv); 1399 1400 dev_set_drvdata(dev, priv); 1401 priv->dev = dev; 1402 1403 ret = tc358768_get_regulators(priv); 1404 if (ret) 1405 return ret; 1406 1407 priv->refclk = devm_clk_get(dev, "refclk"); 1408 if (IS_ERR(priv->refclk)) 1409 return PTR_ERR(priv->refclk); 1410 1411 /* 1412 * RESX is low active, to disable tc358768 initially (keep in reset) 1413 * the gpio line must be LOW. This is the ASSERTED state of 1414 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED). 1415 */ 1416 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1417 GPIOD_OUT_HIGH); 1418 if (IS_ERR(priv->reset_gpio)) 1419 return PTR_ERR(priv->reset_gpio); 1420 1421 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config); 1422 if (IS_ERR(priv->regmap)) { 1423 dev_err(dev, "Failed to init regmap\n"); 1424 return PTR_ERR(priv->regmap); 1425 } 1426 1427 priv->dsi_host.dev = dev; 1428 priv->dsi_host.ops = &tc358768_dsi_host_ops; 1429 1430 priv->bridge.timings = &default_tc358768_timings; 1431 priv->bridge.of_node = np; 1432 1433 i2c_set_clientdata(client, priv); 1434 1435 return mipi_dsi_host_register(&priv->dsi_host); 1436 } 1437 1438 static void tc358768_i2c_remove(struct i2c_client *client) 1439 { 1440 struct tc358768_priv *priv = i2c_get_clientdata(client); 1441 1442 mipi_dsi_host_unregister(&priv->dsi_host); 1443 } 1444 1445 static struct i2c_driver tc358768_driver = { 1446 .driver = { 1447 .name = "tc358768", 1448 .of_match_table = tc358768_of_ids, 1449 }, 1450 .id_table = tc358768_i2c_ids, 1451 .probe = tc358768_i2c_probe, 1452 .remove = tc358768_i2c_remove, 1453 }; 1454 module_i2c_driver(tc358768_driver); 1455 1456 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1457 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge"); 1458 MODULE_LICENSE("GPL v2"); 1459