1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Brad Volkin <bradley.d.volkin@intel.com>
25 *
26 */
27
28 #include <linux/highmem.h>
29
30 #include <drm/drm_cache.h>
31 #include <drm/drm_print.h>
32
33 #include "gt/intel_engine.h"
34 #include "gt/intel_engine_regs.h"
35 #include "gt/intel_gpu_commands.h"
36 #include "gt/intel_gt_regs.h"
37
38 #include "i915_cmd_parser.h"
39 #include "i915_drv.h"
40 #include "i915_memcpy.h"
41 #include "i915_reg.h"
42
43 /**
44 * DOC: batch buffer command parser
45 *
46 * Motivation:
47 * Certain OpenGL features (e.g. transform feedback, performance monitoring)
48 * require userspace code to submit batches containing commands such as
49 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
50 * generations of the hardware will noop these commands in "unsecure" batches
51 * (which includes all userspace batches submitted via i915) even though the
52 * commands may be safe and represent the intended programming model of the
53 * device.
54 *
55 * The software command parser is similar in operation to the command parsing
56 * done in hardware for unsecure batches. However, the software parser allows
57 * some operations that would be noop'd by hardware, if the parser determines
58 * the operation is safe, and submits the batch as "secure" to prevent hardware
59 * parsing.
60 *
61 * Threats:
62 * At a high level, the hardware (and software) checks attempt to prevent
63 * granting userspace undue privileges. There are three categories of privilege.
64 *
65 * First, commands which are explicitly defined as privileged or which should
66 * only be used by the kernel driver. The parser rejects such commands
67 *
68 * Second, commands which access registers. To support correct/enhanced
69 * userspace functionality, particularly certain OpenGL extensions, the parser
70 * provides a whitelist of registers which userspace may safely access
71 *
72 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
73 * The parser always rejects such commands.
74 *
75 * The majority of the problematic commands fall in the MI_* range, with only a
76 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
77 *
78 * Implementation:
79 * Each engine maintains tables of commands and registers which the parser
80 * uses in scanning batch buffers submitted to that engine.
81 *
82 * Since the set of commands that the parser must check for is significantly
83 * smaller than the number of commands supported, the parser tables contain only
84 * those commands required by the parser. This generally works because command
85 * opcode ranges have standard command length encodings. So for commands that
86 * the parser does not need to check, it can easily skip them. This is
87 * implemented via a per-engine length decoding vfunc.
88 *
89 * Unfortunately, there are a number of commands that do not follow the standard
90 * length encoding for their opcode range, primarily amongst the MI_* commands.
91 * To handle this, the parser provides a way to define explicit "skip" entries
92 * in the per-engine command tables.
93 *
94 * Other command table entries map fairly directly to high level categories
95 * mentioned above: rejected, register whitelist. The parser implements a number
96 * of checks, including the privileged memory checks, via a general bitmasking
97 * mechanism.
98 */
99
100 /*
101 * A command that requires special handling by the command parser.
102 */
103 struct drm_i915_cmd_descriptor {
104 /*
105 * Flags describing how the command parser processes the command.
106 *
107 * CMD_DESC_FIXED: The command has a fixed length if this is set,
108 * a length mask if not set
109 * CMD_DESC_SKIP: The command is allowed but does not follow the
110 * standard length encoding for the opcode range in
111 * which it falls
112 * CMD_DESC_REJECT: The command is never allowed
113 * CMD_DESC_REGISTER: The command should be checked against the
114 * register whitelist for the appropriate ring
115 */
116 u32 flags;
117 #define CMD_DESC_FIXED (1<<0)
118 #define CMD_DESC_SKIP (1<<1)
119 #define CMD_DESC_REJECT (1<<2)
120 #define CMD_DESC_REGISTER (1<<3)
121 #define CMD_DESC_BITMASK (1<<4)
122
123 /*
124 * The command's unique identification bits and the bitmask to get them.
125 * This isn't strictly the opcode field as defined in the spec and may
126 * also include type, subtype, and/or subop fields.
127 */
128 struct {
129 u32 value;
130 u32 mask;
131 } cmd;
132
133 /*
134 * The command's length. The command is either fixed length (i.e. does
135 * not include a length field) or has a length field mask. The flag
136 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
137 * a length mask. All command entries in a command table must include
138 * length information.
139 */
140 union {
141 u32 fixed;
142 u32 mask;
143 } length;
144
145 /*
146 * Describes where to find a register address in the command to check
147 * against the ring's register whitelist. Only valid if flags has the
148 * CMD_DESC_REGISTER bit set.
149 *
150 * A non-zero step value implies that the command may access multiple
151 * registers in sequence (e.g. LRI), in that case step gives the
152 * distance in dwords between individual offset fields.
153 */
154 struct {
155 u32 offset;
156 u32 mask;
157 u32 step;
158 } reg;
159
160 #define MAX_CMD_DESC_BITMASKS 3
161 /*
162 * Describes command checks where a particular dword is masked and
163 * compared against an expected value. If the command does not match
164 * the expected value, the parser rejects it. Only valid if flags has
165 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
166 * are valid.
167 *
168 * If the check specifies a non-zero condition_mask then the parser
169 * only performs the check when the bits specified by condition_mask
170 * are non-zero.
171 */
172 struct {
173 u32 offset;
174 u32 mask;
175 u32 expected;
176 u32 condition_offset;
177 u32 condition_mask;
178 } bits[MAX_CMD_DESC_BITMASKS];
179 };
180
181 /*
182 * A table of commands requiring special handling by the command parser.
183 *
184 * Each engine has an array of tables. Each table consists of an array of
185 * command descriptors, which must be sorted with command opcodes in
186 * ascending order.
187 */
188 struct drm_i915_cmd_table {
189 const struct drm_i915_cmd_descriptor *table;
190 int count;
191 };
192
193 #define STD_MI_OPCODE_SHIFT (32 - 9)
194 #define STD_3D_OPCODE_SHIFT (32 - 16)
195 #define STD_2D_OPCODE_SHIFT (32 - 10)
196 #define STD_MFX_OPCODE_SHIFT (32 - 16)
197 #define MIN_OPCODE_SHIFT 16
198
199 #define CMD(op, opm, f, lm, fl, ...) \
200 { \
201 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \
202 .cmd = { (op & ~0u << (opm)), ~0u << (opm) }, \
203 .length = { (lm) }, \
204 __VA_ARGS__ \
205 }
206
207 /* Convenience macros to compress the tables */
208 #define SMI STD_MI_OPCODE_SHIFT
209 #define S3D STD_3D_OPCODE_SHIFT
210 #define S2D STD_2D_OPCODE_SHIFT
211 #define SMFX STD_MFX_OPCODE_SHIFT
212 #define F true
213 #define S CMD_DESC_SKIP
214 #define R CMD_DESC_REJECT
215 #define W CMD_DESC_REGISTER
216 #define B CMD_DESC_BITMASK
217
218 /* Command Mask Fixed Len Action
219 ---------------------------------------------------------- */
220 static const struct drm_i915_cmd_descriptor gen7_common_cmds[] = {
221 CMD( MI_NOOP, SMI, F, 1, S ),
222 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
223 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ),
224 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
225 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
226 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
227 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
228 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
229 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
230 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
231 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B,
232 .reg = { .offset = 1, .mask = 0x007FFFFC },
233 .bits = {{
234 .offset = 0,
235 .mask = MI_GLOBAL_GTT,
236 .expected = 0,
237 }}, ),
238 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B,
239 .reg = { .offset = 1, .mask = 0x007FFFFC },
240 .bits = {{
241 .offset = 0,
242 .mask = MI_GLOBAL_GTT,
243 .expected = 0,
244 }}, ),
245 /*
246 * MI_BATCH_BUFFER_START requires some special handling. It's not
247 * really a 'skip' action but it doesn't seem like it's worth adding
248 * a new action. See intel_engine_cmd_parser().
249 */
250 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
251 };
252
253 static const struct drm_i915_cmd_descriptor gen7_render_cmds[] = {
254 CMD( MI_FLUSH, SMI, F, 1, S ),
255 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
256 CMD( MI_PREDICATE, SMI, F, 1, S ),
257 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
258 CMD( MI_SET_APPID, SMI, F, 1, S ),
259 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
260 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
261 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
262 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
263 .bits = {{
264 .offset = 0,
265 .mask = MI_GLOBAL_GTT,
266 .expected = 0,
267 }}, ),
268 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
269 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
270 .bits = {{
271 .offset = 0,
272 .mask = MI_GLOBAL_GTT,
273 .expected = 0,
274 }}, ),
275 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
276 .bits = {{
277 .offset = 1,
278 .mask = MI_REPORT_PERF_COUNT_GGTT,
279 .expected = 0,
280 }}, ),
281 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
282 .bits = {{
283 .offset = 0,
284 .mask = MI_GLOBAL_GTT,
285 .expected = 0,
286 }}, ),
287 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
288 CMD( PIPELINE_SELECT, S3D, F, 1, S ),
289 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
290 .bits = {{
291 .offset = 2,
292 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
293 .expected = 0,
294 }}, ),
295 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
296 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
297 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
298 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
299 .bits = {{
300 .offset = 1,
301 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
302 .expected = 0,
303 },
304 {
305 .offset = 1,
306 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
307 PIPE_CONTROL_STORE_DATA_INDEX),
308 .expected = 0,
309 .condition_offset = 1,
310 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
311 }}, ),
312 };
313
314 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
315 CMD( MI_SET_PREDICATE, SMI, F, 1, S ),
316 CMD( MI_RS_CONTROL, SMI, F, 1, S ),
317 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
318 CMD( MI_SET_APPID, SMI, F, 1, S ),
319 CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
320 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
321 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
322 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
323 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
324 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
325 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
326 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
327 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ),
328 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ),
329
330 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ),
331 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ),
332 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ),
333 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ),
334 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ),
335 };
336
337 static const struct drm_i915_cmd_descriptor gen7_video_cmds[] = {
338 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
339 CMD( MI_SET_APPID, SMI, F, 1, S ),
340 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
341 .bits = {{
342 .offset = 0,
343 .mask = MI_GLOBAL_GTT,
344 .expected = 0,
345 }}, ),
346 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
347 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
348 .bits = {{
349 .offset = 0,
350 .mask = MI_FLUSH_DW_NOTIFY,
351 .expected = 0,
352 },
353 {
354 .offset = 1,
355 .mask = MI_FLUSH_DW_USE_GTT,
356 .expected = 0,
357 .condition_offset = 0,
358 .condition_mask = MI_FLUSH_DW_OP_MASK,
359 },
360 {
361 .offset = 0,
362 .mask = MI_FLUSH_DW_STORE_INDEX,
363 .expected = 0,
364 .condition_offset = 0,
365 .condition_mask = MI_FLUSH_DW_OP_MASK,
366 }}, ),
367 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
368 .bits = {{
369 .offset = 0,
370 .mask = MI_GLOBAL_GTT,
371 .expected = 0,
372 }}, ),
373 /*
374 * MFX_WAIT doesn't fit the way we handle length for most commands.
375 * It has a length field but it uses a non-standard length bias.
376 * It is always 1 dword though, so just treat it as fixed length.
377 */
378 CMD( MFX_WAIT, SMFX, F, 1, S ),
379 };
380
381 static const struct drm_i915_cmd_descriptor gen7_vecs_cmds[] = {
382 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
383 CMD( MI_SET_APPID, SMI, F, 1, S ),
384 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
385 .bits = {{
386 .offset = 0,
387 .mask = MI_GLOBAL_GTT,
388 .expected = 0,
389 }}, ),
390 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
391 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
392 .bits = {{
393 .offset = 0,
394 .mask = MI_FLUSH_DW_NOTIFY,
395 .expected = 0,
396 },
397 {
398 .offset = 1,
399 .mask = MI_FLUSH_DW_USE_GTT,
400 .expected = 0,
401 .condition_offset = 0,
402 .condition_mask = MI_FLUSH_DW_OP_MASK,
403 },
404 {
405 .offset = 0,
406 .mask = MI_FLUSH_DW_STORE_INDEX,
407 .expected = 0,
408 .condition_offset = 0,
409 .condition_mask = MI_FLUSH_DW_OP_MASK,
410 }}, ),
411 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
412 .bits = {{
413 .offset = 0,
414 .mask = MI_GLOBAL_GTT,
415 .expected = 0,
416 }}, ),
417 };
418
419 static const struct drm_i915_cmd_descriptor gen7_blt_cmds[] = {
420 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
421 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
422 .bits = {{
423 .offset = 0,
424 .mask = MI_GLOBAL_GTT,
425 .expected = 0,
426 }}, ),
427 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
428 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
429 .bits = {{
430 .offset = 0,
431 .mask = MI_FLUSH_DW_NOTIFY,
432 .expected = 0,
433 },
434 {
435 .offset = 1,
436 .mask = MI_FLUSH_DW_USE_GTT,
437 .expected = 0,
438 .condition_offset = 0,
439 .condition_mask = MI_FLUSH_DW_OP_MASK,
440 },
441 {
442 .offset = 0,
443 .mask = MI_FLUSH_DW_STORE_INDEX,
444 .expected = 0,
445 .condition_offset = 0,
446 .condition_mask = MI_FLUSH_DW_OP_MASK,
447 }}, ),
448 CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
449 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
450 };
451
452 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
453 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
454 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
455 };
456
457 /*
458 * For Gen9 we can still rely on the h/w to enforce cmd security, and only
459 * need to re-enforce the register access checks. We therefore only need to
460 * teach the cmdparser how to find the end of each command, and identify
461 * register accesses. The table doesn't need to reject any commands, and so
462 * the only commands listed here are:
463 * 1) Those that touch registers
464 * 2) Those that do not have the default 8-bit length
465 *
466 * Note that the default MI length mask chosen for this table is 0xFF, not
467 * the 0x3F used on older devices. This is because the vast majority of MI
468 * cmds on Gen9 use a standard 8-bit Length field.
469 * All the Gen9 blitter instructions are standard 0xFF length mask, and
470 * none allow access to non-general registers, so in fact no BLT cmds are
471 * included in the table at all.
472 *
473 */
474 static const struct drm_i915_cmd_descriptor gen9_blt_cmds[] = {
475 CMD( MI_NOOP, SMI, F, 1, S ),
476 CMD( MI_USER_INTERRUPT, SMI, F, 1, S ),
477 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ),
478 CMD( MI_FLUSH, SMI, F, 1, S ),
479 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
480 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
481 CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
482 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
483 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, S ),
484 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, S ),
485 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ),
486 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
487 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
488 CMD( MI_UPDATE_GTT, SMI, !F, 0x3FF, S ),
489 CMD( MI_STORE_REGISTER_MEM_GEN8, SMI, F, 4, W,
490 .reg = { .offset = 1, .mask = 0x007FFFFC } ),
491 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, S ),
492 CMD( MI_LOAD_REGISTER_MEM_GEN8, SMI, F, 4, W,
493 .reg = { .offset = 1, .mask = 0x007FFFFC } ),
494 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
495 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
496
497 /*
498 * We allow BB_START but apply further checks. We just sanitize the
499 * basic fields here.
500 */
501 #define MI_BB_START_OPERAND_MASK GENMASK(SMI-1, 0)
502 #define MI_BB_START_OPERAND_EXPECT (MI_BATCH_PPGTT_HSW | 1)
503 CMD( MI_BATCH_BUFFER_START_GEN8, SMI, !F, 0xFF, B,
504 .bits = {{
505 .offset = 0,
506 .mask = MI_BB_START_OPERAND_MASK,
507 .expected = MI_BB_START_OPERAND_EXPECT,
508 }}, ),
509 };
510
511 static const struct drm_i915_cmd_descriptor noop_desc =
512 CMD(MI_NOOP, SMI, F, 1, S);
513
514 #undef CMD
515 #undef SMI
516 #undef S3D
517 #undef S2D
518 #undef SMFX
519 #undef F
520 #undef S
521 #undef R
522 #undef W
523 #undef B
524
525 static const struct drm_i915_cmd_table gen7_render_cmd_table[] = {
526 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
527 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) },
528 };
529
530 static const struct drm_i915_cmd_table hsw_render_ring_cmd_table[] = {
531 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
532 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) },
533 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
534 };
535
536 static const struct drm_i915_cmd_table gen7_video_cmd_table[] = {
537 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
538 { gen7_video_cmds, ARRAY_SIZE(gen7_video_cmds) },
539 };
540
541 static const struct drm_i915_cmd_table hsw_vebox_cmd_table[] = {
542 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
543 { gen7_vecs_cmds, ARRAY_SIZE(gen7_vecs_cmds) },
544 };
545
546 static const struct drm_i915_cmd_table gen7_blt_cmd_table[] = {
547 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
548 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) },
549 };
550
551 static const struct drm_i915_cmd_table hsw_blt_ring_cmd_table[] = {
552 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
553 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) },
554 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
555 };
556
557 static const struct drm_i915_cmd_table gen9_blt_cmd_table[] = {
558 { gen9_blt_cmds, ARRAY_SIZE(gen9_blt_cmds) },
559 };
560
561
562 /*
563 * Register whitelists, sorted by increasing register offset.
564 */
565
566 /*
567 * An individual whitelist entry granting access to register addr. If
568 * mask is non-zero the argument of immediate register writes will be
569 * AND-ed with mask, and the command will be rejected if the result
570 * doesn't match value.
571 *
572 * Registers with non-zero mask are only allowed to be written using
573 * LRI.
574 */
575 struct drm_i915_reg_descriptor {
576 i915_reg_t addr;
577 u32 mask;
578 u32 value;
579 };
580
581 /* Convenience macro for adding 32-bit registers. */
582 #define REG32(_reg, ...) \
583 { .addr = (_reg), __VA_ARGS__ }
584
585 #define REG32_IDX(_reg, idx) \
586 { .addr = _reg(idx) }
587
588 /*
589 * Convenience macro for adding 64-bit registers.
590 *
591 * Some registers that userspace accesses are 64 bits. The register
592 * access commands only allow 32-bit accesses. Hence, we have to include
593 * entries for both halves of the 64-bit registers.
594 */
595 #define REG64(_reg) \
596 { .addr = _reg }, \
597 { .addr = _reg ## _UDW }
598
599 #define REG64_IDX(_reg, idx) \
600 { .addr = _reg(idx) }, \
601 { .addr = _reg ## _UDW(idx) }
602
603 #define REG64_BASE_IDX(_reg, base, idx) \
604 { .addr = _reg(base, idx) }, \
605 { .addr = _reg ## _UDW(base, idx) }
606
607 static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
608 REG64(GPGPU_THREADS_DISPATCHED),
609 REG64(HS_INVOCATION_COUNT),
610 REG64(DS_INVOCATION_COUNT),
611 REG64(IA_VERTICES_COUNT),
612 REG64(IA_PRIMITIVES_COUNT),
613 REG64(VS_INVOCATION_COUNT),
614 REG64(GS_INVOCATION_COUNT),
615 REG64(GS_PRIMITIVES_COUNT),
616 REG64(CL_INVOCATION_COUNT),
617 REG64(CL_PRIMITIVES_COUNT),
618 REG64(PS_INVOCATION_COUNT),
619 REG64(PS_DEPTH_COUNT),
620 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
621 REG64_IDX(MI_PREDICATE_SRC0, RENDER_RING_BASE),
622 REG64_IDX(MI_PREDICATE_SRC1, RENDER_RING_BASE),
623 REG32(GEN7_3DPRIM_END_OFFSET),
624 REG32(GEN7_3DPRIM_START_VERTEX),
625 REG32(GEN7_3DPRIM_VERTEX_COUNT),
626 REG32(GEN7_3DPRIM_INSTANCE_COUNT),
627 REG32(GEN7_3DPRIM_START_INSTANCE),
628 REG32(GEN7_3DPRIM_BASE_VERTEX),
629 REG32(GEN7_GPGPU_DISPATCHDIMX),
630 REG32(GEN7_GPGPU_DISPATCHDIMY),
631 REG32(GEN7_GPGPU_DISPATCHDIMZ),
632 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
633 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
634 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
635 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
636 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3),
637 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0),
638 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1),
639 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2),
640 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3),
641 REG32(GEN7_SO_WRITE_OFFSET(0)),
642 REG32(GEN7_SO_WRITE_OFFSET(1)),
643 REG32(GEN7_SO_WRITE_OFFSET(2)),
644 REG32(GEN7_SO_WRITE_OFFSET(3)),
645 REG32(GEN7_L3SQCREG1),
646 REG32(GEN7_L3CNTLREG2),
647 REG32(GEN7_L3CNTLREG3),
648 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
649 };
650
651 static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
652 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0),
653 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1),
654 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2),
655 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3),
656 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4),
657 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5),
658 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6),
659 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 7),
660 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 8),
661 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 9),
662 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 10),
663 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 11),
664 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 12),
665 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 13),
666 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 14),
667 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 15),
668 REG32(HSW_SCRATCH1,
669 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
670 .value = 0),
671 REG32(HSW_ROW_CHICKEN3,
672 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
673 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
674 .value = 0),
675 };
676
677 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
678 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
679 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
680 REG32(BCS_SWCTRL),
681 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
682 };
683
684 static const struct drm_i915_reg_descriptor gen9_blt_regs[] = {
685 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
686 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
687 REG32(BCS_SWCTRL),
688 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
689 REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),
690 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0),
691 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1),
692 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2),
693 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3),
694 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4),
695 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 5),
696 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 6),
697 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 7),
698 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 8),
699 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 9),
700 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 10),
701 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 11),
702 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 12),
703 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 13),
704 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 14),
705 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 15),
706 };
707
708 #undef REG64
709 #undef REG32
710
711 struct drm_i915_reg_table {
712 const struct drm_i915_reg_descriptor *regs;
713 int num_regs;
714 };
715
716 static const struct drm_i915_reg_table ivb_render_reg_tables[] = {
717 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) },
718 };
719
720 static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
721 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) },
722 };
723
724 static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
725 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) },
726 { hsw_render_regs, ARRAY_SIZE(hsw_render_regs) },
727 };
728
729 static const struct drm_i915_reg_table hsw_blt_reg_tables[] = {
730 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) },
731 };
732
733 static const struct drm_i915_reg_table gen9_blt_reg_tables[] = {
734 { gen9_blt_regs, ARRAY_SIZE(gen9_blt_regs) },
735 };
736
gen7_render_get_cmd_length_mask(u32 cmd_header)737 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
738 {
739 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
740 u32 subclient =
741 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
742
743 if (client == INSTR_MI_CLIENT)
744 return 0x3F;
745 else if (client == INSTR_RC_CLIENT) {
746 if (subclient == INSTR_MEDIA_SUBCLIENT)
747 return 0xFFFF;
748 else
749 return 0xFF;
750 }
751
752 DRM_DEBUG("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
753 return 0;
754 }
755
gen7_bsd_get_cmd_length_mask(u32 cmd_header)756 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
757 {
758 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
759 u32 subclient =
760 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
761 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
762
763 if (client == INSTR_MI_CLIENT)
764 return 0x3F;
765 else if (client == INSTR_RC_CLIENT) {
766 if (subclient == INSTR_MEDIA_SUBCLIENT) {
767 if (op == 6)
768 return 0xFFFF;
769 else
770 return 0xFFF;
771 } else
772 return 0xFF;
773 }
774
775 DRM_DEBUG("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
776 return 0;
777 }
778
gen7_blt_get_cmd_length_mask(u32 cmd_header)779 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
780 {
781 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
782
783 if (client == INSTR_MI_CLIENT)
784 return 0x3F;
785 else if (client == INSTR_BC_CLIENT)
786 return 0xFF;
787
788 DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
789 return 0;
790 }
791
gen9_blt_get_cmd_length_mask(u32 cmd_header)792 static u32 gen9_blt_get_cmd_length_mask(u32 cmd_header)
793 {
794 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
795
796 if (client == INSTR_MI_CLIENT || client == INSTR_BC_CLIENT)
797 return 0xFF;
798
799 DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
800 return 0;
801 }
802
validate_cmds_sorted(const struct intel_engine_cs * engine,const struct drm_i915_cmd_table * cmd_tables,int cmd_table_count)803 static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
804 const struct drm_i915_cmd_table *cmd_tables,
805 int cmd_table_count)
806 {
807 int i;
808 bool ret = true;
809
810 if (!cmd_tables || cmd_table_count == 0)
811 return true;
812
813 for (i = 0; i < cmd_table_count; i++) {
814 const struct drm_i915_cmd_table *table = &cmd_tables[i];
815 u32 previous = 0;
816 int j;
817
818 for (j = 0; j < table->count; j++) {
819 const struct drm_i915_cmd_descriptor *desc =
820 &table->table[j];
821 u32 curr = desc->cmd.value & desc->cmd.mask;
822
823 if (curr < previous) {
824 drm_err(&engine->i915->drm,
825 "CMD: %s [%d] command table not sorted: "
826 "table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
827 engine->name, engine->id,
828 i, j, curr, previous);
829 ret = false;
830 }
831
832 previous = curr;
833 }
834 }
835
836 return ret;
837 }
838
check_sorted(const struct intel_engine_cs * engine,const struct drm_i915_reg_descriptor * reg_table,int reg_count)839 static bool check_sorted(const struct intel_engine_cs *engine,
840 const struct drm_i915_reg_descriptor *reg_table,
841 int reg_count)
842 {
843 int i;
844 u32 previous = 0;
845 bool ret = true;
846
847 for (i = 0; i < reg_count; i++) {
848 u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
849
850 if (curr < previous) {
851 drm_err(&engine->i915->drm,
852 "CMD: %s [%d] register table not sorted: "
853 "entry=%d reg=0x%08X prev=0x%08X\n",
854 engine->name, engine->id,
855 i, curr, previous);
856 ret = false;
857 }
858
859 previous = curr;
860 }
861
862 return ret;
863 }
864
validate_regs_sorted(struct intel_engine_cs * engine)865 static bool validate_regs_sorted(struct intel_engine_cs *engine)
866 {
867 int i;
868 const struct drm_i915_reg_table *table;
869
870 for (i = 0; i < engine->reg_table_count; i++) {
871 table = &engine->reg_tables[i];
872 if (!check_sorted(engine, table->regs, table->num_regs))
873 return false;
874 }
875
876 return true;
877 }
878
879 struct cmd_node {
880 const struct drm_i915_cmd_descriptor *desc;
881 struct hlist_node node;
882 };
883
884 /*
885 * Different command ranges have different numbers of bits for the opcode. For
886 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
887 * problem is that, for example, MI commands use bits 22:16 for other fields
888 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
889 * we mask a command from a batch it could hash to the wrong bucket due to
890 * non-opcode bits being set. But if we don't include those bits, some 3D
891 * commands may hash to the same bucket due to not including opcode bits that
892 * make the command unique. For now, we will risk hashing to the same bucket.
893 */
cmd_header_key(u32 x)894 static inline u32 cmd_header_key(u32 x)
895 {
896 switch (x >> INSTR_CLIENT_SHIFT) {
897 default:
898 case INSTR_MI_CLIENT:
899 return x >> STD_MI_OPCODE_SHIFT;
900 case INSTR_RC_CLIENT:
901 return x >> STD_3D_OPCODE_SHIFT;
902 case INSTR_BC_CLIENT:
903 return x >> STD_2D_OPCODE_SHIFT;
904 }
905 }
906
init_hash_table(struct intel_engine_cs * engine,const struct drm_i915_cmd_table * cmd_tables,int cmd_table_count)907 static int init_hash_table(struct intel_engine_cs *engine,
908 const struct drm_i915_cmd_table *cmd_tables,
909 int cmd_table_count)
910 {
911 int i, j;
912
913 hash_init(engine->cmd_hash);
914
915 for (i = 0; i < cmd_table_count; i++) {
916 const struct drm_i915_cmd_table *table = &cmd_tables[i];
917
918 for (j = 0; j < table->count; j++) {
919 const struct drm_i915_cmd_descriptor *desc =
920 &table->table[j];
921 struct cmd_node *desc_node = kmalloc_obj(*desc_node);
922
923 if (!desc_node)
924 return -ENOMEM;
925
926 desc_node->desc = desc;
927 hash_add(engine->cmd_hash, &desc_node->node,
928 cmd_header_key(desc->cmd.value));
929 }
930 }
931
932 return 0;
933 }
934
fini_hash_table(struct intel_engine_cs * engine)935 static void fini_hash_table(struct intel_engine_cs *engine)
936 {
937 struct hlist_node *tmp;
938 struct cmd_node *desc_node;
939 int i;
940
941 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
942 hash_del(&desc_node->node);
943 kfree(desc_node);
944 }
945 }
946
947 /**
948 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine
949 * @engine: the engine to initialize
950 *
951 * Optionally initializes fields related to batch buffer command parsing in the
952 * struct intel_engine_cs based on whether the platform requires software
953 * command parsing.
954 */
intel_engine_init_cmd_parser(struct intel_engine_cs * engine)955 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
956 {
957 const struct drm_i915_cmd_table *cmd_tables;
958 int cmd_table_count;
959 int ret;
960
961 if (GRAPHICS_VER(engine->i915) != 7 && !(GRAPHICS_VER(engine->i915) == 9 &&
962 engine->class == COPY_ENGINE_CLASS))
963 return 0;
964
965 switch (engine->class) {
966 case RENDER_CLASS:
967 if (IS_HASWELL(engine->i915)) {
968 cmd_tables = hsw_render_ring_cmd_table;
969 cmd_table_count =
970 ARRAY_SIZE(hsw_render_ring_cmd_table);
971 } else {
972 cmd_tables = gen7_render_cmd_table;
973 cmd_table_count = ARRAY_SIZE(gen7_render_cmd_table);
974 }
975
976 if (IS_HASWELL(engine->i915)) {
977 engine->reg_tables = hsw_render_reg_tables;
978 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
979 } else {
980 engine->reg_tables = ivb_render_reg_tables;
981 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
982 }
983 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
984 break;
985 case VIDEO_DECODE_CLASS:
986 cmd_tables = gen7_video_cmd_table;
987 cmd_table_count = ARRAY_SIZE(gen7_video_cmd_table);
988 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
989 break;
990 case COPY_ENGINE_CLASS:
991 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
992 if (GRAPHICS_VER(engine->i915) == 9) {
993 cmd_tables = gen9_blt_cmd_table;
994 cmd_table_count = ARRAY_SIZE(gen9_blt_cmd_table);
995 engine->get_cmd_length_mask =
996 gen9_blt_get_cmd_length_mask;
997
998 /* BCS Engine unsafe without parser */
999 engine->flags |= I915_ENGINE_REQUIRES_CMD_PARSER;
1000 } else if (IS_HASWELL(engine->i915)) {
1001 cmd_tables = hsw_blt_ring_cmd_table;
1002 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmd_table);
1003 } else {
1004 cmd_tables = gen7_blt_cmd_table;
1005 cmd_table_count = ARRAY_SIZE(gen7_blt_cmd_table);
1006 }
1007
1008 if (GRAPHICS_VER(engine->i915) == 9) {
1009 engine->reg_tables = gen9_blt_reg_tables;
1010 engine->reg_table_count =
1011 ARRAY_SIZE(gen9_blt_reg_tables);
1012 } else if (IS_HASWELL(engine->i915)) {
1013 engine->reg_tables = hsw_blt_reg_tables;
1014 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
1015 } else {
1016 engine->reg_tables = ivb_blt_reg_tables;
1017 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
1018 }
1019 break;
1020 case VIDEO_ENHANCEMENT_CLASS:
1021 cmd_tables = hsw_vebox_cmd_table;
1022 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmd_table);
1023 /* VECS can use the same length_mask function as VCS */
1024 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
1025 break;
1026 default:
1027 MISSING_CASE(engine->class);
1028 goto out;
1029 }
1030
1031 if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) {
1032 drm_err(&engine->i915->drm,
1033 "%s: command descriptions are not sorted\n",
1034 engine->name);
1035 goto out;
1036 }
1037 if (!validate_regs_sorted(engine)) {
1038 drm_err(&engine->i915->drm,
1039 "%s: registers are not sorted\n", engine->name);
1040 goto out;
1041 }
1042
1043 ret = init_hash_table(engine, cmd_tables, cmd_table_count);
1044 if (ret) {
1045 drm_err(&engine->i915->drm,
1046 "%s: initialised failed!\n", engine->name);
1047 fini_hash_table(engine);
1048 goto out;
1049 }
1050
1051 engine->flags |= I915_ENGINE_USING_CMD_PARSER;
1052
1053 out:
1054 if (intel_engine_requires_cmd_parser(engine) &&
1055 !intel_engine_using_cmd_parser(engine))
1056 return -EINVAL;
1057
1058 return 0;
1059 }
1060
1061 /**
1062 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields
1063 * @engine: the engine to clean up
1064 *
1065 * Releases any resources related to command parsing that may have been
1066 * initialized for the specified engine.
1067 */
intel_engine_cleanup_cmd_parser(struct intel_engine_cs * engine)1068 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)
1069 {
1070 if (!intel_engine_using_cmd_parser(engine))
1071 return;
1072
1073 fini_hash_table(engine);
1074 }
1075
1076 static const struct drm_i915_cmd_descriptor*
find_cmd_in_table(struct intel_engine_cs * engine,u32 cmd_header)1077 find_cmd_in_table(struct intel_engine_cs *engine,
1078 u32 cmd_header)
1079 {
1080 struct cmd_node *desc_node;
1081
1082 hash_for_each_possible(engine->cmd_hash, desc_node, node,
1083 cmd_header_key(cmd_header)) {
1084 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
1085 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
1086 return desc;
1087 }
1088
1089 return NULL;
1090 }
1091
1092 /*
1093 * Returns a pointer to a descriptor for the command specified by cmd_header.
1094 *
1095 * The caller must supply space for a default descriptor via the default_desc
1096 * parameter. If no descriptor for the specified command exists in the engine's
1097 * command parser tables, this function fills in default_desc based on the
1098 * engine's default length encoding and returns default_desc.
1099 */
1100 static const struct drm_i915_cmd_descriptor*
find_cmd(struct intel_engine_cs * engine,u32 cmd_header,const struct drm_i915_cmd_descriptor * desc,struct drm_i915_cmd_descriptor * default_desc)1101 find_cmd(struct intel_engine_cs *engine,
1102 u32 cmd_header,
1103 const struct drm_i915_cmd_descriptor *desc,
1104 struct drm_i915_cmd_descriptor *default_desc)
1105 {
1106 u32 mask;
1107
1108 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
1109 return desc;
1110
1111 desc = find_cmd_in_table(engine, cmd_header);
1112 if (desc)
1113 return desc;
1114
1115 mask = engine->get_cmd_length_mask(cmd_header);
1116 if (!mask)
1117 return NULL;
1118
1119 default_desc->cmd.value = cmd_header;
1120 default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT;
1121 default_desc->length.mask = mask;
1122 default_desc->flags = CMD_DESC_SKIP;
1123 return default_desc;
1124 }
1125
1126 static const struct drm_i915_reg_descriptor *
__find_reg(const struct drm_i915_reg_descriptor * table,int count,u32 addr)1127 __find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr)
1128 {
1129 int start = 0, end = count;
1130 while (start < end) {
1131 int mid = start + (end - start) / 2;
1132 int ret = addr - i915_mmio_reg_offset(table[mid].addr);
1133 if (ret < 0)
1134 end = mid;
1135 else if (ret > 0)
1136 start = mid + 1;
1137 else
1138 return &table[mid];
1139 }
1140 return NULL;
1141 }
1142
1143 static const struct drm_i915_reg_descriptor *
find_reg(const struct intel_engine_cs * engine,u32 addr)1144 find_reg(const struct intel_engine_cs *engine, u32 addr)
1145 {
1146 const struct drm_i915_reg_table *table = engine->reg_tables;
1147 const struct drm_i915_reg_descriptor *reg = NULL;
1148 int count = engine->reg_table_count;
1149
1150 for (; !reg && (count > 0); ++table, --count)
1151 reg = __find_reg(table->regs, table->num_regs, addr);
1152
1153 return reg;
1154 }
1155
1156 /* Returns a vmap'd pointer to dst_obj, which the caller must unmap */
copy_batch(struct drm_i915_gem_object * dst_obj,struct drm_i915_gem_object * src_obj,unsigned long offset,unsigned long length,bool * needs_clflush_after)1157 static u32 *copy_batch(struct drm_i915_gem_object *dst_obj,
1158 struct drm_i915_gem_object *src_obj,
1159 unsigned long offset, unsigned long length,
1160 bool *needs_clflush_after)
1161 {
1162 unsigned int src_needs_clflush;
1163 unsigned int dst_needs_clflush;
1164 void *dst, *src;
1165 int ret;
1166
1167 ret = i915_gem_object_prepare_write(dst_obj, &dst_needs_clflush);
1168 if (ret)
1169 return ERR_PTR(ret);
1170
1171 dst = i915_gem_object_pin_map(dst_obj, I915_MAP_WB);
1172 i915_gem_object_finish_access(dst_obj);
1173 if (IS_ERR(dst))
1174 return dst;
1175
1176 ret = i915_gem_object_prepare_read(src_obj, &src_needs_clflush);
1177 if (ret) {
1178 i915_gem_object_unpin_map(dst_obj);
1179 return ERR_PTR(ret);
1180 }
1181
1182 src = ERR_PTR(-ENODEV);
1183 if (src_needs_clflush && i915_has_memcpy_from_wc()) {
1184 src = i915_gem_object_pin_map(src_obj, I915_MAP_WC);
1185 if (!IS_ERR(src)) {
1186 i915_unaligned_memcpy_from_wc(dst,
1187 src + offset,
1188 length);
1189 i915_gem_object_unpin_map(src_obj);
1190 }
1191 }
1192 if (IS_ERR(src)) {
1193 unsigned long x, n, remain;
1194 void *ptr;
1195
1196 /*
1197 * We can avoid clflushing partial cachelines before the write
1198 * if we only every write full cache-lines. Since we know that
1199 * both the source and destination are in multiples of
1200 * PAGE_SIZE, we can simply round up to the next cacheline.
1201 * We don't care about copying too much here as we only
1202 * validate up to the end of the batch.
1203 */
1204 remain = length;
1205 if (dst_needs_clflush & CLFLUSH_BEFORE)
1206 remain = round_up(remain,
1207 boot_cpu_data.x86_clflush_size);
1208
1209 ptr = dst;
1210 x = offset_in_page(offset);
1211 for (n = offset >> PAGE_SHIFT; remain; n++) {
1212 int len = min(remain, PAGE_SIZE - x);
1213
1214 src = kmap_local_page(i915_gem_object_get_page(src_obj, n));
1215 if (src_needs_clflush)
1216 drm_clflush_virt_range(src + x, len);
1217 memcpy(ptr, src + x, len);
1218 kunmap_local(src);
1219
1220 ptr += len;
1221 remain -= len;
1222 x = 0;
1223 }
1224 }
1225
1226 i915_gem_object_finish_access(src_obj);
1227
1228 memset32(dst + length, 0, (dst_obj->base.size - length) / sizeof(u32));
1229
1230 /* dst_obj is returned with vmap pinned */
1231 *needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER;
1232
1233 return dst;
1234 }
1235
cmd_desc_is(const struct drm_i915_cmd_descriptor * const desc,const u32 cmd)1236 static inline bool cmd_desc_is(const struct drm_i915_cmd_descriptor * const desc,
1237 const u32 cmd)
1238 {
1239 return desc->cmd.value == (cmd & desc->cmd.mask);
1240 }
1241
check_cmd(const struct intel_engine_cs * engine,const struct drm_i915_cmd_descriptor * desc,const u32 * cmd,u32 length)1242 static bool check_cmd(const struct intel_engine_cs *engine,
1243 const struct drm_i915_cmd_descriptor *desc,
1244 const u32 *cmd, u32 length)
1245 {
1246 if (desc->flags & CMD_DESC_SKIP)
1247 return true;
1248
1249 if (desc->flags & CMD_DESC_REJECT) {
1250 DRM_DEBUG("CMD: Rejected command: 0x%08X\n", *cmd);
1251 return false;
1252 }
1253
1254 if (desc->flags & CMD_DESC_REGISTER) {
1255 /*
1256 * Get the distance between individual register offset
1257 * fields if the command can perform more than one
1258 * access at a time.
1259 */
1260 const u32 step = desc->reg.step ? desc->reg.step : length;
1261 u32 offset;
1262
1263 for (offset = desc->reg.offset; offset < length;
1264 offset += step) {
1265 const u32 reg_addr = cmd[offset] & desc->reg.mask;
1266 const struct drm_i915_reg_descriptor *reg =
1267 find_reg(engine, reg_addr);
1268
1269 if (!reg) {
1270 DRM_DEBUG("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n",
1271 reg_addr, *cmd, engine->name);
1272 return false;
1273 }
1274
1275 /*
1276 * Check the value written to the register against the
1277 * allowed mask/value pair given in the whitelist entry.
1278 */
1279 if (reg->mask) {
1280 if (cmd_desc_is(desc, MI_LOAD_REGISTER_MEM)) {
1281 DRM_DEBUG("CMD: Rejected LRM to masked register 0x%08X\n",
1282 reg_addr);
1283 return false;
1284 }
1285
1286 if (cmd_desc_is(desc, MI_LOAD_REGISTER_REG)) {
1287 DRM_DEBUG("CMD: Rejected LRR to masked register 0x%08X\n",
1288 reg_addr);
1289 return false;
1290 }
1291
1292 if (cmd_desc_is(desc, MI_LOAD_REGISTER_IMM(1)) &&
1293 (offset + 2 > length ||
1294 (cmd[offset + 1] & reg->mask) != reg->value)) {
1295 DRM_DEBUG("CMD: Rejected LRI to masked register 0x%08X\n",
1296 reg_addr);
1297 return false;
1298 }
1299 }
1300 }
1301 }
1302
1303 if (desc->flags & CMD_DESC_BITMASK) {
1304 int i;
1305
1306 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
1307 u32 dword;
1308
1309 if (desc->bits[i].mask == 0)
1310 break;
1311
1312 if (desc->bits[i].condition_mask != 0) {
1313 u32 offset =
1314 desc->bits[i].condition_offset;
1315 u32 condition = cmd[offset] &
1316 desc->bits[i].condition_mask;
1317
1318 if (condition == 0)
1319 continue;
1320 }
1321
1322 if (desc->bits[i].offset >= length) {
1323 DRM_DEBUG("CMD: Rejected command 0x%08X, too short to check bitmask (%s)\n",
1324 *cmd, engine->name);
1325 return false;
1326 }
1327
1328 dword = cmd[desc->bits[i].offset] &
1329 desc->bits[i].mask;
1330
1331 if (dword != desc->bits[i].expected) {
1332 DRM_DEBUG("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n",
1333 *cmd,
1334 desc->bits[i].mask,
1335 desc->bits[i].expected,
1336 dword, engine->name);
1337 return false;
1338 }
1339 }
1340 }
1341
1342 return true;
1343 }
1344
check_bbstart(u32 * cmd,u32 offset,u32 length,u32 batch_length,u64 batch_addr,u64 shadow_addr,const unsigned long * jump_whitelist)1345 static int check_bbstart(u32 *cmd, u32 offset, u32 length,
1346 u32 batch_length,
1347 u64 batch_addr,
1348 u64 shadow_addr,
1349 const unsigned long *jump_whitelist)
1350 {
1351 u64 jump_offset, jump_target;
1352 u32 target_cmd_offset, target_cmd_index;
1353
1354 /* For igt compatibility on older platforms */
1355 if (!jump_whitelist) {
1356 DRM_DEBUG("CMD: Rejecting BB_START for ggtt based submission\n");
1357 return -EACCES;
1358 }
1359
1360 if (length != 3) {
1361 DRM_DEBUG("CMD: Recursive BB_START with bad length(%u)\n",
1362 length);
1363 return -EINVAL;
1364 }
1365
1366 jump_target = *(u64 *)(cmd + 1);
1367 jump_offset = jump_target - batch_addr;
1368
1369 /*
1370 * Any underflow of jump_target is guaranteed to be outside the range
1371 * of a u32, so >= test catches both too large and too small
1372 */
1373 if (jump_offset >= batch_length) {
1374 DRM_DEBUG("CMD: BB_START to 0x%llx jumps out of BB\n",
1375 jump_target);
1376 return -EINVAL;
1377 }
1378
1379 /*
1380 * This cannot overflow a u32 because we already checked jump_offset
1381 * is within the BB, and the batch_length is a u32
1382 */
1383 target_cmd_offset = lower_32_bits(jump_offset);
1384 target_cmd_index = target_cmd_offset / sizeof(u32);
1385
1386 *(u64 *)(cmd + 1) = shadow_addr + target_cmd_offset;
1387
1388 if (target_cmd_index == offset)
1389 return 0;
1390
1391 if (IS_ERR(jump_whitelist))
1392 return PTR_ERR(jump_whitelist);
1393
1394 if (!test_bit(target_cmd_index, jump_whitelist)) {
1395 DRM_DEBUG("CMD: BB_START to 0x%llx not a previously executed cmd\n",
1396 jump_target);
1397 return -EINVAL;
1398 }
1399
1400 return 0;
1401 }
1402
alloc_whitelist(u32 batch_length)1403 static unsigned long *alloc_whitelist(u32 batch_length)
1404 {
1405 unsigned long *jmp;
1406
1407 /*
1408 * We expect batch_length to be less than 256KiB for known users,
1409 * i.e. we need at most an 8KiB bitmap allocation which should be
1410 * reasonably cheap due to kmalloc caches.
1411 */
1412
1413 /* Prefer to report transient allocation failure rather than hit oom */
1414 jmp = bitmap_zalloc(DIV_ROUND_UP(batch_length, sizeof(u32)),
1415 GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
1416 if (!jmp)
1417 return ERR_PTR(-ENOMEM);
1418
1419 return jmp;
1420 }
1421
1422 #define LENGTH_BIAS 2
1423
1424 /**
1425 * intel_engine_cmd_parser() - parse a batch buffer for privilege violations
1426 * @engine: the engine on which the batch is to execute
1427 * @batch: the batch buffer in question
1428 * @batch_offset: byte offset in the batch at which execution starts
1429 * @batch_length: length of the commands in batch_obj
1430 * @shadow: validated copy of the batch buffer in question
1431 * @trampoline: true if we need to trampoline into privileged execution
1432 *
1433 * Parses the specified batch buffer looking for privilege violations as
1434 * described in the overview.
1435 *
1436 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1437 * if the batch appears legal but should use hardware parsing
1438 */
1439
intel_engine_cmd_parser(struct intel_engine_cs * engine,struct i915_vma * batch,unsigned long batch_offset,unsigned long batch_length,struct i915_vma * shadow,bool trampoline)1440 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1441 struct i915_vma *batch,
1442 unsigned long batch_offset,
1443 unsigned long batch_length,
1444 struct i915_vma *shadow,
1445 bool trampoline)
1446 {
1447 u32 *cmd, *batch_end, offset = 0;
1448 struct drm_i915_cmd_descriptor default_desc = noop_desc;
1449 const struct drm_i915_cmd_descriptor *desc = &default_desc;
1450 bool needs_clflush_after = false;
1451 unsigned long *jump_whitelist;
1452 u64 batch_addr, shadow_addr;
1453 int ret = 0;
1454
1455 GEM_BUG_ON(!IS_ALIGNED(batch_offset, sizeof(*cmd)));
1456 GEM_BUG_ON(!IS_ALIGNED(batch_length, sizeof(*cmd)));
1457 GEM_BUG_ON(range_overflows_t(u64, batch_offset, batch_length,
1458 batch->size));
1459 GEM_BUG_ON(!batch_length);
1460
1461 cmd = copy_batch(shadow->obj, batch->obj,
1462 batch_offset, batch_length,
1463 &needs_clflush_after);
1464 if (IS_ERR(cmd)) {
1465 DRM_DEBUG("CMD: Failed to copy batch\n");
1466 return PTR_ERR(cmd);
1467 }
1468
1469 jump_whitelist = NULL;
1470 if (!trampoline)
1471 /* Defer failure until attempted use */
1472 jump_whitelist = alloc_whitelist(batch_length);
1473
1474 shadow_addr = gen8_canonical_addr(i915_vma_offset(shadow));
1475 batch_addr = gen8_canonical_addr(i915_vma_offset(batch) + batch_offset);
1476
1477 /*
1478 * We use the batch length as size because the shadow object is as
1479 * large or larger and copy_batch() will write MI_NOPs to the extra
1480 * space. Parsing should be faster in some cases this way.
1481 */
1482 batch_end = cmd + batch_length / sizeof(*batch_end);
1483 do {
1484 u32 length;
1485
1486 if (*cmd == MI_BATCH_BUFFER_END)
1487 break;
1488
1489 desc = find_cmd(engine, *cmd, desc, &default_desc);
1490 if (!desc) {
1491 DRM_DEBUG("CMD: Unrecognized command: 0x%08X\n", *cmd);
1492 ret = -EINVAL;
1493 break;
1494 }
1495
1496 if (desc->flags & CMD_DESC_FIXED)
1497 length = desc->length.fixed;
1498 else
1499 length = (*cmd & desc->length.mask) + LENGTH_BIAS;
1500
1501 if ((batch_end - cmd) < length) {
1502 DRM_DEBUG("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1503 *cmd,
1504 length,
1505 batch_end - cmd);
1506 ret = -EINVAL;
1507 break;
1508 }
1509
1510 if (!check_cmd(engine, desc, cmd, length)) {
1511 ret = -EACCES;
1512 break;
1513 }
1514
1515 if (cmd_desc_is(desc, MI_BATCH_BUFFER_START)) {
1516 ret = check_bbstart(cmd, offset, length, batch_length,
1517 batch_addr, shadow_addr,
1518 jump_whitelist);
1519 break;
1520 }
1521
1522 if (!IS_ERR_OR_NULL(jump_whitelist))
1523 __set_bit(offset, jump_whitelist);
1524
1525 cmd += length;
1526 offset += length;
1527 if (cmd >= batch_end) {
1528 DRM_DEBUG("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1529 ret = -EINVAL;
1530 break;
1531 }
1532 } while (1);
1533
1534 if (trampoline) {
1535 /*
1536 * With the trampoline, the shadow is executed twice.
1537 *
1538 * 1 - starting at offset 0, in privileged mode
1539 * 2 - starting at offset batch_len, as non-privileged
1540 *
1541 * Only if the batch is valid and safe to execute, do we
1542 * allow the first privileged execution to proceed. If not,
1543 * we terminate the first batch and use the second batchbuffer
1544 * entry to chain to the original unsafe non-privileged batch,
1545 * leaving it to the HW to validate.
1546 */
1547 *batch_end = MI_BATCH_BUFFER_END;
1548
1549 if (ret) {
1550 /* Batch unsafe to execute with privileges, cancel! */
1551 cmd = page_mask_bits(shadow->obj->mm.mapping);
1552 *cmd = MI_BATCH_BUFFER_END;
1553
1554 /* If batch is unsafe but valid, jump to the original */
1555 if (ret == -EACCES) {
1556 unsigned int flags;
1557
1558 flags = MI_BATCH_NON_SECURE_I965;
1559 if (IS_HASWELL(engine->i915))
1560 flags = MI_BATCH_NON_SECURE_HSW;
1561
1562 GEM_BUG_ON(!IS_GRAPHICS_VER(engine->i915, 6, 7));
1563 __gen6_emit_bb_start(batch_end,
1564 batch_addr,
1565 flags);
1566
1567 ret = 0; /* allow execution */
1568 }
1569 }
1570 }
1571
1572 i915_gem_object_flush_map(shadow->obj);
1573
1574 if (!IS_ERR_OR_NULL(jump_whitelist))
1575 kfree(jump_whitelist);
1576 i915_gem_object_unpin_map(shadow->obj);
1577 return ret;
1578 }
1579
1580 /**
1581 * i915_cmd_parser_get_version() - get the cmd parser version number
1582 * @dev_priv: i915 device private
1583 *
1584 * The cmd parser maintains a simple increasing integer version number suitable
1585 * for passing to userspace clients to determine what operations are permitted.
1586 *
1587 * Return: the current version number of the cmd parser
1588 */
i915_cmd_parser_get_version(struct drm_i915_private * dev_priv)1589 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)
1590 {
1591 struct intel_engine_cs *engine;
1592 bool active = false;
1593
1594 /* If the command parser is not enabled, report 0 - unsupported */
1595 for_each_uabi_engine(engine, dev_priv) {
1596 if (intel_engine_using_cmd_parser(engine)) {
1597 active = true;
1598 break;
1599 }
1600 }
1601 if (!active)
1602 return 0;
1603
1604 /*
1605 * Command parser version history
1606 *
1607 * 1. Initial version. Checks batches and reports violations, but leaves
1608 * hardware parsing enabled (so does not allow new use cases).
1609 * 2. Allow access to the MI_PREDICATE_SRC0 and
1610 * MI_PREDICATE_SRC1 registers.
1611 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
1612 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
1613 * 5. GPGPU dispatch compute indirect registers.
1614 * 6. TIMESTAMP register and Haswell CS GPR registers
1615 * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers.
1616 * 8. Don't report cmd_check() failures as EINVAL errors to userspace;
1617 * rely on the HW to NOOP disallowed commands as it would without
1618 * the parser enabled.
1619 * 9. Don't whitelist or handle oacontrol specially, as ownership
1620 * for oacontrol state is moving to i915-perf.
1621 * 10. Support for Gen9 BCS Parsing
1622 */
1623 return 10;
1624 }
1625