1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Microchip switch driver common header
3 *
4 * Copyright (C) 2017-2025 Microchip Technology Inc.
5 */
6
7 #ifndef __KSZ_COMMON_H
8 #define __KSZ_COMMON_H
9
10 #include <linux/etherdevice.h>
11 #include <linux/irqdomain.h>
12 #include <linux/kernel.h>
13 #include <linux/mutex.h>
14 #include <linux/pcs/pcs-xpcs.h>
15 #include <linux/phy.h>
16 #include <linux/regmap.h>
17 #include <net/dsa.h>
18 #include <net/pkt_cls.h>
19 #include <linux/irq.h>
20 #include <linux/platform_data/microchip-ksz.h>
21
22 #include "ksz_ptp.h"
23
24 #define KSZ_MAX_NUM_PORTS 8
25 /* all KSZ switches count ports from 1 */
26 #define KSZ_PORT_1 0
27 #define KSZ_PORT_2 1
28 #define KSZ_PORT_4 3
29
30 struct ksz_device;
31 struct ksz_port;
32 struct phylink_mac_ops;
33
34 enum ksz_regmap_width {
35 KSZ_REGMAP_8,
36 KSZ_REGMAP_16,
37 KSZ_REGMAP_32,
38 __KSZ_NUM_REGMAPS,
39 };
40
41 struct vlan_table {
42 u32 table[3];
43 };
44
45 struct ksz_stats_raw {
46 u64 rx_hi;
47 u64 rx_undersize;
48 u64 rx_fragments;
49 u64 rx_oversize;
50 u64 rx_jabbers;
51 u64 rx_symbol_err;
52 u64 rx_crc_err;
53 u64 rx_align_err;
54 u64 rx_mac_ctrl;
55 u64 rx_pause;
56 u64 rx_bcast;
57 u64 rx_mcast;
58 u64 rx_ucast;
59 u64 rx_64_or_less;
60 u64 rx_65_127;
61 u64 rx_128_255;
62 u64 rx_256_511;
63 u64 rx_512_1023;
64 u64 rx_1024_1522;
65 u64 rx_1523_2000;
66 u64 rx_2001;
67 u64 tx_hi;
68 u64 tx_late_col;
69 u64 tx_pause;
70 u64 tx_bcast;
71 u64 tx_mcast;
72 u64 tx_ucast;
73 u64 tx_deferred;
74 u64 tx_total_col;
75 u64 tx_exc_col;
76 u64 tx_single_col;
77 u64 tx_mult_col;
78 u64 rx_total;
79 u64 tx_total;
80 u64 rx_discards;
81 u64 tx_discards;
82 };
83
84 struct ksz_port_mib {
85 struct mutex cnt_mutex; /* structure access */
86 u8 cnt_ptr;
87 u64 *counters;
88 struct rtnl_link_stats64 stats64;
89 struct ethtool_pause_stats pause_stats;
90 struct spinlock stats64_lock;
91 };
92
93 struct ksz_mib_names {
94 int index;
95 char string[ETH_GSTRING_LEN];
96 };
97
98 struct ksz_chip_data {
99 u32 chip_id;
100 const char *dev_name;
101 int num_vlans;
102 int num_alus;
103 int num_statics;
104 int cpu_ports;
105 int port_cnt;
106 u8 port_nirqs;
107 u8 num_tx_queues;
108 u8 num_ipms; /* number of Internal Priority Maps */
109 bool tc_cbs_supported;
110
111 /**
112 * @phy_side_mdio_supported: Indicates if the chip supports an additional
113 * side MDIO channel for accessing integrated PHYs.
114 */
115 bool phy_side_mdio_supported;
116 const struct ksz_dev_ops *ops;
117 const struct dsa_switch_ops *switch_ops;
118 const struct phylink_mac_ops *phylink_mac_ops;
119 bool phy_errata_9477;
120 bool ksz87xx_eee_link_erratum;
121 const struct ksz_mib_names *mib_names;
122 int mib_cnt;
123 u8 reg_mib_cnt;
124 const u16 *regs;
125 const u32 *masks;
126 const u8 *shifts;
127 const u8 *xmii_ctrl0;
128 const u8 *xmii_ctrl1;
129 int stp_ctrl_reg;
130 int broadcast_ctrl_reg;
131 int multicast_ctrl_reg;
132 int start_ctrl_reg;
133 bool supports_mii[KSZ_MAX_NUM_PORTS];
134 bool supports_rmii[KSZ_MAX_NUM_PORTS];
135 bool supports_rgmii[KSZ_MAX_NUM_PORTS];
136 bool internal_phy[KSZ_MAX_NUM_PORTS];
137 bool gbit_capable[KSZ_MAX_NUM_PORTS];
138 bool ptp_capable;
139 u8 sgmii_port;
140 const struct regmap_access_table *wr_table;
141 const struct regmap_access_table *rd_table;
142 };
143
144 struct ksz_irq {
145 u16 masked;
146 u16 reg_mask;
147 u16 reg_status;
148 struct irq_domain *domain;
149 int nirqs;
150 int irq_num;
151 char name[16];
152 struct ksz_device *dev;
153 u16 irq0_offset;
154 };
155
156 struct ksz_ptp_irq {
157 struct ksz_port *port;
158 u16 ts_reg;
159 bool ts_en;
160 char name[16];
161 int num;
162 };
163
164 struct ksz_switch_macaddr {
165 unsigned char addr[ETH_ALEN];
166 refcount_t refcount;
167 };
168
169 struct ksz_port {
170 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */
171 bool learning;
172 bool isolated;
173 int stp_state;
174 int speed;
175 int duplex;
176 bool link;
177
178 u32 fiber:1; /* port is fiber */
179 u32 force:1;
180 u32 read:1; /* read MIB counters in background */
181 u32 freeze:1; /* MIB counter freeze is enabled */
182 u32 sgmii_adv_write:1;
183
184 struct ksz_port_mib mib;
185 phy_interface_t interface;
186 u32 rgmii_tx_val;
187 u32 rgmii_rx_val;
188 struct ksz_device *ksz_dev;
189 void *acl_priv;
190 struct ksz_irq pirq;
191 u8 num;
192 struct phylink_pcs *pcs;
193 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP)
194 struct kernel_hwtstamp_config tstamp_config;
195 bool hwts_tx_en;
196 bool hwts_rx_en;
197 bool last_tx_is_pdelayresp;
198 struct ksz_irq ptpirq;
199 struct ksz_ptp_irq ptpmsg_irq[3];
200 ktime_t tstamp_msg;
201 struct completion tstamp_msg_comp;
202 #endif
203 bool manual_flow;
204 };
205
206 struct ksz_device {
207 struct dsa_switch *ds;
208 struct ksz_platform_data *pdata;
209 const struct ksz_chip_data *info;
210
211 struct mutex dev_mutex; /* device access */
212 struct mutex regmap_mutex; /* regmap access */
213 struct mutex alu_mutex; /* ALU access */
214 struct mutex vlan_mutex; /* vlan access */
215 const struct ksz_dev_ops *dev_ops;
216
217 struct device *dev;
218 struct regmap *regmap[__KSZ_NUM_REGMAPS];
219
220 void *priv;
221 int irq;
222
223 struct gpio_desc *reset_gpio; /* Optional reset GPIO */
224
225 /* chip specific data */
226 u32 chip_id;
227 u8 chip_rev;
228 int cpu_port; /* port connected to CPU */
229 int phy_port_cnt;
230 phy_interface_t compat_interface;
231 bool synclko_125;
232 bool synclko_disable;
233 bool wakeup_source;
234 bool pme_active_high;
235
236 struct vlan_table *vlan_cache;
237
238 struct ksz_port *ports;
239 struct delayed_work mib_read;
240 unsigned long mib_read_interval;
241 u16 mirror_rx;
242 u16 mirror_tx;
243 u16 port_mask;
244 struct mutex lock_irq; /* IRQ Access */
245 struct ksz_irq girq;
246 struct ksz_ptp_data ptp_data;
247
248 struct ksz_switch_macaddr *switch_macaddr;
249 struct net_device *hsr_dev; /* HSR */
250 u8 hsr_ports;
251
252 /**
253 * @phy_addr_map: Array mapping switch ports to their corresponding PHY
254 * addresses.
255 */
256 u8 phy_addr_map[KSZ_MAX_NUM_PORTS];
257
258 /**
259 * @parent_mdio_bus: Pointer to the external MDIO bus controller.
260 *
261 * This points to an external MDIO bus controller that is used to access
262 * the PHYs integrated within the switch. Unlike an integrated MDIO
263 * bus, this external controller provides a direct path for managing
264 * the switch’s internal PHYs, bypassing the main SPI interface.
265 */
266 struct mii_bus *parent_mdio_bus;
267
268 /* KSZ87xx low-loss tuning state */
269 u8 lpf_bw; /* KSZ87XX_PHY_LPF_* */
270 u8 eq_init; /* DSP EQ initial value */
271 };
272
273 /* List of supported models */
274 enum ksz_model {
275 KSZ8463,
276 KSZ8563,
277 KSZ8567,
278 KSZ8795,
279 KSZ8794,
280 KSZ8765,
281 KSZ88X3,
282 KSZ8864,
283 KSZ8895,
284 KSZ9477,
285 KSZ9896,
286 KSZ9897,
287 KSZ9893,
288 KSZ9563,
289 KSZ9567,
290 LAN9370,
291 LAN9371,
292 LAN9372,
293 LAN9373,
294 LAN9374,
295 LAN9646,
296 };
297
298 enum ksz_regs {
299 REG_SW_MAC_ADDR,
300 REG_IND_CTRL_0,
301 REG_IND_DATA_8,
302 REG_IND_DATA_CHECK,
303 REG_IND_DATA_HI,
304 REG_IND_DATA_LO,
305 REG_IND_MIB_CHECK,
306 REG_IND_BYTE,
307 P_FORCE_CTRL,
308 P_LINK_STATUS,
309 P_LOCAL_CTRL,
310 P_NEG_RESTART_CTRL,
311 P_REMOTE_STATUS,
312 P_SPEED_STATUS,
313 S_TAIL_TAG_CTRL,
314 P_STP_CTRL,
315 S_START_CTRL,
316 S_BROADCAST_CTRL,
317 S_MULTICAST_CTRL,
318 P_XMII_CTRL_0,
319 P_XMII_CTRL_1,
320 REG_SW_PME_CTRL,
321 REG_PORT_PME_STATUS,
322 REG_PORT_PME_CTRL,
323 PTP_CLK_CTRL,
324 PTP_RTC_NANOSEC,
325 PTP_RTC_SEC,
326 PTP_RTC_SUB_NANOSEC,
327 PTP_SUBNANOSEC_RATE,
328 PTP_MSG_CONF1,
329 };
330
331 enum ksz_masks {
332 PORT_802_1P_REMAPPING,
333 SW_TAIL_TAG_ENABLE,
334 MIB_COUNTER_OVERFLOW,
335 MIB_COUNTER_VALID,
336 VLAN_TABLE_FID,
337 VLAN_TABLE_MEMBERSHIP,
338 VLAN_TABLE_VALID,
339 STATIC_MAC_TABLE_VALID,
340 STATIC_MAC_TABLE_USE_FID,
341 STATIC_MAC_TABLE_FID,
342 STATIC_MAC_TABLE_OVERRIDE,
343 STATIC_MAC_TABLE_FWD_PORTS,
344 DYNAMIC_MAC_TABLE_ENTRIES_H,
345 DYNAMIC_MAC_TABLE_MAC_EMPTY,
346 DYNAMIC_MAC_TABLE_NOT_READY,
347 DYNAMIC_MAC_TABLE_ENTRIES,
348 DYNAMIC_MAC_TABLE_FID,
349 DYNAMIC_MAC_TABLE_SRC_PORT,
350 DYNAMIC_MAC_TABLE_TIMESTAMP,
351 ALU_STAT_WRITE,
352 ALU_STAT_READ,
353 ALU_STAT_DIRECT,
354 ALU_RESV_MCAST_ADDR,
355 P_MII_TX_FLOW_CTRL,
356 P_MII_RX_FLOW_CTRL,
357 };
358
359 enum ksz_shifts {
360 VLAN_TABLE_MEMBERSHIP_S,
361 VLAN_TABLE,
362 STATIC_MAC_FWD_PORTS,
363 STATIC_MAC_FID,
364 DYNAMIC_MAC_ENTRIES_H,
365 DYNAMIC_MAC_ENTRIES,
366 DYNAMIC_MAC_FID,
367 DYNAMIC_MAC_TIMESTAMP,
368 DYNAMIC_MAC_SRC_PORT,
369 ALU_STAT_INDEX,
370 };
371
372 enum ksz_xmii_ctrl0 {
373 P_MII_100MBIT,
374 P_MII_10MBIT,
375 P_MII_FULL_DUPLEX,
376 P_MII_HALF_DUPLEX,
377 };
378
379 enum ksz_xmii_ctrl1 {
380 P_RGMII_SEL,
381 P_RMII_SEL,
382 P_GMII_SEL,
383 P_MII_SEL,
384 P_GMII_1GBIT,
385 P_GMII_NOT_1GBIT,
386 };
387
388 struct alu_struct {
389 /* entry 1 */
390 u8 is_static:1;
391 u8 is_src_filter:1;
392 u8 is_dst_filter:1;
393 u8 prio_age:3;
394 u32 _reserv_0_1:23;
395 u8 mstp:3;
396 /* entry 2 */
397 u8 is_override:1;
398 u8 is_use_fid:1;
399 u32 _reserv_1_1:23;
400 u8 port_forward:7;
401 /* entry 3 & 4*/
402 u32 _reserv_2_1:9;
403 u8 fid:7;
404 u8 mac[ETH_ALEN];
405 };
406
407 struct ksz_dev_ops {
408 u32 (*get_port_addr)(int port, int offset);
409 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member);
410
411 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr,
412 u64 *cnt);
413 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr,
414 u64 *dropped, u64 *cnt);
415 void (*r_mib_stat64)(struct ksz_device *dev, int port);
416 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value);
417 int (*pme_pread8)(struct ksz_device *dev, int port, int offset,
418 u8 *data);
419 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset,
420 u8 data);
421 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
422 void (*port_init_cnt)(struct ksz_device *dev, int port);
423 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val);
424 int (*init)(struct ksz_device *dev);
425 };
426
427 struct ksz_device *ksz_switch_alloc(struct device *base,
428 const struct ksz_chip_data *chip,
429 void *priv);
430 int ksz_switch_register(struct ksz_device *dev);
431 void ksz_switch_remove(struct ksz_device *dev);
432 int ksz_switch_suspend(struct device *dev);
433 int ksz_switch_resume(struct device *dev);
434
435 void ksz_teardown(struct dsa_switch *ds);
436
437 void ksz_init_mib_timer(struct ksz_device *dev);
438 void ksz_r_mib_stats64(struct ksz_device *dev, int port);
439 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
440 extern const struct ksz_chip_data ksz_switch_chips[];
441 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
442 struct netlink_ext_ack *extack);
443 void ksz_switch_macaddr_put(struct dsa_switch *ds);
444 void ksz_switch_shutdown(struct ksz_device *dev);
445 int ksz_handle_wake_reason(struct ksz_device *dev, int port);
446
447 int ksz_sset_count(struct dsa_switch *ds, int port, int sset);
448 void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
449 uint64_t *buf);
450 void ksz_get_stats64(struct dsa_switch *ds, int port,
451 struct rtnl_link_stats64 *s);
452 void ksz_get_pause_stats(struct dsa_switch *ds, int port,
453 struct ethtool_pause_stats *pause_stats);
454 void ksz_get_strings(struct dsa_switch *ds, int port,
455 u32 stringset, uint8_t *buf);
456
457 int ksz_port_bridge_join(struct dsa_switch *ds, int port,
458 struct dsa_bridge bridge,
459 bool *tx_fwd_offload,
460 struct netlink_ext_ack *extack);
461 void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
462 struct dsa_bridge bridge);
463 int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
464 struct switchdev_brport_flags flags,
465 struct netlink_ext_ack *extack);
466 int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
467 struct switchdev_brport_flags flags,
468 struct netlink_ext_ack *extack);
469
470 void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
471 struct phylink_config *config);
472 void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config);
473 int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config,
474 u32 timer, bool tx_clock_stop);
475 void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface);
476 bool ksz_phylink_need_config(struct phylink_config *config, unsigned int mode);
477 void ksz_phylink_mac_config(struct phylink_config *config,
478 unsigned int mode,
479 const struct phylink_link_state *state);
480 void ksz_phylink_mac_link_down(struct phylink_config *config,
481 unsigned int mode,
482 phy_interface_t interface);
483
484 int ksz_set_mac_eee(struct dsa_switch *ds, int port,
485 struct ethtool_keee *e);
486
487 int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
488 int band);
489 int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
490 struct tc_cbs_qopt_offload *qopt);
491 int ksz_tc_ets_validate(struct ksz_device *dev, int port,
492 struct tc_ets_qopt_offload_replace_params *p);
493 int ksz_setup_tc(struct dsa_switch *ds, int port,
494 enum tc_setup_type type, void *type_data);
495
496 void ksz_get_wol(struct dsa_switch *ds, int port,
497 struct ethtool_wolinfo *wol);
498 int ksz_set_wol(struct dsa_switch *ds, int port,
499 struct ethtool_wolinfo *wol);
500 int ksz_port_set_mac_address(struct dsa_switch *ds, int port,
501 const unsigned char *addr);
502
503 int ksz_suspend(struct dsa_switch *ds);
504 int ksz_resume(struct dsa_switch *ds);
505
506 int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus,
507 struct device_node *mdio_np);
508 int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum);
509 int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val);
510 int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum);
511 int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val);
512 int ksz_mdio_register(struct ksz_device *dev);
513 void ksz_irq_bus_lock(struct irq_data *d);
514 void ksz_irq_bus_sync_unlock(struct irq_data *d);
515 int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq,
516 const struct irq_domain_ops *ops);
517 int ksz_pirq_setup(struct ksz_device *dev, u8 p);
518 int ksz_girq_setup(struct ksz_device *dev);
519 void ksz_irq_free(struct ksz_irq *kirq);
520
521 struct ksz_driver_strength_prop {
522 const char *name;
523 int offset;
524 int value;
525 };
526
527 enum ksz_driver_strength_type {
528 KSZ_DRIVER_STRENGTH_HI,
529 KSZ_DRIVER_STRENGTH_LO,
530 KSZ_DRIVER_STRENGTH_IO,
531 };
532
533 /**
534 * struct ksz_drive_strength - drive strength mapping
535 * @reg_val: register value
536 * @microamp: microamp value
537 */
538 struct ksz_drive_strength {
539 u32 reg_val;
540 u32 microamp;
541 };
542
543 void ksz_drive_strength_error(struct ksz_device *dev,
544 const struct ksz_drive_strength *array,
545 size_t array_size, int microamp);
546 int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array,
547 size_t array_size, int microamp);
548 int ksz_drive_strength_write(struct ksz_device *dev,
549 struct ksz_driver_strength_prop *props,
550 int num_props);
551
552 /* Common register access functions */
ksz_regmap_8(struct ksz_device * dev)553 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev)
554 {
555 return dev->regmap[KSZ_REGMAP_8];
556 }
557
ksz_regmap_16(struct ksz_device * dev)558 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev)
559 {
560 return dev->regmap[KSZ_REGMAP_16];
561 }
562
ksz_regmap_32(struct ksz_device * dev)563 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev)
564 {
565 return dev->regmap[KSZ_REGMAP_32];
566 }
567
ksz_is_ksz8463(struct ksz_device * dev)568 static inline bool ksz_is_ksz8463(struct ksz_device *dev)
569 {
570 return dev->chip_id == KSZ8463_CHIP_ID;
571 }
572
ksz_read8(struct ksz_device * dev,u32 reg,u8 * val)573 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val)
574 {
575 unsigned int value;
576 int ret = regmap_read(ksz_regmap_8(dev), reg, &value);
577
578 if (ret)
579 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,
580 ERR_PTR(ret));
581
582 *val = value;
583 return ret;
584 }
585
ksz_read16(struct ksz_device * dev,u32 reg,u16 * val)586 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val)
587 {
588 unsigned int value;
589 int ret = regmap_read(ksz_regmap_16(dev), reg, &value);
590
591 if (ret)
592 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,
593 ERR_PTR(ret));
594
595 *val = value;
596 return ret;
597 }
598
ksz_read32(struct ksz_device * dev,u32 reg,u32 * val)599 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
600 {
601 unsigned int value;
602 int ret = regmap_read(ksz_regmap_32(dev), reg, &value);
603
604 if (ret)
605 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,
606 ERR_PTR(ret));
607
608 *val = value;
609 return ret;
610 }
611
ksz_read64(struct ksz_device * dev,u32 reg,u64 * val)612 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
613 {
614 u32 value[2];
615 int ret;
616
617 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2);
618 if (ret)
619 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,
620 ERR_PTR(ret));
621 else
622 *val = (u64)value[0] << 32 | value[1];
623
624 return ret;
625 }
626
ksz_write8(struct ksz_device * dev,u32 reg,u8 value)627 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
628 {
629 int ret;
630
631 ret = regmap_write(ksz_regmap_8(dev), reg, value);
632 if (ret)
633 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,
634 ERR_PTR(ret));
635
636 return ret;
637 }
638
ksz_write16(struct ksz_device * dev,u32 reg,u16 value)639 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value)
640 {
641 int ret;
642
643 ret = regmap_write(ksz_regmap_16(dev), reg, value);
644 if (ret)
645 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,
646 ERR_PTR(ret));
647
648 return ret;
649 }
650
ksz_write32(struct ksz_device * dev,u32 reg,u32 value)651 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
652 {
653 int ret;
654
655 ret = regmap_write(ksz_regmap_32(dev), reg, value);
656 if (ret)
657 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,
658 ERR_PTR(ret));
659
660 return ret;
661 }
662
ksz_rmw16(struct ksz_device * dev,u32 reg,u16 mask,u16 value)663 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask,
664 u16 value)
665 {
666 int ret;
667
668 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value);
669 if (ret)
670 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg,
671 ERR_PTR(ret));
672
673 return ret;
674 }
675
ksz_rmw32(struct ksz_device * dev,u32 reg,u32 mask,u32 value)676 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask,
677 u32 value)
678 {
679 int ret;
680
681 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value);
682 if (ret)
683 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg,
684 ERR_PTR(ret));
685
686 return ret;
687 }
688
ksz_write64(struct ksz_device * dev,u32 reg,u64 value)689 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
690 {
691 u32 val[2];
692
693 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
694 value = swab64(value);
695 val[0] = swab32(value & 0xffffffffULL);
696 val[1] = swab32(value >> 32ULL);
697
698 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2);
699 }
700
ksz_rmw8(struct ksz_device * dev,int offset,u8 mask,u8 val)701 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val)
702 {
703 int ret;
704
705 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val);
706 if (ret)
707 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset,
708 ERR_PTR(ret));
709
710 return ret;
711 }
712
ksz_pread8(struct ksz_device * dev,int port,int offset,u8 * data)713 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset,
714 u8 *data)
715 {
716 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);
717 }
718
ksz_pread16(struct ksz_device * dev,int port,int offset,u16 * data)719 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset,
720 u16 *data)
721 {
722 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);
723 }
724
ksz_pread32(struct ksz_device * dev,int port,int offset,u32 * data)725 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset,
726 u32 *data)
727 {
728 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);
729 }
730
ksz_pwrite8(struct ksz_device * dev,int port,int offset,u8 data)731 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset,
732 u8 data)
733 {
734 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);
735 }
736
ksz_pwrite16(struct ksz_device * dev,int port,int offset,u16 data)737 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset,
738 u16 data)
739 {
740 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset),
741 data);
742 }
743
ksz_pwrite32(struct ksz_device * dev,int port,int offset,u32 data)744 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset,
745 u32 data)
746 {
747 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset),
748 data);
749 }
750
ksz_prmw8(struct ksz_device * dev,int port,int offset,u8 mask,u8 val)751 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset,
752 u8 mask, u8 val)
753 {
754 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset),
755 mask, val);
756 }
757
ksz_prmw32(struct ksz_device * dev,int port,int offset,u32 mask,u32 val)758 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset,
759 u32 mask, u32 val)
760 {
761 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset),
762 mask, val);
763 }
764
ksz_regmap_lock(void * __mtx)765 static inline void ksz_regmap_lock(void *__mtx)
766 {
767 struct mutex *mtx = __mtx;
768 mutex_lock(mtx);
769 }
770
ksz_regmap_unlock(void * __mtx)771 static inline void ksz_regmap_unlock(void *__mtx)
772 {
773 struct mutex *mtx = __mtx;
774 mutex_unlock(mtx);
775 }
776
ksz_is_ksz87xx(struct ksz_device * dev)777 static inline bool ksz_is_ksz87xx(struct ksz_device *dev)
778 {
779 return dev->chip_id == KSZ8795_CHIP_ID ||
780 dev->chip_id == KSZ8794_CHIP_ID ||
781 dev->chip_id == KSZ8765_CHIP_ID;
782 }
783
ksz_is_ksz88x3(struct ksz_device * dev)784 static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
785 {
786 return dev->chip_id == KSZ88X3_CHIP_ID;
787 }
788
ksz_is_8895_family(struct ksz_device * dev)789 static inline bool ksz_is_8895_family(struct ksz_device *dev)
790 {
791 return dev->chip_id == KSZ8895_CHIP_ID ||
792 dev->chip_id == KSZ8864_CHIP_ID;
793 }
794
is_ksz8(struct ksz_device * dev)795 static inline bool is_ksz8(struct ksz_device *dev)
796 {
797 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) ||
798 ksz_is_8895_family(dev) || ksz_is_ksz8463(dev);
799 }
800
is_ksz88xx(struct ksz_device * dev)801 static inline bool is_ksz88xx(struct ksz_device *dev)
802 {
803 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev) ||
804 ksz_is_ksz8463(dev);
805 }
806
is_ksz9477(struct ksz_device * dev)807 static inline bool is_ksz9477(struct ksz_device *dev)
808 {
809 return dev->chip_id == KSZ9477_CHIP_ID;
810 }
811
is_lan937x(struct ksz_device * dev)812 static inline int is_lan937x(struct ksz_device *dev)
813 {
814 return dev->chip_id == LAN9370_CHIP_ID ||
815 dev->chip_id == LAN9371_CHIP_ID ||
816 dev->chip_id == LAN9372_CHIP_ID ||
817 dev->chip_id == LAN9373_CHIP_ID ||
818 dev->chip_id == LAN9374_CHIP_ID;
819 }
820
is_lan937x_tx_phy(struct ksz_device * dev,int port)821 static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port)
822 {
823 return (dev->chip_id == LAN9371_CHIP_ID ||
824 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4;
825 }
826
ksz_get_sgmii_port(struct ksz_device * dev)827 static inline int ksz_get_sgmii_port(struct ksz_device *dev)
828 {
829 return dev->info->sgmii_port - 1;
830 }
831
ksz_has_sgmii_port(struct ksz_device * dev)832 static inline bool ksz_has_sgmii_port(struct ksz_device *dev)
833 {
834 return dev->info->sgmii_port > 0;
835 }
836
ksz_is_sgmii_port(struct ksz_device * dev,int port)837 static inline bool ksz_is_sgmii_port(struct ksz_device *dev, int port)
838 {
839 return dev->info->sgmii_port == port + 1;
840 }
841
842 /* STP State Defines */
843 #define PORT_TX_ENABLE BIT(2)
844 #define PORT_RX_ENABLE BIT(1)
845 #define PORT_LEARN_DISABLE BIT(0)
846
847 /* Switch ID Defines */
848 #define REG_CHIP_ID0 0x00
849
850 #define SW_FAMILY_ID_M GENMASK(15, 8)
851 #define KSZ84_FAMILY_ID 0x84
852 #define KSZ87_FAMILY_ID 0x87
853 #define KSZ88_FAMILY_ID 0x88
854 #define KSZ8895_FAMILY_ID 0x95
855
856 #define KSZ8_PORT_STATUS_0 0x08
857 #define KSZ8_PORT_FIBER_MODE BIT(7)
858
859 #define SW_CHIP_ID_M GENMASK(7, 4)
860 #define KSZ87_CHIP_ID_94 0x6
861 #define KSZ87_CHIP_ID_95 0x9
862 #define KSZ88_CHIP_ID_63 0x3
863 #define KSZ8895_CHIP_ID_95 0x4
864 #define KSZ8895_CHIP_ID_95R 0x6
865
866 /* KSZ8895 specific register */
867 #define REG_KSZ8864_CHIP_ID 0xFE
868 #define SW_KSZ8864 BIT(7)
869
870 #define SW_REV_ID_M GENMASK(7, 4)
871
872 /* KSZ9893, KSZ9563, KSZ8563 specific register */
873 #define REG_CHIP_ID4 0x0f
874 #define SKU_ID_KSZ8563 0x3c
875 #define SKU_ID_KSZ9563 0x1c
876
877 /* Driver set switch broadcast storm protection at 10% rate. */
878 #define BROADCAST_STORM_PROT_RATE 10
879
880 /* 148,800 frames * 67 ms / 100 */
881 #define BROADCAST_STORM_VALUE 9969
882
883 #define BROADCAST_STORM_RATE_HI 0x07
884 #define BROADCAST_STORM_RATE_LO 0xFF
885 #define BROADCAST_STORM_RATE 0x07FF
886
887 #define MULTICAST_STORM_DISABLE BIT(6)
888
889 #define SW_START 0x01
890
891 /* xMII configuration */
892 #define P_MII_DUPLEX_M BIT(6)
893 #define P_MII_100MBIT_M BIT(4)
894
895 #define P_GMII_1GBIT_M BIT(6)
896 #define P_RGMII_ID_IG_ENABLE BIT(4)
897 #define P_RGMII_ID_EG_ENABLE BIT(3)
898 #define P_MII_MAC_MODE BIT(2)
899 #define P_MII_SEL_M 0x3
900
901 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */
902 #define PME_WOL_MAGICPKT BIT(2)
903 #define PME_WOL_LINKUP BIT(1)
904 #define PME_WOL_ENERGY BIT(0)
905
906 #define PME_ENABLE BIT(1)
907 #define PME_POLARITY BIT(0)
908
909 #define KSZ87XX_REG_INT_EN 0x7D
910 #define KSZ87XX_INT_PME_MASK BIT(4)
911
912 /* Interrupt */
913 #define REG_SW_PORT_INT_STATUS__1 0x001B
914 #define REG_SW_PORT_INT_MASK__1 0x001F
915
916 #define REG_PORT_INT_STATUS 0x001B
917 #define REG_PORT_INT_MASK 0x001F
918
919 #define PORT_SRC_PHY_INT 1
920 #define PORT_SRC_PTP_INT 2
921
922 #define KSZ8795_HUGE_PACKET_SIZE 2000
923 #define KSZ8863_HUGE_PACKET_SIZE 1916
924 #define KSZ8863_NORMAL_PACKET_SIZE 1536
925 #define KSZ8_LEGAL_PACKET_SIZE 1518
926 #define KSZ9477_MAX_FRAME_SIZE 9000
927
928 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e
929 /* Drive Strength of I/O Pad
930 * 0: 8mA, 1: 16mA
931 */
932 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6)
933
934 #define KSZ8795_REG_SW_CTRL_20 0xa3
935 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d
936 #define SW_DRIVE_STRENGTH_M 0x7
937 #define SW_DRIVE_STRENGTH_2MA 0
938 #define SW_DRIVE_STRENGTH_4MA 1
939 #define SW_DRIVE_STRENGTH_8MA 2
940 #define SW_DRIVE_STRENGTH_12MA 3
941 #define SW_DRIVE_STRENGTH_16MA 4
942 #define SW_DRIVE_STRENGTH_20MA 5
943 #define SW_DRIVE_STRENGTH_24MA 6
944 #define SW_DRIVE_STRENGTH_28MA 7
945 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4
946 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0
947
948 /* TXQ Split Control Register for per-port, per-queue configuration.
949 * Register 0xAF is TXQ Split for Q3 on Port 1.
950 * Register offset formula: 0xAF + (port * 4) + (3 - queue)
951 * where: port = 0..2, queue = 0..3
952 */
953 #define KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue) \
954 (0xAF + ((port) * 4) + (3 - (queue)))
955
956 /* Bit 7 selects between:
957 * 0 = Strict priority mode (highest-priority queue first)
958 * 1 = Weighted Fair Queuing (WFQ) mode:
959 * Queue weights: Q3:Q2:Q1:Q0 = 8:4:2:1
960 * If any queues are empty, weight is redistributed.
961 *
962 * Note: This is referred to as "Weighted Fair Queuing" (WFQ) in KSZ8863/8873
963 * documentation, and as "Weighted Round Robin" (WRR) in KSZ9477 family docs.
964 */
965 #define KSZ8873_TXQ_WFQ_ENABLE BIT(7)
966
967 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420
968 #define KSZ9477_OUT_RATE_NO_LIMIT 0
969
970 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808
971
972 #define KSZ9477_PORT_TC_MAP_S 4
973
974 /* CBS related registers */
975 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900
976
977 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914
978
979 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6)
980 #define MTI_SCHEDULE_STRICT_PRIO 0
981 #define MTI_SCHEDULE_WRR 2
982 #define MTI_SHAPING_M GENMASK(5, 4)
983 #define MTI_SHAPING_OFF 0
984 #define MTI_SHAPING_SRP 1
985 #define MTI_SHAPING_TIME_AWARE 2
986
987 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915
988 #define KSZ9477_DEFAULT_WRR_WEIGHT 1
989
990 #define REG_PORT_MTI_HI_WATER_MARK 0x0916
991 #define REG_PORT_MTI_LO_WATER_MARK 0x0918
992
993 /* Regmap tables generation */
994 #define KSZ_SPI_OP_RD 3
995 #define KSZ_SPI_OP_WR 2
996
997 #define swabnot_used(x) 0
998
999 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \
1000 swab##swp((opcode) << ((regbits) + (regpad)))
1001
1002 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \
1003 { \
1004 .name = #width, \
1005 .val_bits = (width), \
1006 .reg_stride = 1, \
1007 .reg_bits = (regbits) + (regalign), \
1008 .pad_bits = (regpad), \
1009 .max_register = BIT(regbits) - 1, \
1010 .cache_type = REGCACHE_NONE, \
1011 .read_flag_mask = \
1012 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \
1013 regbits, regpad), \
1014 .write_flag_mask = \
1015 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \
1016 regbits, regpad), \
1017 .lock = ksz_regmap_lock, \
1018 .unlock = ksz_regmap_unlock, \
1019 .reg_format_endian = REGMAP_ENDIAN_BIG, \
1020 .val_format_endian = REGMAP_ENDIAN_BIG \
1021 }
1022
1023 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \
1024 static const struct regmap_config ksz##_regmap_config[] = { \
1025 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \
1026 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \
1027 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \
1028 }
1029
1030 #define KSZ8463_REGMAP_ENTRY(width, regbits, regpad, regalign) \
1031 { \
1032 .name = #width, \
1033 .val_bits = (width), \
1034 .reg_stride = (width / 8), \
1035 .reg_bits = (regbits) + (regalign), \
1036 .pad_bits = (regpad), \
1037 .read = ksz8463_spi_read, \
1038 .write = ksz8463_spi_write, \
1039 .max_register = BIT(regbits) - 1, \
1040 .cache_type = REGCACHE_NONE, \
1041 .zero_flag_mask = 1, \
1042 .use_single_read = 1, \
1043 .use_single_write = 1, \
1044 .lock = ksz_regmap_lock, \
1045 .unlock = ksz_regmap_unlock, \
1046 }
1047
1048 #define KSZ8463_REGMAP_TABLE(ksz, regbits, regpad, regalign) \
1049 static const struct regmap_config ksz##_regmap_config[] = { \
1050 [KSZ_REGMAP_8] = KSZ8463_REGMAP_ENTRY(8, (regbits), (regpad), (regalign)), \
1051 [KSZ_REGMAP_16] = KSZ8463_REGMAP_ENTRY(16, (regbits), (regpad), (regalign)), \
1052 [KSZ_REGMAP_32] = KSZ8463_REGMAP_ENTRY(32, (regbits), (regpad), (regalign)), \
1053 }
1054
1055 #endif
1056