1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020 Intel Corporation. */
3
4 #ifndef __CXL_H__
5 #define __CXL_H__
6
7 #include <linux/libnvdimm.h>
8 #include <linux/bitfield.h>
9 #include <linux/notifier.h>
10 #include <linux/bitops.h>
11 #include <linux/log2.h>
12 #include <linux/node.h>
13 #include <linux/io.h>
14 #include <linux/range.h>
15
16 extern const struct nvdimm_security_ops *cxl_security_ops;
17
18 /**
19 * DOC: cxl objects
20 *
21 * The CXL core objects like ports, decoders, and regions are shared
22 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers
23 * (port-driver, region-driver, nvdimm object-drivers... etc).
24 */
25
26 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */
27 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K
28
29 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/
30 #define CXL_CM_OFFSET 0x1000
31 #define CXL_CM_CAP_HDR_OFFSET 0x0
32 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0)
33 #define CM_CAP_HDR_CAP_ID 1
34 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16)
35 #define CM_CAP_HDR_CAP_VERSION 1
36 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20)
37 #define CM_CAP_HDR_CACHE_MEM_VERSION 1
38 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24)
39 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20)
40
41 #define CXL_CM_CAP_CAP_ID_RAS 0x2
42 #define CXL_CM_CAP_CAP_ID_HDM 0x5
43 #define CXL_CM_CAP_CAP_HDM_VERSION 1
44
45 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
46 #define CXL_HDM_DECODER_CAP_OFFSET 0x0
47 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0)
48 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
49 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8)
50 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9)
51 #define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11)
52 #define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12)
53 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4
54 #define CXL_HDM_DECODER_ENABLE BIT(1)
55 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10)
56 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14)
57 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18)
58 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c)
59 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20)
60 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0)
61 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4)
62 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8)
63 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9)
64 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10)
65 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11)
66 #define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12)
67 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24)
68 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28)
69 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i)
70 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i)
71
72 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */
73 #define CXL_DECODER_MIN_GRANULARITY 256
74 #define CXL_DECODER_MAX_ENCODED_IG 6
75
cxl_hdm_decoder_count(u32 cap_hdr)76 static inline int cxl_hdm_decoder_count(u32 cap_hdr)
77 {
78 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
79
80 return val ? val * 2 : 1;
81 }
82
83 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
eig_to_granularity(u16 eig,unsigned int * granularity)84 static inline int eig_to_granularity(u16 eig, unsigned int *granularity)
85 {
86 if (eig > CXL_DECODER_MAX_ENCODED_IG)
87 return -EINVAL;
88 *granularity = CXL_DECODER_MIN_GRANULARITY << eig;
89 return 0;
90 }
91
92 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
eiw_to_ways(u8 eiw,unsigned int * ways)93 static inline int eiw_to_ways(u8 eiw, unsigned int *ways)
94 {
95 switch (eiw) {
96 case 0 ... 4:
97 *ways = 1 << eiw;
98 break;
99 case 8 ... 10:
100 *ways = 3 << (eiw - 8);
101 break;
102 default:
103 return -EINVAL;
104 }
105
106 return 0;
107 }
108
granularity_to_eig(int granularity,u16 * eig)109 static inline int granularity_to_eig(int granularity, u16 *eig)
110 {
111 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY ||
112 !is_power_of_2(granularity))
113 return -EINVAL;
114 *eig = ilog2(granularity) - 8;
115 return 0;
116 }
117
ways_to_eiw(unsigned int ways,u8 * eiw)118 static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
119 {
120 if (ways > 16)
121 return -EINVAL;
122 if (is_power_of_2(ways)) {
123 *eiw = ilog2(ways);
124 return 0;
125 }
126 if (ways % 3)
127 return -EINVAL;
128 ways /= 3;
129 if (!is_power_of_2(ways))
130 return -EINVAL;
131 *eiw = ilog2(ways) + 8;
132 return 0;
133 }
134
135 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */
136 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0
137 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0))
138 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4
139 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0))
140 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8)
141 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8
142 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0))
143 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC
144 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0)
145 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10
146 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0)
147 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14
148 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0)
149 #define CXL_RAS_HEADER_LOG_OFFSET 0x18
150 #define CXL_RAS_CAPABILITY_LENGTH 0x58
151 #define CXL_HEADERLOG_SIZE SZ_512
152 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32)
153
154 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
155 #define CXLDEV_CAP_ARRAY_OFFSET 0x0
156 #define CXLDEV_CAP_ARRAY_CAP_ID 0
157 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0)
158 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)
159 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */
160 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0)
161 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */
162 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1
163 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2
164 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3
165 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000
166
167 /* CXL 3.0 8.2.8.3.1 Event Status Register */
168 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00
169 #define CXLDEV_EVENT_STATUS_INFO BIT(0)
170 #define CXLDEV_EVENT_STATUS_WARN BIT(1)
171 #define CXLDEV_EVENT_STATUS_FAIL BIT(2)
172 #define CXLDEV_EVENT_STATUS_FATAL BIT(3)
173
174 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \
175 CXLDEV_EVENT_STATUS_WARN | \
176 CXLDEV_EVENT_STATUS_FAIL | \
177 CXLDEV_EVENT_STATUS_FATAL)
178
179 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */
180 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0)
181 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4)
182
183 /* CXL 2.0 8.2.8.4 Mailbox Registers */
184 #define CXLDEV_MBOX_CAPS_OFFSET 0x00
185 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0)
186 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6)
187 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7)
188 #define CXLDEV_MBOX_CTRL_OFFSET 0x04
189 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0)
190 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2)
191 #define CXLDEV_MBOX_CMD_OFFSET 0x08
192 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
193 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16)
194 #define CXLDEV_MBOX_STATUS_OFFSET 0x10
195 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0)
196 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32)
197 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18
198 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
199 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16)
200 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32)
201 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48)
202 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20
203
204 /*
205 * Using struct_group() allows for per register-block-type helper routines,
206 * without requiring block-type agnostic code to include the prefix.
207 */
208 struct cxl_regs {
209 /*
210 * Common set of CXL Component register block base pointers
211 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
212 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure
213 */
214 struct_group_tagged(cxl_component_regs, component,
215 void __iomem *hdm_decoder;
216 void __iomem *ras;
217 );
218 /*
219 * Common set of CXL Device register block base pointers
220 * @status: CXL 2.0 8.2.8.3 Device Status Registers
221 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers
222 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers
223 */
224 struct_group_tagged(cxl_device_regs, device_regs,
225 void __iomem *status, *mbox, *memdev;
226 );
227
228 struct_group_tagged(cxl_pmu_regs, pmu_regs,
229 void __iomem *pmu;
230 );
231
232 /*
233 * RCH downstream port specific RAS register
234 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB
235 */
236 struct_group_tagged(cxl_rch_regs, rch_regs,
237 void __iomem *dport_aer;
238 );
239
240 /*
241 * RCD upstream port specific PCIe cap register
242 * @pcie_cap: CXL 3.0 8.2.1.2 RCD Upstream Port RCRB
243 */
244 struct_group_tagged(cxl_rcd_regs, rcd_regs,
245 void __iomem *rcd_pcie_cap;
246 );
247 };
248
249 struct cxl_reg_map {
250 bool valid;
251 int id;
252 unsigned long offset;
253 unsigned long size;
254 };
255
256 struct cxl_component_reg_map {
257 struct cxl_reg_map hdm_decoder;
258 struct cxl_reg_map ras;
259 };
260
261 struct cxl_device_reg_map {
262 struct cxl_reg_map status;
263 struct cxl_reg_map mbox;
264 struct cxl_reg_map memdev;
265 };
266
267 struct cxl_pmu_reg_map {
268 struct cxl_reg_map pmu;
269 };
270
271 /**
272 * struct cxl_register_map - DVSEC harvested register block mapping parameters
273 * @host: device for devm operations and logging
274 * @base: virtual base of the register-block-BAR + @block_offset
275 * @resource: physical resource base of the register block
276 * @max_size: maximum mapping size to perform register search
277 * @reg_type: see enum cxl_regloc_type
278 * @component_map: cxl_reg_map for component registers
279 * @device_map: cxl_reg_maps for device registers
280 * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units
281 */
282 struct cxl_register_map {
283 struct device *host;
284 void __iomem *base;
285 resource_size_t resource;
286 resource_size_t max_size;
287 u8 reg_type;
288 union {
289 struct cxl_component_reg_map component_map;
290 struct cxl_device_reg_map device_map;
291 struct cxl_pmu_reg_map pmu_map;
292 };
293 };
294
295 void cxl_probe_component_regs(struct device *dev, void __iomem *base,
296 struct cxl_component_reg_map *map);
297 void cxl_probe_device_regs(struct device *dev, void __iomem *base,
298 struct cxl_device_reg_map *map);
299 int cxl_map_component_regs(const struct cxl_register_map *map,
300 struct cxl_component_regs *regs,
301 unsigned long map_mask);
302 int cxl_map_device_regs(const struct cxl_register_map *map,
303 struct cxl_device_regs *regs);
304 int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs);
305
306 #define CXL_INSTANCES_COUNT -1
307 enum cxl_regloc_type;
308 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type);
309 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type,
310 struct cxl_register_map *map, unsigned int index);
311 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
312 struct cxl_register_map *map);
313 int cxl_setup_regs(struct cxl_register_map *map);
314 struct cxl_dport;
315 resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
316 struct cxl_dport *dport);
317 int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport);
318
319 #define CXL_RESOURCE_NONE ((resource_size_t) -1)
320 #define CXL_TARGET_STRLEN 20
321
322 /*
323 * cxl_decoder flags that define the type of memory / devices this
324 * decoder supports as well as configuration lock status See "CXL 2.0
325 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details.
326 * Additionally indicate whether decoder settings were autodetected,
327 * user customized.
328 */
329 #define CXL_DECODER_F_RAM BIT(0)
330 #define CXL_DECODER_F_PMEM BIT(1)
331 #define CXL_DECODER_F_TYPE2 BIT(2)
332 #define CXL_DECODER_F_TYPE3 BIT(3)
333 #define CXL_DECODER_F_LOCK BIT(4)
334 #define CXL_DECODER_F_ENABLE BIT(5)
335 #define CXL_DECODER_F_NORMALIZED_ADDRESSING BIT(6)
336
337 enum cxl_decoder_type {
338 CXL_DECODER_DEVMEM = 2,
339 CXL_DECODER_HOSTONLYMEM = 3,
340 };
341
342 /*
343 * Current specification goes up to 8, double that seems a reasonable
344 * software max for the foreseeable future
345 */
346 #define CXL_DECODER_MAX_INTERLEAVE 16
347
348 #define CXL_QOS_CLASS_INVALID -1
349
350 /**
351 * struct cxl_decoder - Common CXL HDM Decoder Attributes
352 * @dev: this decoder's device
353 * @id: kernel device name id
354 * @hpa_range: Host physical address range mapped by this decoder
355 * @interleave_ways: number of cxl_dports in this decode
356 * @interleave_granularity: data stride per dport
357 * @target_type: accelerator vs expander (type2 vs type3) selector
358 * @region: currently assigned region for this decoder
359 * @flags: memory type capabilities and locking
360 * @target_map: cached copy of hardware port-id list, available at init
361 * before all @dport objects have been instantiated. While
362 * dport id is 8bit, CFMWS interleave targets are 32bits.
363 * @commit: device/decoder-type specific callback to commit settings to hw
364 * @reset: device/decoder-type specific callback to reset hw settings
365 */
366 struct cxl_decoder {
367 struct device dev;
368 int id;
369 struct range hpa_range;
370 int interleave_ways;
371 int interleave_granularity;
372 enum cxl_decoder_type target_type;
373 struct cxl_region *region;
374 unsigned long flags;
375 u32 target_map[CXL_DECODER_MAX_INTERLEAVE];
376 int (*commit)(struct cxl_decoder *cxld);
377 void (*reset)(struct cxl_decoder *cxld);
378 };
379
380 /*
381 * Track whether this decoder is reserved for region autodiscovery, or
382 * free for userspace provisioning.
383 */
384 enum cxl_decoder_state {
385 CXL_DECODER_STATE_MANUAL,
386 CXL_DECODER_STATE_AUTO,
387 };
388
389 /**
390 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder
391 * @cxld: base cxl_decoder_object
392 * @dpa_res: actively claimed DPA span of this decoder
393 * @skip: offset into @dpa_res where @cxld.hpa_range maps
394 * @state: autodiscovery state
395 * @part: partition index this decoder maps
396 * @pos: interleave position in @cxld.region
397 */
398 struct cxl_endpoint_decoder {
399 struct cxl_decoder cxld;
400 struct resource *dpa_res;
401 resource_size_t skip;
402 enum cxl_decoder_state state;
403 int part;
404 int pos;
405 };
406
407 /**
408 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder
409 * @cxld: base cxl_decoder object
410 * @nr_targets: number of elements in @target
411 * @target: active ordered target list in current decoder configuration
412 *
413 * The 'switch' decoder type represents the decoder instances of cxl_port's that
414 * route from the root of a CXL memory decode topology to the endpoints. They
415 * come in two flavors, root-level decoders, statically defined by platform
416 * firmware, and mid-level decoders, where interleave-granularity,
417 * interleave-width, and the target list are mutable.
418 */
419 struct cxl_switch_decoder {
420 struct cxl_decoder cxld;
421 int nr_targets;
422 struct cxl_dport *target[];
423 };
424
425 struct cxl_root_decoder;
426 /**
427 * struct cxl_rd_ops - CXL root decoder callback operations
428 * @hpa_to_spa: Convert host physical address to system physical address
429 * @spa_to_hpa: Convert system physical address to host physical address
430 */
431 struct cxl_rd_ops {
432 u64 (*hpa_to_spa)(struct cxl_root_decoder *cxlrd, u64 hpa);
433 u64 (*spa_to_hpa)(struct cxl_root_decoder *cxlrd, u64 spa);
434 };
435
436 /**
437 * struct cxl_root_decoder - Static platform CXL address decoder
438 * @res: host / parent resource for region allocations
439 * @cache_size: extended linear cache size if exists, otherwise zero.
440 * @region_id: region id for next region provisioning event
441 * @platform_data: platform specific configuration data
442 * @range_lock: sync region autodiscovery by address range
443 * @qos_class: QoS performance class cookie
444 * @ops: CXL root decoder operations
445 * @cxlsd: base cxl switch decoder
446 */
447 struct cxl_root_decoder {
448 struct resource *res;
449 resource_size_t cache_size;
450 atomic_t region_id;
451 void *platform_data;
452 struct mutex range_lock;
453 int qos_class;
454 struct cxl_rd_ops ops;
455 struct cxl_switch_decoder cxlsd;
456 };
457
458 /*
459 * enum cxl_config_state - State machine for region configuration
460 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely
461 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more
462 * changes to interleave_ways or interleave_granularity
463 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now
464 * active
465 * @CXL_CONFIG_RESET_PENDING: see commit_store()
466 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware
467 */
468 enum cxl_config_state {
469 CXL_CONFIG_IDLE,
470 CXL_CONFIG_INTERLEAVE_ACTIVE,
471 CXL_CONFIG_ACTIVE,
472 CXL_CONFIG_RESET_PENDING,
473 CXL_CONFIG_COMMIT,
474 };
475
476 /**
477 * struct cxl_region_params - region settings
478 * @state: allow the driver to lockdown further parameter changes
479 * @uuid: unique id for persistent regions
480 * @interleave_ways: number of endpoints in the region
481 * @interleave_granularity: capacity each endpoint contributes to a stripe
482 * @res: allocated iomem capacity for this region
483 * @targets: active ordered targets in current decoder configuration
484 * @nr_targets: number of targets
485 * @cache_size: extended linear cache size if exists, otherwise zero.
486 *
487 * State transitions are protected by cxl_rwsem.region
488 */
489 struct cxl_region_params {
490 enum cxl_config_state state;
491 uuid_t uuid;
492 int interleave_ways;
493 int interleave_granularity;
494 struct resource *res;
495 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE];
496 int nr_targets;
497 resource_size_t cache_size;
498 };
499
500 enum cxl_partition_mode {
501 CXL_PARTMODE_RAM,
502 CXL_PARTMODE_PMEM,
503 };
504
505 /*
506 * Indicate whether this region has been assembled by autodetection or
507 * userspace assembly. Prevent endpoint decoders outside of automatic
508 * detection from being added to the region.
509 */
510 #define CXL_REGION_F_AUTO 0
511
512 /*
513 * Require that a committed region successfully complete a teardown once
514 * any of its associated decoders have been torn down. This maintains
515 * the commit state for the region since there are committed decoders,
516 * but blocks cxl_region_probe().
517 */
518 #define CXL_REGION_F_NEEDS_RESET 1
519
520 /*
521 * Indicate whether this region is locked due to 1 or more decoders that have
522 * been locked. The approach of all or nothing is taken with regard to the
523 * locked attribute. CXL_REGION_F_NEEDS_RESET should not be set if this flag is
524 * set.
525 */
526 #define CXL_REGION_F_LOCK 2
527
528 /*
529 * Indicate Normalized Addressing. Use it to disable SPA conversion if
530 * HPA != SPA and an address translation callback handler does not
531 * exist. Flag is needed by AMD Zen5 platforms.
532 */
533 #define CXL_REGION_F_NORMALIZED_ADDRESSING 3
534
535 /**
536 * struct cxl_region - CXL region
537 * @dev: This region's device
538 * @id: This region's id. Id is globally unique across all regions
539 * @cxlrd: Region's root decoder
540 * @hpa_range: Address range occupied by the region
541 * @mode: Operational mode of the mapped capacity
542 * @type: Endpoint decoder target type
543 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown
544 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge
545 * @flags: Region state flags
546 * @params: active + config params for the region
547 * @coord: QoS access coordinates for the region
548 * @node_notifier: notifier for setting the access coordinates to node
549 * @adist_notifier: notifier for calculating the abstract distance of node
550 */
551 struct cxl_region {
552 struct device dev;
553 int id;
554 struct cxl_root_decoder *cxlrd;
555 struct range hpa_range;
556 enum cxl_partition_mode mode;
557 enum cxl_decoder_type type;
558 struct cxl_nvdimm_bridge *cxl_nvb;
559 struct cxl_pmem_region *cxlr_pmem;
560 unsigned long flags;
561 struct cxl_region_params params;
562 struct access_coordinate coord[ACCESS_COORDINATE_MAX];
563 struct notifier_block node_notifier;
564 struct notifier_block adist_notifier;
565 };
566
567 struct cxl_nvdimm_bridge {
568 int id;
569 struct device dev;
570 struct cxl_port *port;
571 struct nvdimm_bus *nvdimm_bus;
572 struct nvdimm_bus_descriptor nd_desc;
573 };
574
575 #define CXL_DEV_ID_LEN 19
576
577 enum {
578 CXL_NVD_F_INVALIDATED = 0,
579 };
580
581 struct cxl_nvdimm {
582 struct device dev;
583 struct cxl_memdev *cxlmd;
584 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */
585 u64 dirty_shutdowns;
586 unsigned long flags;
587 };
588
589 struct cxl_pmem_region_mapping {
590 struct cxl_memdev *cxlmd;
591 struct cxl_nvdimm *cxl_nvd;
592 u64 start;
593 u64 size;
594 int position;
595 };
596
597 struct cxl_pmem_region {
598 struct device dev;
599 struct cxl_region *cxlr;
600 struct nd_region *nd_region;
601 struct range hpa_range;
602 int nr_mappings;
603 struct cxl_pmem_region_mapping mapping[];
604 };
605
606 struct cxl_dax_region {
607 struct device dev;
608 struct cxl_region *cxlr;
609 struct range hpa_range;
610 };
611
612 /**
613 * struct cxl_port - logical collection of upstream port devices and
614 * downstream port devices to construct a CXL memory
615 * decode hierarchy.
616 * @dev: this port's device
617 * @uport_dev: PCI or platform device implementing the upstream port capability
618 * @host_bridge: Shortcut to the platform attach point for this port
619 * @id: id for port device-name
620 * @dports: cxl_dport instances referenced by decoders
621 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port
622 * @regions: cxl_region_ref instances, regions mapped by this port
623 * @parent_dport: dport that points to this port in the parent
624 * @decoder_ida: allocator for decoder ids
625 * @reg_map: component and ras register mapping parameters
626 * @regs: mapped component registers
627 * @nr_dports: number of entries in @dports
628 * @hdm_end: track last allocated HDM decoder instance for allocation ordering
629 * @commit_end: cursor to track highest committed decoder for commit ordering
630 * @dead: last ep has been removed, force port re-creation
631 * @depth: How deep this port is relative to the root. depth 0 is the root.
632 * @cdat: Cached CDAT data
633 * @cdat_available: Should a CDAT attribute be available in sysfs
634 * @pci_latency: Upstream latency in picoseconds
635 * @component_reg_phys: Physical address of component register
636 */
637 struct cxl_port {
638 struct device dev;
639 struct device *uport_dev;
640 struct device *host_bridge;
641 int id;
642 struct xarray dports;
643 struct xarray endpoints;
644 struct xarray regions;
645 struct cxl_dport *parent_dport;
646 struct ida decoder_ida;
647 struct cxl_register_map reg_map;
648 struct cxl_component_regs regs;
649 int nr_dports;
650 int hdm_end;
651 int commit_end;
652 bool dead;
653 unsigned int depth;
654 struct cxl_cdat {
655 void *table;
656 size_t length;
657 } cdat;
658 bool cdat_available;
659 long pci_latency;
660 resource_size_t component_reg_phys;
661 };
662
663 struct cxl_root;
664
665 struct cxl_root_ops {
666 int (*qos_class)(struct cxl_root *cxl_root,
667 struct access_coordinate *coord, int entries,
668 int *qos_class);
669 int (*translation_setup_root)(struct cxl_root *cxl_root, void *data);
670 };
671
672 /**
673 * struct cxl_root - logical collection of root cxl_port items
674 *
675 * @port: cxl_port member
676 * @ops: cxl root operations
677 */
678 struct cxl_root {
679 struct cxl_port port;
680 struct cxl_root_ops ops;
681 };
682
683 static inline struct cxl_root *
to_cxl_root(const struct cxl_port * port)684 to_cxl_root(const struct cxl_port *port)
685 {
686 return container_of(port, struct cxl_root, port);
687 }
688
689 static inline struct cxl_dport *
cxl_find_dport_by_dev(struct cxl_port * port,const struct device * dport_dev)690 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
691 {
692 return xa_load(&port->dports, (unsigned long)dport_dev);
693 }
694
695 struct cxl_rcrb_info {
696 resource_size_t base;
697 u16 aer_cap;
698 };
699
700 /**
701 * struct cxl_dport - CXL downstream port
702 * @dport_dev: PCI bridge or firmware device representing the downstream link
703 * @reg_map: component and ras register mapping parameters
704 * @port_id: unique hardware identifier for dport in decoder target list
705 * @rcrb: Data about the Root Complex Register Block layout
706 * @rch: Indicate whether this dport was enumerated in RCH or VH mode
707 * @port: reference to cxl_port that contains this downstream port
708 * @regs: Dport parsed register blocks
709 * @coord: access coordinates (bandwidth and latency performance attributes)
710 * @link_latency: calculated PCIe downstream latency
711 * @gpf_dvsec: Cached GPF port DVSEC
712 */
713 struct cxl_dport {
714 struct device *dport_dev;
715 struct cxl_register_map reg_map;
716 int port_id;
717 struct cxl_rcrb_info rcrb;
718 bool rch;
719 struct cxl_port *port;
720 struct cxl_regs regs;
721 struct access_coordinate coord[ACCESS_COORDINATE_MAX];
722 long link_latency;
723 int gpf_dvsec;
724 };
725
726 /**
727 * struct cxl_ep - track an endpoint's interest in a port
728 * @ep: device that hosts a generic CXL endpoint (expander or accelerator)
729 * @dport: which dport routes to this endpoint on @port
730 * @next: cxl switch port across the link attached to @dport NULL if
731 * attached to an endpoint
732 */
733 struct cxl_ep {
734 struct device *ep;
735 struct cxl_dport *dport;
736 struct cxl_port *next;
737 };
738
739 /**
740 * struct cxl_region_ref - track a region's interest in a port
741 * @port: point in topology to install this reference
742 * @decoder: decoder assigned for @region in @port
743 * @region: region for this reference
744 * @endpoints: cxl_ep references for region members beneath @port
745 * @nr_targets_set: track how many targets have been programmed during setup
746 * @nr_eps: number of endpoints beneath @port
747 * @nr_targets: number of distinct targets needed to reach @nr_eps
748 */
749 struct cxl_region_ref {
750 struct cxl_port *port;
751 struct cxl_decoder *decoder;
752 struct cxl_region *region;
753 struct xarray endpoints;
754 int nr_targets_set;
755 int nr_eps;
756 int nr_targets;
757 };
758
759 /*
760 * The platform firmware device hosting the root is also the top of the
761 * CXL port topology. All other CXL ports have another CXL port as their
762 * parent and their ->uport_dev / host device is out-of-line of the port
763 * ancestry.
764 */
is_cxl_root(struct cxl_port * port)765 static inline bool is_cxl_root(struct cxl_port *port)
766 {
767 return port->uport_dev == port->dev.parent;
768 }
769
770 /* Address translation functions exported to cxl_translate test module only */
771 int cxl_validate_translation_params(u8 eiw, u16 eig, int pos);
772 u64 cxl_calculate_hpa_offset(u64 dpa_offset, int pos, u8 eiw, u16 eig);
773 u64 cxl_calculate_dpa_offset(u64 hpa_offset, u8 eiw, u16 eig);
774 int cxl_calculate_position(u64 hpa_offset, u8 eiw, u16 eig);
775 struct cxl_cxims_data {
776 int nr_maps;
777 u64 xormaps[] __counted_by(nr_maps);
778 };
779
780 #if IS_ENABLED(CONFIG_CXL_ACPI)
781 u64 cxl_do_xormap_calc(struct cxl_cxims_data *cximsd, u64 addr, int hbiw);
782 #else
cxl_do_xormap_calc(struct cxl_cxims_data * cximsd,u64 addr,int hbiw)783 static inline u64 cxl_do_xormap_calc(struct cxl_cxims_data *cximsd, u64 addr, int hbiw)
784 {
785 return ULLONG_MAX;
786 }
787 #endif
788
789 int cxl_num_decoders_committed(struct cxl_port *port);
790 bool is_cxl_port(const struct device *dev);
791 struct cxl_port *to_cxl_port(const struct device *dev);
792 struct cxl_port *parent_port_of(struct cxl_port *port);
793 void cxl_port_commit_reap(struct cxl_decoder *cxld);
794 struct pci_bus;
795 int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev,
796 struct pci_bus *bus);
797 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
798 struct cxl_port *devm_cxl_add_port(struct device *host,
799 struct device *uport_dev,
800 resource_size_t component_reg_phys,
801 struct cxl_dport *parent_dport);
802 struct cxl_root *devm_cxl_add_root(struct device *host);
803 int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
804 struct cxl_dport *parent_dport);
805 struct cxl_root *find_cxl_root(struct cxl_port *port);
806
807 DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_device(&_T->port.dev))
808 DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev))
809 DEFINE_FREE(put_cxl_root_decoder, struct cxl_root_decoder *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->cxlsd.cxld.dev))
810 DEFINE_FREE(put_cxl_region, struct cxl_region *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev))
811
812 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
813 void cxl_bus_rescan(void);
814 void cxl_bus_drain(void);
815 struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev,
816 struct cxl_dport **dport);
817 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
818 struct cxl_dport **dport);
819 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd);
820
821 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
822 struct device *dport, int port_id,
823 resource_size_t component_reg_phys);
824 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
825 struct device *dport_dev, int port_id,
826 resource_size_t rcrb);
827
828 #ifdef CONFIG_CXL_ATL
829 void cxl_setup_prm_address_translation(struct cxl_root *cxl_root);
830 #else
831 static inline
cxl_setup_prm_address_translation(struct cxl_root * cxl_root)832 void cxl_setup_prm_address_translation(struct cxl_root *cxl_root) {}
833 #endif
834
835 struct cxl_decoder *to_cxl_decoder(struct device *dev);
836 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
837 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);
838 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev);
839 bool is_root_decoder(struct device *dev);
840 bool is_switch_decoder(struct device *dev);
841 bool is_endpoint_decoder(struct device *dev);
842 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
843 unsigned int nr_targets);
844 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
845 unsigned int nr_targets);
846 int cxl_decoder_add(struct cxl_decoder *cxld);
847 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
848 int cxl_decoder_add_locked(struct cxl_decoder *cxld);
849 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
cxl_root_decoder_autoremove(struct device * host,struct cxl_root_decoder * cxlrd)850 static inline int cxl_root_decoder_autoremove(struct device *host,
851 struct cxl_root_decoder *cxlrd)
852 {
853 return cxl_decoder_autoremove(host, &cxlrd->cxlsd.cxld);
854 }
855 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint);
856
857 /**
858 * struct cxl_endpoint_dvsec_info - Cached DVSEC info
859 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time
860 * @ranges: Number of active HDM ranges this device uses.
861 * @port: endpoint port associated with this info instance
862 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
863 */
864 struct cxl_endpoint_dvsec_info {
865 bool mem_enabled;
866 int ranges;
867 struct cxl_port *port;
868 struct range dvsec_range[2];
869 };
870
871 int devm_cxl_switch_port_decoders_setup(struct cxl_port *port);
872 int devm_cxl_endpoint_decoders_setup(struct cxl_port *port);
873 void cxl_port_update_decoder_targets(struct cxl_port *port,
874 struct cxl_dport *dport);
875 int cxl_port_setup_regs(struct cxl_port *port,
876 resource_size_t component_reg_phys);
877
878 struct cxl_dev_state;
879 int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds,
880 struct cxl_endpoint_dvsec_info *info);
881
882 bool is_cxl_region(struct device *dev);
883
884 extern const struct bus_type cxl_bus_type;
885
886 /*
887 * Note, add_dport() is expressly for the cxl_port driver. TODO: investigate a
888 * type-safe driver model where probe()/remove() take the type of object implied
889 * by @id and the add_dport() op only defined for the CXL_DEVICE_PORT driver
890 * template.
891 */
892 struct cxl_driver {
893 const char *name;
894 int (*probe)(struct device *dev);
895 void (*remove)(struct device *dev);
896 struct cxl_dport *(*add_dport)(struct cxl_port *port,
897 struct device *dport_dev);
898 struct device_driver drv;
899 int id;
900 };
901
902 #define to_cxl_drv(__drv) container_of_const(__drv, struct cxl_driver, drv)
903
904 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner,
905 const char *modname);
906 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME)
907 void cxl_driver_unregister(struct cxl_driver *cxl_drv);
908
909 #define module_cxl_driver(__cxl_driver) \
910 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister)
911
912 #define CXL_DEVICE_NVDIMM_BRIDGE 1
913 #define CXL_DEVICE_NVDIMM 2
914 #define CXL_DEVICE_PORT 3
915 #define CXL_DEVICE_ROOT 4
916 #define CXL_DEVICE_MEMORY_EXPANDER 5
917 #define CXL_DEVICE_REGION 6
918 #define CXL_DEVICE_PMEM_REGION 7
919 #define CXL_DEVICE_DAX_REGION 8
920 #define CXL_DEVICE_PMU 9
921
922 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
923 #define CXL_MODALIAS_FMT "cxl:t%d"
924
925 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev);
926 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
927 struct cxl_port *port);
928 struct cxl_nvdimm_bridge *__devm_cxl_add_nvdimm_bridge(struct device *host,
929 struct cxl_port *port);
930 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev);
931 bool is_cxl_nvdimm(struct device *dev);
932 int devm_cxl_add_nvdimm(struct device *host, struct cxl_port *port,
933 struct cxl_memdev *cxlmd);
934 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port);
935
936 #ifdef CONFIG_CXL_REGION
937 bool is_cxl_pmem_region(struct device *dev);
938 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev);
939 int cxl_add_to_region(struct cxl_endpoint_decoder *cxled);
940 struct cxl_dax_region *to_cxl_dax_region(struct device *dev);
941 u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, u64 spa);
942 #else
is_cxl_pmem_region(struct device * dev)943 static inline bool is_cxl_pmem_region(struct device *dev)
944 {
945 return false;
946 }
to_cxl_pmem_region(struct device * dev)947 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev)
948 {
949 return NULL;
950 }
cxl_add_to_region(struct cxl_endpoint_decoder * cxled)951 static inline int cxl_add_to_region(struct cxl_endpoint_decoder *cxled)
952 {
953 return 0;
954 }
to_cxl_dax_region(struct device * dev)955 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev)
956 {
957 return NULL;
958 }
cxl_port_get_spa_cache_alias(struct cxl_port * endpoint,u64 spa)959 static inline u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint,
960 u64 spa)
961 {
962 return 0;
963 }
964 #endif
965
966 void cxl_endpoint_parse_cdat(struct cxl_port *port);
967 void cxl_switch_parse_cdat(struct cxl_dport *dport);
968
969 int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
970 struct access_coordinate *coord);
971 void cxl_region_perf_data_calculate(struct cxl_region *cxlr,
972 struct cxl_endpoint_decoder *cxled);
973 void cxl_region_shared_upstream_bandwidth_update(struct cxl_region *cxlr);
974
975 void cxl_memdev_update_perf(struct cxl_memdev *cxlmd);
976
977 void cxl_coordinates_combine(struct access_coordinate *out,
978 struct access_coordinate *c1,
979 struct access_coordinate *c2);
980
981 bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port);
982 struct cxl_dport *devm_cxl_add_dport_by_dev(struct cxl_port *port,
983 struct device *dport_dev);
984
985 /*
986 * Unit test builds overrides this to __weak, find the 'strong' version
987 * of these symbols in tools/testing/cxl/.
988 */
989 #ifndef __mock
990 #define __mock static
991 #endif
992
993 u16 cxl_gpf_get_dvsec(struct device *dev);
994
995 #endif /* __CXL_H__ */
996