1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5677-spi.c -- RT5677 ALSA SoC audio codec driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Oder Chiou <oder_chiou@realtek.com> 7 */ 8 9 #include <linux/cleanup.h> 10 #include <linux/module.h> 11 #include <linux/input.h> 12 #include <linux/spi/spi.h> 13 #include <linux/device.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/slab.h> 19 #include <linux/sched.h> 20 #include <linux/uaccess.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/pm_qos.h> 23 #include <linux/sysfs.h> 24 #include <linux/clk.h> 25 #include <linux/firmware.h> 26 #include <linux/acpi.h> 27 28 #include <sound/soc.h> 29 30 #include "rt5677.h" 31 #include "rt5677-spi.h" 32 33 #define DRV_NAME "rt5677spi" 34 35 #define RT5677_SPI_BURST_LEN 240 36 #define RT5677_SPI_HEADER 5 37 #define RT5677_SPI_FREQ 6000000 38 39 /* The AddressPhase and DataPhase of SPI commands are MSB first on the wire. 40 * DataPhase word size of 16-bit commands is 2 bytes. 41 * DataPhase word size of 32-bit commands is 4 bytes. 42 * DataPhase word size of burst commands is 8 bytes. 43 * The DSP CPU is little-endian. 44 */ 45 #define RT5677_SPI_WRITE_BURST 0x5 46 #define RT5677_SPI_READ_BURST 0x4 47 #define RT5677_SPI_WRITE_32 0x3 48 #define RT5677_SPI_READ_32 0x2 49 #define RT5677_SPI_WRITE_16 0x1 50 #define RT5677_SPI_READ_16 0x0 51 52 #define RT5677_BUF_BYTES_TOTAL 0x20000 53 #define RT5677_MIC_BUF_ADDR 0x60030000 54 #define RT5677_MODEL_ADDR 0x5FFC9800 55 #define RT5677_MIC_BUF_BYTES ((u32)(RT5677_BUF_BYTES_TOTAL - \ 56 sizeof(u32))) 57 #define RT5677_MIC_BUF_FIRST_READ_SIZE 0x10000 58 59 static struct spi_device *g_spi; 60 static DEFINE_MUTEX(spi_mutex); 61 /* Serializes access to the DSP context against the exported hotword callback */ 62 static DEFINE_MUTEX(dsp_lock); 63 64 struct rt5677_dsp { 65 struct device *dev; 66 struct delayed_work copy_work; 67 struct mutex dma_lock; 68 struct snd_pcm_substream *substream; 69 size_t dma_offset; /* zero-based offset into runtime->dma_area */ 70 size_t avail_bytes; /* number of new bytes since last period */ 71 u32 mic_read_offset; /* zero-based offset into DSP's mic buffer */ 72 bool new_hotword; /* a new hotword is fired */ 73 }; 74 75 static const struct snd_pcm_hardware rt5677_spi_pcm_hardware = { 76 .info = SNDRV_PCM_INFO_MMAP | 77 SNDRV_PCM_INFO_MMAP_VALID | 78 SNDRV_PCM_INFO_INTERLEAVED, 79 .formats = SNDRV_PCM_FMTBIT_S16_LE, 80 .period_bytes_min = PAGE_SIZE, 81 .period_bytes_max = RT5677_BUF_BYTES_TOTAL / 8, 82 .periods_min = 8, 83 .periods_max = 8, 84 .channels_min = 1, 85 .channels_max = 1, 86 .buffer_bytes_max = RT5677_BUF_BYTES_TOTAL, 87 }; 88 89 static struct snd_soc_dai_driver rt5677_spi_dai = { 90 /* The DAI name "rt5677-dsp-cpu-dai" is not used. The actual DAI name 91 * registered with ASoC is the name of the device "spi-RT5677AA:00", 92 * because we only have one DAI. See snd_soc_register_dais(). 93 */ 94 .name = "rt5677-dsp-cpu-dai", 95 .id = 0, 96 .capture = { 97 .stream_name = "DSP Capture", 98 .channels_min = 1, 99 .channels_max = 1, 100 .rates = SNDRV_PCM_RATE_16000, 101 .formats = SNDRV_PCM_FMTBIT_S16_LE, 102 }, 103 }; 104 105 /* PCM for streaming audio from the DSP buffer */ 106 static int rt5677_spi_pcm_open( 107 struct snd_soc_component *component, 108 struct snd_pcm_substream *substream) 109 { 110 snd_soc_set_runtime_hwparams(substream, &rt5677_spi_pcm_hardware); 111 return 0; 112 } 113 114 static int rt5677_spi_pcm_close( 115 struct snd_soc_component *component, 116 struct snd_pcm_substream *substream) 117 { 118 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 119 struct snd_soc_component *codec_component = 120 snd_soc_rtdcom_lookup(rtd, "rt5677"); 121 struct rt5677_priv *rt5677 = 122 snd_soc_component_get_drvdata(codec_component); 123 struct rt5677_dsp *rt5677_dsp = 124 snd_soc_component_get_drvdata(component); 125 126 cancel_delayed_work_sync(&rt5677_dsp->copy_work); 127 rt5677->set_dsp_vad(codec_component, false); 128 return 0; 129 } 130 131 static int rt5677_spi_hw_params( 132 struct snd_soc_component *component, 133 struct snd_pcm_substream *substream, 134 struct snd_pcm_hw_params *hw_params) 135 { 136 struct rt5677_dsp *rt5677_dsp = 137 snd_soc_component_get_drvdata(component); 138 139 guard(mutex)(&rt5677_dsp->dma_lock); 140 rt5677_dsp->substream = substream; 141 142 return 0; 143 } 144 145 static int rt5677_spi_hw_free( 146 struct snd_soc_component *component, 147 struct snd_pcm_substream *substream) 148 { 149 struct rt5677_dsp *rt5677_dsp = 150 snd_soc_component_get_drvdata(component); 151 152 guard(mutex)(&rt5677_dsp->dma_lock); 153 rt5677_dsp->substream = NULL; 154 155 return 0; 156 } 157 158 static int rt5677_spi_prepare( 159 struct snd_soc_component *component, 160 struct snd_pcm_substream *substream) 161 { 162 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 163 struct snd_soc_component *rt5677_component = 164 snd_soc_rtdcom_lookup(rtd, "rt5677"); 165 struct rt5677_priv *rt5677 = 166 snd_soc_component_get_drvdata(rt5677_component); 167 struct rt5677_dsp *rt5677_dsp = 168 snd_soc_component_get_drvdata(component); 169 170 rt5677->set_dsp_vad(rt5677_component, true); 171 rt5677_dsp->dma_offset = 0; 172 rt5677_dsp->avail_bytes = 0; 173 return 0; 174 } 175 176 static snd_pcm_uframes_t rt5677_spi_pcm_pointer( 177 struct snd_soc_component *component, 178 struct snd_pcm_substream *substream) 179 { 180 struct snd_pcm_runtime *runtime = substream->runtime; 181 struct rt5677_dsp *rt5677_dsp = 182 snd_soc_component_get_drvdata(component); 183 184 return bytes_to_frames(runtime, rt5677_dsp->dma_offset); 185 } 186 187 static int rt5677_spi_mic_write_offset(u32 *mic_write_offset) 188 { 189 int ret; 190 /* Grab the first 4 bytes that hold the write pointer on the 191 * dsp, and check to make sure that it points somewhere inside the 192 * buffer. 193 */ 194 ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR, mic_write_offset, 195 sizeof(u32)); 196 if (ret) 197 return ret; 198 /* Adjust the offset so that it's zero-based */ 199 *mic_write_offset = *mic_write_offset - sizeof(u32); 200 return *mic_write_offset < RT5677_MIC_BUF_BYTES ? 0 : -EFAULT; 201 } 202 203 /* 204 * Copy one contiguous block of audio samples from the DSP mic buffer to the 205 * dma_area of the pcm runtime. The receiving buffer may wrap around. 206 * @begin: start offset of the block to copy, in bytes. 207 * @end: offset of the first byte after the block to copy, must be greater 208 * than or equal to begin. 209 * 210 * Return: Zero if successful, or a negative error code on failure. 211 */ 212 static int rt5677_spi_copy_block(struct rt5677_dsp *rt5677_dsp, 213 u32 begin, u32 end) 214 { 215 struct snd_pcm_runtime *runtime = rt5677_dsp->substream->runtime; 216 size_t bytes_per_frame = frames_to_bytes(runtime, 1); 217 size_t first_chunk_len, second_chunk_len; 218 int ret; 219 220 if (begin > end || runtime->dma_bytes < 2 * bytes_per_frame) { 221 dev_err(rt5677_dsp->dev, 222 "Invalid copy from (%u, %u), dma_area size %zu\n", 223 begin, end, runtime->dma_bytes); 224 return -EINVAL; 225 } 226 227 /* The block to copy is empty */ 228 if (begin == end) 229 return 0; 230 231 /* If the incoming chunk is too big for the receiving buffer, only the 232 * last "receiving buffer size - one frame" bytes are copied. 233 */ 234 if (end - begin > runtime->dma_bytes - bytes_per_frame) 235 begin = end - (runtime->dma_bytes - bytes_per_frame); 236 237 /* May need to split to two chunks, calculate the size of each */ 238 first_chunk_len = end - begin; 239 second_chunk_len = 0; 240 if (rt5677_dsp->dma_offset + first_chunk_len > runtime->dma_bytes) { 241 /* Receiving buffer wrapped around */ 242 second_chunk_len = first_chunk_len; 243 first_chunk_len = runtime->dma_bytes - rt5677_dsp->dma_offset; 244 second_chunk_len -= first_chunk_len; 245 } 246 247 /* Copy first chunk */ 248 ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR + sizeof(u32) + begin, 249 runtime->dma_area + rt5677_dsp->dma_offset, 250 first_chunk_len); 251 if (ret) 252 return ret; 253 rt5677_dsp->dma_offset += first_chunk_len; 254 if (rt5677_dsp->dma_offset == runtime->dma_bytes) 255 rt5677_dsp->dma_offset = 0; 256 257 /* Copy second chunk */ 258 if (second_chunk_len) { 259 ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR + sizeof(u32) + 260 begin + first_chunk_len, runtime->dma_area, 261 second_chunk_len); 262 if (!ret) 263 rt5677_dsp->dma_offset = second_chunk_len; 264 } 265 return ret; 266 } 267 268 /* 269 * Copy a given amount of audio samples from the DSP mic buffer starting at 270 * mic_read_offset, to the dma_area of the pcm runtime. The source buffer may 271 * wrap around. mic_read_offset is updated after successful copy. 272 * @amount: amount of samples to copy, in bytes. 273 * 274 * Return: Zero if successful, or a negative error code on failure. 275 */ 276 static int rt5677_spi_copy(struct rt5677_dsp *rt5677_dsp, u32 amount) 277 { 278 int ret = 0; 279 u32 target; 280 281 if (amount == 0) 282 return ret; 283 284 target = rt5677_dsp->mic_read_offset + amount; 285 /* Copy the first chunk in DSP's mic buffer */ 286 ret |= rt5677_spi_copy_block(rt5677_dsp, rt5677_dsp->mic_read_offset, 287 min(target, RT5677_MIC_BUF_BYTES)); 288 289 if (target >= RT5677_MIC_BUF_BYTES) { 290 /* Wrap around, copy the second chunk */ 291 target -= RT5677_MIC_BUF_BYTES; 292 ret |= rt5677_spi_copy_block(rt5677_dsp, 0, target); 293 } 294 295 if (!ret) 296 rt5677_dsp->mic_read_offset = target; 297 return ret; 298 } 299 300 /* 301 * A delayed work that streams audio samples from the DSP mic buffer to the 302 * dma_area of the pcm runtime via SPI. 303 */ 304 static void rt5677_spi_copy_work(struct work_struct *work) 305 { 306 struct rt5677_dsp *rt5677_dsp = 307 container_of(work, struct rt5677_dsp, copy_work.work); 308 struct snd_pcm_runtime *runtime; 309 u32 mic_write_offset; 310 size_t new_bytes, copy_bytes, period_bytes; 311 unsigned int delay; 312 int ret = 0; 313 314 /* Ensure runtime->dma_area buffer does not go away while copying. */ 315 guard(mutex)(&rt5677_dsp->dma_lock); 316 if (!rt5677_dsp->substream) { 317 dev_err(rt5677_dsp->dev, "No pcm substream\n"); 318 return; 319 } 320 321 runtime = rt5677_dsp->substream->runtime; 322 323 if (rt5677_spi_mic_write_offset(&mic_write_offset)) { 324 dev_err(rt5677_dsp->dev, "No mic_write_offset\n"); 325 return; 326 } 327 328 /* If this is the first time that we've asked for streaming data after 329 * a hotword is fired, we should start reading from the previous 2 330 * seconds of audio from wherever the mic_write_offset is currently. 331 */ 332 if (rt5677_dsp->new_hotword) { 333 rt5677_dsp->new_hotword = false; 334 /* See if buffer wraparound happens */ 335 if (mic_write_offset < RT5677_MIC_BUF_FIRST_READ_SIZE) 336 rt5677_dsp->mic_read_offset = RT5677_MIC_BUF_BYTES - 337 (RT5677_MIC_BUF_FIRST_READ_SIZE - 338 mic_write_offset); 339 else 340 rt5677_dsp->mic_read_offset = mic_write_offset - 341 RT5677_MIC_BUF_FIRST_READ_SIZE; 342 } 343 344 /* Calculate the amount of new samples in bytes */ 345 if (rt5677_dsp->mic_read_offset <= mic_write_offset) 346 new_bytes = mic_write_offset - rt5677_dsp->mic_read_offset; 347 else 348 new_bytes = RT5677_MIC_BUF_BYTES + mic_write_offset 349 - rt5677_dsp->mic_read_offset; 350 351 /* Copy all new samples from DSP mic buffer, one period at a time */ 352 period_bytes = snd_pcm_lib_period_bytes(rt5677_dsp->substream); 353 while (new_bytes) { 354 copy_bytes = min(new_bytes, period_bytes 355 - rt5677_dsp->avail_bytes); 356 ret = rt5677_spi_copy(rt5677_dsp, copy_bytes); 357 if (ret) { 358 dev_err(rt5677_dsp->dev, "Copy failed %d\n", ret); 359 return; 360 } 361 rt5677_dsp->avail_bytes += copy_bytes; 362 if (rt5677_dsp->avail_bytes >= period_bytes) { 363 snd_pcm_period_elapsed(rt5677_dsp->substream); 364 rt5677_dsp->avail_bytes = 0; 365 } 366 new_bytes -= copy_bytes; 367 } 368 369 delay = bytes_to_frames(runtime, period_bytes) / runtime->rate; 370 schedule_delayed_work(&rt5677_dsp->copy_work, secs_to_jiffies(delay)); 371 } 372 373 static int rt5677_spi_pcm_new(struct snd_soc_component *component, 374 struct snd_soc_pcm_runtime *rtd) 375 { 376 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_VMALLOC, 377 NULL, 0, 0); 378 return 0; 379 } 380 381 static int rt5677_spi_pcm_probe(struct snd_soc_component *component) 382 { 383 struct rt5677_dsp *rt5677_dsp; 384 385 rt5677_dsp = kzalloc_obj(*rt5677_dsp); 386 if (!rt5677_dsp) 387 return -ENOMEM; 388 rt5677_dsp->dev = &g_spi->dev; 389 mutex_init(&rt5677_dsp->dma_lock); 390 INIT_DELAYED_WORK(&rt5677_dsp->copy_work, rt5677_spi_copy_work); 391 392 snd_soc_component_set_drvdata(component, rt5677_dsp); 393 return 0; 394 } 395 396 static void rt5677_spi_pcm_remove(struct snd_soc_component *component) 397 { 398 struct rt5677_dsp *rt5677_dsp = 399 snd_soc_component_get_drvdata(component); 400 401 scoped_guard(mutex, &dsp_lock) 402 snd_soc_component_set_drvdata(component, NULL); 403 404 cancel_delayed_work_sync(&rt5677_dsp->copy_work); 405 mutex_destroy(&rt5677_dsp->dma_lock); 406 kfree(rt5677_dsp); 407 } 408 409 static const struct snd_soc_component_driver rt5677_spi_dai_component = { 410 .name = DRV_NAME, 411 .probe = rt5677_spi_pcm_probe, 412 .remove = rt5677_spi_pcm_remove, 413 .open = rt5677_spi_pcm_open, 414 .close = rt5677_spi_pcm_close, 415 .hw_params = rt5677_spi_hw_params, 416 .hw_free = rt5677_spi_hw_free, 417 .prepare = rt5677_spi_prepare, 418 .pointer = rt5677_spi_pcm_pointer, 419 .pcm_new = rt5677_spi_pcm_new, 420 .legacy_dai_naming = 1, 421 }; 422 423 /* Select a suitable transfer command for the next transfer to ensure 424 * the transfer address is always naturally aligned while minimizing 425 * the total number of transfers required. 426 * 427 * 3 transfer commands are available: 428 * RT5677_SPI_READ/WRITE_16: Transfer 2 bytes 429 * RT5677_SPI_READ/WRITE_32: Transfer 4 bytes 430 * RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes 431 * 432 * Note: 433 * 16 Bit writes and reads are restricted to the address range 434 * 0x18020000 ~ 0x18021000 435 * 436 * For example, reading 256 bytes at 0x60030004 uses the following commands: 437 * 0x60030004 RT5677_SPI_READ_32 4 bytes 438 * 0x60030008 RT5677_SPI_READ_BURST 240 bytes 439 * 0x600300F8 RT5677_SPI_READ_BURST 8 bytes 440 * 0x60030100 RT5677_SPI_READ_32 4 bytes 441 * 442 * Input: 443 * @read: true for read commands; false for write commands 444 * @align: alignment of the next transfer address 445 * @remain: number of bytes remaining to transfer 446 * 447 * Output: 448 * @len: number of bytes to transfer with the selected command 449 * Returns the selected command 450 */ 451 static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len) 452 { 453 u8 cmd; 454 455 if (align == 4 || remain <= 4) { 456 cmd = RT5677_SPI_READ_32; 457 *len = 4; 458 } else { 459 cmd = RT5677_SPI_READ_BURST; 460 *len = (((remain - 1) >> 3) + 1) << 3; 461 *len = min_t(u32, *len, RT5677_SPI_BURST_LEN); 462 } 463 return read ? cmd : cmd + 1; 464 } 465 466 /* Copy dstlen bytes from src to dst, while reversing byte order for each word. 467 * If srclen < dstlen, zeros are padded. 468 */ 469 static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen) 470 { 471 u32 w, i, si; 472 u32 word_size = min_t(u32, dstlen, 8); 473 474 for (w = 0; w < dstlen; w += word_size) { 475 for (i = 0; i < word_size && i + w < dstlen; i++) { 476 si = w + word_size - i - 1; 477 dst[w + i] = si < srclen ? src[si] : 0; 478 } 479 } 480 } 481 482 /* Read DSP address space using SPI. addr and len have to be 4-byte aligned. */ 483 int rt5677_spi_read(u32 addr, void *rxbuf, size_t len) 484 { 485 u32 offset; 486 int status = 0; 487 struct spi_transfer t[2]; 488 struct spi_message m; 489 /* +4 bytes is for the DummyPhase following the AddressPhase */ 490 u8 header[RT5677_SPI_HEADER + 4]; 491 u8 body[RT5677_SPI_BURST_LEN]; 492 u8 spi_cmd; 493 u8 *cb = rxbuf; 494 495 if (!g_spi) 496 return -ENODEV; 497 498 if ((addr & 3) || (len & 3)) { 499 dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len); 500 return -EACCES; 501 } 502 503 memset(t, 0, sizeof(t)); 504 t[0].tx_buf = header; 505 t[0].len = sizeof(header); 506 t[0].speed_hz = RT5677_SPI_FREQ; 507 t[1].rx_buf = body; 508 t[1].speed_hz = RT5677_SPI_FREQ; 509 spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); 510 511 for (offset = 0; offset < len; offset += t[1].len) { 512 spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7, 513 len - offset, &t[1].len); 514 515 /* Construct SPI message header */ 516 header[0] = spi_cmd; 517 header[1] = ((addr + offset) & 0xff000000) >> 24; 518 header[2] = ((addr + offset) & 0x00ff0000) >> 16; 519 header[3] = ((addr + offset) & 0x0000ff00) >> 8; 520 header[4] = ((addr + offset) & 0x000000ff) >> 0; 521 522 scoped_guard(mutex, &spi_mutex) 523 status |= spi_sync(g_spi, &m); 524 525 /* Copy data back to caller buffer */ 526 rt5677_spi_reverse(cb + offset, len - offset, body, t[1].len); 527 } 528 return status; 529 } 530 EXPORT_SYMBOL_GPL(rt5677_spi_read); 531 532 /* Write DSP address space using SPI. addr has to be 4-byte aligned. 533 * If len is not 4-byte aligned, then extra zeros are written at the end 534 * as padding. 535 */ 536 int rt5677_spi_write(u32 addr, const void *txbuf, size_t len) 537 { 538 u32 offset; 539 int status = 0; 540 struct spi_transfer t; 541 struct spi_message m; 542 /* +1 byte is for the DummyPhase following the DataPhase */ 543 u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1]; 544 u8 *body = buf + RT5677_SPI_HEADER; 545 u8 spi_cmd; 546 const u8 *cb = txbuf; 547 548 if (!g_spi) 549 return -ENODEV; 550 551 if (addr & 3) { 552 dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len); 553 return -EACCES; 554 } 555 556 memset(&t, 0, sizeof(t)); 557 t.tx_buf = buf; 558 t.speed_hz = RT5677_SPI_FREQ; 559 spi_message_init_with_transfers(&m, &t, 1); 560 561 for (offset = 0; offset < len;) { 562 spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7, 563 len - offset, &t.len); 564 565 /* Construct SPI message header */ 566 buf[0] = spi_cmd; 567 buf[1] = ((addr + offset) & 0xff000000) >> 24; 568 buf[2] = ((addr + offset) & 0x00ff0000) >> 16; 569 buf[3] = ((addr + offset) & 0x0000ff00) >> 8; 570 buf[4] = ((addr + offset) & 0x000000ff) >> 0; 571 572 /* Fetch data from caller buffer */ 573 rt5677_spi_reverse(body, t.len, cb + offset, len - offset); 574 offset += t.len; 575 t.len += RT5677_SPI_HEADER + 1; 576 577 scoped_guard(mutex, &spi_mutex) 578 status |= spi_sync(g_spi, &m); 579 } 580 return status; 581 } 582 EXPORT_SYMBOL_GPL(rt5677_spi_write); 583 584 int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw) 585 { 586 return rt5677_spi_write(addr, fw->data, fw->size); 587 } 588 EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware); 589 590 void rt5677_spi_hotword_detected(void) 591 { 592 struct rt5677_dsp *rt5677_dsp; 593 594 if (!g_spi) 595 return; 596 597 guard(mutex)(&dsp_lock); 598 599 rt5677_dsp = dev_get_drvdata(&g_spi->dev); 600 if (!rt5677_dsp) { 601 dev_err(&g_spi->dev, "Can't get rt5677_dsp\n"); 602 return; 603 } 604 605 scoped_guard(mutex, &rt5677_dsp->dma_lock) { 606 dev_info(rt5677_dsp->dev, "Hotword detected\n"); 607 rt5677_dsp->new_hotword = true; 608 } 609 610 schedule_delayed_work(&rt5677_dsp->copy_work, 0); 611 } 612 EXPORT_SYMBOL_GPL(rt5677_spi_hotword_detected); 613 614 static int rt5677_spi_probe(struct spi_device *spi) 615 { 616 int ret; 617 618 g_spi = spi; 619 620 ret = devm_snd_soc_register_component(&spi->dev, 621 &rt5677_spi_dai_component, 622 &rt5677_spi_dai, 1); 623 if (ret < 0) 624 dev_err(&spi->dev, "Failed to register component.\n"); 625 626 return ret; 627 } 628 629 #ifdef CONFIG_ACPI 630 static const struct acpi_device_id rt5677_spi_acpi_id[] = { 631 { "10EC5677" }, 632 { "RT5677AA" }, 633 { } 634 }; 635 MODULE_DEVICE_TABLE(acpi, rt5677_spi_acpi_id); 636 #endif 637 638 static const struct spi_device_id rt5677_spi_ids[] = { 639 { "rt5677", 0 }, 640 { }, 641 }; 642 MODULE_DEVICE_TABLE(spi, rt5677_spi_ids); 643 644 static struct spi_driver rt5677_spi_driver = { 645 .driver = { 646 .name = DRV_NAME, 647 .acpi_match_table = ACPI_PTR(rt5677_spi_acpi_id), 648 }, 649 .probe = rt5677_spi_probe, 650 .id_table = rt5677_spi_ids, 651 }; 652 module_spi_driver(rt5677_spi_driver); 653 654 MODULE_DESCRIPTION("ASoC RT5677 SPI driver"); 655 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 656 MODULE_LICENSE("GPL v2"); 657