1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * cxd2841er.c
4 *
5 * Sony digital demodulator driver for
6 * CXD2841ER - DVB-S/S2/T/T2/C/C2
7 * CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
8 *
9 * Copyright 2012 Sony Corporation
10 * Copyright (C) 2014 NetUP Inc.
11 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
12 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/string.h>
18 #include <linux/slab.h>
19 #include <linux/bitops.h>
20 #include <linux/math64.h>
21 #include <linux/log2.h>
22 #include <linux/dynamic_debug.h>
23 #include <linux/kernel.h>
24
25 #include <linux/int_log.h>
26 #include <media/dvb_frontend.h>
27 #include "cxd2841er.h"
28 #include "cxd2841er_priv.h"
29
30 #define MAX_WRITE_REGSIZE 16
31 #define LOG2_E_100X 144
32
33 #define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24))
34
35 /* DVB-C constellation */
36 enum sony_dvbc_constellation_t {
37 SONY_DVBC_CONSTELLATION_16QAM,
38 SONY_DVBC_CONSTELLATION_32QAM,
39 SONY_DVBC_CONSTELLATION_64QAM,
40 SONY_DVBC_CONSTELLATION_128QAM,
41 SONY_DVBC_CONSTELLATION_256QAM
42 };
43
44 enum cxd2841er_state {
45 STATE_SHUTDOWN = 0,
46 STATE_SLEEP_S,
47 STATE_ACTIVE_S,
48 STATE_SLEEP_TC,
49 STATE_ACTIVE_TC
50 };
51
52 struct cxd2841er_priv {
53 struct dvb_frontend frontend;
54 struct i2c_adapter *i2c;
55 u8 i2c_addr_slvx;
56 u8 i2c_addr_slvt;
57 const struct cxd2841er_config *config;
58 enum cxd2841er_state state;
59 u8 system;
60 enum cxd2841er_xtal xtal;
61 enum fe_caps caps;
62 u32 flags;
63 unsigned long stats_time;
64 };
65
66 static const struct cxd2841er_cnr_data s_cn_data[] = {
67 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
68 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
69 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
70 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
71 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
72 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
73 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
74 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
75 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
76 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
77 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
78 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
79 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
80 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
81 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
82 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
83 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
84 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
85 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
86 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
87 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
88 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
89 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
90 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
91 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
92 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
93 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
94 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
95 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
96 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
97 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
98 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
99 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
100 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
101 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
102 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
103 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
104 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
105 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
106 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
107 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
108 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
109 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
110 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
111 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
112 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
113 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
114 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
115 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
116 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
117 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
118 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
119 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
120 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
121 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
122 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
123 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
124 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
125 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
126 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
127 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
128 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
129 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
130 { 0x0015, 19900 }, { 0x0014, 20000 },
131 };
132
133 static const struct cxd2841er_cnr_data s2_cn_data[] = {
134 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
135 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
136 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
137 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
138 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
139 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
140 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
141 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
142 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
143 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
144 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
145 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
146 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
147 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
148 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
149 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
150 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
151 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
152 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
153 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
154 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
155 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
156 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
157 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
158 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
159 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
160 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
161 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
162 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
163 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
164 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
165 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
166 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
167 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
168 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
169 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
170 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
171 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
172 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
173 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
174 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
175 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
176 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
177 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
178 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
179 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
180 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
181 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
182 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
183 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
184 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
185 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
186 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
187 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
188 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
189 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
190 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
191 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
192 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
193 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
194 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
195 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
196 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
197 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
198 };
199
200 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv);
201 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv);
202
cxd2841er_i2c_debug(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 write,const u8 * data,u32 len)203 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
204 u8 addr, u8 reg, u8 write,
205 const u8 *data, u32 len)
206 {
207 dev_dbg(&priv->i2c->dev,
208 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d data %*ph\n",
209 (write == 0 ? "read" : "write"), addr, reg, len, len, data);
210 }
211
cxd2841er_write_regs(struct cxd2841er_priv * priv,u8 addr,u8 reg,const u8 * data,u32 len)212 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
213 u8 addr, u8 reg, const u8 *data, u32 len)
214 {
215 int ret;
216 u8 buf[MAX_WRITE_REGSIZE + 1];
217 u8 i2c_addr = (addr == I2C_SLVX ?
218 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
219 struct i2c_msg msg[1] = {
220 {
221 .addr = i2c_addr,
222 .flags = 0,
223 .len = len + 1,
224 .buf = buf,
225 }
226 };
227
228 if (len + 1 >= sizeof(buf)) {
229 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
230 reg, len + 1);
231 return -E2BIG;
232 }
233
234 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
235 buf[0] = reg;
236 memcpy(&buf[1], data, len);
237
238 ret = i2c_transfer(priv->i2c, msg, 1);
239 if (ret >= 0 && ret != 1)
240 ret = -EIO;
241 if (ret < 0) {
242 dev_warn(&priv->i2c->dev,
243 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
244 KBUILD_MODNAME, ret, i2c_addr, reg, len);
245 return ret;
246 }
247 return 0;
248 }
249
cxd2841er_write_reg(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 val)250 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
251 u8 addr, u8 reg, u8 val)
252 {
253 u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
254
255 return cxd2841er_write_regs(priv, addr, reg, &tmp, 1);
256 }
257
cxd2841er_read_regs(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 * val,u32 len)258 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
259 u8 addr, u8 reg, u8 *val, u32 len)
260 {
261 int ret;
262 u8 i2c_addr = (addr == I2C_SLVX ?
263 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
264 struct i2c_msg msg[2] = {
265 {
266 .addr = i2c_addr,
267 .flags = 0,
268 .len = 1,
269 .buf = ®,
270 }, {
271 .addr = i2c_addr,
272 .flags = I2C_M_RD,
273 .len = len,
274 .buf = val,
275 }
276 };
277
278 ret = i2c_transfer(priv->i2c, msg, 2);
279 if (ret >= 0 && ret != 2)
280 ret = -EIO;
281 if (ret < 0) {
282 dev_warn(&priv->i2c->dev,
283 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
284 KBUILD_MODNAME, ret, i2c_addr, reg);
285 return ret;
286 }
287 cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
288 return 0;
289 }
290
cxd2841er_read_reg(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 * val)291 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
292 u8 addr, u8 reg, u8 *val)
293 {
294 return cxd2841er_read_regs(priv, addr, reg, val, 1);
295 }
296
cxd2841er_set_reg_bits(struct cxd2841er_priv * priv,u8 addr,u8 reg,u8 data,u8 mask)297 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
298 u8 addr, u8 reg, u8 data, u8 mask)
299 {
300 int res;
301 u8 rdata;
302
303 if (mask != 0xff) {
304 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
305 if (res)
306 return res;
307 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
308 }
309 return cxd2841er_write_reg(priv, addr, reg, data);
310 }
311
cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal,u32 ifhz)312 static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz)
313 {
314 return div_u64(ifhz * 16777216ull,
315 (xtal == SONY_XTAL_24000) ? 48000000 : 41000000);
316 }
317
cxd2841er_calc_iffreq(u32 ifhz)318 static u32 cxd2841er_calc_iffreq(u32 ifhz)
319 {
320 return cxd2841er_calc_iffreq_xtal(SONY_XTAL_20500, ifhz);
321 }
322
cxd2841er_get_if_hz(struct cxd2841er_priv * priv,u32 def_hz)323 static int cxd2841er_get_if_hz(struct cxd2841er_priv *priv, u32 def_hz)
324 {
325 u32 hz;
326
327 if (priv->frontend.ops.tuner_ops.get_if_frequency
328 && (priv->flags & CXD2841ER_AUTO_IFHZ))
329 priv->frontend.ops.tuner_ops.get_if_frequency(
330 &priv->frontend, &hz);
331 else
332 hz = def_hz;
333
334 return hz;
335 }
336
cxd2841er_tuner_set(struct dvb_frontend * fe)337 static int cxd2841er_tuner_set(struct dvb_frontend *fe)
338 {
339 struct cxd2841er_priv *priv = fe->demodulator_priv;
340
341 if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
342 fe->ops.i2c_gate_ctrl(fe, 1);
343 if (fe->ops.tuner_ops.set_params)
344 fe->ops.tuner_ops.set_params(fe);
345 if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
346 fe->ops.i2c_gate_ctrl(fe, 0);
347
348 return 0;
349 }
350
cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv * priv,u32 symbol_rate)351 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
352 u32 symbol_rate)
353 {
354 u32 reg_value = 0;
355 u8 data[3] = {0, 0, 0};
356
357 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
358 /*
359 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
360 * = ((symbolRateKSps * 2^14) + 500) / 1000
361 * = ((symbolRateKSps * 16384) + 500) / 1000
362 */
363 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
364 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
365 dev_err(&priv->i2c->dev,
366 "%s(): reg_value is out of range\n", __func__);
367 return -EINVAL;
368 }
369 data[0] = (u8)((reg_value >> 16) & 0x0F);
370 data[1] = (u8)((reg_value >> 8) & 0xFF);
371 data[2] = (u8)(reg_value & 0xFF);
372 /* Set SLV-T Bank : 0xAE */
373 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
374 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
375 return 0;
376 }
377
378 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
379 u8 system);
380
cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv * priv,u8 system,u32 symbol_rate)381 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
382 u8 system, u32 symbol_rate)
383 {
384 int ret;
385 u8 data[4] = { 0, 0, 0, 0 };
386
387 if (priv->state != STATE_SLEEP_S) {
388 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
389 __func__, (int)priv->state);
390 return -EINVAL;
391 }
392 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
393 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
394 /* Set demod mode */
395 if (system == SYS_DVBS) {
396 data[0] = 0x0A;
397 } else if (system == SYS_DVBS2) {
398 data[0] = 0x0B;
399 } else {
400 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
401 __func__, system);
402 return -EINVAL;
403 }
404 /* Set SLV-X Bank : 0x00 */
405 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
406 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
407 /* DVB-S/S2 */
408 data[0] = 0x00;
409 /* Set SLV-T Bank : 0x00 */
410 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
411 /* Enable S/S2 auto detection 1 */
412 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
413 /* Set SLV-T Bank : 0xAE */
414 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
415 /* Enable S/S2 auto detection 2 */
416 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
417 /* Set SLV-T Bank : 0x00 */
418 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
419 /* Enable demod clock */
420 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
421 /* Enable ADC clock */
422 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
423 /* Enable ADC 1 */
424 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
425 /* Enable ADC 2 */
426 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
427 /* Set SLV-X Bank : 0x00 */
428 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
429 /* Enable ADC 3 */
430 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
431 /* Set SLV-T Bank : 0xA3 */
432 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
433 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
434 data[0] = 0x07;
435 data[1] = 0x3B;
436 data[2] = 0x08;
437 data[3] = 0xC5;
438 /* Set SLV-T Bank : 0xAB */
439 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
440 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
441 data[0] = 0x05;
442 data[1] = 0x80;
443 data[2] = 0x0A;
444 data[3] = 0x80;
445 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
446 data[0] = 0x0C;
447 data[1] = 0xCC;
448 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
449 /* Set demod parameter */
450 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
451 if (ret != 0)
452 return ret;
453 /* Set SLV-T Bank : 0x00 */
454 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
455 /* disable Hi-Z setting 1 */
456 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
457 /* disable Hi-Z setting 2 */
458 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
459 priv->state = STATE_ACTIVE_S;
460 return 0;
461 }
462
463 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
464 u32 bandwidth);
465
466 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
467 u32 bandwidth);
468
469 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
470 u32 bandwidth);
471
472 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
473 u32 bandwidth);
474
475 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
476
477 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
478
479 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
480
481 static int cxd2841er_sleep_tc(struct dvb_frontend *fe);
482
cxd2841er_retune_active(struct cxd2841er_priv * priv,struct dtv_frontend_properties * p)483 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
484 struct dtv_frontend_properties *p)
485 {
486 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
487 if (priv->state != STATE_ACTIVE_S &&
488 priv->state != STATE_ACTIVE_TC) {
489 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
490 __func__, priv->state);
491 return -EINVAL;
492 }
493 /* Set SLV-T Bank : 0x00 */
494 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
495 /* disable TS output */
496 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
497 if (priv->state == STATE_ACTIVE_S)
498 return cxd2841er_dvbs2_set_symbol_rate(
499 priv, p->symbol_rate / 1000);
500 else if (priv->state == STATE_ACTIVE_TC) {
501 switch (priv->system) {
502 case SYS_DVBT:
503 return cxd2841er_sleep_tc_to_active_t_band(
504 priv, p->bandwidth_hz);
505 case SYS_DVBT2:
506 return cxd2841er_sleep_tc_to_active_t2_band(
507 priv, p->bandwidth_hz);
508 case SYS_DVBC_ANNEX_A:
509 return cxd2841er_sleep_tc_to_active_c_band(
510 priv, p->bandwidth_hz);
511 case SYS_ISDBT:
512 cxd2841er_active_i_to_sleep_tc(priv);
513 cxd2841er_sleep_tc_to_shutdown(priv);
514 cxd2841er_shutdown_to_sleep_tc(priv);
515 return cxd2841er_sleep_tc_to_active_i(
516 priv, p->bandwidth_hz);
517 }
518 }
519 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
520 __func__, priv->system);
521 return -EINVAL;
522 }
523
cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv * priv)524 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
525 {
526 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
527 if (priv->state != STATE_ACTIVE_S) {
528 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
529 __func__, priv->state);
530 return -EINVAL;
531 }
532 /* Set SLV-T Bank : 0x00 */
533 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
534 /* disable TS output */
535 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
536 /* enable Hi-Z setting 1 */
537 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
538 /* enable Hi-Z setting 2 */
539 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
540 /* Set SLV-X Bank : 0x00 */
541 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
542 /* disable ADC 1 */
543 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
544 /* Set SLV-T Bank : 0x00 */
545 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
546 /* disable ADC clock */
547 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
548 /* disable ADC 2 */
549 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
550 /* disable ADC 3 */
551 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
552 /* SADC Bias ON */
553 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
554 /* disable demod clock */
555 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
556 /* Set SLV-T Bank : 0xAE */
557 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
558 /* disable S/S2 auto detection1 */
559 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
560 /* Set SLV-T Bank : 0x00 */
561 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
562 /* disable S/S2 auto detection2 */
563 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
564 priv->state = STATE_SLEEP_S;
565 return 0;
566 }
567
cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv * priv)568 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
569 {
570 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
571 if (priv->state != STATE_SLEEP_S) {
572 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
573 __func__, priv->state);
574 return -EINVAL;
575 }
576 /* Set SLV-T Bank : 0x00 */
577 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
578 /* Disable DSQOUT */
579 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
580 /* Disable DSQIN */
581 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
582 /* Set SLV-X Bank : 0x00 */
583 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
584 /* Disable oscillator */
585 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
586 /* Set demod mode */
587 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
588 priv->state = STATE_SHUTDOWN;
589 return 0;
590 }
591
cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv * priv)592 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
593 {
594 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
595 if (priv->state != STATE_SLEEP_TC) {
596 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
597 __func__, priv->state);
598 return -EINVAL;
599 }
600 /* Set SLV-X Bank : 0x00 */
601 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
602 /* Disable oscillator */
603 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
604 /* Set demod mode */
605 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
606 priv->state = STATE_SHUTDOWN;
607 return 0;
608 }
609
cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv * priv)610 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
611 {
612 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
613 if (priv->state != STATE_ACTIVE_TC) {
614 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
615 __func__, priv->state);
616 return -EINVAL;
617 }
618 /* Set SLV-T Bank : 0x00 */
619 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
620 /* disable TS output */
621 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
622 /* enable Hi-Z setting 1 */
623 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
624 /* enable Hi-Z setting 2 */
625 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
626 /* Set SLV-X Bank : 0x00 */
627 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
628 /* disable ADC 1 */
629 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
630 /* Set SLV-T Bank : 0x00 */
631 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
632 /* Disable ADC 2 */
633 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
634 /* Disable ADC 3 */
635 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
636 /* Disable ADC clock */
637 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
638 /* Disable RF level monitor */
639 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
640 /* Disable demod clock */
641 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
642 priv->state = STATE_SLEEP_TC;
643 return 0;
644 }
645
cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv * priv)646 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
647 {
648 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
649 if (priv->state != STATE_ACTIVE_TC) {
650 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
651 __func__, priv->state);
652 return -EINVAL;
653 }
654 /* Set SLV-T Bank : 0x00 */
655 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
656 /* disable TS output */
657 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
658 /* enable Hi-Z setting 1 */
659 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
660 /* enable Hi-Z setting 2 */
661 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
662 /* Cancel DVB-T2 setting */
663 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
664 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
665 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
666 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
667 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
668 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
669 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
670 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
671 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
672 /* Set SLV-X Bank : 0x00 */
673 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
674 /* disable ADC 1 */
675 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
676 /* Set SLV-T Bank : 0x00 */
677 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
678 /* Disable ADC 2 */
679 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
680 /* Disable ADC 3 */
681 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
682 /* Disable ADC clock */
683 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
684 /* Disable RF level monitor */
685 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
686 /* Disable demod clock */
687 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
688 priv->state = STATE_SLEEP_TC;
689 return 0;
690 }
691
cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv * priv)692 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
693 {
694 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
695 if (priv->state != STATE_ACTIVE_TC) {
696 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
697 __func__, priv->state);
698 return -EINVAL;
699 }
700 /* Set SLV-T Bank : 0x00 */
701 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
702 /* disable TS output */
703 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
704 /* enable Hi-Z setting 1 */
705 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
706 /* enable Hi-Z setting 2 */
707 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
708 /* Cancel DVB-C setting */
709 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
710 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
711 /* Set SLV-X Bank : 0x00 */
712 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
713 /* disable ADC 1 */
714 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
715 /* Set SLV-T Bank : 0x00 */
716 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
717 /* Disable ADC 2 */
718 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
719 /* Disable ADC 3 */
720 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
721 /* Disable ADC clock */
722 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
723 /* Disable RF level monitor */
724 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
725 /* Disable demod clock */
726 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
727 priv->state = STATE_SLEEP_TC;
728 return 0;
729 }
730
cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv * priv)731 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
732 {
733 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
734 if (priv->state != STATE_ACTIVE_TC) {
735 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
736 __func__, priv->state);
737 return -EINVAL;
738 }
739 /* Set SLV-T Bank : 0x00 */
740 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
741 /* disable TS output */
742 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
743 /* enable Hi-Z setting 1 */
744 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
745 /* enable Hi-Z setting 2 */
746 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
747
748 /* TODO: Cancel demod parameter */
749
750 /* Set SLV-X Bank : 0x00 */
751 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
752 /* disable ADC 1 */
753 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
754 /* Set SLV-T Bank : 0x00 */
755 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
756 /* Disable ADC 2 */
757 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
758 /* Disable ADC 3 */
759 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
760 /* Disable ADC clock */
761 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
762 /* Disable RF level monitor */
763 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
764 /* Disable demod clock */
765 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
766 priv->state = STATE_SLEEP_TC;
767 return 0;
768 }
769
cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv * priv)770 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
771 {
772 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
773 if (priv->state != STATE_SHUTDOWN) {
774 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
775 __func__, priv->state);
776 return -EINVAL;
777 }
778 /* Set SLV-X Bank : 0x00 */
779 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
780 /* Clear all demodulator registers */
781 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
782 usleep_range(3000, 5000);
783 /* Set SLV-X Bank : 0x00 */
784 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
785 /* Set demod SW reset */
786 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
787
788 switch (priv->xtal) {
789 case SONY_XTAL_20500:
790 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
791 break;
792 case SONY_XTAL_24000:
793 /* Select demod frequency */
794 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
795 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
796 break;
797 case SONY_XTAL_41000:
798 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
799 break;
800 default:
801 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
802 __func__, priv->xtal);
803 return -EINVAL;
804 }
805
806 /* Set demod mode */
807 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
808 /* Clear demod SW reset */
809 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
810 usleep_range(1000, 2000);
811 /* Set SLV-T Bank : 0x00 */
812 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
813 /* enable DSQOUT */
814 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
815 /* enable DSQIN */
816 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
817 /* TADC Bias On */
818 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
819 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
820 /* SADC Bias On */
821 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
822 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
823 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
824 priv->state = STATE_SLEEP_S;
825 return 0;
826 }
827
cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv * priv)828 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
829 {
830 u8 data = 0;
831
832 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
833 if (priv->state != STATE_SHUTDOWN) {
834 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
835 __func__, priv->state);
836 return -EINVAL;
837 }
838 /* Set SLV-X Bank : 0x00 */
839 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
840 /* Clear all demodulator registers */
841 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
842 usleep_range(3000, 5000);
843 /* Set SLV-X Bank : 0x00 */
844 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
845 /* Set demod SW reset */
846 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
847 /* Select ADC clock mode */
848 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
849
850 switch (priv->xtal) {
851 case SONY_XTAL_20500:
852 data = 0x0;
853 break;
854 case SONY_XTAL_24000:
855 /* Select demod frequency */
856 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
857 data = 0x3;
858 break;
859 case SONY_XTAL_41000:
860 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
861 data = 0x1;
862 break;
863 }
864 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
865 /* Clear demod SW reset */
866 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
867 usleep_range(1000, 2000);
868 /* Set SLV-T Bank : 0x00 */
869 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
870 /* TADC Bias On */
871 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
872 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
873 /* SADC Bias On */
874 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
875 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
876 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
877 priv->state = STATE_SLEEP_TC;
878 return 0;
879 }
880
cxd2841er_tune_done(struct cxd2841er_priv * priv)881 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
882 {
883 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
884 /* Set SLV-T Bank : 0x00 */
885 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
886 /* SW Reset */
887 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
888 /* Enable TS output */
889 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
890 return 0;
891 }
892
893 /* Set TS parallel mode */
cxd2841er_set_ts_clock_mode(struct cxd2841er_priv * priv,u8 system)894 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
895 u8 system)
896 {
897 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
898
899 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
900 /* Set SLV-T Bank : 0x00 */
901 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
902 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
903 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
904 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
905 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
906 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
907
908 /*
909 * slave Bank Addr Bit default Name
910 * <SLV-T> 00h C4h [1:0] 2'b?? OSERCKMODE
911 */
912 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
913 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
914 /*
915 * slave Bank Addr Bit default Name
916 * <SLV-T> 00h D1h [1:0] 2'b?? OSERDUTYMODE
917 */
918 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd1,
919 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
920 /*
921 * slave Bank Addr Bit default Name
922 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
923 */
924 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
925 /*
926 * Disable TS IF Clock
927 * slave Bank Addr Bit default Name
928 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
929 */
930 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
931 /*
932 * slave Bank Addr Bit default Name
933 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
934 */
935 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33,
936 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
937 /*
938 * Enable TS IF Clock
939 * slave Bank Addr Bit default Name
940 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
941 */
942 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
943
944 if (system == SYS_DVBT) {
945 /* Enable parity period for DVB-T */
946 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
947 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
948 } else if (system == SYS_DVBC_ANNEX_A) {
949 /* Enable parity period for DVB-C */
950 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
951 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
952 }
953 }
954
cxd2841er_chip_id(struct cxd2841er_priv * priv)955 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
956 {
957 u8 chip_id = 0;
958
959 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
960 if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
961 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
962 else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
963 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
964
965 return chip_id;
966 }
967
cxd2841er_read_status_s(struct dvb_frontend * fe,enum fe_status * status)968 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
969 enum fe_status *status)
970 {
971 u8 reg = 0;
972 struct cxd2841er_priv *priv = fe->demodulator_priv;
973
974 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
975 *status = 0;
976 if (priv->state != STATE_ACTIVE_S) {
977 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
978 __func__, priv->state);
979 return -EINVAL;
980 }
981 /* Set SLV-T Bank : 0xA0 */
982 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
983 /*
984 * slave Bank Addr Bit Signal name
985 * <SLV-T> A0h 11h [2] ITSLOCK
986 */
987 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, ®);
988 if (reg & 0x04) {
989 *status = FE_HAS_SIGNAL
990 | FE_HAS_CARRIER
991 | FE_HAS_VITERBI
992 | FE_HAS_SYNC
993 | FE_HAS_LOCK;
994 }
995 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
996 return 0;
997 }
998
cxd2841er_read_status_t_t2(struct cxd2841er_priv * priv,u8 * sync,u8 * tslock,u8 * unlock)999 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
1000 u8 *sync, u8 *tslock, u8 *unlock)
1001 {
1002 u8 data = 0;
1003
1004 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1005 if (priv->state != STATE_ACTIVE_TC)
1006 return -EINVAL;
1007 if (priv->system == SYS_DVBT) {
1008 /* Set SLV-T Bank : 0x10 */
1009 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1010 } else {
1011 /* Set SLV-T Bank : 0x20 */
1012 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1013 }
1014 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1015 if ((data & 0x07) == 0x07) {
1016 dev_dbg(&priv->i2c->dev,
1017 "%s(): invalid hardware state detected\n", __func__);
1018 *sync = 0;
1019 *tslock = 0;
1020 *unlock = 0;
1021 } else {
1022 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
1023 *tslock = ((data & 0x20) ? 1 : 0);
1024 *unlock = ((data & 0x10) ? 1 : 0);
1025 }
1026 return 0;
1027 }
1028
cxd2841er_read_status_c(struct cxd2841er_priv * priv,u8 * tslock)1029 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
1030 {
1031 u8 data;
1032
1033 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1034 if (priv->state != STATE_ACTIVE_TC)
1035 return -EINVAL;
1036 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1037 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
1038 if ((data & 0x01) == 0) {
1039 *tslock = 0;
1040 } else {
1041 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1042 *tslock = ((data & 0x20) ? 1 : 0);
1043 }
1044 return 0;
1045 }
1046
cxd2841er_read_status_i(struct cxd2841er_priv * priv,u8 * sync,u8 * tslock,u8 * unlock)1047 static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
1048 u8 *sync, u8 *tslock, u8 *unlock)
1049 {
1050 u8 data = 0;
1051
1052 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1053 if (priv->state != STATE_ACTIVE_TC)
1054 return -EINVAL;
1055 /* Set SLV-T Bank : 0x60 */
1056 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1057 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1058 dev_dbg(&priv->i2c->dev,
1059 "%s(): lock=0x%x\n", __func__, data);
1060 *sync = ((data & 0x02) ? 1 : 0);
1061 *tslock = ((data & 0x01) ? 1 : 0);
1062 *unlock = ((data & 0x10) ? 1 : 0);
1063 return 0;
1064 }
1065
cxd2841er_read_status_tc(struct dvb_frontend * fe,enum fe_status * status)1066 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1067 enum fe_status *status)
1068 {
1069 int ret = 0;
1070 u8 sync = 0;
1071 u8 tslock = 0;
1072 u8 unlock = 0;
1073 struct cxd2841er_priv *priv = fe->demodulator_priv;
1074
1075 *status = 0;
1076 if (priv->state == STATE_ACTIVE_TC) {
1077 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1078 ret = cxd2841er_read_status_t_t2(
1079 priv, &sync, &tslock, &unlock);
1080 if (ret)
1081 goto done;
1082 if (unlock)
1083 goto done;
1084 if (sync)
1085 *status = FE_HAS_SIGNAL |
1086 FE_HAS_CARRIER |
1087 FE_HAS_VITERBI |
1088 FE_HAS_SYNC;
1089 if (tslock)
1090 *status |= FE_HAS_LOCK;
1091 } else if (priv->system == SYS_ISDBT) {
1092 ret = cxd2841er_read_status_i(
1093 priv, &sync, &tslock, &unlock);
1094 if (ret)
1095 goto done;
1096 if (unlock)
1097 goto done;
1098 if (sync)
1099 *status = FE_HAS_SIGNAL |
1100 FE_HAS_CARRIER |
1101 FE_HAS_VITERBI |
1102 FE_HAS_SYNC;
1103 if (tslock)
1104 *status |= FE_HAS_LOCK;
1105 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1106 ret = cxd2841er_read_status_c(priv, &tslock);
1107 if (ret)
1108 goto done;
1109 if (tslock)
1110 *status = FE_HAS_SIGNAL |
1111 FE_HAS_CARRIER |
1112 FE_HAS_VITERBI |
1113 FE_HAS_SYNC |
1114 FE_HAS_LOCK;
1115 }
1116 }
1117 done:
1118 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1119 return ret;
1120 }
1121
cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv * priv,int * offset)1122 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1123 int *offset)
1124 {
1125 u8 data[3];
1126 u8 is_hs_mode;
1127 s32 cfrl_ctrlval;
1128 s32 temp_div, temp_q, temp_r;
1129
1130 if (priv->state != STATE_ACTIVE_S) {
1131 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1132 __func__, priv->state);
1133 return -EINVAL;
1134 }
1135 /*
1136 * Get High Sampling Rate mode
1137 * slave Bank Addr Bit Signal name
1138 * <SLV-T> A0h 10h [0] ITRL_LOCK
1139 */
1140 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1141 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1142 if (data[0] & 0x01) {
1143 /*
1144 * slave Bank Addr Bit Signal name
1145 * <SLV-T> A0h 50h [4] IHSMODE
1146 */
1147 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1148 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1149 } else {
1150 dev_dbg(&priv->i2c->dev,
1151 "%s(): unable to detect sampling rate mode\n",
1152 __func__);
1153 return -EINVAL;
1154 }
1155 /*
1156 * slave Bank Addr Bit Signal name
1157 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
1158 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
1159 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
1160 */
1161 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1162 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1163 (((u32)data[1] & 0xFF) << 8) |
1164 ((u32)data[2] & 0xFF), 20);
1165 temp_div = (is_hs_mode ? 1048576 : 1572864);
1166 if (cfrl_ctrlval > 0) {
1167 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1168 temp_div, &temp_r);
1169 } else {
1170 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1171 temp_div, &temp_r);
1172 }
1173 if (temp_r >= temp_div / 2)
1174 temp_q++;
1175 if (cfrl_ctrlval > 0)
1176 temp_q *= -1;
1177 *offset = temp_q;
1178 return 0;
1179 }
1180
cxd2841er_get_carrier_offset_i(struct cxd2841er_priv * priv,u32 bandwidth,int * offset)1181 static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1182 u32 bandwidth, int *offset)
1183 {
1184 u8 data[4];
1185
1186 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1187 if (priv->state != STATE_ACTIVE_TC) {
1188 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1189 __func__, priv->state);
1190 return -EINVAL;
1191 }
1192 if (priv->system != SYS_ISDBT) {
1193 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1194 __func__, priv->system);
1195 return -EINVAL;
1196 }
1197 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1198 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1199 *offset = -1 * sign_extend32(
1200 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1201 ((u32)data[2] << 8) | (u32)data[3], 29);
1202
1203 switch (bandwidth) {
1204 case 6000000:
1205 *offset = -1 * ((*offset) * 8/264);
1206 break;
1207 case 7000000:
1208 *offset = -1 * ((*offset) * 8/231);
1209 break;
1210 case 8000000:
1211 *offset = -1 * ((*offset) * 8/198);
1212 break;
1213 default:
1214 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1215 __func__, bandwidth);
1216 return -EINVAL;
1217 }
1218
1219 dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1220 __func__, bandwidth, *offset);
1221
1222 return 0;
1223 }
1224
cxd2841er_get_carrier_offset_t(struct cxd2841er_priv * priv,u32 bandwidth,int * offset)1225 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1226 u32 bandwidth, int *offset)
1227 {
1228 u8 data[4];
1229
1230 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1231 if (priv->state != STATE_ACTIVE_TC) {
1232 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1233 __func__, priv->state);
1234 return -EINVAL;
1235 }
1236 if (priv->system != SYS_DVBT) {
1237 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1238 __func__, priv->system);
1239 return -EINVAL;
1240 }
1241 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1242 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1243 *offset = -1 * sign_extend32(
1244 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1245 ((u32)data[2] << 8) | (u32)data[3], 29);
1246 *offset *= (bandwidth / 1000000);
1247 *offset /= 235;
1248 return 0;
1249 }
1250
cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv * priv,u32 bandwidth,int * offset)1251 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1252 u32 bandwidth, int *offset)
1253 {
1254 u8 data[4];
1255
1256 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1257 if (priv->state != STATE_ACTIVE_TC) {
1258 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1259 __func__, priv->state);
1260 return -EINVAL;
1261 }
1262 if (priv->system != SYS_DVBT2) {
1263 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1264 __func__, priv->system);
1265 return -EINVAL;
1266 }
1267 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1268 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1269 *offset = -1 * sign_extend32(
1270 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1271 ((u32)data[2] << 8) | (u32)data[3], 27);
1272 switch (bandwidth) {
1273 case 1712000:
1274 *offset /= 582;
1275 break;
1276 case 5000000:
1277 case 6000000:
1278 case 7000000:
1279 case 8000000:
1280 *offset *= (bandwidth / 1000000);
1281 *offset /= 940;
1282 break;
1283 default:
1284 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1285 __func__, bandwidth);
1286 return -EINVAL;
1287 }
1288 return 0;
1289 }
1290
cxd2841er_get_carrier_offset_c(struct cxd2841er_priv * priv,int * offset)1291 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1292 int *offset)
1293 {
1294 u8 data[2];
1295
1296 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1297 if (priv->state != STATE_ACTIVE_TC) {
1298 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1299 __func__, priv->state);
1300 return -EINVAL;
1301 }
1302 if (priv->system != SYS_DVBC_ANNEX_A) {
1303 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1304 __func__, priv->system);
1305 return -EINVAL;
1306 }
1307 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1308 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1309 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1310 | (u32)data[1], 13), 16384);
1311 return 0;
1312 }
1313
cxd2841er_read_packet_errors_c(struct cxd2841er_priv * priv,u32 * penum)1314 static int cxd2841er_read_packet_errors_c(
1315 struct cxd2841er_priv *priv, u32 *penum)
1316 {
1317 u8 data[3];
1318
1319 *penum = 0;
1320 if (priv->state != STATE_ACTIVE_TC) {
1321 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1322 __func__, priv->state);
1323 return -EINVAL;
1324 }
1325 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1326 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1327 if (data[2] & 0x01)
1328 *penum = ((u32)data[0] << 8) | (u32)data[1];
1329 return 0;
1330 }
1331
cxd2841er_read_packet_errors_t(struct cxd2841er_priv * priv,u32 * penum)1332 static int cxd2841er_read_packet_errors_t(
1333 struct cxd2841er_priv *priv, u32 *penum)
1334 {
1335 u8 data[3];
1336
1337 *penum = 0;
1338 if (priv->state != STATE_ACTIVE_TC) {
1339 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1340 __func__, priv->state);
1341 return -EINVAL;
1342 }
1343 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1344 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1345 if (data[2] & 0x01)
1346 *penum = ((u32)data[0] << 8) | (u32)data[1];
1347 return 0;
1348 }
1349
cxd2841er_read_packet_errors_t2(struct cxd2841er_priv * priv,u32 * penum)1350 static int cxd2841er_read_packet_errors_t2(
1351 struct cxd2841er_priv *priv, u32 *penum)
1352 {
1353 u8 data[3];
1354
1355 *penum = 0;
1356 if (priv->state != STATE_ACTIVE_TC) {
1357 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1358 __func__, priv->state);
1359 return -EINVAL;
1360 }
1361 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1362 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1363 if (data[0] & 0x01)
1364 *penum = ((u32)data[1] << 8) | (u32)data[2];
1365 return 0;
1366 }
1367
cxd2841er_read_packet_errors_i(struct cxd2841er_priv * priv,u32 * penum)1368 static int cxd2841er_read_packet_errors_i(
1369 struct cxd2841er_priv *priv, u32 *penum)
1370 {
1371 u8 data[2];
1372
1373 *penum = 0;
1374 if (priv->state != STATE_ACTIVE_TC) {
1375 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1376 __func__, priv->state);
1377 return -EINVAL;
1378 }
1379 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1380 cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1381
1382 if (!(data[0] & 0x01))
1383 return 0;
1384
1385 /* Layer A */
1386 cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1387 *penum = ((u32)data[0] << 8) | (u32)data[1];
1388
1389 /* Layer B */
1390 cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1391 *penum += ((u32)data[0] << 8) | (u32)data[1];
1392
1393 /* Layer C */
1394 cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1395 *penum += ((u32)data[0] << 8) | (u32)data[1];
1396
1397 return 0;
1398 }
1399
cxd2841er_read_ber_c(struct cxd2841er_priv * priv,u32 * bit_error,u32 * bit_count)1400 static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
1401 u32 *bit_error, u32 *bit_count)
1402 {
1403 u8 data[3];
1404 u32 bit_err, period_exp;
1405
1406 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1407 if (priv->state != STATE_ACTIVE_TC) {
1408 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1409 __func__, priv->state);
1410 return -EINVAL;
1411 }
1412 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1413 cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
1414 if (!(data[0] & 0x80)) {
1415 dev_dbg(&priv->i2c->dev,
1416 "%s(): no valid BER data\n", __func__);
1417 return -EINVAL;
1418 }
1419 bit_err = ((u32)(data[0] & 0x3f) << 16) |
1420 ((u32)data[1] << 8) |
1421 (u32)data[2];
1422 cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
1423 period_exp = data[0] & 0x1f;
1424
1425 if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
1426 dev_dbg(&priv->i2c->dev,
1427 "%s(): period_exp(%u) or bit_err(%u) not in range. no valid BER data\n",
1428 __func__, period_exp, bit_err);
1429 return -EINVAL;
1430 }
1431
1432 dev_dbg(&priv->i2c->dev,
1433 "%s(): period_exp(%u) or bit_err(%u) count=%d\n",
1434 __func__, period_exp, bit_err,
1435 ((1 << period_exp) * 204 * 8));
1436
1437 *bit_error = bit_err;
1438 *bit_count = ((1 << period_exp) * 204 * 8);
1439
1440 return 0;
1441 }
1442
cxd2841er_read_ber_i(struct cxd2841er_priv * priv,u32 * bit_error,u32 * bit_count)1443 static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv,
1444 u32 *bit_error, u32 *bit_count)
1445 {
1446 u8 data[3];
1447 u8 pktnum[2];
1448
1449 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1450 if (priv->state != STATE_ACTIVE_TC) {
1451 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1452 __func__, priv->state);
1453 return -EINVAL;
1454 }
1455
1456 cxd2841er_freeze_regs(priv);
1457 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1458 cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum));
1459 cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data));
1460 cxd2841er_unfreeze_regs(priv);
1461
1462 if (!pktnum[0] && !pktnum[1]) {
1463 dev_dbg(&priv->i2c->dev,
1464 "%s(): no valid BER data\n", __func__);
1465 return -EINVAL;
1466 }
1467
1468 *bit_error = ((u32)(data[0] & 0x7F) << 16) |
1469 ((u32)data[1] << 8) | data[2];
1470 *bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8);
1471 dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n",
1472 __func__, *bit_error, *bit_count);
1473
1474 return 0;
1475 }
1476
cxd2841er_mon_read_ber_s(struct cxd2841er_priv * priv,u32 * bit_error,u32 * bit_count)1477 static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
1478 u32 *bit_error, u32 *bit_count)
1479 {
1480 u8 data[11];
1481
1482 /* Set SLV-T Bank : 0xA0 */
1483 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1484 /*
1485 * slave Bank Addr Bit Signal name
1486 * <SLV-T> A0h 35h [0] IFVBER_VALID
1487 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1488 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1489 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1490 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1491 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1492 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1493 */
1494 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1495 if (data[0] & 0x01) {
1496 *bit_error = ((u32)(data[1] & 0x3F) << 16) |
1497 ((u32)(data[2] & 0xFF) << 8) |
1498 (u32)(data[3] & 0xFF);
1499 *bit_count = ((u32)(data[8] & 0x3F) << 16) |
1500 ((u32)(data[9] & 0xFF) << 8) |
1501 (u32)(data[10] & 0xFF);
1502 if ((*bit_count == 0) || (*bit_error > *bit_count)) {
1503 dev_dbg(&priv->i2c->dev,
1504 "%s(): invalid bit_error %d, bit_count %d\n",
1505 __func__, *bit_error, *bit_count);
1506 return -EINVAL;
1507 }
1508 return 0;
1509 }
1510 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1511 return -EINVAL;
1512 }
1513
1514
cxd2841er_mon_read_ber_s2(struct cxd2841er_priv * priv,u32 * bit_error,u32 * bit_count)1515 static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
1516 u32 *bit_error, u32 *bit_count)
1517 {
1518 u8 data[5];
1519 u32 period;
1520
1521 /* Set SLV-T Bank : 0xB2 */
1522 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1523 /*
1524 * slave Bank Addr Bit Signal name
1525 * <SLV-T> B2h 30h [0] IFLBER_VALID
1526 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1527 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1528 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1529 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1530 */
1531 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1532 if (data[0] & 0x01) {
1533 /* Bit error count */
1534 *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1535 ((u32)(data[2] & 0xFF) << 16) |
1536 ((u32)(data[3] & 0xFF) << 8) |
1537 (u32)(data[4] & 0xFF);
1538
1539 /* Set SLV-T Bank : 0xA0 */
1540 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1541 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1542 /* Measurement period */
1543 period = (u32)(1 << (data[0] & 0x0F));
1544 if (period == 0) {
1545 dev_dbg(&priv->i2c->dev,
1546 "%s(): period is 0\n", __func__);
1547 return -EINVAL;
1548 }
1549 if (*bit_error > (period * 64800)) {
1550 dev_dbg(&priv->i2c->dev,
1551 "%s(): invalid bit_err 0x%x period 0x%x\n",
1552 __func__, *bit_error, period);
1553 return -EINVAL;
1554 }
1555 *bit_count = period * 64800;
1556
1557 return 0;
1558 } else {
1559 dev_dbg(&priv->i2c->dev,
1560 "%s(): no data available\n", __func__);
1561 }
1562 return -EINVAL;
1563 }
1564
cxd2841er_read_ber_t2(struct cxd2841er_priv * priv,u32 * bit_error,u32 * bit_count)1565 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
1566 u32 *bit_error, u32 *bit_count)
1567 {
1568 u8 data[4];
1569 u32 period_exp, n_ldpc;
1570
1571 if (priv->state != STATE_ACTIVE_TC) {
1572 dev_dbg(&priv->i2c->dev,
1573 "%s(): invalid state %d\n", __func__, priv->state);
1574 return -EINVAL;
1575 }
1576 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1577 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1578 if (!(data[0] & 0x10)) {
1579 dev_dbg(&priv->i2c->dev,
1580 "%s(): no valid BER data\n", __func__);
1581 return -EINVAL;
1582 }
1583 *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1584 ((u32)data[1] << 16) |
1585 ((u32)data[2] << 8) |
1586 (u32)data[3];
1587 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1588 period_exp = data[0] & 0x0f;
1589 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1590 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1591 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1592 if (*bit_error > ((1U << period_exp) * n_ldpc)) {
1593 dev_dbg(&priv->i2c->dev,
1594 "%s(): invalid BER value\n", __func__);
1595 return -EINVAL;
1596 }
1597
1598 /*
1599 * FIXME: the right thing would be to return bit_error untouched,
1600 * but, as we don't know the scale returned by the counters, let's
1601 * at least preserver BER = bit_error/bit_count.
1602 */
1603 if (period_exp >= 4) {
1604 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
1605 *bit_error *= 3125ULL;
1606 } else {
1607 *bit_count = (1U << period_exp) * (n_ldpc / 200);
1608 *bit_error *= 50000ULL;
1609 }
1610 return 0;
1611 }
1612
cxd2841er_read_ber_t(struct cxd2841er_priv * priv,u32 * bit_error,u32 * bit_count)1613 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
1614 u32 *bit_error, u32 *bit_count)
1615 {
1616 u8 data[2];
1617 u32 period;
1618
1619 if (priv->state != STATE_ACTIVE_TC) {
1620 dev_dbg(&priv->i2c->dev,
1621 "%s(): invalid state %d\n", __func__, priv->state);
1622 return -EINVAL;
1623 }
1624 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1625 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1626 if (!(data[0] & 0x01)) {
1627 dev_dbg(&priv->i2c->dev,
1628 "%s(): no valid BER data\n", __func__);
1629 return 0;
1630 }
1631 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1632 *bit_error = ((u32)data[0] << 8) | (u32)data[1];
1633 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1634 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1635
1636 /*
1637 * FIXME: the right thing would be to return bit_error untouched,
1638 * but, as we don't know the scale returned by the counters, let's
1639 * at least preserver BER = bit_error/bit_count.
1640 */
1641 *bit_count = period / 128;
1642 *bit_error *= 78125ULL;
1643 return 0;
1644 }
1645
cxd2841er_freeze_regs(struct cxd2841er_priv * priv)1646 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv)
1647 {
1648 /*
1649 * Freeze registers: ensure multiple separate register reads
1650 * are from the same snapshot
1651 */
1652 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1653 return 0;
1654 }
1655
cxd2841er_unfreeze_regs(struct cxd2841er_priv * priv)1656 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv)
1657 {
1658 /*
1659 * un-freeze registers
1660 */
1661 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00);
1662 return 0;
1663 }
1664
cxd2841er_dvbs_read_snr(struct cxd2841er_priv * priv,u8 delsys,u32 * snr)1665 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
1666 u8 delsys, u32 *snr)
1667 {
1668 u8 data[3];
1669 u32 res = 0, value;
1670 int min_index, max_index, index;
1671 static const struct cxd2841er_cnr_data *cn_data;
1672
1673 cxd2841er_freeze_regs(priv);
1674 /* Set SLV-T Bank : 0xA1 */
1675 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1676 /*
1677 * slave Bank Addr Bit Signal name
1678 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1679 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1680 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1681 */
1682 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1683 cxd2841er_unfreeze_regs(priv);
1684
1685 if (data[0] & 0x01) {
1686 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1687 min_index = 0;
1688 if (delsys == SYS_DVBS) {
1689 cn_data = s_cn_data;
1690 max_index = ARRAY_SIZE(s_cn_data) - 1;
1691 } else {
1692 cn_data = s2_cn_data;
1693 max_index = ARRAY_SIZE(s2_cn_data) - 1;
1694 }
1695 if (value >= cn_data[min_index].value) {
1696 res = cn_data[min_index].cnr_x1000;
1697 goto done;
1698 }
1699 if (value <= cn_data[max_index].value) {
1700 res = cn_data[max_index].cnr_x1000;
1701 goto done;
1702 }
1703 while ((max_index - min_index) > 1) {
1704 index = (max_index + min_index) / 2;
1705 if (value == cn_data[index].value) {
1706 res = cn_data[index].cnr_x1000;
1707 goto done;
1708 } else if (value > cn_data[index].value)
1709 max_index = index;
1710 else
1711 min_index = index;
1712 if ((max_index - min_index) <= 1) {
1713 if (value == cn_data[max_index].value) {
1714 res = cn_data[max_index].cnr_x1000;
1715 goto done;
1716 } else {
1717 res = cn_data[min_index].cnr_x1000;
1718 goto done;
1719 }
1720 }
1721 }
1722 } else {
1723 dev_dbg(&priv->i2c->dev,
1724 "%s(): no data available\n", __func__);
1725 return -EINVAL;
1726 }
1727 done:
1728 *snr = res;
1729 return 0;
1730 }
1731
sony_log(uint32_t x)1732 static uint32_t sony_log(uint32_t x)
1733 {
1734 return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
1735 }
1736
cxd2841er_read_snr_c(struct cxd2841er_priv * priv,u32 * snr)1737 static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
1738 {
1739 u32 reg;
1740 u8 data[2];
1741 enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
1742
1743 *snr = 0;
1744 if (priv->state != STATE_ACTIVE_TC) {
1745 dev_dbg(&priv->i2c->dev,
1746 "%s(): invalid state %d\n",
1747 __func__, priv->state);
1748 return -EINVAL;
1749 }
1750
1751 cxd2841er_freeze_regs(priv);
1752 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1753 cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
1754 qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
1755 cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
1756 cxd2841er_unfreeze_regs(priv);
1757
1758 reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
1759 if (reg == 0) {
1760 dev_dbg(&priv->i2c->dev,
1761 "%s(): reg value out of range\n", __func__);
1762 return 0;
1763 }
1764
1765 switch (qam) {
1766 case SONY_DVBC_CONSTELLATION_16QAM:
1767 case SONY_DVBC_CONSTELLATION_64QAM:
1768 case SONY_DVBC_CONSTELLATION_256QAM:
1769 /* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */
1770 if (reg < 126)
1771 reg = 126;
1772 *snr = -95 * (int32_t)sony_log(reg) + 95941;
1773 break;
1774 case SONY_DVBC_CONSTELLATION_32QAM:
1775 case SONY_DVBC_CONSTELLATION_128QAM:
1776 /* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */
1777 if (reg < 69)
1778 reg = 69;
1779 *snr = -88 * (int32_t)sony_log(reg) + 86999;
1780 break;
1781 default:
1782 return -EINVAL;
1783 }
1784
1785 return 0;
1786 }
1787
cxd2841er_read_snr_t(struct cxd2841er_priv * priv,u32 * snr)1788 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1789 {
1790 u32 reg;
1791 u8 data[2];
1792
1793 *snr = 0;
1794 if (priv->state != STATE_ACTIVE_TC) {
1795 dev_dbg(&priv->i2c->dev,
1796 "%s(): invalid state %d\n", __func__, priv->state);
1797 return -EINVAL;
1798 }
1799
1800 cxd2841er_freeze_regs(priv);
1801 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1802 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1803 cxd2841er_unfreeze_regs(priv);
1804
1805 reg = ((u32)data[0] << 8) | (u32)data[1];
1806 if (reg == 0) {
1807 dev_dbg(&priv->i2c->dev,
1808 "%s(): reg value out of range\n", __func__);
1809 return 0;
1810 }
1811 if (reg > 4996)
1812 reg = 4996;
1813 *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(5350 - reg)) + 285);
1814 return 0;
1815 }
1816
cxd2841er_read_snr_t2(struct cxd2841er_priv * priv,u32 * snr)1817 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1818 {
1819 u32 reg;
1820 u8 data[2];
1821
1822 *snr = 0;
1823 if (priv->state != STATE_ACTIVE_TC) {
1824 dev_dbg(&priv->i2c->dev,
1825 "%s(): invalid state %d\n", __func__, priv->state);
1826 return -EINVAL;
1827 }
1828
1829 cxd2841er_freeze_regs(priv);
1830 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1831 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1832 cxd2841er_unfreeze_regs(priv);
1833
1834 reg = ((u32)data[0] << 8) | (u32)data[1];
1835 if (reg == 0) {
1836 dev_dbg(&priv->i2c->dev,
1837 "%s(): reg value out of range\n", __func__);
1838 return 0;
1839 }
1840 if (reg > 10876)
1841 reg = 10876;
1842 *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(12600 - reg)) + 320);
1843 return 0;
1844 }
1845
cxd2841er_read_snr_i(struct cxd2841er_priv * priv,u32 * snr)1846 static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1847 {
1848 u32 reg;
1849 u8 data[2];
1850
1851 *snr = 0;
1852 if (priv->state != STATE_ACTIVE_TC) {
1853 dev_dbg(&priv->i2c->dev,
1854 "%s(): invalid state %d\n", __func__,
1855 priv->state);
1856 return -EINVAL;
1857 }
1858
1859 cxd2841er_freeze_regs(priv);
1860 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1861 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1862 cxd2841er_unfreeze_regs(priv);
1863
1864 reg = ((u32)data[0] << 8) | (u32)data[1];
1865 if (reg == 0) {
1866 dev_dbg(&priv->i2c->dev,
1867 "%s(): reg value out of range\n", __func__);
1868 return 0;
1869 }
1870 *snr = 10000 * (intlog10(reg) >> 24) - 9031;
1871 return 0;
1872 }
1873
cxd2841er_read_agc_gain_c(struct cxd2841er_priv * priv,u8 delsys)1874 static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1875 u8 delsys)
1876 {
1877 u8 data[2];
1878
1879 cxd2841er_write_reg(
1880 priv, I2C_SLVT, 0x00, 0x40);
1881 cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1882 dev_dbg(&priv->i2c->dev,
1883 "%s(): AGC value=%u\n",
1884 __func__, (((u16)data[0] & 0x0F) << 8) |
1885 (u16)(data[1] & 0xFF));
1886 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1887 }
1888
cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv * priv,u8 delsys)1889 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1890 u8 delsys)
1891 {
1892 u8 data[2];
1893
1894 cxd2841er_write_reg(
1895 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1896 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1897 dev_dbg(&priv->i2c->dev,
1898 "%s(): AGC value=%u\n",
1899 __func__, (((u16)data[0] & 0x0F) << 8) |
1900 (u16)(data[1] & 0xFF));
1901 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1902 }
1903
cxd2841er_read_agc_gain_i(struct cxd2841er_priv * priv,u8 delsys)1904 static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1905 u8 delsys)
1906 {
1907 u8 data[2];
1908
1909 cxd2841er_write_reg(
1910 priv, I2C_SLVT, 0x00, 0x60);
1911 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1912
1913 dev_dbg(&priv->i2c->dev,
1914 "%s(): AGC value=%u\n",
1915 __func__, (((u16)data[0] & 0x0F) << 8) |
1916 (u16)(data[1] & 0xFF));
1917 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1918 }
1919
cxd2841er_read_agc_gain_s(struct cxd2841er_priv * priv)1920 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1921 {
1922 u8 data[2];
1923
1924 /* Set SLV-T Bank : 0xA0 */
1925 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1926 /*
1927 * slave Bank Addr Bit Signal name
1928 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1929 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1930 */
1931 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1932 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1933 }
1934
cxd2841er_read_ber(struct dvb_frontend * fe)1935 static void cxd2841er_read_ber(struct dvb_frontend *fe)
1936 {
1937 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1938 struct cxd2841er_priv *priv = fe->demodulator_priv;
1939 u32 bit_error = 0, bit_count = 0;
1940 int ret;
1941
1942 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1943 switch (p->delivery_system) {
1944 case SYS_DVBC_ANNEX_A:
1945 case SYS_DVBC_ANNEX_B:
1946 case SYS_DVBC_ANNEX_C:
1947 ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
1948 break;
1949 case SYS_ISDBT:
1950 ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count);
1951 break;
1952 case SYS_DVBS:
1953 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
1954 break;
1955 case SYS_DVBS2:
1956 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
1957 break;
1958 case SYS_DVBT:
1959 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
1960 break;
1961 case SYS_DVBT2:
1962 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
1963 break;
1964 default:
1965 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1966 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1967 return;
1968 }
1969
1970 if (!ret) {
1971 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1972 p->post_bit_error.stat[0].uvalue += bit_error;
1973 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1974 p->post_bit_count.stat[0].uvalue += bit_count;
1975 } else {
1976 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1977 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1978 }
1979 }
1980
cxd2841er_read_signal_strength(struct dvb_frontend * fe)1981 static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
1982 {
1983 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1984 struct cxd2841er_priv *priv = fe->demodulator_priv;
1985 s32 strength;
1986
1987 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1988 switch (p->delivery_system) {
1989 case SYS_DVBT:
1990 case SYS_DVBT2:
1991 strength = cxd2841er_read_agc_gain_t_t2(priv,
1992 p->delivery_system);
1993 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1994 /* Formula was empirically determinated @ 410 MHz */
1995 p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
1996 break; /* Code moved out of the function */
1997 case SYS_DVBC_ANNEX_A:
1998 case SYS_DVBC_ANNEX_B:
1999 case SYS_DVBC_ANNEX_C:
2000 strength = cxd2841er_read_agc_gain_c(priv,
2001 p->delivery_system);
2002 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2003 /*
2004 * Formula was empirically determinated via linear regression,
2005 * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
2006 * stream modulated with QAM64
2007 */
2008 p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
2009 break;
2010 case SYS_ISDBT:
2011 strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
2012 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2013 /*
2014 * Formula was empirically determinated via linear regression,
2015 * using frequencies: 175 MHz, 410 MHz and 800 MHz.
2016 */
2017 p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
2018 break;
2019 case SYS_DVBS:
2020 case SYS_DVBS2:
2021 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
2022 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2023 p->strength.stat[0].uvalue = strength;
2024 break;
2025 default:
2026 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2027 break;
2028 }
2029 }
2030
cxd2841er_read_snr(struct dvb_frontend * fe)2031 static void cxd2841er_read_snr(struct dvb_frontend *fe)
2032 {
2033 u32 tmp = 0;
2034 int ret = 0;
2035 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2036 struct cxd2841er_priv *priv = fe->demodulator_priv;
2037
2038 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2039 switch (p->delivery_system) {
2040 case SYS_DVBC_ANNEX_A:
2041 case SYS_DVBC_ANNEX_B:
2042 case SYS_DVBC_ANNEX_C:
2043 ret = cxd2841er_read_snr_c(priv, &tmp);
2044 break;
2045 case SYS_DVBT:
2046 ret = cxd2841er_read_snr_t(priv, &tmp);
2047 break;
2048 case SYS_DVBT2:
2049 ret = cxd2841er_read_snr_t2(priv, &tmp);
2050 break;
2051 case SYS_ISDBT:
2052 ret = cxd2841er_read_snr_i(priv, &tmp);
2053 break;
2054 case SYS_DVBS:
2055 case SYS_DVBS2:
2056 ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
2057 break;
2058 default:
2059 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
2060 __func__, p->delivery_system);
2061 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2062 return;
2063 }
2064
2065 dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n",
2066 __func__, (int32_t)tmp);
2067
2068 if (!ret) {
2069 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2070 p->cnr.stat[0].svalue = tmp;
2071 } else {
2072 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2073 }
2074 }
2075
cxd2841er_read_ucblocks(struct dvb_frontend * fe)2076 static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
2077 {
2078 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2079 struct cxd2841er_priv *priv = fe->demodulator_priv;
2080 u32 ucblocks = 0;
2081
2082 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2083 switch (p->delivery_system) {
2084 case SYS_DVBC_ANNEX_A:
2085 case SYS_DVBC_ANNEX_B:
2086 case SYS_DVBC_ANNEX_C:
2087 cxd2841er_read_packet_errors_c(priv, &ucblocks);
2088 break;
2089 case SYS_DVBT:
2090 cxd2841er_read_packet_errors_t(priv, &ucblocks);
2091 break;
2092 case SYS_DVBT2:
2093 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
2094 break;
2095 case SYS_ISDBT:
2096 cxd2841er_read_packet_errors_i(priv, &ucblocks);
2097 break;
2098 default:
2099 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2100 return;
2101 }
2102 dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks);
2103
2104 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2105 p->block_error.stat[0].uvalue = ucblocks;
2106 }
2107
cxd2841er_dvbt2_set_profile(struct cxd2841er_priv * priv,enum cxd2841er_dvbt2_profile_t profile)2108 static int cxd2841er_dvbt2_set_profile(
2109 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
2110 {
2111 u8 tune_mode;
2112 u8 seq_not2d_time;
2113
2114 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2115 switch (profile) {
2116 case DVBT2_PROFILE_BASE:
2117 tune_mode = 0x01;
2118 /* Set early unlock time */
2119 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
2120 break;
2121 case DVBT2_PROFILE_LITE:
2122 tune_mode = 0x05;
2123 /* Set early unlock time */
2124 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2125 break;
2126 case DVBT2_PROFILE_ANY:
2127 tune_mode = 0x00;
2128 /* Set early unlock time */
2129 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2130 break;
2131 default:
2132 return -EINVAL;
2133 }
2134 /* Set SLV-T Bank : 0x2E */
2135 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
2136 /* Set profile and tune mode */
2137 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
2138 /* Set SLV-T Bank : 0x2B */
2139 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2140 /* Set early unlock detection time */
2141 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
2142 return 0;
2143 }
2144
cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv * priv,u8 is_auto,u8 plp_id)2145 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
2146 u8 is_auto, u8 plp_id)
2147 {
2148 if (is_auto) {
2149 dev_dbg(&priv->i2c->dev,
2150 "%s() using auto PLP selection\n", __func__);
2151 } else {
2152 dev_dbg(&priv->i2c->dev,
2153 "%s() using manual PLP selection, ID %d\n",
2154 __func__, plp_id);
2155 }
2156 /* Set SLV-T Bank : 0x23 */
2157 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2158 if (!is_auto) {
2159 /* Manual PLP selection mode. Set the data PLP Id. */
2160 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
2161 }
2162 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
2163 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
2164 return 0;
2165 }
2166
cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv * priv,u32 bandwidth)2167 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
2168 u32 bandwidth)
2169 {
2170 u32 iffreq, ifhz;
2171 u8 data[MAX_WRITE_REGSIZE];
2172
2173 static const uint8_t nominalRate8bw[3][5] = {
2174 /* TRCG Nominal Rate [37:0] */
2175 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2176 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2177 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
2178 };
2179
2180 static const uint8_t nominalRate7bw[3][5] = {
2181 /* TRCG Nominal Rate [37:0] */
2182 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2183 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2184 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
2185 };
2186
2187 static const uint8_t nominalRate6bw[3][5] = {
2188 /* TRCG Nominal Rate [37:0] */
2189 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2190 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2191 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
2192 };
2193
2194 static const uint8_t nominalRate5bw[3][5] = {
2195 /* TRCG Nominal Rate [37:0] */
2196 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2197 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2198 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
2199 };
2200
2201 static const uint8_t nominalRate17bw[3][5] = {
2202 /* TRCG Nominal Rate [37:0] */
2203 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
2204 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
2205 {0x58, 0xE2, 0xAF, 0xE0, 0xBC} /* 41MHz XTal */
2206 };
2207
2208 static const uint8_t itbCoef8bw[3][14] = {
2209 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2210 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2211 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
2212 0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
2213 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2214 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
2215 };
2216
2217 static const uint8_t itbCoef7bw[3][14] = {
2218 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2219 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2220 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
2221 0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
2222 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2223 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
2224 };
2225
2226 static const uint8_t itbCoef6bw[3][14] = {
2227 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2228 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2229 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2230 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2231 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2232 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2233 };
2234
2235 static const uint8_t itbCoef5bw[3][14] = {
2236 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2237 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2238 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2239 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2240 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2241 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2242 };
2243
2244 static const uint8_t itbCoef17bw[3][14] = {
2245 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2246 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
2247 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
2248 0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal */
2249 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2250 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99} /* 41MHz XTal */
2251 };
2252
2253 /* Set SLV-T Bank : 0x20 */
2254 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2255
2256 switch (bandwidth) {
2257 case 8000000:
2258 /* <Timing Recovery setting> */
2259 cxd2841er_write_regs(priv, I2C_SLVT,
2260 0x9F, nominalRate8bw[priv->xtal], 5);
2261
2262 /* Set SLV-T Bank : 0x27 */
2263 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2264 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2265 0x7a, 0x00, 0x0f);
2266
2267 /* Set SLV-T Bank : 0x10 */
2268 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2269
2270 /* Group delay equaliser settings for
2271 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2272 */
2273 if (priv->flags & CXD2841ER_ASCOT)
2274 cxd2841er_write_regs(priv, I2C_SLVT,
2275 0xA6, itbCoef8bw[priv->xtal], 14);
2276 /* <IF freq setting> */
2277 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2278 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2279 data[0] = (u8) ((iffreq >> 16) & 0xff);
2280 data[1] = (u8)((iffreq >> 8) & 0xff);
2281 data[2] = (u8)(iffreq & 0xff);
2282 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2283 /* System bandwidth setting */
2284 cxd2841er_set_reg_bits(
2285 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2286 break;
2287 case 7000000:
2288 /* <Timing Recovery setting> */
2289 cxd2841er_write_regs(priv, I2C_SLVT,
2290 0x9F, nominalRate7bw[priv->xtal], 5);
2291
2292 /* Set SLV-T Bank : 0x27 */
2293 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2294 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2295 0x7a, 0x00, 0x0f);
2296
2297 /* Set SLV-T Bank : 0x10 */
2298 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2299
2300 /* Group delay equaliser settings for
2301 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2302 */
2303 if (priv->flags & CXD2841ER_ASCOT)
2304 cxd2841er_write_regs(priv, I2C_SLVT,
2305 0xA6, itbCoef7bw[priv->xtal], 14);
2306 /* <IF freq setting> */
2307 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2308 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2309 data[0] = (u8) ((iffreq >> 16) & 0xff);
2310 data[1] = (u8)((iffreq >> 8) & 0xff);
2311 data[2] = (u8)(iffreq & 0xff);
2312 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2313 /* System bandwidth setting */
2314 cxd2841er_set_reg_bits(
2315 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2316 break;
2317 case 6000000:
2318 /* <Timing Recovery setting> */
2319 cxd2841er_write_regs(priv, I2C_SLVT,
2320 0x9F, nominalRate6bw[priv->xtal], 5);
2321
2322 /* Set SLV-T Bank : 0x27 */
2323 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2324 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2325 0x7a, 0x00, 0x0f);
2326
2327 /* Set SLV-T Bank : 0x10 */
2328 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2329
2330 /* Group delay equaliser settings for
2331 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2332 */
2333 if (priv->flags & CXD2841ER_ASCOT)
2334 cxd2841er_write_regs(priv, I2C_SLVT,
2335 0xA6, itbCoef6bw[priv->xtal], 14);
2336 /* <IF freq setting> */
2337 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2338 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2339 data[0] = (u8) ((iffreq >> 16) & 0xff);
2340 data[1] = (u8)((iffreq >> 8) & 0xff);
2341 data[2] = (u8)(iffreq & 0xff);
2342 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2343 /* System bandwidth setting */
2344 cxd2841er_set_reg_bits(
2345 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2346 break;
2347 case 5000000:
2348 /* <Timing Recovery setting> */
2349 cxd2841er_write_regs(priv, I2C_SLVT,
2350 0x9F, nominalRate5bw[priv->xtal], 5);
2351
2352 /* Set SLV-T Bank : 0x27 */
2353 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2354 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2355 0x7a, 0x00, 0x0f);
2356
2357 /* Set SLV-T Bank : 0x10 */
2358 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2359
2360 /* Group delay equaliser settings for
2361 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2362 */
2363 if (priv->flags & CXD2841ER_ASCOT)
2364 cxd2841er_write_regs(priv, I2C_SLVT,
2365 0xA6, itbCoef5bw[priv->xtal], 14);
2366 /* <IF freq setting> */
2367 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2368 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2369 data[0] = (u8) ((iffreq >> 16) & 0xff);
2370 data[1] = (u8)((iffreq >> 8) & 0xff);
2371 data[2] = (u8)(iffreq & 0xff);
2372 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2373 /* System bandwidth setting */
2374 cxd2841er_set_reg_bits(
2375 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2376 break;
2377 case 1712000:
2378 /* <Timing Recovery setting> */
2379 cxd2841er_write_regs(priv, I2C_SLVT,
2380 0x9F, nominalRate17bw[priv->xtal], 5);
2381
2382 /* Set SLV-T Bank : 0x27 */
2383 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2384 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2385 0x7a, 0x03, 0x0f);
2386
2387 /* Set SLV-T Bank : 0x10 */
2388 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2389
2390 /* Group delay equaliser settings for
2391 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2392 */
2393 if (priv->flags & CXD2841ER_ASCOT)
2394 cxd2841er_write_regs(priv, I2C_SLVT,
2395 0xA6, itbCoef17bw[priv->xtal], 14);
2396 /* <IF freq setting> */
2397 ifhz = cxd2841er_get_if_hz(priv, 3500000);
2398 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2399 data[0] = (u8) ((iffreq >> 16) & 0xff);
2400 data[1] = (u8)((iffreq >> 8) & 0xff);
2401 data[2] = (u8)(iffreq & 0xff);
2402 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2403 /* System bandwidth setting */
2404 cxd2841er_set_reg_bits(
2405 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
2406 break;
2407 default:
2408 return -EINVAL;
2409 }
2410 return 0;
2411 }
2412
cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv * priv,u32 bandwidth)2413 static int cxd2841er_sleep_tc_to_active_t_band(
2414 struct cxd2841er_priv *priv, u32 bandwidth)
2415 {
2416 u8 data[MAX_WRITE_REGSIZE];
2417 u32 iffreq, ifhz;
2418 static const u8 nominalRate8bw[3][5] = {
2419 /* TRCG Nominal Rate [37:0] */
2420 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2421 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2422 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
2423 };
2424 static const u8 nominalRate7bw[3][5] = {
2425 /* TRCG Nominal Rate [37:0] */
2426 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2427 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2428 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
2429 };
2430 static const u8 nominalRate6bw[3][5] = {
2431 /* TRCG Nominal Rate [37:0] */
2432 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2433 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2434 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
2435 };
2436 static const u8 nominalRate5bw[3][5] = {
2437 /* TRCG Nominal Rate [37:0] */
2438 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2439 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2440 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
2441 };
2442
2443 static const u8 itbCoef8bw[3][14] = {
2444 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2445 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2446 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2447 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
2448 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2449 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
2450 };
2451 static const u8 itbCoef7bw[3][14] = {
2452 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2453 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2454 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2455 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
2456 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2457 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
2458 };
2459 static const u8 itbCoef6bw[3][14] = {
2460 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2461 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2462 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2463 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2464 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2465 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2466 };
2467 static const u8 itbCoef5bw[3][14] = {
2468 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2469 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2470 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2471 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2472 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2473 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2474 };
2475
2476 /* Set SLV-T Bank : 0x13 */
2477 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2478 /* Echo performance optimization setting */
2479 data[0] = 0x01;
2480 data[1] = 0x14;
2481 cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2482
2483 /* Set SLV-T Bank : 0x10 */
2484 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2485
2486 switch (bandwidth) {
2487 case 8000000:
2488 /* <Timing Recovery setting> */
2489 cxd2841er_write_regs(priv, I2C_SLVT,
2490 0x9F, nominalRate8bw[priv->xtal], 5);
2491 /* Group delay equaliser settings for
2492 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2493 */
2494 if (priv->flags & CXD2841ER_ASCOT)
2495 cxd2841er_write_regs(priv, I2C_SLVT,
2496 0xA6, itbCoef8bw[priv->xtal], 14);
2497 /* <IF freq setting> */
2498 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2499 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2500 data[0] = (u8) ((iffreq >> 16) & 0xff);
2501 data[1] = (u8)((iffreq >> 8) & 0xff);
2502 data[2] = (u8)(iffreq & 0xff);
2503 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2504 /* System bandwidth setting */
2505 cxd2841er_set_reg_bits(
2506 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2507
2508 /* Demod core latency setting */
2509 if (priv->xtal == SONY_XTAL_24000) {
2510 data[0] = 0x15;
2511 data[1] = 0x28;
2512 } else {
2513 data[0] = 0x01;
2514 data[1] = 0xE0;
2515 }
2516 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2517
2518 /* Notch filter setting */
2519 data[0] = 0x01;
2520 data[1] = 0x02;
2521 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2522 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2523 break;
2524 case 7000000:
2525 /* <Timing Recovery setting> */
2526 cxd2841er_write_regs(priv, I2C_SLVT,
2527 0x9F, nominalRate7bw[priv->xtal], 5);
2528 /* Group delay equaliser settings for
2529 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2530 */
2531 if (priv->flags & CXD2841ER_ASCOT)
2532 cxd2841er_write_regs(priv, I2C_SLVT,
2533 0xA6, itbCoef7bw[priv->xtal], 14);
2534 /* <IF freq setting> */
2535 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2536 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2537 data[0] = (u8) ((iffreq >> 16) & 0xff);
2538 data[1] = (u8)((iffreq >> 8) & 0xff);
2539 data[2] = (u8)(iffreq & 0xff);
2540 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2541 /* System bandwidth setting */
2542 cxd2841er_set_reg_bits(
2543 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2544
2545 /* Demod core latency setting */
2546 if (priv->xtal == SONY_XTAL_24000) {
2547 data[0] = 0x1F;
2548 data[1] = 0xF8;
2549 } else {
2550 data[0] = 0x12;
2551 data[1] = 0xF8;
2552 }
2553 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2554
2555 /* Notch filter setting */
2556 data[0] = 0x00;
2557 data[1] = 0x03;
2558 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2559 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2560 break;
2561 case 6000000:
2562 /* <Timing Recovery setting> */
2563 cxd2841er_write_regs(priv, I2C_SLVT,
2564 0x9F, nominalRate6bw[priv->xtal], 5);
2565 /* Group delay equaliser settings for
2566 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2567 */
2568 if (priv->flags & CXD2841ER_ASCOT)
2569 cxd2841er_write_regs(priv, I2C_SLVT,
2570 0xA6, itbCoef6bw[priv->xtal], 14);
2571 /* <IF freq setting> */
2572 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2573 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2574 data[0] = (u8) ((iffreq >> 16) & 0xff);
2575 data[1] = (u8)((iffreq >> 8) & 0xff);
2576 data[2] = (u8)(iffreq & 0xff);
2577 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2578 /* System bandwidth setting */
2579 cxd2841er_set_reg_bits(
2580 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2581
2582 /* Demod core latency setting */
2583 if (priv->xtal == SONY_XTAL_24000) {
2584 data[0] = 0x25;
2585 data[1] = 0x4C;
2586 } else {
2587 data[0] = 0x1F;
2588 data[1] = 0xDC;
2589 }
2590 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2591
2592 /* Notch filter setting */
2593 data[0] = 0x00;
2594 data[1] = 0x03;
2595 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2596 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2597 break;
2598 case 5000000:
2599 /* <Timing Recovery setting> */
2600 cxd2841er_write_regs(priv, I2C_SLVT,
2601 0x9F, nominalRate5bw[priv->xtal], 5);
2602 /* Group delay equaliser settings for
2603 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2604 */
2605 if (priv->flags & CXD2841ER_ASCOT)
2606 cxd2841er_write_regs(priv, I2C_SLVT,
2607 0xA6, itbCoef5bw[priv->xtal], 14);
2608 /* <IF freq setting> */
2609 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2610 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2611 data[0] = (u8) ((iffreq >> 16) & 0xff);
2612 data[1] = (u8)((iffreq >> 8) & 0xff);
2613 data[2] = (u8)(iffreq & 0xff);
2614 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2615 /* System bandwidth setting */
2616 cxd2841er_set_reg_bits(
2617 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2618
2619 /* Demod core latency setting */
2620 if (priv->xtal == SONY_XTAL_24000) {
2621 data[0] = 0x2C;
2622 data[1] = 0xC2;
2623 } else {
2624 data[0] = 0x26;
2625 data[1] = 0x3C;
2626 }
2627 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2628
2629 /* Notch filter setting */
2630 data[0] = 0x00;
2631 data[1] = 0x03;
2632 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2633 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2634 break;
2635 }
2636
2637 return 0;
2638 }
2639
cxd2841er_sleep_tc_to_active_i_band(struct cxd2841er_priv * priv,u32 bandwidth)2640 static int cxd2841er_sleep_tc_to_active_i_band(
2641 struct cxd2841er_priv *priv, u32 bandwidth)
2642 {
2643 u32 iffreq, ifhz;
2644 u8 data[3];
2645
2646 /* TRCG Nominal Rate */
2647 static const u8 nominalRate8bw[3][5] = {
2648 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2649 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2650 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2651 };
2652
2653 static const u8 nominalRate7bw[3][5] = {
2654 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2655 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2656 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2657 };
2658
2659 static const u8 nominalRate6bw[3][5] = {
2660 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2661 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2662 {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
2663 };
2664
2665 static const u8 itbCoef8bw[3][14] = {
2666 {0x00}, /* 20.5MHz XTal */
2667 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2668 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2669 {0x0}, /* 41MHz XTal */
2670 };
2671
2672 static const u8 itbCoef7bw[3][14] = {
2673 {0x00}, /* 20.5MHz XTal */
2674 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2675 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2676 {0x00}, /* 41MHz XTal */
2677 };
2678
2679 static const u8 itbCoef6bw[3][14] = {
2680 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2681 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2682 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2683 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
2684 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2685 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
2686 };
2687
2688 dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2689 /* Set SLV-T Bank : 0x10 */
2690 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2691
2692 /* 20.5/41MHz Xtal support is not available
2693 * on ISDB-T 7MHzBW and 8MHzBW
2694 */
2695 if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2696 dev_err(&priv->i2c->dev,
2697 "%s(): bandwidth %d supported only for 24MHz xtal\n",
2698 __func__, bandwidth);
2699 return -EINVAL;
2700 }
2701
2702 switch (bandwidth) {
2703 case 8000000:
2704 /* TRCG Nominal Rate */
2705 cxd2841er_write_regs(priv, I2C_SLVT,
2706 0x9F, nominalRate8bw[priv->xtal], 5);
2707 /* Group delay equaliser settings for ASCOT tuners optimized */
2708 if (priv->flags & CXD2841ER_ASCOT)
2709 cxd2841er_write_regs(priv, I2C_SLVT,
2710 0xA6, itbCoef8bw[priv->xtal], 14);
2711
2712 /* IF freq setting */
2713 ifhz = cxd2841er_get_if_hz(priv, 4750000);
2714 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2715 data[0] = (u8) ((iffreq >> 16) & 0xff);
2716 data[1] = (u8)((iffreq >> 8) & 0xff);
2717 data[2] = (u8)(iffreq & 0xff);
2718 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2719
2720 /* System bandwidth setting */
2721 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2722
2723 /* Demod core latency setting */
2724 data[0] = 0x13;
2725 data[1] = 0xFC;
2726 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2727
2728 /* Acquisition optimization setting */
2729 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2730 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2731 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2732 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2733 break;
2734 case 7000000:
2735 /* TRCG Nominal Rate */
2736 cxd2841er_write_regs(priv, I2C_SLVT,
2737 0x9F, nominalRate7bw[priv->xtal], 5);
2738 /* Group delay equaliser settings for ASCOT tuners optimized */
2739 if (priv->flags & CXD2841ER_ASCOT)
2740 cxd2841er_write_regs(priv, I2C_SLVT,
2741 0xA6, itbCoef7bw[priv->xtal], 14);
2742
2743 /* IF freq setting */
2744 ifhz = cxd2841er_get_if_hz(priv, 4150000);
2745 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2746 data[0] = (u8) ((iffreq >> 16) & 0xff);
2747 data[1] = (u8)((iffreq >> 8) & 0xff);
2748 data[2] = (u8)(iffreq & 0xff);
2749 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2750
2751 /* System bandwidth setting */
2752 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2753
2754 /* Demod core latency setting */
2755 data[0] = 0x1A;
2756 data[1] = 0xFA;
2757 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2758
2759 /* Acquisition optimization setting */
2760 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2761 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2762 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2763 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2764 break;
2765 case 6000000:
2766 /* TRCG Nominal Rate */
2767 cxd2841er_write_regs(priv, I2C_SLVT,
2768 0x9F, nominalRate6bw[priv->xtal], 5);
2769 /* Group delay equaliser settings for ASCOT tuners optimized */
2770 if (priv->flags & CXD2841ER_ASCOT)
2771 cxd2841er_write_regs(priv, I2C_SLVT,
2772 0xA6, itbCoef6bw[priv->xtal], 14);
2773
2774 /* IF freq setting */
2775 ifhz = cxd2841er_get_if_hz(priv, 3550000);
2776 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2777 data[0] = (u8) ((iffreq >> 16) & 0xff);
2778 data[1] = (u8)((iffreq >> 8) & 0xff);
2779 data[2] = (u8)(iffreq & 0xff);
2780 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2781
2782 /* System bandwidth setting */
2783 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2784
2785 /* Demod core latency setting */
2786 if (priv->xtal == SONY_XTAL_24000) {
2787 data[0] = 0x1F;
2788 data[1] = 0x79;
2789 } else {
2790 data[0] = 0x1A;
2791 data[1] = 0xE2;
2792 }
2793 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2794
2795 /* Acquisition optimization setting */
2796 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2797 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2798 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2799 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2800 break;
2801 default:
2802 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2803 __func__, bandwidth);
2804 return -EINVAL;
2805 }
2806 return 0;
2807 }
2808
cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv * priv,u32 bandwidth)2809 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2810 u32 bandwidth)
2811 {
2812 u8 bw7_8mhz_b10_a6[] = {
2813 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2814 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2815 u8 bw6mhz_b10_a6[] = {
2816 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2817 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2818 u8 b10_b6[3];
2819 u32 iffreq, ifhz;
2820
2821 if (bandwidth != 6000000 &&
2822 bandwidth != 7000000 &&
2823 bandwidth != 8000000) {
2824 dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n",
2825 __func__, bandwidth);
2826 bandwidth = 8000000;
2827 }
2828
2829 dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
2830 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2831 switch (bandwidth) {
2832 case 8000000:
2833 case 7000000:
2834 if (priv->flags & CXD2841ER_ASCOT)
2835 cxd2841er_write_regs(
2836 priv, I2C_SLVT, 0xa6,
2837 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2838 ifhz = cxd2841er_get_if_hz(priv, 4900000);
2839 iffreq = cxd2841er_calc_iffreq(ifhz);
2840 break;
2841 case 6000000:
2842 if (priv->flags & CXD2841ER_ASCOT)
2843 cxd2841er_write_regs(
2844 priv, I2C_SLVT, 0xa6,
2845 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2846 ifhz = cxd2841er_get_if_hz(priv, 3700000);
2847 iffreq = cxd2841er_calc_iffreq(ifhz);
2848 break;
2849 default:
2850 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2851 __func__, bandwidth);
2852 return -EINVAL;
2853 }
2854 /* <IF freq setting> */
2855 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2856 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2857 b10_b6[2] = (u8)(iffreq & 0xff);
2858 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2859 /* Set SLV-T Bank : 0x11 */
2860 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2861 switch (bandwidth) {
2862 case 8000000:
2863 case 7000000:
2864 cxd2841er_set_reg_bits(
2865 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2866 break;
2867 case 6000000:
2868 cxd2841er_set_reg_bits(
2869 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2870 break;
2871 }
2872 /* Set SLV-T Bank : 0x40 */
2873 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2874 switch (bandwidth) {
2875 case 8000000:
2876 cxd2841er_set_reg_bits(
2877 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2878 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
2879 break;
2880 case 7000000:
2881 cxd2841er_set_reg_bits(
2882 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2883 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
2884 break;
2885 case 6000000:
2886 cxd2841er_set_reg_bits(
2887 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2888 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
2889 break;
2890 }
2891 return 0;
2892 }
2893
cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv * priv,u32 bandwidth)2894 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2895 u32 bandwidth)
2896 {
2897 u8 data[2] = { 0x09, 0x54 };
2898 u8 data24m[3] = {0xDC, 0x6C, 0x00};
2899
2900 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2901 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2902 /* Set SLV-X Bank : 0x00 */
2903 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2904 /* Set demod mode */
2905 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2906 /* Set SLV-T Bank : 0x00 */
2907 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2908 /* Enable demod clock */
2909 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2910 /* Disable RF level monitor */
2911 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2912 /* Enable ADC clock */
2913 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2914 /* Enable ADC 1 */
2915 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2916 /* Enable ADC 2 & 3 */
2917 if (priv->xtal == SONY_XTAL_41000) {
2918 data[0] = 0x0A;
2919 data[1] = 0xD4;
2920 }
2921 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2922 /* Enable ADC 4 */
2923 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2924 /* Set SLV-T Bank : 0x10 */
2925 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2926 /* IFAGC gain settings */
2927 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2928 /* Set SLV-T Bank : 0x11 */
2929 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2930 /* BBAGC TARGET level setting */
2931 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2932 /* Set SLV-T Bank : 0x10 */
2933 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2934 /* ASCOT setting */
2935 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
2936 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
2937 /* Set SLV-T Bank : 0x18 */
2938 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2939 /* Pre-RS BER monitor setting */
2940 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2941 /* FEC Auto Recovery setting */
2942 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2943 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2944 /* Set SLV-T Bank : 0x00 */
2945 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2946 /* TSIF setting */
2947 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2948 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2949
2950 if (priv->xtal == SONY_XTAL_24000) {
2951 /* Set SLV-T Bank : 0x10 */
2952 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2953 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2954 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2955 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2956 }
2957
2958 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2959 /* Set SLV-T Bank : 0x00 */
2960 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2961 /* Disable HiZ Setting 1 */
2962 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2963 /* Disable HiZ Setting 2 */
2964 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2965 priv->state = STATE_ACTIVE_TC;
2966 return 0;
2967 }
2968
cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv * priv,u32 bandwidth)2969 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2970 u32 bandwidth)
2971 {
2972 u8 data[MAX_WRITE_REGSIZE];
2973
2974 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2975 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2976 /* Set SLV-X Bank : 0x00 */
2977 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2978 /* Set demod mode */
2979 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2980 /* Set SLV-T Bank : 0x00 */
2981 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2982 /* Enable demod clock */
2983 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2984 /* Disable RF level monitor */
2985 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
2986 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2987 /* Enable ADC clock */
2988 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2989 /* Enable ADC 1 */
2990 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2991
2992 if (priv->xtal == SONY_XTAL_41000) {
2993 data[0] = 0x0A;
2994 data[1] = 0xD4;
2995 } else {
2996 data[0] = 0x09;
2997 data[1] = 0x54;
2998 }
2999
3000 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3001 /* Enable ADC 4 */
3002 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3003 /* Set SLV-T Bank : 0x10 */
3004 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3005 /* IFAGC gain settings */
3006 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
3007 /* Set SLV-T Bank : 0x11 */
3008 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3009 /* BBAGC TARGET level setting */
3010 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
3011 /* Set SLV-T Bank : 0x10 */
3012 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3013 /* ASCOT setting */
3014 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3015 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3016 /* Set SLV-T Bank : 0x20 */
3017 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3018 /* Acquisition optimization setting */
3019 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
3020 /* Set SLV-T Bank : 0x2b */
3021 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3022 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
3023 /* Set SLV-T Bank : 0x23 */
3024 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
3025 /* L1 Control setting */
3026 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
3027 /* Set SLV-T Bank : 0x00 */
3028 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3029 /* TSIF setting */
3030 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3031 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3032 /* DVB-T2 initial setting */
3033 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
3034 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
3035 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
3036 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
3037 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
3038 /* Set SLV-T Bank : 0x2a */
3039 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
3040 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
3041 /* Set SLV-T Bank : 0x2b */
3042 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3043 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
3044
3045 /* 24MHz Xtal setting */
3046 if (priv->xtal == SONY_XTAL_24000) {
3047 /* Set SLV-T Bank : 0x11 */
3048 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3049 data[0] = 0xEB;
3050 data[1] = 0x03;
3051 data[2] = 0x3B;
3052 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
3053
3054 /* Set SLV-T Bank : 0x20 */
3055 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3056 data[0] = 0x5E;
3057 data[1] = 0x5E;
3058 data[2] = 0x47;
3059 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
3060
3061 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
3062
3063 data[0] = 0x3F;
3064 data[1] = 0xFF;
3065 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
3066
3067 /* Set SLV-T Bank : 0x24 */
3068 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
3069 data[0] = 0x0B;
3070 data[1] = 0x72;
3071 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
3072
3073 data[0] = 0x93;
3074 data[1] = 0xF3;
3075 data[2] = 0x00;
3076 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
3077
3078 data[0] = 0x05;
3079 data[1] = 0xB8;
3080 data[2] = 0xD8;
3081 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
3082
3083 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
3084
3085 /* Set SLV-T Bank : 0x25 */
3086 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
3087 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
3088
3089 /* Set SLV-T Bank : 0x27 */
3090 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
3091 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
3092
3093 /* Set SLV-T Bank : 0x2B */
3094 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
3095 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
3096 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
3097
3098 /* Set SLV-T Bank : 0x2D */
3099 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
3100 data[0] = 0x89;
3101 data[1] = 0x89;
3102 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
3103
3104 /* Set SLV-T Bank : 0x5E */
3105 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
3106 data[0] = 0x24;
3107 data[1] = 0x95;
3108 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
3109 }
3110
3111 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
3112
3113 /* Set SLV-T Bank : 0x00 */
3114 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3115 /* Disable HiZ Setting 1 */
3116 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3117 /* Disable HiZ Setting 2 */
3118 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3119 priv->state = STATE_ACTIVE_TC;
3120 return 0;
3121 }
3122
3123 /* ISDB-Tb part */
cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv * priv,u32 bandwidth)3124 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
3125 u32 bandwidth)
3126 {
3127 u8 data[2] = { 0x09, 0x54 };
3128 u8 data24m[2] = {0x60, 0x00};
3129 u8 data24m2[3] = {0xB7, 0x1B, 0x00};
3130
3131 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3132 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
3133 /* Set SLV-X Bank : 0x00 */
3134 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3135 /* Set demod mode */
3136 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
3137 /* Set SLV-T Bank : 0x00 */
3138 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3139 /* Enable demod clock */
3140 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3141 /* Enable RF level monitor */
3142 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
3143 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
3144 /* Enable ADC clock */
3145 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3146 /* Enable ADC 1 */
3147 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3148 /* xtal freq 20.5MHz or 24M */
3149 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3150 /* Enable ADC 4 */
3151 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3152 /* ASCOT setting */
3153 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3154 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3155 /* FEC Auto Recovery setting */
3156 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
3157 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
3158 /* ISDB-T initial setting */
3159 /* Set SLV-T Bank : 0x00 */
3160 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3161 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
3162 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
3163 /* Set SLV-T Bank : 0x10 */
3164 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3165 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
3166 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
3167 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
3168 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
3169 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
3170 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
3171 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
3172 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
3173 /* Set SLV-T Bank : 0x15 */
3174 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
3175 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
3176 /* Set SLV-T Bank : 0x1E */
3177 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
3178 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
3179 /* Set SLV-T Bank : 0x63 */
3180 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
3181 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
3182
3183 /* for xtal 24MHz */
3184 /* Set SLV-T Bank : 0x10 */
3185 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3186 cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
3187 /* Set SLV-T Bank : 0x60 */
3188 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
3189 cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
3190
3191 cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
3192 /* Set SLV-T Bank : 0x00 */
3193 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3194 /* Disable HiZ Setting 1 */
3195 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3196 /* Disable HiZ Setting 2 */
3197 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3198 priv->state = STATE_ACTIVE_TC;
3199 return 0;
3200 }
3201
cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv * priv,u32 bandwidth)3202 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
3203 u32 bandwidth)
3204 {
3205 u8 data[2] = { 0x09, 0x54 };
3206
3207 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3208 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
3209 /* Set SLV-X Bank : 0x00 */
3210 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3211 /* Set demod mode */
3212 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
3213 /* Set SLV-T Bank : 0x00 */
3214 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3215 /* Enable demod clock */
3216 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3217 /* Disable RF level monitor */
3218 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
3219 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
3220 /* Enable ADC clock */
3221 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3222 /* Enable ADC 1 */
3223 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3224 /* xtal freq 20.5MHz */
3225 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3226 /* Enable ADC 4 */
3227 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3228 /* Set SLV-T Bank : 0x10 */
3229 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3230 /* IFAGC gain settings */
3231 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
3232 /* Set SLV-T Bank : 0x11 */
3233 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3234 /* BBAGC TARGET level setting */
3235 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
3236 /* Set SLV-T Bank : 0x10 */
3237 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3238 /* ASCOT setting */
3239 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3240 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3241 /* Set SLV-T Bank : 0x40 */
3242 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
3243 /* Demod setting */
3244 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
3245 /* Set SLV-T Bank : 0x00 */
3246 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3247 /* TSIF setting */
3248 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3249 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3250
3251 cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
3252 /* Set SLV-T Bank : 0x00 */
3253 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3254 /* Disable HiZ Setting 1 */
3255 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3256 /* Disable HiZ Setting 2 */
3257 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3258 priv->state = STATE_ACTIVE_TC;
3259 return 0;
3260 }
3261
cxd2841er_get_frontend(struct dvb_frontend * fe,struct dtv_frontend_properties * p)3262 static int cxd2841er_get_frontend(struct dvb_frontend *fe,
3263 struct dtv_frontend_properties *p)
3264 {
3265 enum fe_status status = 0;
3266 struct cxd2841er_priv *priv = fe->demodulator_priv;
3267
3268 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3269 if (priv->state == STATE_ACTIVE_S)
3270 cxd2841er_read_status_s(fe, &status);
3271 else if (priv->state == STATE_ACTIVE_TC)
3272 cxd2841er_read_status_tc(fe, &status);
3273
3274 if (priv->state == STATE_ACTIVE_TC || priv->state == STATE_ACTIVE_S)
3275 cxd2841er_read_signal_strength(fe);
3276 else
3277 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3278
3279 if (status & FE_HAS_LOCK) {
3280 if (priv->stats_time &&
3281 (!time_after(jiffies, priv->stats_time)))
3282 return 0;
3283
3284 /* Prevent retrieving stats faster than once per second */
3285 priv->stats_time = jiffies + msecs_to_jiffies(1000);
3286
3287 cxd2841er_read_snr(fe);
3288 cxd2841er_read_ucblocks(fe);
3289 cxd2841er_read_ber(fe);
3290 } else {
3291 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3292 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3293 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3294 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3295 }
3296 return 0;
3297 }
3298
cxd2841er_set_frontend_s(struct dvb_frontend * fe)3299 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
3300 {
3301 int ret = 0, i, timeout, carr_offset;
3302 enum fe_status status;
3303 struct cxd2841er_priv *priv = fe->demodulator_priv;
3304 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3305 u32 symbol_rate = p->symbol_rate/1000;
3306
3307 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
3308 __func__,
3309 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
3310 p->frequency, symbol_rate, priv->xtal);
3311
3312 if (priv->flags & CXD2841ER_EARLY_TUNE)
3313 cxd2841er_tuner_set(fe);
3314
3315 switch (priv->state) {
3316 case STATE_SLEEP_S:
3317 ret = cxd2841er_sleep_s_to_active_s(
3318 priv, p->delivery_system, symbol_rate);
3319 break;
3320 case STATE_ACTIVE_S:
3321 ret = cxd2841er_retune_active(priv, p);
3322 break;
3323 default:
3324 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3325 __func__, priv->state);
3326 ret = -EINVAL;
3327 goto done;
3328 }
3329 if (ret) {
3330 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3331 goto done;
3332 }
3333
3334 if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3335 cxd2841er_tuner_set(fe);
3336
3337 cxd2841er_tune_done(priv);
3338 timeout = DIV_ROUND_UP(3000000, symbol_rate) + 150;
3339
3340 i = 0;
3341 do {
3342 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3343 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3344 cxd2841er_read_status_s(fe, &status);
3345 if (status & FE_HAS_LOCK)
3346 break;
3347 i++;
3348 } while (i < timeout / CXD2841ER_DVBS_POLLING_INVL);
3349
3350 if (status & FE_HAS_LOCK) {
3351 if (cxd2841er_get_carrier_offset_s_s2(
3352 priv, &carr_offset)) {
3353 ret = -EINVAL;
3354 goto done;
3355 }
3356 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3357 __func__, carr_offset);
3358 }
3359 done:
3360 /* Reset stats */
3361 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3362 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3363 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3364 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3365 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3366
3367 /* Reset the wait for jiffies logic */
3368 priv->stats_time = 0;
3369
3370 return ret;
3371 }
3372
cxd2841er_set_frontend_tc(struct dvb_frontend * fe)3373 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3374 {
3375 int ret = 0, timeout;
3376 enum fe_status status;
3377 struct cxd2841er_priv *priv = fe->demodulator_priv;
3378 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3379
3380 dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3381 __func__, p->delivery_system, p->bandwidth_hz);
3382
3383 if (priv->flags & CXD2841ER_EARLY_TUNE)
3384 cxd2841er_tuner_set(fe);
3385
3386 /* deconfigure/put demod to sleep on delsys switch if active */
3387 if (priv->state == STATE_ACTIVE_TC &&
3388 priv->system != p->delivery_system) {
3389 dev_dbg(&priv->i2c->dev, "%s(): old_delsys=%d, new_delsys=%d -> sleep\n",
3390 __func__, priv->system, p->delivery_system);
3391 cxd2841er_sleep_tc(fe);
3392 }
3393
3394 if (p->delivery_system == SYS_DVBT) {
3395 priv->system = SYS_DVBT;
3396 switch (priv->state) {
3397 case STATE_SLEEP_TC:
3398 ret = cxd2841er_sleep_tc_to_active_t(
3399 priv, p->bandwidth_hz);
3400 break;
3401 case STATE_ACTIVE_TC:
3402 ret = cxd2841er_retune_active(priv, p);
3403 break;
3404 default:
3405 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3406 __func__, priv->state);
3407 ret = -EINVAL;
3408 }
3409 } else if (p->delivery_system == SYS_DVBT2) {
3410 priv->system = SYS_DVBT2;
3411 cxd2841er_dvbt2_set_plp_config(priv,
3412 (int)(p->stream_id > 255), p->stream_id);
3413 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3414 switch (priv->state) {
3415 case STATE_SLEEP_TC:
3416 ret = cxd2841er_sleep_tc_to_active_t2(priv,
3417 p->bandwidth_hz);
3418 break;
3419 case STATE_ACTIVE_TC:
3420 ret = cxd2841er_retune_active(priv, p);
3421 break;
3422 default:
3423 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3424 __func__, priv->state);
3425 ret = -EINVAL;
3426 }
3427 } else if (p->delivery_system == SYS_ISDBT) {
3428 priv->system = SYS_ISDBT;
3429 switch (priv->state) {
3430 case STATE_SLEEP_TC:
3431 ret = cxd2841er_sleep_tc_to_active_i(
3432 priv, p->bandwidth_hz);
3433 break;
3434 case STATE_ACTIVE_TC:
3435 ret = cxd2841er_retune_active(priv, p);
3436 break;
3437 default:
3438 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3439 __func__, priv->state);
3440 ret = -EINVAL;
3441 }
3442 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3443 p->delivery_system == SYS_DVBC_ANNEX_C) {
3444 priv->system = SYS_DVBC_ANNEX_A;
3445 /* correct bandwidth */
3446 if (p->bandwidth_hz != 6000000 &&
3447 p->bandwidth_hz != 7000000 &&
3448 p->bandwidth_hz != 8000000) {
3449 p->bandwidth_hz = 8000000;
3450 dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3451 __func__, p->bandwidth_hz);
3452 }
3453
3454 switch (priv->state) {
3455 case STATE_SLEEP_TC:
3456 ret = cxd2841er_sleep_tc_to_active_c(
3457 priv, p->bandwidth_hz);
3458 break;
3459 case STATE_ACTIVE_TC:
3460 ret = cxd2841er_retune_active(priv, p);
3461 break;
3462 default:
3463 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3464 __func__, priv->state);
3465 ret = -EINVAL;
3466 }
3467 } else {
3468 dev_dbg(&priv->i2c->dev,
3469 "%s(): invalid delivery system %d\n",
3470 __func__, p->delivery_system);
3471 ret = -EINVAL;
3472 }
3473 if (ret)
3474 goto done;
3475
3476 if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3477 cxd2841er_tuner_set(fe);
3478
3479 cxd2841er_tune_done(priv);
3480
3481 if (priv->flags & CXD2841ER_NO_WAIT_LOCK)
3482 goto done;
3483
3484 timeout = 2500;
3485 while (timeout > 0) {
3486 ret = cxd2841er_read_status_tc(fe, &status);
3487 if (ret)
3488 goto done;
3489 if (status & FE_HAS_LOCK)
3490 break;
3491 msleep(20);
3492 timeout -= 20;
3493 }
3494 if (timeout < 0)
3495 dev_dbg(&priv->i2c->dev,
3496 "%s(): LOCK wait timeout\n", __func__);
3497 done:
3498 return ret;
3499 }
3500
cxd2841er_tune_s(struct dvb_frontend * fe,bool re_tune,unsigned int mode_flags,unsigned int * delay,enum fe_status * status)3501 static int cxd2841er_tune_s(struct dvb_frontend *fe,
3502 bool re_tune,
3503 unsigned int mode_flags,
3504 unsigned int *delay,
3505 enum fe_status *status)
3506 {
3507 int ret, carrier_offset;
3508 struct cxd2841er_priv *priv = fe->demodulator_priv;
3509 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3510
3511 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3512 if (re_tune) {
3513 ret = cxd2841er_set_frontend_s(fe);
3514 if (ret)
3515 return ret;
3516 cxd2841er_read_status_s(fe, status);
3517 if (*status & FE_HAS_LOCK) {
3518 if (cxd2841er_get_carrier_offset_s_s2(
3519 priv, &carrier_offset))
3520 return -EINVAL;
3521 p->frequency += carrier_offset;
3522 ret = cxd2841er_set_frontend_s(fe);
3523 if (ret)
3524 return ret;
3525 }
3526 }
3527 *delay = HZ / 5;
3528 return cxd2841er_read_status_s(fe, status);
3529 }
3530
cxd2841er_tune_tc(struct dvb_frontend * fe,bool re_tune,unsigned int mode_flags,unsigned int * delay,enum fe_status * status)3531 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3532 bool re_tune,
3533 unsigned int mode_flags,
3534 unsigned int *delay,
3535 enum fe_status *status)
3536 {
3537 int ret, carrier_offset;
3538 struct cxd2841er_priv *priv = fe->demodulator_priv;
3539 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3540
3541 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3542 re_tune, p->bandwidth_hz);
3543 if (re_tune) {
3544 ret = cxd2841er_set_frontend_tc(fe);
3545 if (ret)
3546 return ret;
3547 cxd2841er_read_status_tc(fe, status);
3548 if (*status & FE_HAS_LOCK) {
3549 switch (priv->system) {
3550 case SYS_ISDBT:
3551 ret = cxd2841er_get_carrier_offset_i(
3552 priv, p->bandwidth_hz,
3553 &carrier_offset);
3554 if (ret)
3555 return ret;
3556 break;
3557 case SYS_DVBT:
3558 ret = cxd2841er_get_carrier_offset_t(
3559 priv, p->bandwidth_hz,
3560 &carrier_offset);
3561 if (ret)
3562 return ret;
3563 break;
3564 case SYS_DVBT2:
3565 ret = cxd2841er_get_carrier_offset_t2(
3566 priv, p->bandwidth_hz,
3567 &carrier_offset);
3568 if (ret)
3569 return ret;
3570 break;
3571 case SYS_DVBC_ANNEX_A:
3572 ret = cxd2841er_get_carrier_offset_c(
3573 priv, &carrier_offset);
3574 if (ret)
3575 return ret;
3576 break;
3577 default:
3578 dev_dbg(&priv->i2c->dev,
3579 "%s(): invalid delivery system %d\n",
3580 __func__, priv->system);
3581 return -EINVAL;
3582 }
3583 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3584 __func__, carrier_offset);
3585 p->frequency += carrier_offset;
3586 ret = cxd2841er_set_frontend_tc(fe);
3587 if (ret)
3588 return ret;
3589 }
3590 }
3591 *delay = HZ / 5;
3592 return cxd2841er_read_status_tc(fe, status);
3593 }
3594
cxd2841er_sleep_s(struct dvb_frontend * fe)3595 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3596 {
3597 struct cxd2841er_priv *priv = fe->demodulator_priv;
3598
3599 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3600 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3601 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3602 return 0;
3603 }
3604
cxd2841er_sleep_tc(struct dvb_frontend * fe)3605 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3606 {
3607 struct cxd2841er_priv *priv = fe->demodulator_priv;
3608
3609 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3610
3611 if (priv->state == STATE_ACTIVE_TC) {
3612 switch (priv->system) {
3613 case SYS_DVBT:
3614 cxd2841er_active_t_to_sleep_tc(priv);
3615 break;
3616 case SYS_DVBT2:
3617 cxd2841er_active_t2_to_sleep_tc(priv);
3618 break;
3619 case SYS_ISDBT:
3620 cxd2841er_active_i_to_sleep_tc(priv);
3621 break;
3622 case SYS_DVBC_ANNEX_A:
3623 cxd2841er_active_c_to_sleep_tc(priv);
3624 break;
3625 default:
3626 dev_warn(&priv->i2c->dev,
3627 "%s(): unknown delivery system %d\n",
3628 __func__, priv->system);
3629 }
3630 }
3631 if (priv->state != STATE_SLEEP_TC) {
3632 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3633 __func__, priv->state);
3634 return -EINVAL;
3635 }
3636 return 0;
3637 }
3638
cxd2841er_shutdown_tc(struct dvb_frontend * fe)3639 static int cxd2841er_shutdown_tc(struct dvb_frontend *fe)
3640 {
3641 struct cxd2841er_priv *priv = fe->demodulator_priv;
3642
3643 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3644
3645 if (!cxd2841er_sleep_tc(fe))
3646 cxd2841er_sleep_tc_to_shutdown(priv);
3647 return 0;
3648 }
3649
cxd2841er_send_burst(struct dvb_frontend * fe,enum fe_sec_mini_cmd burst)3650 static int cxd2841er_send_burst(struct dvb_frontend *fe,
3651 enum fe_sec_mini_cmd burst)
3652 {
3653 u8 data;
3654 struct cxd2841er_priv *priv = fe->demodulator_priv;
3655
3656 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3657 (burst == SEC_MINI_A ? "A" : "B"));
3658 if (priv->state != STATE_SLEEP_S &&
3659 priv->state != STATE_ACTIVE_S) {
3660 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3661 __func__, priv->state);
3662 return -EINVAL;
3663 }
3664 data = (burst == SEC_MINI_A ? 0 : 1);
3665 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3666 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3667 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3668 return 0;
3669 }
3670
cxd2841er_set_tone(struct dvb_frontend * fe,enum fe_sec_tone_mode tone)3671 static int cxd2841er_set_tone(struct dvb_frontend *fe,
3672 enum fe_sec_tone_mode tone)
3673 {
3674 u8 data;
3675 struct cxd2841er_priv *priv = fe->demodulator_priv;
3676
3677 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3678 (tone == SEC_TONE_ON ? "On" : "Off"));
3679 if (priv->state != STATE_SLEEP_S &&
3680 priv->state != STATE_ACTIVE_S) {
3681 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3682 __func__, priv->state);
3683 return -EINVAL;
3684 }
3685 data = (tone == SEC_TONE_ON ? 1 : 0);
3686 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3687 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3688 return 0;
3689 }
3690
cxd2841er_send_diseqc_msg(struct dvb_frontend * fe,struct dvb_diseqc_master_cmd * cmd)3691 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3692 struct dvb_diseqc_master_cmd *cmd)
3693 {
3694 int i;
3695 u8 data[12];
3696 struct cxd2841er_priv *priv = fe->demodulator_priv;
3697
3698 if (priv->state != STATE_SLEEP_S &&
3699 priv->state != STATE_ACTIVE_S) {
3700 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3701 __func__, priv->state);
3702 return -EINVAL;
3703 }
3704 dev_dbg(&priv->i2c->dev,
3705 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3706 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3707 /* DiDEqC enable */
3708 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3709 /* cmd1 length & data */
3710 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3711 memset(data, 0, sizeof(data));
3712 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3713 data[i] = cmd->msg[i];
3714 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3715 /* repeat count for cmd1 */
3716 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3717 /* repeat count for cmd2: always 0 */
3718 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3719 /* start transmit */
3720 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3721 /* wait for 1 sec timeout */
3722 for (i = 0; i < 50; i++) {
3723 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3724 if (!data[0]) {
3725 dev_dbg(&priv->i2c->dev,
3726 "%s(): DiSEqC cmd has been sent\n", __func__);
3727 return 0;
3728 }
3729 msleep(20);
3730 }
3731 dev_dbg(&priv->i2c->dev,
3732 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3733 return -ETIMEDOUT;
3734 }
3735
cxd2841er_release(struct dvb_frontend * fe)3736 static void cxd2841er_release(struct dvb_frontend *fe)
3737 {
3738 struct cxd2841er_priv *priv = fe->demodulator_priv;
3739
3740 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3741 kfree(priv);
3742 }
3743
cxd2841er_i2c_gate_ctrl(struct dvb_frontend * fe,int enable)3744 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3745 {
3746 struct cxd2841er_priv *priv = fe->demodulator_priv;
3747
3748 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3749 cxd2841er_set_reg_bits(
3750 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3751 return 0;
3752 }
3753
cxd2841er_get_algo(struct dvb_frontend * fe)3754 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3755 {
3756 struct cxd2841er_priv *priv = fe->demodulator_priv;
3757
3758 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3759 return DVBFE_ALGO_HW;
3760 }
3761
cxd2841er_init_stats(struct dvb_frontend * fe)3762 static void cxd2841er_init_stats(struct dvb_frontend *fe)
3763 {
3764 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3765
3766 p->strength.len = 1;
3767 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3768 p->cnr.len = 1;
3769 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3770 p->block_error.len = 1;
3771 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3772 p->post_bit_error.len = 1;
3773 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3774 p->post_bit_count.len = 1;
3775 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3776 }
3777
3778
cxd2841er_init_s(struct dvb_frontend * fe)3779 static int cxd2841er_init_s(struct dvb_frontend *fe)
3780 {
3781 struct cxd2841er_priv *priv = fe->demodulator_priv;
3782
3783 /* sanity. force demod to SHUTDOWN state */
3784 if (priv->state == STATE_SLEEP_S) {
3785 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3786 __func__);
3787 cxd2841er_sleep_s_to_shutdown(priv);
3788 } else if (priv->state == STATE_ACTIVE_S) {
3789 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3790 __func__);
3791 cxd2841er_active_s_to_sleep_s(priv);
3792 cxd2841er_sleep_s_to_shutdown(priv);
3793 }
3794
3795 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3796 cxd2841er_shutdown_to_sleep_s(priv);
3797 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3798 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3799 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3800
3801 cxd2841er_init_stats(fe);
3802
3803 return 0;
3804 }
3805
cxd2841er_init_tc(struct dvb_frontend * fe)3806 static int cxd2841er_init_tc(struct dvb_frontend *fe)
3807 {
3808 struct cxd2841er_priv *priv = fe->demodulator_priv;
3809 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3810
3811 dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3812 __func__, p->bandwidth_hz);
3813 cxd2841er_shutdown_to_sleep_tc(priv);
3814 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 (0 for NO_AGCNEG */
3815 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3816 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb,
3817 ((priv->flags & CXD2841ER_NO_AGCNEG) ? 0x00 : 0x40), 0x40);
3818 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3819 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3820 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3821 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3822 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
3823 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80);
3824
3825 /* clear TSCFG bits 3+4 */
3826 if (priv->flags & CXD2841ER_TSBITS)
3827 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18);
3828
3829 cxd2841er_init_stats(fe);
3830
3831 return 0;
3832 }
3833
3834 static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3835 static struct dvb_frontend_ops cxd2841er_t_c_ops;
3836
cxd2841er_attach(struct cxd2841er_config * cfg,struct i2c_adapter * i2c,u8 system)3837 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3838 struct i2c_adapter *i2c,
3839 u8 system)
3840 {
3841 u8 chip_id = 0;
3842 const char *type;
3843 const char *name;
3844 struct cxd2841er_priv *priv = NULL;
3845
3846 /* allocate memory for the internal state */
3847 priv = kzalloc_obj(struct cxd2841er_priv);
3848 if (!priv)
3849 return NULL;
3850 priv->i2c = i2c;
3851 priv->config = cfg;
3852 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3853 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
3854 priv->xtal = cfg->xtal;
3855 priv->flags = cfg->flags;
3856 priv->frontend.demodulator_priv = priv;
3857 dev_info(&priv->i2c->dev,
3858 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3859 __func__, priv->i2c,
3860 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3861 chip_id = cxd2841er_chip_id(priv);
3862 switch (chip_id) {
3863 case CXD2837ER_CHIP_ID:
3864 snprintf(cxd2841er_t_c_ops.info.name, 128,
3865 "Sony CXD2837ER DVB-T/T2/C demodulator");
3866 name = "CXD2837ER";
3867 type = "C/T/T2";
3868 break;
3869 case CXD2838ER_CHIP_ID:
3870 snprintf(cxd2841er_t_c_ops.info.name, 128,
3871 "Sony CXD2838ER ISDB-T demodulator");
3872 cxd2841er_t_c_ops.delsys[0] = SYS_ISDBT;
3873 cxd2841er_t_c_ops.delsys[1] = SYS_UNDEFINED;
3874 cxd2841er_t_c_ops.delsys[2] = SYS_UNDEFINED;
3875 name = "CXD2838ER";
3876 type = "ISDB-T";
3877 break;
3878 case CXD2841ER_CHIP_ID:
3879 snprintf(cxd2841er_t_c_ops.info.name, 128,
3880 "Sony CXD2841ER DVB-T/T2/C demodulator");
3881 name = "CXD2841ER";
3882 type = "T/T2/C/ISDB-T";
3883 break;
3884 case CXD2843ER_CHIP_ID:
3885 snprintf(cxd2841er_t_c_ops.info.name, 128,
3886 "Sony CXD2843ER DVB-T/T2/C/C2 demodulator");
3887 name = "CXD2843ER";
3888 type = "C/C2/T/T2";
3889 break;
3890 case CXD2854ER_CHIP_ID:
3891 snprintf(cxd2841er_t_c_ops.info.name, 128,
3892 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3893 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3894 name = "CXD2854ER";
3895 type = "C/C2/T/T2/ISDB-T";
3896 break;
3897 default:
3898 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3899 __func__, chip_id);
3900 priv->frontend.demodulator_priv = NULL;
3901 kfree(priv);
3902 return NULL;
3903 }
3904
3905 /* create dvb_frontend */
3906 if (system == SYS_DVBS) {
3907 memcpy(&priv->frontend.ops,
3908 &cxd2841er_dvbs_s2_ops,
3909 sizeof(struct dvb_frontend_ops));
3910 type = "S/S2";
3911 } else {
3912 memcpy(&priv->frontend.ops,
3913 &cxd2841er_t_c_ops,
3914 sizeof(struct dvb_frontend_ops));
3915 }
3916
3917 dev_info(&priv->i2c->dev,
3918 "%s(): attaching %s DVB-%s frontend\n",
3919 __func__, name, type);
3920 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3921 __func__, chip_id);
3922 return &priv->frontend;
3923 }
3924
cxd2841er_attach_s(struct cxd2841er_config * cfg,struct i2c_adapter * i2c)3925 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3926 struct i2c_adapter *i2c)
3927 {
3928 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3929 }
3930 EXPORT_SYMBOL_GPL(cxd2841er_attach_s);
3931
cxd2841er_attach_t_c(struct cxd2841er_config * cfg,struct i2c_adapter * i2c)3932 struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
3933 struct i2c_adapter *i2c)
3934 {
3935 return cxd2841er_attach(cfg, i2c, 0);
3936 }
3937 EXPORT_SYMBOL_GPL(cxd2841er_attach_t_c);
3938
3939 static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3940 .delsys = { SYS_DVBS, SYS_DVBS2 },
3941 .info = {
3942 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
3943 .frequency_min_hz = 500 * MHz,
3944 .frequency_max_hz = 2500 * MHz,
3945 .symbol_rate_min = 1000000,
3946 .symbol_rate_max = 45000000,
3947 .symbol_rate_tolerance = 500,
3948 .caps = FE_CAN_INVERSION_AUTO |
3949 FE_CAN_FEC_AUTO |
3950 FE_CAN_QPSK,
3951 },
3952 .init = cxd2841er_init_s,
3953 .sleep = cxd2841er_sleep_s,
3954 .release = cxd2841er_release,
3955 .set_frontend = cxd2841er_set_frontend_s,
3956 .get_frontend = cxd2841er_get_frontend,
3957 .read_status = cxd2841er_read_status_s,
3958 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3959 .get_frontend_algo = cxd2841er_get_algo,
3960 .set_tone = cxd2841er_set_tone,
3961 .diseqc_send_burst = cxd2841er_send_burst,
3962 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3963 .tune = cxd2841er_tune_s
3964 };
3965
3966 static struct dvb_frontend_ops cxd2841er_t_c_ops = {
3967 .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
3968 .info = {
3969 .name = "", /* will set in attach function */
3970 .caps = FE_CAN_FEC_1_2 |
3971 FE_CAN_FEC_2_3 |
3972 FE_CAN_FEC_3_4 |
3973 FE_CAN_FEC_5_6 |
3974 FE_CAN_FEC_7_8 |
3975 FE_CAN_FEC_AUTO |
3976 FE_CAN_QPSK |
3977 FE_CAN_QAM_16 |
3978 FE_CAN_QAM_32 |
3979 FE_CAN_QAM_64 |
3980 FE_CAN_QAM_128 |
3981 FE_CAN_QAM_256 |
3982 FE_CAN_QAM_AUTO |
3983 FE_CAN_TRANSMISSION_MODE_AUTO |
3984 FE_CAN_GUARD_INTERVAL_AUTO |
3985 FE_CAN_HIERARCHY_AUTO |
3986 FE_CAN_MUTE_TS |
3987 FE_CAN_2G_MODULATION,
3988 .frequency_min_hz = 42 * MHz,
3989 .frequency_max_hz = 1002 * MHz,
3990 .symbol_rate_min = 870000,
3991 .symbol_rate_max = 11700000
3992 },
3993 .init = cxd2841er_init_tc,
3994 .sleep = cxd2841er_shutdown_tc,
3995 .release = cxd2841er_release,
3996 .set_frontend = cxd2841er_set_frontend_tc,
3997 .get_frontend = cxd2841er_get_frontend,
3998 .read_status = cxd2841er_read_status_tc,
3999 .tune = cxd2841er_tune_tc,
4000 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
4001 .get_frontend_algo = cxd2841er_get_algo
4002 };
4003
4004 MODULE_DESCRIPTION("Sony CXD2837/38/41/43/54ER DVB-C/C2/T/T2/S/S2 demodulator driver");
4005 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
4006 MODULE_LICENSE("GPL");
4007