1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Helper routines for R-Car sound ADG.
4 //
5 // Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 #include <linux/clk-provider.h>
7 #include <linux/clkdev.h>
8 #include "rsnd.h"
9
10 #define CLKA 0
11 #define CLKB 1
12 #define CLKC 2
13 #define CLKI 3
14 #define CLKINMAX 4
15
16 #define CLKOUT 0
17 #define CLKOUT1 1
18 #define CLKOUT2 2
19 #define CLKOUT3 3
20 #define CLKOUTMAX 4
21
22 /* Maximum SSI count for per-SSI clocks */
23 #define ADG_SSI_MAX 10
24
25 #define BRGCKR_31 (1 << 31)
26 #define BRRx_MASK(x) (0x3FF & x)
27
28 static struct rsnd_mod_ops adg_ops = {
29 .name = "adg",
30 };
31
32 #define ADG_HZ_441 0
33 #define ADG_HZ_48 1
34 #define ADG_HZ_SIZE 2
35
36 struct rsnd_adg {
37 struct clk *adg;
38 struct clk *clkin[CLKINMAX];
39 struct clk *clkout[CLKOUTMAX];
40 /* RZ/G3E: per-SSI ADG clocks (adg-ssi-0 through adg-ssi-9) */
41 struct clk *clk_adg_ssi[ADG_SSI_MAX];
42 struct clk *clk_ssif_supply;
43 struct clk *null_clk;
44 struct clk_onecell_data onecell;
45 struct rsnd_mod mod;
46 int clkin_rate[CLKINMAX];
47 bool ssi_clk_prepared;
48 bool clk_enabled;
49 int clkin_size;
50 int clkout_size;
51 u32 ckr;
52 u32 brga;
53 u32 brgb;
54
55 int brg_rate[ADG_HZ_SIZE]; /* BRGA / BRGB */
56 };
57
58 #define for_each_rsnd_clkin(pos, adg, i) \
59 for (i = 0; \
60 (i < adg->clkin_size) && \
61 ((pos) = adg->clkin[i]); \
62 i++)
63 #define for_each_rsnd_clkout(pos, adg, i) \
64 for (i = 0; \
65 (i < adg->clkout_size) && \
66 ((pos) = adg->clkout[i]); \
67 i++)
68 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
69
70 static const char * const clkin_name_gen4[] = {
71 [CLKA] = "clkin",
72 };
73
74 static const char * const clkin_name_gen2[] = {
75 [CLKA] = "clk_a",
76 [CLKB] = "clk_b",
77 [CLKC] = "clk_c",
78 [CLKI] = "clk_i",
79 };
80
81 static const char * const clkin_name_rzg3e[] = {
82 [CLKA] = "audio-clka",
83 [CLKB] = "audio-clkb",
84 [CLKC] = "audio-clkc",
85 [CLKI] = "audio-clki",
86 };
87
88 static const char * const clkout_name_gen2[] = {
89 [CLKOUT] = "audio_clkout",
90 [CLKOUT1] = "audio_clkout1",
91 [CLKOUT2] = "audio_clkout2",
92 [CLKOUT3] = "audio_clkout3",
93 };
94
rsnd_adg_calculate_brgx(unsigned long div)95 static u32 rsnd_adg_calculate_brgx(unsigned long div)
96 {
97 int i;
98
99 if (!div)
100 return 0;
101
102 for (i = 3; i >= 0; i--) {
103 int ratio = 2 << (i * 2);
104 if (0 == (div % ratio))
105 return (u32)((i << 8) | ((div / ratio) - 1));
106 }
107
108 return ~0;
109 }
110
rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream * io)111 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
112 {
113 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
114 int id = rsnd_mod_id(ssi_mod);
115 int ws = id;
116
117 if (rsnd_ssi_is_pin_sharing(io)) {
118 switch (id) {
119 case 1:
120 case 2:
121 case 9:
122 ws = 0;
123 break;
124 case 4:
125 ws = 3;
126 break;
127 case 8:
128 ws = 7;
129 break;
130 }
131 } else {
132 /*
133 * SSI8 is not connected to ADG.
134 * Thus SSI9 is using ws = 8
135 */
136 if (id == 9)
137 ws = 8;
138 }
139
140 return (0x6 + ws) << 8;
141 }
142
__rsnd_adg_get_timesel_ratio(struct rsnd_priv * priv,struct rsnd_dai_stream * io,unsigned int target_rate,unsigned int * target_val,unsigned int * target_en)143 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
144 struct rsnd_dai_stream *io,
145 unsigned int target_rate,
146 unsigned int *target_val,
147 unsigned int *target_en)
148 {
149 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
150 struct device *dev = rsnd_priv_to_dev(priv);
151 int sel;
152 unsigned int val, en;
153 unsigned int min, diff;
154 unsigned int sel_rate[] = {
155 adg->clkin_rate[CLKA], /* 0000: CLKA */
156 adg->clkin_rate[CLKB], /* 0001: CLKB */
157 adg->clkin_rate[CLKC], /* 0010: CLKC */
158 adg->brg_rate[ADG_HZ_441], /* 0011: BRGA */
159 adg->brg_rate[ADG_HZ_48], /* 0100: BRGB */
160 };
161
162 min = ~0;
163 val = 0;
164 en = 0;
165 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
166 int idx = 0;
167 int step = 2;
168 int div;
169
170 if (!sel_rate[sel])
171 continue;
172
173 for (div = 2; div <= 98304; div += step) {
174 diff = abs(target_rate - sel_rate[sel] / div);
175 if (min > diff) {
176 val = (sel << 8) | idx;
177 min = diff;
178 en = 1 << (sel + 1); /* fixme */
179 }
180
181 /*
182 * step of 0_0000 / 0_0001 / 0_1101
183 * are out of order
184 */
185 if ((idx > 2) && (idx % 2))
186 step *= 2;
187 if (idx == 0x1c) {
188 div += step;
189 step *= 2;
190 }
191 idx++;
192 }
193 }
194
195 if (min == ~0) {
196 dev_err(dev, "no Input clock\n");
197 return;
198 }
199
200 *target_val = val;
201 if (target_en)
202 *target_en = en;
203 }
204
rsnd_adg_get_timesel_ratio(struct rsnd_priv * priv,struct rsnd_dai_stream * io,unsigned int in_rate,unsigned int out_rate,u32 * in,u32 * out,u32 * en)205 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
206 struct rsnd_dai_stream *io,
207 unsigned int in_rate,
208 unsigned int out_rate,
209 u32 *in, u32 *out, u32 *en)
210 {
211 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
212 unsigned int target_rate;
213 u32 *target_val;
214 u32 _in;
215 u32 _out;
216 u32 _en;
217
218 /* default = SSI WS */
219 _in =
220 _out = rsnd_adg_ssi_ws_timing_gen2(io);
221
222 target_rate = 0;
223 target_val = NULL;
224 _en = 0;
225 if (runtime->rate != in_rate) {
226 target_rate = out_rate;
227 target_val = &_out;
228 } else if (runtime->rate != out_rate) {
229 target_rate = in_rate;
230 target_val = &_in;
231 }
232
233 if (target_rate)
234 __rsnd_adg_get_timesel_ratio(priv, io,
235 target_rate,
236 target_val, &_en);
237
238 if (in)
239 *in = _in;
240 if (out)
241 *out = _out;
242 if (en)
243 *en = _en;
244 }
245
rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod * cmd_mod,struct rsnd_dai_stream * io)246 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
247 struct rsnd_dai_stream *io)
248 {
249 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
250 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
251 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
252 int id = rsnd_mod_id(cmd_mod);
253 int shift = (id % 2) ? 16 : 0;
254 u32 mask, val;
255
256 rsnd_adg_get_timesel_ratio(priv, io,
257 rsnd_src_get_in_rate(priv, io),
258 rsnd_src_get_out_rate(priv, io),
259 NULL, &val, NULL);
260
261 val = val << shift;
262 mask = 0x0f1f << shift;
263
264 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
265
266 return 0;
267 }
268
rsnd_adg_set_src_timesel_gen2(struct rsnd_mod * src_mod,struct rsnd_dai_stream * io,unsigned int in_rate,unsigned int out_rate)269 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
270 struct rsnd_dai_stream *io,
271 unsigned int in_rate,
272 unsigned int out_rate)
273 {
274 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
275 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
276 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
277 u32 in, out;
278 u32 mask, en;
279 int id = rsnd_mod_id(src_mod);
280 int shift = (id % 2) ? 16 : 0;
281
282 rsnd_mod_make_sure(src_mod, RSND_MOD_SRC);
283
284 rsnd_adg_get_timesel_ratio(priv, io,
285 in_rate, out_rate,
286 &in, &out, &en);
287
288 in = in << shift;
289 out = out << shift;
290 mask = 0x0f1f << shift;
291
292 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2), mask, in);
293 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out);
294
295 if (en)
296 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
297
298 return 0;
299 }
300
rsnd_adg_set_ssi_clk(struct rsnd_mod * ssi_mod,u32 val)301 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
302 {
303 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
304 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
305 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
306 struct device *dev = rsnd_priv_to_dev(priv);
307 int id = rsnd_mod_id(ssi_mod);
308 int shift = (id % 4) * 8;
309 u32 mask = 0xFF << shift;
310
311 rsnd_mod_make_sure(ssi_mod, RSND_MOD_SSI);
312
313 val = val << shift;
314
315 /*
316 * SSI 8 is not connected to ADG.
317 * it works with SSI 7
318 */
319 if (id == 8)
320 return;
321
322 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val);
323
324 dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
325 }
326
rsnd_adg_clk_query(struct rsnd_priv * priv,unsigned int rate)327 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
328 {
329 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
330 struct clk *clk;
331 int i;
332 int sel_table[] = {
333 [CLKA] = 0x1,
334 [CLKB] = 0x2,
335 [CLKC] = 0x3,
336 [CLKI] = 0x0,
337 };
338
339 /*
340 * find suitable clock from
341 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
342 */
343 for_each_rsnd_clkin(clk, adg, i)
344 if (rate == adg->clkin_rate[i])
345 return sel_table[i];
346
347 /*
348 * find divided clock from BRGA/BRGB
349 */
350 if (rate == adg->brg_rate[ADG_HZ_441])
351 return 0x10;
352
353 if (rate == adg->brg_rate[ADG_HZ_48])
354 return 0x20;
355
356 return -EIO;
357 }
358
rsnd_adg_ssi_clk_stop(struct rsnd_mod * ssi_mod)359 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
360 {
361 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
362 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
363 int id = rsnd_mod_id(ssi_mod);
364
365 rsnd_adg_set_ssi_clk(ssi_mod, 0);
366
367 /* RZ/G3E: only disable here, unprepare is done in hw_free */
368 clk_disable(adg->clk_adg_ssi[id]);
369 clk_disable(adg->clk_ssif_supply);
370
371 return 0;
372 }
373
rsnd_adg_ssi_clk_try_start(struct rsnd_mod * ssi_mod,unsigned int rate)374 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
375 {
376 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
377 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
378 struct device *dev = rsnd_priv_to_dev(priv);
379 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
380 int id = rsnd_mod_id(ssi_mod);
381 int ret, data;
382 u32 ckr = 0;
383
384 data = rsnd_adg_clk_query(priv, rate);
385 if (data < 0)
386 return data;
387
388 rsnd_adg_set_ssi_clk(ssi_mod, data);
389
390 ckr = adg->ckr & ~BRGCKR_31;
391 if (0 == (rate % 8000))
392 ckr |= BRGCKR_31; /* use BRGB output = 48kHz */
393 if (ckr != adg->ckr) {
394 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr);
395 adg->ckr = ckr;
396 }
397
398 dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
399 (ckr) ? 'B' : 'A',
400 (ckr) ? adg->brg_rate[ADG_HZ_48] :
401 adg->brg_rate[ADG_HZ_441]);
402
403 /*
404 * RZ/G3E: enable per-SSI and supply clocks
405 */
406 ret = clk_enable(adg->clk_adg_ssi[id]);
407 if (ret) {
408 dev_err(dev, "Cannot enable adg-ssi-%d ADG clock\n", id);
409 return ret;
410 }
411
412 ret = clk_enable(adg->clk_ssif_supply);
413 if (ret) {
414 dev_err(dev, "Cannot enable SSIF supply clock\n");
415 clk_disable(adg->clk_adg_ssi[id]);
416 return ret;
417 }
418
419 return 0;
420 }
421
rsnd_adg_ssi_clk_prepare(struct rsnd_adg * adg)422 static int rsnd_adg_ssi_clk_prepare(struct rsnd_adg *adg)
423 {
424 int i, ret;
425
426 if (adg->ssi_clk_prepared)
427 return 0;
428
429 for (i = 0; i < ADG_SSI_MAX; i++) {
430 ret = clk_prepare(adg->clk_adg_ssi[i]);
431 if (ret)
432 goto unwind;
433 }
434 ret = clk_prepare(adg->clk_ssif_supply);
435 if (ret)
436 goto unwind;
437
438 adg->ssi_clk_prepared = true;
439 return 0;
440
441 unwind:
442 while (i--)
443 clk_unprepare(adg->clk_adg_ssi[i]);
444 return ret;
445 }
446
rsnd_adg_ssi_clk_unprepare(struct rsnd_adg * adg)447 static void rsnd_adg_ssi_clk_unprepare(struct rsnd_adg *adg)
448 {
449 int i;
450
451 if (!adg->ssi_clk_prepared)
452 return;
453 adg->ssi_clk_prepared = false;
454
455 clk_unprepare(adg->clk_ssif_supply);
456 for (i = 0; i < ADG_SSI_MAX; i++)
457 clk_unprepare(adg->clk_adg_ssi[i]);
458 }
459
rsnd_adg_clk_control(struct rsnd_priv * priv,int enable)460 int rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
461 {
462 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
463 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
464 struct clk *clk;
465 int ret = 0, i;
466
467 /*
468 * rsnd_adg_clk_enable() and rsnd_adg_clk_disable() can be called
469 * redundantly, for example when system suspend follows a resume
470 * whose enable failed. Make this function idempotent so that the
471 * "adg" clock, which has no clkin_rate[] style guard, is never
472 * disabled twice.
473 */
474 if (enable) {
475 if (adg->clk_enabled)
476 return 0;
477 } else {
478 if (!adg->clk_enabled)
479 return 0;
480 adg->clk_enabled = false;
481 }
482
483 if (enable) {
484 ret = clk_prepare_enable(adg->adg);
485 if (ret < 0)
486 return ret;
487
488 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr);
489 rsnd_mod_write(adg_mod, BRRA, adg->brga);
490 rsnd_mod_write(adg_mod, BRRB, adg->brgb);
491 }
492
493 for_each_rsnd_clkin(clk, adg, i) {
494 if (enable) {
495 ret = clk_prepare_enable(clk);
496
497 /*
498 * We shouldn't use clk_get_rate() under
499 * atomic context. Let's keep it when
500 * rsnd_adg_clk_enable() was called
501 */
502 if (ret < 0)
503 break;
504
505 adg->clkin_rate[i] = clk_get_rate(clk);
506 } else {
507 if (adg->clkin_rate[i])
508 clk_disable_unprepare(clk);
509
510 adg->clkin_rate[i] = 0;
511 }
512 }
513
514 /*
515 * rsnd_adg_clk_enable() might return error (_disable() will not).
516 * We need to rollback in such case
517 */
518 /*
519 * RZ/G3E per-SSI ADG and SSIF supply clocks.
520 *
521 * Follow the same style as for_each_rsnd_clkin() above: on enable,
522 * try to prepare every clock and accumulate the error. On disable,
523 * unprepare every clock. Absent optional clocks are NULL, for
524 * which clk_prepare() and clk_unprepare() are no-ops.
525 */
526 if (enable) {
527 int sub_ret = rsnd_adg_ssi_clk_prepare(adg);
528
529 /* Preserve the first error from the clkin loop above. */
530 if (sub_ret && !ret)
531 ret = sub_ret;
532 } else {
533 rsnd_adg_ssi_clk_unprepare(adg);
534 }
535
536 /*
537 * rsnd_adg_clk_enable() might return error (_disable() will not).
538 * We need to rollback in such case
539 */
540 if (ret < 0) {
541 /*
542 * Mark as enabled so that the rollback below is not
543 * short-circuited by the idempotency guard. It clears
544 * the flag again on its way through.
545 */
546 adg->clk_enabled = true;
547 rsnd_adg_clk_disable(priv);
548 return ret;
549 }
550
551 /* disable adg */
552 if (!enable)
553 clk_disable_unprepare(adg->adg);
554 else
555 adg->clk_enabled = true;
556
557 return ret;
558 }
559
rsnd_adg_create_null_clk(struct rsnd_priv * priv,const char * const name,const char * parent)560 static struct clk *rsnd_adg_create_null_clk(struct rsnd_priv *priv,
561 const char * const name,
562 const char *parent)
563 {
564 struct device *dev = rsnd_priv_to_dev(priv);
565 struct clk *clk;
566
567 clk = clk_register_fixed_rate(dev, name, parent, 0, 0);
568 if (IS_ERR(clk)) {
569 dev_err(dev, "create null clk error\n");
570 return ERR_CAST(clk);
571 }
572
573 return clk;
574 }
575
rsnd_adg_null_clk_get(struct rsnd_priv * priv)576 static struct clk *rsnd_adg_null_clk_get(struct rsnd_priv *priv)
577 {
578 struct rsnd_adg *adg = priv->adg;
579
580 if (!adg->null_clk) {
581 static const char * const name = "rsnd_adg_null";
582
583 adg->null_clk = rsnd_adg_create_null_clk(priv, name, NULL);
584 }
585
586 return adg->null_clk;
587 }
588
rsnd_adg_null_clk_clean(struct rsnd_priv * priv)589 static void rsnd_adg_null_clk_clean(struct rsnd_priv *priv)
590 {
591 struct rsnd_adg *adg = priv->adg;
592
593 if (adg->null_clk)
594 clk_unregister_fixed_rate(adg->null_clk);
595 }
596
rsnd_adg_get_clkin(struct rsnd_priv * priv)597 static int rsnd_adg_get_clkin(struct rsnd_priv *priv)
598 {
599 struct rsnd_adg *adg = priv->adg;
600 struct device *dev = rsnd_priv_to_dev(priv);
601 struct clk *clk;
602 const char * const *clkin_name;
603 int clkin_size;
604 int i;
605
606 clkin_name = clkin_name_gen2;
607 clkin_size = ARRAY_SIZE(clkin_name_gen2);
608 if (rsnd_is_gen4(priv)) {
609 clkin_name = clkin_name_gen4;
610 clkin_size = ARRAY_SIZE(clkin_name_gen4);
611 } else if (rsnd_is_rzg3e(priv)) {
612 clkin_name = clkin_name_rzg3e;
613 clkin_size = ARRAY_SIZE(clkin_name_rzg3e);
614 }
615
616 /*
617 * get adg
618 * No "adg" is not error
619 */
620 clk = devm_clk_get(dev, "adg");
621 if (IS_ERR(clk))
622 clk = rsnd_adg_null_clk_get(priv);
623 adg->adg = clk;
624
625 /* get clkin */
626 for (i = 0; i < clkin_size; i++) {
627 clk = devm_clk_get(dev, clkin_name[i]);
628
629 if (IS_ERR(clk))
630 clk = rsnd_adg_null_clk_get(priv);
631 if (IS_ERR(clk))
632 goto err;
633
634 adg->clkin[i] = clk;
635 }
636
637 adg->clkin_size = clkin_size;
638
639 return 0;
640
641 err:
642 dev_err(dev, "adg clock IN get failed\n");
643
644 rsnd_adg_null_clk_clean(priv);
645
646 return -EIO;
647 }
648
rsnd_adg_unregister_clkout(struct rsnd_priv * priv)649 static void rsnd_adg_unregister_clkout(struct rsnd_priv *priv)
650 {
651 struct rsnd_adg *adg = priv->adg;
652 struct clk *clk;
653 int i;
654
655 for_each_rsnd_clkout(clk, adg, i)
656 clk_unregister_fixed_rate(clk);
657 }
658
rsnd_adg_get_clkout(struct rsnd_priv * priv)659 static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
660 {
661 struct rsnd_adg *adg = priv->adg;
662 struct clk *clk;
663 struct device *dev = rsnd_priv_to_dev(priv);
664 struct device_node *np = dev->of_node;
665 struct property *prop;
666 u32 ckr, brgx, brga, brgb;
667 u32 req_rate[ADG_HZ_SIZE] = {};
668 uint32_t count = 0;
669 unsigned long req_Hz[ADG_HZ_SIZE];
670 int clkout_size;
671 int i, req_size;
672 int approximate = 0;
673 const char *parent_clk_name = NULL;
674 const char * const *clkout_name;
675 int brg_table[] = {
676 [CLKA] = 0x0,
677 [CLKB] = 0x1,
678 [CLKC] = 0x4,
679 [CLKI] = 0x2,
680 };
681
682 ckr = 0;
683 brga = 0xff; /* default */
684 brgb = 0xff; /* default */
685
686 /*
687 * ADG supports BRRA/BRRB output only
688 * this means all clkout0/1/2/3 will be same rate
689 */
690 prop = of_find_property(np, "clock-frequency", NULL);
691 if (!prop)
692 goto rsnd_adg_get_clkout_end;
693
694 req_size = prop->length / sizeof(u32);
695 if (req_size > ADG_HZ_SIZE) {
696 dev_err(dev, "too many clock-frequency\n");
697 return -EINVAL;
698 }
699
700 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
701 req_Hz[ADG_HZ_48] = 0;
702 req_Hz[ADG_HZ_441] = 0;
703 for (i = 0; i < req_size; i++) {
704 if (0 == (req_rate[i] % 44100))
705 req_Hz[ADG_HZ_441] = req_rate[i];
706 if (0 == (req_rate[i] % 48000))
707 req_Hz[ADG_HZ_48] = req_rate[i];
708 }
709
710 /*
711 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
712 * have 44.1kHz or 48kHz base clocks for now.
713 *
714 * SSI itself can divide parent clock by 1/1 - 1/16
715 * see
716 * rsnd_adg_ssi_clk_try_start()
717 * rsnd_ssi_master_clk_start()
718 */
719
720 /*
721 * [APPROXIMATE]
722 *
723 * clk_i (internal clock) can't create accurate rate, it will be approximate rate.
724 *
725 * <Note>
726 *
727 * clk_i needs x2 of required maximum rate.
728 * see
729 * - Minimum division of BRRA/BRRB
730 * - rsnd_ssi_clk_query()
731 *
732 * Sample Settings for TDM 8ch, 32bit width
733 *
734 * 8(ch) x 32(bit) x 44100(Hz) x 2<Note> = 22579200
735 * 8(ch) x 32(bit) x 48000(Hz) x 2<Note> = 24576000
736 *
737 * clock-frequency = <22579200 24576000>;
738 */
739 for_each_rsnd_clkin(clk, adg, i) {
740 u32 rate, div;
741
742 rate = clk_get_rate(clk);
743
744 if (0 == rate) /* not used */
745 continue;
746
747 /* BRGA */
748
749 if (i == CLKI)
750 /* see [APPROXIMATE] */
751 rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_441]) * req_Hz[ADG_HZ_441];
752 if (!adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441] && (0 == rate % 44100)) {
753 div = rate / req_Hz[ADG_HZ_441];
754 brgx = rsnd_adg_calculate_brgx(div);
755 if (BRRx_MASK(brgx) == brgx) {
756 brga = brgx;
757 adg->brg_rate[ADG_HZ_441] = rate / div;
758 ckr |= brg_table[i] << 20;
759 if (req_Hz[ADG_HZ_441])
760 parent_clk_name = __clk_get_name(clk);
761 if (i == CLKI)
762 approximate = 1;
763 }
764 }
765
766 /* BRGB */
767
768 if (i == CLKI)
769 /* see [APPROXIMATE] */
770 rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_48]) * req_Hz[ADG_HZ_48];
771 if (!adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48] && (0 == rate % 48000)) {
772 div = rate / req_Hz[ADG_HZ_48];
773 brgx = rsnd_adg_calculate_brgx(div);
774 if (BRRx_MASK(brgx) == brgx) {
775 brgb = brgx;
776 adg->brg_rate[ADG_HZ_48] = rate / div;
777 ckr |= brg_table[i] << 16;
778 if (req_Hz[ADG_HZ_48])
779 parent_clk_name = __clk_get_name(clk);
780 if (i == CLKI)
781 approximate = 1;
782 }
783 }
784 }
785
786 if (!(adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48]) &&
787 !(adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441]))
788 goto rsnd_adg_get_clkout_end;
789
790 if (approximate)
791 dev_info(dev, "It uses CLK_I as approximate rate");
792
793 clkout_name = clkout_name_gen2;
794 clkout_size = ARRAY_SIZE(clkout_name_gen2);
795 if (rsnd_is_gen4(priv))
796 clkout_size = 1; /* reuse clkout_name_gen2[] */
797
798 /*
799 * ADG supports BRRA/BRRB output only.
800 * this means all clkout0/1/2/3 will be * same rate
801 */
802
803 of_property_read_u32(np, "#clock-cells", &count);
804 /*
805 * for clkout
806 */
807 if (!count) {
808 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
809 parent_clk_name, 0, req_rate[0]);
810 if (IS_ERR_OR_NULL(clk))
811 goto err;
812
813 adg->clkout[CLKOUT] = clk;
814 adg->clkout_size = 1;
815 of_clk_add_provider(np, of_clk_src_simple_get, clk);
816 }
817 /*
818 * for clkout0/1/2/3
819 */
820 else {
821 for (i = 0; i < clkout_size; i++) {
822 clk = clk_register_fixed_rate(dev, clkout_name[i],
823 parent_clk_name, 0,
824 req_rate[0]);
825 if (IS_ERR_OR_NULL(clk))
826 goto err;
827
828 adg->clkout[i] = clk;
829 }
830 adg->onecell.clks = adg->clkout;
831 adg->onecell.clk_num = clkout_size;
832 adg->clkout_size = clkout_size;
833 of_clk_add_provider(np, of_clk_src_onecell_get,
834 &adg->onecell);
835 }
836
837 rsnd_adg_get_clkout_end:
838 if (0 == (req_rate[0] % 8000))
839 ckr |= BRGCKR_31; /* use BRGB output = 48kHz */
840
841 adg->ckr = ckr;
842 adg->brga = brga;
843 adg->brgb = brgb;
844
845 return 0;
846
847 err:
848 dev_err(dev, "adg clock OUT get failed\n");
849
850 rsnd_adg_unregister_clkout(priv);
851
852 return -EIO;
853 }
854
855 #if defined(DEBUG) || defined(CONFIG_DEBUG_FS)
856 __printf(3, 4)
dbg_msg(struct device * dev,struct seq_file * m,const char * fmt,...)857 static void dbg_msg(struct device *dev, struct seq_file *m,
858 const char *fmt, ...)
859 {
860 char msg[128];
861 va_list args;
862
863 va_start(args, fmt);
864 vsnprintf(msg, sizeof(msg), fmt, args);
865 va_end(args);
866
867 if (m)
868 seq_puts(m, msg);
869 else
870 dev_dbg(dev, "%s", msg);
871 }
872
rsnd_adg_clk_dbg_info(struct rsnd_priv * priv,struct seq_file * m)873 void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m)
874 {
875 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
876 struct device *dev = rsnd_priv_to_dev(priv);
877 struct clk *clk;
878 int i;
879
880 for_each_rsnd_clkin(clk, adg, i)
881 dbg_msg(dev, m, "%-18s : %pa : %ld\n",
882 __clk_get_name(clk), clk, clk_get_rate(clk));
883
884 dbg_msg(dev, m, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
885 adg->ckr, adg->brga, adg->brgb);
886 dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->brg_rate[ADG_HZ_441]);
887 dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->brg_rate[ADG_HZ_48]);
888
889 /*
890 * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
891 * by BRGCKR::BRGCKR_31
892 */
893 for_each_rsnd_clkout(clk, adg, i)
894 dbg_msg(dev, m, "%-18s : %pa : %ld\n",
895 __clk_get_name(clk), clk, clk_get_rate(clk));
896 }
897 #else
898 #define rsnd_adg_clk_dbg_info(priv, m)
899 #endif
900
rsnd_adg_get_ssi_clks(struct rsnd_priv * priv)901 static int rsnd_adg_get_ssi_clks(struct rsnd_priv *priv)
902 {
903 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
904 struct device *dev = rsnd_priv_to_dev(priv);
905 char name[16];
906 int i;
907
908 /* SSIF supply clock */
909 adg->clk_ssif_supply = devm_clk_get_optional(dev, "ssif_supply");
910 if (IS_ERR(adg->clk_ssif_supply))
911 return dev_err_probe(dev, PTR_ERR(adg->clk_ssif_supply),
912 "failed to get ssif_supply clock\n");
913
914 /* Per-SSI ADG clocks (RZ/G3E-only; no legacy dotted form exists) */
915 for (i = 0; i < ADG_SSI_MAX; i++) {
916 snprintf(name, sizeof(name), "adg-ssi-%d", i);
917 adg->clk_adg_ssi[i] = devm_clk_get_optional(dev, name);
918 if (IS_ERR(adg->clk_adg_ssi[i]))
919 return dev_err_probe(dev, PTR_ERR(adg->clk_adg_ssi[i]),
920 "failed to get %s clock\n", name);
921 }
922
923 return 0;
924 }
925
rsnd_adg_probe(struct rsnd_priv * priv)926 int rsnd_adg_probe(struct rsnd_priv *priv)
927 {
928 struct reset_control *rstc;
929 struct rsnd_adg *adg;
930 struct device *dev = rsnd_priv_to_dev(priv);
931 int ret;
932
933 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
934 if (!adg)
935 return -ENOMEM;
936
937 rstc = devm_reset_control_get_optional_exclusive(dev, "adg");
938 if (IS_ERR(rstc))
939 return dev_err_probe(dev, PTR_ERR(rstc), "failed to get adg reset\n");
940
941 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops, NULL, rstc, 0, 0);
942 if (ret)
943 return ret;
944
945 priv->adg = adg;
946
947 ret = rsnd_adg_get_clkin(priv);
948 if (ret)
949 return ret;
950
951 ret = rsnd_adg_get_clkout(priv);
952 if (ret)
953 return ret;
954
955 /* RZ/G3E-specific: per-SSI ADG and SSIF supply clocks */
956 ret = rsnd_adg_get_ssi_clks(priv);
957 if (ret)
958 return ret;
959
960 ret = rsnd_adg_clk_enable(priv);
961 if (ret)
962 return ret;
963
964 rsnd_adg_clk_dbg_info(priv, NULL);
965
966 return 0;
967 }
968
rsnd_adg_remove(struct rsnd_priv * priv)969 void rsnd_adg_remove(struct rsnd_priv *priv)
970 {
971 struct device *dev = rsnd_priv_to_dev(priv);
972 struct device_node *np = dev->of_node;
973
974 rsnd_adg_unregister_clkout(priv);
975
976 of_clk_del_provider(np);
977
978 rsnd_adg_clk_disable(priv);
979
980 /* It should be called after rsnd_adg_clk_disable() */
981 rsnd_adg_null_clk_clean(priv);
982 }
983
rsnd_adg_mod_get(struct rsnd_priv * priv)984 static struct rsnd_mod *rsnd_adg_mod_get(struct rsnd_priv *priv)
985 {
986 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
987
988 if (!adg)
989 return NULL;
990
991 return rsnd_mod_get(adg);
992 }
993
rsnd_adg_suspend(struct rsnd_priv * priv)994 void rsnd_adg_suspend(struct rsnd_priv *priv)
995 {
996 struct rsnd_mod *mod = rsnd_adg_mod_get(priv);
997
998 if (mod)
999 rsnd_suspend_clk_reset(mod->clk, mod->rstc);
1000 }
1001
rsnd_adg_resume(struct rsnd_priv * priv)1002 void rsnd_adg_resume(struct rsnd_priv *priv)
1003 {
1004 struct rsnd_mod *mod = rsnd_adg_mod_get(priv);
1005
1006 if (mod)
1007 rsnd_resume_clk_reset(mod->clk, mod->rstc);
1008 }
1009