1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * HD-audio core stuff 4 */ 5 6 #ifndef __SOUND_HDAUDIO_H 7 #define __SOUND_HDAUDIO_H 8 9 #include <linux/device.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/io-64-nonatomic-lo-hi.h> 13 #include <linux/iopoll.h> 14 #include <linux/device-id/hda.h> 15 #include <linux/pci.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/timecounter.h> 18 #include <sound/core.h> 19 #include <sound/pcm.h> 20 #include <sound/memalloc.h> 21 #include <sound/hda_verbs.h> 22 #include <drm/intel/i915_component.h> 23 24 /* codec node id */ 25 typedef u16 hda_nid_t; 26 27 struct hdac_bus; 28 struct hdac_stream; 29 struct hdac_device; 30 struct hdac_driver; 31 struct hdac_widget_tree; 32 struct hda_device_id; 33 34 /* 35 * exported bus type 36 */ 37 extern const struct bus_type snd_hda_bus_type; 38 39 /* 40 * generic arrays 41 */ 42 struct snd_array { 43 unsigned int used; 44 unsigned int alloced; 45 unsigned int elem_size; 46 unsigned int alloc_align; 47 void *list; 48 }; 49 50 /* 51 * HD-audio codec base device 52 */ 53 struct hdac_device { 54 struct device dev; 55 int type; 56 struct hdac_bus *bus; 57 unsigned int addr; /* codec address */ 58 struct list_head list; /* list point for bus codec_list */ 59 60 hda_nid_t afg; /* AFG node id */ 61 hda_nid_t mfg; /* MFG node id */ 62 63 /* ids */ 64 unsigned int vendor_id; 65 unsigned int subsystem_id; 66 unsigned int revision_id; 67 unsigned int afg_function_id; 68 unsigned int mfg_function_id; 69 unsigned int afg_unsol:1; 70 unsigned int mfg_unsol:1; 71 72 unsigned int power_caps; /* FG power caps */ 73 74 const char *vendor_name; /* codec vendor name */ 75 const char *chip_name; /* codec chip name */ 76 77 /* verb exec op override */ 78 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, 79 unsigned int flags, unsigned int *res); 80 81 /* widgets */ 82 unsigned int num_nodes; 83 hda_nid_t start_nid, end_nid; 84 85 /* misc flags */ 86 atomic_t in_pm; /* suspend/resume being performed */ 87 88 /* sysfs */ 89 struct mutex widget_lock; 90 struct hdac_widget_tree *widgets; 91 92 /* regmap */ 93 struct regmap *regmap; 94 struct mutex regmap_lock; 95 struct snd_array vendor_verbs; 96 bool lazy_cache:1; /* don't wake up for writes */ 97 bool caps_overwriting:1; /* caps overwrite being in process */ 98 bool cache_coef:1; /* cache COEF read/write too */ 99 bool registered; /* codec was registered */ 100 bool unsol_disabled; /* unsol events blocked; protected by bus->reg_lock */ 101 }; 102 103 /* device/driver type used for matching */ 104 enum { 105 HDA_DEV_CORE, 106 HDA_DEV_LEGACY, 107 HDA_DEV_ASOC, 108 }; 109 110 enum { 111 SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */ 112 SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */ 113 SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */ 114 }; 115 116 /* direction */ 117 enum { 118 HDA_INPUT, HDA_OUTPUT 119 }; 120 121 #define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev) 122 123 int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus, 124 const char *name, unsigned int addr); 125 void snd_hdac_device_exit(struct hdac_device *dev); 126 int snd_hdac_device_register(struct hdac_device *codec); 127 void snd_hdac_device_disable_unsol(struct hdac_device *codec); 128 void snd_hdac_device_unregister(struct hdac_device *codec); 129 int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name); 130 int snd_hdac_codec_modalias(const struct hdac_device *hdac, char *buf, size_t size); 131 132 int snd_hdac_refresh_widgets(struct hdac_device *codec); 133 134 int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid, 135 unsigned int verb, unsigned int parm, unsigned int *res); 136 int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm, 137 unsigned int *res); 138 int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid, 139 int parm); 140 int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid, 141 unsigned int parm, unsigned int val); 142 int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid, 143 hda_nid_t *conn_list, int max_conns); 144 int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid, 145 hda_nid_t *start_id); 146 unsigned int snd_hdac_stream_format_bits(snd_pcm_format_t format, snd_pcm_subformat_t subformat, 147 unsigned int maxbits); 148 unsigned int snd_hdac_stream_format(unsigned int channels, unsigned int bits, unsigned int rate); 149 unsigned int snd_hdac_spdif_stream_format(unsigned int channels, unsigned int bits, 150 unsigned int rate, unsigned short spdif_ctls); 151 int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid, 152 u32 *ratesp, u64 *formatsp, u32 *subformatsp, 153 unsigned int *bpsp); 154 bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid, 155 unsigned int format); 156 157 int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid, 158 int flags, unsigned int verb, unsigned int parm); 159 int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid, 160 int flags, unsigned int verb, unsigned int parm); 161 bool snd_hdac_check_power_state(struct hdac_device *hdac, 162 hda_nid_t nid, unsigned int target_state); 163 unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac, 164 hda_nid_t nid, unsigned int target_state); 165 /** 166 * snd_hdac_read_parm - read a codec parameter 167 * @codec: the codec object 168 * @nid: NID to read a parameter 169 * @parm: parameter to read 170 * 171 * Returns -1 for error. If you need to distinguish the error more 172 * strictly, use _snd_hdac_read_parm() directly. 173 */ 174 static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, 175 int parm) 176 { 177 unsigned int val; 178 179 return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val; 180 } 181 182 #ifdef CONFIG_PM 183 int snd_hdac_power_up(struct hdac_device *codec); 184 void snd_hdac_power_down(struct hdac_device *codec); 185 int snd_hdac_power_up_pm(struct hdac_device *codec); 186 void snd_hdac_power_down_pm(struct hdac_device *codec); 187 int snd_hdac_keep_power_up(struct hdac_device *codec); 188 189 /* call this at entering into suspend/resume callbacks in codec driver */ 190 static inline void snd_hdac_enter_pm(struct hdac_device *codec) 191 { 192 atomic_inc(&codec->in_pm); 193 } 194 195 /* call this at leaving from suspend/resume callbacks in codec driver */ 196 static inline void snd_hdac_leave_pm(struct hdac_device *codec) 197 { 198 atomic_dec(&codec->in_pm); 199 } 200 201 static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) 202 { 203 return atomic_read(&codec->in_pm); 204 } 205 206 static inline bool snd_hdac_is_power_on(struct hdac_device *codec) 207 { 208 return !pm_runtime_suspended(&codec->dev); 209 } 210 #else 211 static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; } 212 static inline void snd_hdac_power_down(struct hdac_device *codec) {} 213 static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; } 214 static inline void snd_hdac_power_down_pm(struct hdac_device *codec) {} 215 static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; } 216 static inline void snd_hdac_enter_pm(struct hdac_device *codec) {} 217 static inline void snd_hdac_leave_pm(struct hdac_device *codec) {} 218 static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; } 219 static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; } 220 #endif 221 222 /* 223 * HD-audio codec base driver 224 */ 225 struct hdac_driver { 226 struct device_driver driver; 227 int type; 228 const struct hda_device_id *id_table; 229 int (*match)(struct hdac_device *dev, const struct hdac_driver *drv); 230 void (*unsol_event)(struct hdac_device *dev, unsigned int event); 231 232 /* fields used by ext bus APIs */ 233 int (*probe)(struct hdac_device *dev); 234 int (*remove)(struct hdac_device *dev); 235 void (*shutdown)(struct hdac_device *dev); 236 }; 237 238 #define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver) 239 240 const struct hda_device_id * 241 hdac_get_device_id(struct hdac_device *hdev, const struct hdac_driver *drv); 242 243 /* 244 * Bus verb operators 245 */ 246 struct hdac_bus_ops { 247 /* send a single command */ 248 int (*command)(struct hdac_bus *bus, unsigned int cmd); 249 /* get a response from the last command */ 250 int (*get_response)(struct hdac_bus *bus, unsigned int addr, 251 unsigned int *res); 252 /* notify of codec link power-up/down */ 253 void (*link_power)(struct hdac_device *hdev, bool enable); 254 }; 255 256 /* 257 * ops used for ASoC HDA codec drivers 258 */ 259 struct hdac_ext_bus_ops { 260 int (*hdev_attach)(struct hdac_device *hdev); 261 int (*hdev_detach)(struct hdac_device *hdev); 262 }; 263 264 #define HDA_UNSOL_QUEUE_SIZE 64 265 #define HDA_MAX_CODECS 8 /* limit by controller side */ 266 267 /* 268 * CORB/RIRB 269 * 270 * Each CORB entry is 4byte, RIRB is 8byte 271 */ 272 struct hdac_rb { 273 __le32 *buf; /* virtual address of CORB/RIRB buffer */ 274 dma_addr_t addr; /* physical address of CORB/RIRB buffer */ 275 unsigned short rp, wp; /* RIRB read/write pointers */ 276 int cmds[HDA_MAX_CODECS]; /* number of pending requests */ 277 u32 res[HDA_MAX_CODECS]; /* last read value */ 278 }; 279 280 /* 281 * HD-audio bus base driver 282 * 283 * @ppcap: pp capabilities pointer 284 * @spbcap: SPIB capabilities pointer 285 * @mlcap: MultiLink capabilities pointer 286 * @gtscap: gts capabilities pointer 287 * @drsmcap: dma resume capabilities pointer 288 * @num_streams: streams supported 289 * @idx: HDA link index 290 * @hlink_list: link list of HDA links 291 * @lock: lock for link and display power mgmt 292 * @cmd_dma_state: state of cmd DMAs: CORB and RIRB 293 */ 294 struct hdac_bus { 295 struct device *dev; 296 const struct hdac_bus_ops *ops; 297 const struct hdac_ext_bus_ops *ext_ops; 298 299 /* h/w resources */ 300 unsigned long addr; 301 void __iomem *remap_addr; 302 int irq; 303 304 void __iomem *ppcap; 305 void __iomem *spbcap; 306 void __iomem *mlcap; 307 void __iomem *gtscap; 308 void __iomem *drsmcap; 309 310 /* codec linked list */ 311 struct list_head codec_list; 312 unsigned int num_codecs; 313 314 /* link caddr -> codec */ 315 struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1]; 316 317 /* unsolicited event queue */ 318 u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */ 319 unsigned int unsol_rp, unsol_wp; 320 struct work_struct unsol_work; 321 322 /* bit flags of detected codecs */ 323 unsigned long codec_mask; 324 325 /* bit flags of powered codecs */ 326 unsigned long codec_powered; 327 328 /* CORB/RIRB */ 329 struct hdac_rb corb; 330 struct hdac_rb rirb; 331 unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */ 332 wait_queue_head_t rirb_wq; 333 334 /* CORB/RIRB and position buffers */ 335 struct snd_dma_buffer rb; 336 struct snd_dma_buffer posbuf; 337 int dma_type; /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */ 338 339 /* hdac_stream linked list */ 340 struct list_head stream_list; 341 342 /* operation state */ 343 bool chip_init:1; /* h/w initialized */ 344 345 /* behavior flags */ 346 bool aligned_mmio:1; /* aligned MMIO access */ 347 bool sync_write:1; /* sync after verb write */ 348 bool use_posbuf:1; /* use position buffer */ 349 bool snoop:1; /* enable snooping */ 350 bool align_bdle_4k:1; /* BDLE align 4K boundary */ 351 bool reverse_assign:1; /* assign devices in reverse order */ 352 bool corbrp_self_clear:1; /* CORBRP clears itself after reset */ 353 bool polling_mode:1; 354 bool needs_damn_long_delay:1; 355 bool not_use_interrupts:1; /* prohibiting the RIRB IRQ */ 356 bool access_sdnctl_in_dword:1; /* accessing the sdnctl register by dword */ 357 bool use_pio_for_commands:1; /* Use PIO instead of CORB for commands */ 358 359 int poll_count; 360 361 int bdl_pos_adj; /* BDL position adjustment */ 362 363 /* delay time in us for dma stop */ 364 unsigned int dma_stop_delay; 365 366 /* locks */ 367 spinlock_t reg_lock; 368 struct mutex cmd_mutex; 369 struct mutex lock; 370 371 /* DRM component interface */ 372 struct drm_audio_component *audio_component; 373 long display_power_status; 374 unsigned long display_power_active; 375 376 /* parameters required for enhanced capabilities */ 377 int num_streams; 378 int idx; 379 380 /* link management */ 381 struct list_head hlink_list; 382 bool cmd_dma_state; 383 384 /* factor used to derive STRIPE control value */ 385 unsigned int sdo_limit; 386 387 /* address offset between host and hadc */ 388 dma_addr_t addr_offset; 389 }; 390 391 int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev, 392 const struct hdac_bus_ops *ops); 393 void snd_hdac_bus_exit(struct hdac_bus *bus); 394 int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr, 395 unsigned int cmd, unsigned int *res); 396 397 void snd_hdac_codec_link_up(struct hdac_device *codec); 398 void snd_hdac_codec_link_down(struct hdac_device *codec); 399 400 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val); 401 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, 402 unsigned int *res); 403 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus); 404 405 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset); 406 void snd_hdac_bus_stop_chip(struct hdac_bus *bus); 407 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus); 408 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus); 409 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus); 410 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus); 411 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset); 412 void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable); 413 414 void snd_hdac_bus_update_rirb(struct hdac_bus *bus); 415 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, 416 void (*ack)(struct hdac_bus *, 417 struct hdac_stream *)); 418 419 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus); 420 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus); 421 422 #ifdef CONFIG_SND_HDA_ALIGNED_MMIO 423 unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask); 424 void snd_hdac_aligned_write(unsigned int val, void __iomem *addr, 425 unsigned int mask); 426 #define snd_hdac_aligned_mmio(bus) (bus)->aligned_mmio 427 #else 428 #define snd_hdac_aligned_mmio(bus) false 429 #define snd_hdac_aligned_read(addr, mask) 0 430 #define snd_hdac_aligned_write(val, addr, mask) do {} while (0) 431 #endif 432 433 static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr, 434 u8 val) 435 { 436 if (snd_hdac_aligned_mmio(bus)) 437 snd_hdac_aligned_write(val, addr, 0xff); 438 else 439 writeb(val, addr); 440 } 441 442 static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr, 443 u16 val) 444 { 445 if (snd_hdac_aligned_mmio(bus)) 446 snd_hdac_aligned_write(val, addr, 0xffff); 447 else 448 writew(val, addr); 449 } 450 451 static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr) 452 { 453 return snd_hdac_aligned_mmio(bus) ? 454 snd_hdac_aligned_read(addr, 0xff) : readb(addr); 455 } 456 457 static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr) 458 { 459 return snd_hdac_aligned_mmio(bus) ? 460 snd_hdac_aligned_read(addr, 0xffff) : readw(addr); 461 } 462 463 #define snd_hdac_reg_writel(bus, addr, val) writel(val, addr) 464 #define snd_hdac_reg_readl(bus, addr) readl(addr) 465 #define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr) 466 #define snd_hdac_reg_readq(bus, addr) readq(addr) 467 468 /* 469 * macros for easy use 470 */ 471 #define _snd_hdac_chip_writeb(chip, reg, value) \ 472 snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value) 473 #define _snd_hdac_chip_readb(chip, reg) \ 474 snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg)) 475 #define _snd_hdac_chip_writew(chip, reg, value) \ 476 snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value) 477 #define _snd_hdac_chip_readw(chip, reg) \ 478 snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg)) 479 #define _snd_hdac_chip_writel(chip, reg, value) \ 480 snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value) 481 #define _snd_hdac_chip_readl(chip, reg) \ 482 snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg)) 483 484 /* read/write a register, pass without AZX_REG_ prefix */ 485 #define snd_hdac_chip_writel(chip, reg, value) \ 486 _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value) 487 #define snd_hdac_chip_writew(chip, reg, value) \ 488 _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value) 489 #define snd_hdac_chip_writeb(chip, reg, value) \ 490 _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value) 491 #define snd_hdac_chip_readl(chip, reg) \ 492 _snd_hdac_chip_readl(chip, AZX_REG_ ## reg) 493 #define snd_hdac_chip_readw(chip, reg) \ 494 _snd_hdac_chip_readw(chip, AZX_REG_ ## reg) 495 #define snd_hdac_chip_readb(chip, reg) \ 496 _snd_hdac_chip_readb(chip, AZX_REG_ ## reg) 497 498 /* update a register, pass without AZX_REG_ prefix */ 499 #define snd_hdac_chip_updatel(chip, reg, mask, val) \ 500 snd_hdac_chip_writel(chip, reg, \ 501 (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) 502 #define snd_hdac_chip_updatew(chip, reg, mask, val) \ 503 snd_hdac_chip_writew(chip, reg, \ 504 (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) 505 #define snd_hdac_chip_updateb(chip, reg, mask, val) \ 506 snd_hdac_chip_writeb(chip, reg, \ 507 (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) 508 509 /* update register macro */ 510 #define snd_hdac_updatel(addr, reg, mask, val) \ 511 writel(((readl(addr + reg) & ~(mask)) | (val)), addr + reg) 512 513 #define snd_hdac_updatew(addr, reg, mask, val) \ 514 writew(((readw(addr + reg) & ~(mask)) | (val)), addr + reg) 515 516 /* 517 * HD-audio stream 518 */ 519 struct hdac_stream { 520 struct hdac_bus *bus; 521 struct snd_dma_buffer bdl; /* BDL buffer */ 522 __le32 *posbuf; /* position buffer pointer */ 523 int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */ 524 525 unsigned int bufsize; /* size of the play buffer in bytes */ 526 unsigned int period_bytes; /* size of the period in bytes */ 527 unsigned int frags; /* number for period in the play buffer */ 528 unsigned int fifo_size; /* FIFO size */ 529 530 void __iomem *sd_addr; /* stream descriptor pointer */ 531 532 void __iomem *spib_addr; /* software position in buffers stream pointer */ 533 void __iomem *fifo_addr; /* software position Max fifos stream pointer */ 534 535 void __iomem *dpibr_addr; /* DMA position in buffer resume pointer */ 536 u32 dpib; /* DMA position in buffer */ 537 u32 lpib; /* Linear position in buffer */ 538 539 u32 sd_int_sta_mask; /* stream int status mask */ 540 541 /* pcm support */ 542 struct snd_pcm_substream *substream; /* assigned substream, 543 * set in PCM open 544 */ 545 struct snd_compr_stream *cstream; 546 unsigned int format_val; /* format value to be set in the 547 * controller and the codec 548 */ 549 unsigned char stream_tag; /* assigned stream */ 550 unsigned char index; /* stream index */ 551 int assigned_key; /* last device# key assigned to */ 552 553 bool opened:1; 554 bool running:1; 555 bool prepared:1; 556 bool no_period_wakeup:1; 557 bool locked:1; 558 bool stripe:1; /* apply stripe control */ 559 560 u64 curr_pos; 561 /* timestamp */ 562 unsigned long start_wallclk; /* start + minimum wallclk */ 563 unsigned long period_wallclk; /* wallclk for period */ 564 struct timecounter tc; 565 struct cyclecounter cc; 566 int delay_negative_threshold; 567 568 struct list_head list; 569 #ifdef CONFIG_SND_HDA_DSP_LOADER 570 /* DSP access mutex */ 571 struct mutex dsp_mutex; 572 #endif 573 }; 574 575 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, 576 int idx, int direction, int tag); 577 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, 578 struct snd_pcm_substream *substream); 579 void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev); 580 void snd_hdac_stream_release(struct hdac_stream *azx_dev); 581 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, 582 int dir, int stream_tag); 583 584 int snd_hdac_stream_setup(struct hdac_stream *azx_dev, bool code_loading); 585 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev); 586 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev); 587 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, 588 unsigned int format_val); 589 void snd_hdac_stream_start(struct hdac_stream *azx_dev); 590 void snd_hdac_stream_stop(struct hdac_stream *azx_dev); 591 void snd_hdac_stop_streams(struct hdac_bus *bus); 592 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus); 593 void snd_hdac_stream_reset(struct hdac_stream *azx_dev); 594 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, 595 unsigned int streams, unsigned int reg); 596 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, 597 unsigned int streams); 598 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, 599 unsigned int streams, bool start); 600 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, 601 struct snd_pcm_substream *substream); 602 603 void snd_hdac_stream_spbcap_enable(struct hdac_bus *chip, 604 bool enable, int index); 605 int snd_hdac_stream_set_spib(struct hdac_bus *bus, 606 struct hdac_stream *azx_dev, u32 value); 607 void snd_hdac_stream_drsm_enable(struct hdac_bus *bus, 608 bool enable, int index); 609 int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev); 610 int snd_hdac_stream_set_dpibr(struct hdac_bus *bus, 611 struct hdac_stream *azx_dev, u32 value); 612 int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value); 613 614 /* 615 * macros for easy use 616 */ 617 /* read/write a register, pass without AZX_REG_ prefix */ 618 #define snd_hdac_stream_writel(dev, reg, value) \ 619 snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) 620 #define snd_hdac_stream_writew(dev, reg, value) \ 621 snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) 622 #define snd_hdac_stream_writeb(dev, reg, value) \ 623 snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) 624 #define snd_hdac_stream_readl(dev, reg) \ 625 snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) 626 #define snd_hdac_stream_readw(dev, reg) \ 627 snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) 628 #define snd_hdac_stream_readb(dev, reg) \ 629 snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) 630 #define snd_hdac_stream_readb_poll(dev, reg, val, cond, delay_us, timeout_us) \ 631 read_poll_timeout_atomic(snd_hdac_reg_readb, val, cond, delay_us, timeout_us, \ 632 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) 633 #define snd_hdac_stream_readw_poll(dev, reg, val, cond, delay_us, timeout_us) \ 634 read_poll_timeout_atomic(snd_hdac_reg_readw, val, cond, delay_us, timeout_us, \ 635 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) 636 #define snd_hdac_stream_readl_poll(dev, reg, val, cond, delay_us, timeout_us) \ 637 read_poll_timeout_atomic(snd_hdac_reg_readl, val, cond, delay_us, timeout_us, \ 638 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) 639 640 /* update a register, pass without AZX_REG_ prefix */ 641 #define snd_hdac_stream_updatel(dev, reg, mask, val) \ 642 snd_hdac_stream_writel(dev, reg, \ 643 (snd_hdac_stream_readl(dev, reg) & \ 644 ~(mask)) | (val)) 645 #define snd_hdac_stream_updatew(dev, reg, mask, val) \ 646 snd_hdac_stream_writew(dev, reg, \ 647 (snd_hdac_stream_readw(dev, reg) & \ 648 ~(mask)) | (val)) 649 #define snd_hdac_stream_updateb(dev, reg, mask, val) \ 650 snd_hdac_stream_writeb(dev, reg, \ 651 (snd_hdac_stream_readb(dev, reg) & \ 652 ~(mask)) | (val)) 653 654 #ifdef CONFIG_SND_HDA_DSP_LOADER 655 /* DSP lock helpers */ 656 #define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) 657 #define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) 658 #define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) 659 #define snd_hdac_stream_is_locked(dev) ((dev)->locked) 660 DEFINE_GUARD(snd_hdac_dsp_lock, struct hdac_stream *, snd_hdac_dsp_lock(_T), snd_hdac_dsp_unlock(_T)) 661 /* DSP loader helpers */ 662 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, 663 unsigned int byte_size, struct snd_dma_buffer *bufp); 664 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start); 665 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, 666 struct snd_dma_buffer *dmab); 667 #else /* CONFIG_SND_HDA_DSP_LOADER */ 668 #define snd_hdac_dsp_lock_init(dev) do {} while (0) 669 #define snd_hdac_dsp_lock(dev) do {} while (0) 670 #define snd_hdac_dsp_unlock(dev) do {} while (0) 671 #define snd_hdac_stream_is_locked(dev) 0 672 673 static inline int 674 snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, 675 unsigned int byte_size, struct snd_dma_buffer *bufp) 676 { 677 return 0; 678 } 679 680 static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) 681 { 682 } 683 684 static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, 685 struct snd_dma_buffer *dmab) 686 { 687 } 688 #endif /* CONFIG_SND_HDA_DSP_LOADER */ 689 690 /* 691 * Easy macros for widget capabilities 692 */ 693 #define snd_hdac_get_wcaps(codec, nid) \ 694 snd_hdac_read_parm(codec, nid, AC_PAR_AUDIO_WIDGET_CAP) 695 696 /* get the widget type from widget capability bits */ 697 static inline int snd_hdac_get_wcaps_type(unsigned int wcaps) 698 { 699 if (!wcaps) 700 return -1; /* invalid type */ 701 return (wcaps & AC_WCAP_TYPE) >> AC_WCAP_TYPE_SHIFT; 702 } 703 704 /* get the number of supported channels */ 705 static inline unsigned int snd_hdac_get_wcaps_channels(u32 wcaps) 706 { 707 unsigned int chans; 708 709 chans = (wcaps & AC_WCAP_CHAN_CNT_EXT) >> 13; 710 chans = (chans + 1) * 2; 711 712 return chans; 713 } 714 715 /* 716 * generic array helpers 717 */ 718 void *snd_array_new(struct snd_array *array); 719 void snd_array_free(struct snd_array *array); 720 static inline void snd_array_init(struct snd_array *array, unsigned int size, 721 unsigned int align) 722 { 723 array->elem_size = size; 724 array->alloc_align = align; 725 } 726 727 static inline void *snd_array_elem(struct snd_array *array, unsigned int idx) 728 { 729 return array->list + idx * array->elem_size; 730 } 731 732 static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) 733 { 734 return (unsigned long)(ptr - array->list) / array->elem_size; 735 } 736 737 /* a helper macro to iterate for each snd_array element */ 738 #define snd_array_for_each(array, idx, ptr) \ 739 for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \ 740 (ptr) = snd_array_elem(array, ++(idx))) 741 742 /* 743 * Device matching 744 */ 745 746 #define HDA_CONTROLLER_IS_HSW(pci) (pci_match_id((struct pci_device_id []){ \ 747 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_0) }, \ 748 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_2) }, \ 749 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_3) }, \ 750 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BDW) }, \ 751 { } \ 752 }, pci)) 753 754 #define HDA_CONTROLLER_IS_APL(pci) (pci_match_id((struct pci_device_id []){ \ 755 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_APL) }, \ 756 { } \ 757 }, pci)) 758 759 #define HDA_CONTROLLER_IN_GPU(pci) (pci_match_id((struct pci_device_id []){ \ 760 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG1) }, \ 761 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_0) }, \ 762 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_1) }, \ 763 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_2) }, \ 764 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BMG) }, \ 765 { } \ 766 }, pci) || HDA_CONTROLLER_IS_HSW(pci)) 767 768 #endif /* __SOUND_HDAUDIO_H */ 769