1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/kernel.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/nvmem-consumer.h> 14 #include <linux/of.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 22 #include <dt-bindings/phy/phy-qcom-qusb2.h> 23 24 #define QUSB2PHY_PLL 0x0 25 #define QUSB2PHY_PLL_TEST 0x04 26 #define CLK_REF_SEL BIT(7) 27 28 #define QUSB2PHY_PLL_TUNE 0x08 29 #define QUSB2PHY_PLL_USER_CTL1 0x0c 30 #define QUSB2PHY_PLL_USER_CTL2 0x10 31 #define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c 32 #define QUSB2PHY_PLL_PWR_CTRL 0x18 33 34 /* QUSB2PHY_PLL_STATUS register bits */ 35 #define PLL_LOCKED BIT(5) 36 37 /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ 38 #define CORE_READY_STATUS BIT(0) 39 40 /* QUSB2PHY_PORT_POWERDOWN register bits */ 41 #define CLAMP_N_EN BIT(5) 42 #define FREEZIO_N BIT(1) 43 #define POWER_DOWN BIT(0) 44 45 /* QUSB2PHY_PWR_CTRL1 register bits */ 46 #define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) 47 #define PWR_CTRL1_CLAMP_N_EN BIT(1) 48 49 #define QUSB2PHY_REFCLK_ENABLE BIT(0) 50 51 #define PHY_CLK_SCHEME_SEL BIT(0) 52 53 /* QUSB2PHY_INTR_CTRL register bits */ 54 #define DMSE_INTR_HIGH_SEL BIT(4) 55 #define DPSE_INTR_HIGH_SEL BIT(3) 56 #define CHG_DET_INTR_EN BIT(2) 57 #define DMSE_INTR_EN BIT(1) 58 #define DPSE_INTR_EN BIT(0) 59 60 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ 61 #define CORE_PLL_EN_FROM_RESET BIT(4) 62 #define CORE_RESET BIT(5) 63 #define CORE_RESET_MUX BIT(6) 64 65 /* QUSB2PHY_IMP_CTRL1 register bits */ 66 #define IMP_RES_OFFSET_MASK GENMASK(5, 0) 67 #define IMP_RES_OFFSET_SHIFT 0x0 68 69 /* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ 70 #define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0) 71 #define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0 72 73 /* QUSB2PHY_CHG_CONTROL_2 register bits */ 74 #define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4) 75 #define CHG_CTRL2_OFFSET_SHIFT 0x4 76 77 /* QUSB2PHY_PORT_TUNE1 register bits */ 78 #define HSTX_TRIM_MASK GENMASK(7, 4) 79 #define HSTX_TRIM_SHIFT 0x4 80 #define PREEMPH_WIDTH_HALF_BIT BIT(2) 81 #define PREEMPHASIS_EN_MASK GENMASK(1, 0) 82 #define PREEMPHASIS_EN_SHIFT 0x0 83 84 /* QUSB2PHY_PORT_TUNE2 register bits */ 85 #define HSDISC_TRIM_MASK GENMASK(1, 0) 86 #define HSDISC_TRIM_SHIFT 0x0 87 88 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 89 #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c 90 #define QUSB2PHY_PLL_CMODE 0x2c 91 #define QUSB2PHY_PLL_LOCK_DELAY 0x184 92 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4 93 #define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194 94 #define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198 95 #define QUSB2PHY_PWR_CTRL2 0x214 96 #define QUSB2PHY_IMP_CTRL1 0x220 97 #define QUSB2PHY_IMP_CTRL2 0x224 98 #define QUSB2PHY_CHG_CTRL2 0x23c 99 100 struct qusb2_phy_init_tbl { 101 unsigned int offset; 102 unsigned int val; 103 /* 104 * register part of layout ? 105 * if yes, then offset gives index in the reg-layout 106 */ 107 int in_layout; 108 }; 109 110 #define QUSB2_PHY_INIT_CFG(o, v) \ 111 { \ 112 .offset = o, \ 113 .val = v, \ 114 } 115 116 #define QUSB2_PHY_INIT_CFG_L(o, v) \ 117 { \ 118 .offset = o, \ 119 .val = v, \ 120 .in_layout = 1, \ 121 } 122 123 /* set of registers with offsets different per-PHY */ 124 enum qusb2phy_reg_layout { 125 QUSB2PHY_PLL_CORE_INPUT_OVERRIDE, 126 QUSB2PHY_PLL_STATUS, 127 QUSB2PHY_PORT_TUNE1, 128 QUSB2PHY_PORT_TUNE2, 129 QUSB2PHY_PORT_TUNE3, 130 QUSB2PHY_PORT_TUNE4, 131 QUSB2PHY_PORT_TUNE5, 132 QUSB2PHY_PORT_TEST1, 133 QUSB2PHY_PORT_TEST2, 134 QUSB2PHY_PORT_POWERDOWN, 135 QUSB2PHY_INTR_CTRL, 136 }; 137 138 static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = { 139 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14), 140 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8), 141 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3), 142 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), 143 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0), 144 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 145 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 146 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 147 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00), 148 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 149 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 150 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80), 151 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F), 152 }; 153 154 static const struct qusb2_phy_init_tbl ipq5424_init_tbl[] = { 155 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14), 156 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x00), 157 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53), 158 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc3), 159 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 160 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 161 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 162 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00), 163 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 164 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 165 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80), 166 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), 167 }; 168 169 static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = { 170 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xc8), 171 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3), 172 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), 173 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0), 174 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 175 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 176 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 177 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 178 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), 179 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 180 }; 181 182 static const unsigned int ipq6018_regs_layout[] = { 183 [QUSB2PHY_PLL_STATUS] = 0x38, 184 [QUSB2PHY_PORT_TUNE1] = 0x80, 185 [QUSB2PHY_PORT_TUNE2] = 0x84, 186 [QUSB2PHY_PORT_TUNE3] = 0x88, 187 [QUSB2PHY_PORT_TUNE4] = 0x8C, 188 [QUSB2PHY_PORT_TUNE5] = 0x90, 189 [QUSB2PHY_PORT_TEST1] = 0x98, 190 [QUSB2PHY_PORT_TEST2] = 0x9C, 191 [QUSB2PHY_PORT_POWERDOWN] = 0xB4, 192 [QUSB2PHY_INTR_CTRL] = 0xBC, 193 }; 194 195 static const unsigned int msm8996_regs_layout[] = { 196 [QUSB2PHY_PLL_STATUS] = 0x38, 197 [QUSB2PHY_PORT_TUNE1] = 0x80, 198 [QUSB2PHY_PORT_TUNE2] = 0x84, 199 [QUSB2PHY_PORT_TUNE3] = 0x88, 200 [QUSB2PHY_PORT_TUNE4] = 0x8c, 201 [QUSB2PHY_PORT_TUNE5] = 0x90, 202 [QUSB2PHY_PORT_TEST1] = 0xb8, 203 [QUSB2PHY_PORT_TEST2] = 0x9c, 204 [QUSB2PHY_PORT_POWERDOWN] = 0xb4, 205 [QUSB2PHY_INTR_CTRL] = 0xbc, 206 }; 207 208 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = { 209 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), 210 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3), 211 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), 212 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0), 213 214 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 215 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 216 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 217 218 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 219 220 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), 221 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 222 }; 223 224 static const unsigned int msm8998_regs_layout[] = { 225 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, 226 [QUSB2PHY_PLL_STATUS] = 0x1a0, 227 [QUSB2PHY_PORT_TUNE1] = 0x23c, 228 [QUSB2PHY_PORT_TUNE2] = 0x240, 229 [QUSB2PHY_PORT_TUNE3] = 0x244, 230 [QUSB2PHY_PORT_TUNE4] = 0x248, 231 [QUSB2PHY_PORT_TEST1] = 0x24c, 232 [QUSB2PHY_PORT_TEST2] = 0x250, 233 [QUSB2PHY_PORT_POWERDOWN] = 0x210, 234 [QUSB2PHY_INTR_CTRL] = 0x22c, 235 }; 236 237 static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = { 238 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13), 239 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), 240 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), 241 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), 242 243 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5), 244 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09), 245 246 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), 247 }; 248 249 static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = { 250 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), 251 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53), 252 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81), 253 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17), 254 255 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 256 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 257 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 258 259 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 260 261 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), 262 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 263 }; 264 265 static const unsigned int qusb2_v2_regs_layout[] = { 266 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, 267 [QUSB2PHY_PLL_STATUS] = 0x1a0, 268 [QUSB2PHY_PORT_TUNE1] = 0x240, 269 [QUSB2PHY_PORT_TUNE2] = 0x244, 270 [QUSB2PHY_PORT_TUNE3] = 0x248, 271 [QUSB2PHY_PORT_TUNE4] = 0x24c, 272 [QUSB2PHY_PORT_TUNE5] = 0x250, 273 [QUSB2PHY_PORT_TEST1] = 0x254, 274 [QUSB2PHY_PORT_TEST2] = 0x258, 275 [QUSB2PHY_PORT_POWERDOWN] = 0x210, 276 [QUSB2PHY_INTR_CTRL] = 0x230, 277 }; 278 279 static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { 280 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), 281 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), 282 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), 283 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), 284 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), 285 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40), 286 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20), 287 QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21), 288 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0), 289 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58), 290 291 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30), 292 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29), 293 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca), 294 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04), 295 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03), 296 297 QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), 298 }; 299 300 struct qusb2_phy_cfg { 301 const struct qusb2_phy_init_tbl *tbl; 302 /* number of entries in the table */ 303 unsigned int tbl_num; 304 /* offset to PHY_CLK_SCHEME register in TCSR map */ 305 unsigned int clk_scheme_offset; 306 307 /* array of registers with different offsets */ 308 const unsigned int *regs; 309 unsigned int mask_core_ready; 310 unsigned int disable_ctrl; 311 unsigned int autoresume_en; 312 313 /* true if PHY has PLL_TEST register to select clk_scheme */ 314 bool has_pll_test; 315 316 /* true if TUNE1 register must be updated by fused value, else TUNE2 */ 317 bool update_tune1_with_efuse; 318 319 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */ 320 bool has_pll_override; 321 322 /* true if PHY default clk scheme is single-ended */ 323 bool se_clk_scheme_default; 324 }; 325 326 static const struct qusb2_phy_cfg msm8996_phy_cfg = { 327 .tbl = msm8996_init_tbl, 328 .tbl_num = ARRAY_SIZE(msm8996_init_tbl), 329 .regs = msm8996_regs_layout, 330 331 .has_pll_test = true, 332 .se_clk_scheme_default = true, 333 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 334 .mask_core_ready = PLL_LOCKED, 335 .autoresume_en = BIT(3), 336 }; 337 338 static const struct qusb2_phy_cfg msm8998_phy_cfg = { 339 .tbl = msm8998_init_tbl, 340 .tbl_num = ARRAY_SIZE(msm8998_init_tbl), 341 .regs = msm8998_regs_layout, 342 343 .disable_ctrl = POWER_DOWN, 344 .mask_core_ready = CORE_READY_STATUS, 345 .has_pll_override = true, 346 .se_clk_scheme_default = true, 347 .autoresume_en = BIT(0), 348 .update_tune1_with_efuse = true, 349 }; 350 351 static const struct qusb2_phy_cfg ipq6018_phy_cfg = { 352 .tbl = ipq6018_init_tbl, 353 .tbl_num = ARRAY_SIZE(ipq6018_init_tbl), 354 .regs = ipq6018_regs_layout, 355 356 .disable_ctrl = POWER_DOWN, 357 .mask_core_ready = PLL_LOCKED, 358 /* autoresume not used */ 359 .autoresume_en = BIT(0), 360 }; 361 362 static const struct qusb2_phy_cfg ipq5424_phy_cfg = { 363 .tbl = ipq5424_init_tbl, 364 .tbl_num = ARRAY_SIZE(ipq5424_init_tbl), 365 .regs = ipq6018_regs_layout, 366 367 .disable_ctrl = POWER_DOWN, 368 .mask_core_ready = PLL_LOCKED, 369 .autoresume_en = BIT(0), 370 }; 371 372 static const struct qusb2_phy_cfg qcs615_phy_cfg = { 373 .tbl = qcs615_init_tbl, 374 .tbl_num = ARRAY_SIZE(qcs615_init_tbl), 375 .regs = ipq6018_regs_layout, 376 377 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 378 .mask_core_ready = PLL_LOCKED, 379 /* autoresume not used */ 380 .autoresume_en = BIT(0), 381 }; 382 383 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { 384 .tbl = qusb2_v2_init_tbl, 385 .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), 386 .regs = qusb2_v2_regs_layout, 387 388 .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN | 389 POWER_DOWN), 390 .mask_core_ready = CORE_READY_STATUS, 391 .has_pll_override = true, 392 .se_clk_scheme_default = true, 393 .autoresume_en = BIT(0), 394 .update_tune1_with_efuse = true, 395 }; 396 397 static const struct qusb2_phy_cfg sdm660_phy_cfg = { 398 .tbl = msm8996_init_tbl, 399 .tbl_num = ARRAY_SIZE(msm8996_init_tbl), 400 .regs = msm8996_regs_layout, 401 402 .has_pll_test = true, 403 .se_clk_scheme_default = false, 404 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 405 .mask_core_ready = PLL_LOCKED, 406 .autoresume_en = BIT(3), 407 }; 408 409 static const struct qusb2_phy_cfg sm6115_phy_cfg = { 410 .tbl = sm6115_init_tbl, 411 .tbl_num = ARRAY_SIZE(sm6115_init_tbl), 412 .regs = msm8996_regs_layout, 413 414 .has_pll_test = true, 415 .se_clk_scheme_default = true, 416 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 417 .mask_core_ready = PLL_LOCKED, 418 .autoresume_en = BIT(3), 419 }; 420 421 static const char * const qusb2_phy_vreg_names[] = { 422 "vdd", "vdda-pll", "vdda-phy-dpdm", 423 }; 424 425 #define QUSB2_NUM_VREGS ARRAY_SIZE(qusb2_phy_vreg_names) 426 427 /* struct override_param - structure holding qusb2 v2 phy overriding param 428 * set override true if the device tree property exists and read and assign 429 * to value 430 */ 431 struct override_param { 432 bool override; 433 u8 value; 434 }; 435 436 /*struct override_params - structure holding qusb2 v2 phy overriding params 437 * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register 438 * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register 439 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register 440 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1 441 * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register 442 * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register 443 * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register 444 */ 445 struct override_params { 446 struct override_param imp_res_offset; 447 struct override_param hstx_trim; 448 struct override_param preemphasis; 449 struct override_param preemphasis_width; 450 struct override_param bias_ctrl; 451 struct override_param charge_ctrl; 452 struct override_param hsdisc_trim; 453 }; 454 455 /** 456 * struct qusb2_phy - structure holding qusb2 phy attributes 457 * 458 * @phy: generic phy 459 * @base: iomapped memory space for qubs2 phy 460 * 461 * @cfg_ahb_clk: AHB2PHY interface clock 462 * @ref_clk: phy reference clock 463 * @iface_clk: phy interface clock 464 * @phy_reset: phy reset control 465 * @vregs: regulator supplies bulk data 466 * 467 * @tcsr: TCSR syscon register map 468 * @cell: nvmem cell containing phy tuning value 469 * 470 * @overrides: pointer to structure for all overriding tuning params 471 * 472 * @cfg: phy config data 473 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme 474 * @phy_initialized: indicate if PHY has been initialized 475 * @mode: current PHY mode 476 */ 477 struct qusb2_phy { 478 struct phy *phy; 479 void __iomem *base; 480 481 struct clk *cfg_ahb_clk; 482 struct clk *ref_clk; 483 struct clk *iface_clk; 484 struct reset_control *phy_reset; 485 struct regulator_bulk_data vregs[QUSB2_NUM_VREGS]; 486 487 struct regmap *tcsr; 488 struct nvmem_cell *cell; 489 490 struct override_params overrides; 491 492 const struct qusb2_phy_cfg *cfg; 493 bool has_se_clk_scheme; 494 bool phy_initialized; 495 enum phy_mode mode; 496 }; 497 498 static inline void qusb2_write_mask(void __iomem *base, u32 offset, 499 u32 val, u32 mask) 500 { 501 u32 reg; 502 503 reg = readl(base + offset); 504 reg &= ~mask; 505 reg |= val & mask; 506 writel(reg, base + offset); 507 508 /* Ensure above write is completed */ 509 readl(base + offset); 510 } 511 512 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) 513 { 514 u32 reg; 515 516 reg = readl(base + offset); 517 reg |= val; 518 writel(reg, base + offset); 519 520 /* Ensure above write is completed */ 521 readl(base + offset); 522 } 523 524 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val) 525 { 526 u32 reg; 527 528 reg = readl(base + offset); 529 reg &= ~val; 530 writel(reg, base + offset); 531 532 /* Ensure above write is completed */ 533 readl(base + offset); 534 } 535 536 static inline 537 void qcom_qusb2_phy_configure(void __iomem *base, 538 const unsigned int *regs, 539 const struct qusb2_phy_init_tbl tbl[], int num) 540 { 541 int i; 542 543 for (i = 0; i < num; i++) { 544 if (tbl[i].in_layout) 545 writel(tbl[i].val, base + regs[tbl[i].offset]); 546 else 547 writel(tbl[i].val, base + tbl[i].offset); 548 } 549 } 550 551 /* 552 * Update board specific PHY tuning override values if specified from 553 * device tree. 554 */ 555 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy) 556 { 557 const struct qusb2_phy_cfg *cfg = qphy->cfg; 558 struct override_params *or = &qphy->overrides; 559 560 if (or->imp_res_offset.override) 561 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, 562 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT, 563 IMP_RES_OFFSET_MASK); 564 565 if (or->bias_ctrl.override) 566 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2, 567 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT, 568 BIAS_CTRL2_RES_OFFSET_MASK); 569 570 if (or->charge_ctrl.override) 571 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2, 572 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT, 573 CHG_CTRL2_OFFSET_MASK); 574 575 if (or->hstx_trim.override) 576 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 577 or->hstx_trim.value << HSTX_TRIM_SHIFT, 578 HSTX_TRIM_MASK); 579 580 if (or->preemphasis.override) 581 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 582 or->preemphasis.value << PREEMPHASIS_EN_SHIFT, 583 PREEMPHASIS_EN_MASK); 584 585 if (or->preemphasis_width.override) { 586 if (or->preemphasis_width.value == 587 QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT) 588 qusb2_setbits(qphy->base, 589 cfg->regs[QUSB2PHY_PORT_TUNE1], 590 PREEMPH_WIDTH_HALF_BIT); 591 else 592 qusb2_clrbits(qphy->base, 593 cfg->regs[QUSB2PHY_PORT_TUNE1], 594 PREEMPH_WIDTH_HALF_BIT); 595 } 596 597 if (or->hsdisc_trim.override) 598 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], 599 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT, 600 HSDISC_TRIM_MASK); 601 } 602 603 /* 604 * Fetches HS Tx tuning value from nvmem and sets the 605 * QUSB2PHY_PORT_TUNE1/2 register. 606 * For error case, skip setting the value and use the default value. 607 */ 608 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) 609 { 610 struct device *dev = &qphy->phy->dev; 611 const struct qusb2_phy_cfg *cfg = qphy->cfg; 612 u8 *val, hstx_trim; 613 614 /* efuse register is optional */ 615 if (!qphy->cell) 616 return; 617 618 /* 619 * Read efuse register having TUNE2/1 parameter's high nibble. 620 * If efuse register shows value as 0x0 (indicating value is not 621 * fused), or if we fail to find a valid efuse register setting, 622 * then use default value for high nibble that we have already 623 * set while configuring the phy. 624 */ 625 val = nvmem_cell_read(qphy->cell, NULL); 626 if (IS_ERR(val)) { 627 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); 628 return; 629 } 630 hstx_trim = val[0]; 631 kfree(val); 632 if (!hstx_trim) { 633 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); 634 return; 635 } 636 637 /* Fused TUNE1/2 value is the higher nibble only */ 638 if (cfg->update_tune1_with_efuse) 639 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 640 hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK); 641 else 642 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], 643 hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK); 644 } 645 646 static int qusb2_phy_set_mode(struct phy *phy, 647 enum phy_mode mode, int submode) 648 { 649 struct qusb2_phy *qphy = phy_get_drvdata(phy); 650 651 qphy->mode = mode; 652 653 return 0; 654 } 655 656 static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev) 657 { 658 struct qusb2_phy *qphy = dev_get_drvdata(dev); 659 const struct qusb2_phy_cfg *cfg = qphy->cfg; 660 u32 intr_mask; 661 662 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode); 663 664 if (!qphy->phy_initialized) { 665 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 666 return 0; 667 } 668 669 /* 670 * Enable DP/DM interrupts to detect line state changes based on current 671 * speed. In other words, enable the triggers _opposite_ of what the 672 * current D+/D- levels are e.g. if currently D+ high, D- low 673 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high 674 */ 675 intr_mask = DPSE_INTR_EN | DMSE_INTR_EN; 676 switch (qphy->mode) { 677 case PHY_MODE_USB_HOST_HS: 678 case PHY_MODE_USB_HOST_FS: 679 case PHY_MODE_USB_DEVICE_HS: 680 case PHY_MODE_USB_DEVICE_FS: 681 intr_mask |= DMSE_INTR_HIGH_SEL; 682 break; 683 case PHY_MODE_USB_HOST_LS: 684 case PHY_MODE_USB_DEVICE_LS: 685 intr_mask |= DPSE_INTR_HIGH_SEL; 686 break; 687 default: 688 /* No device connected, enable both DP/DM high interrupt */ 689 intr_mask |= DMSE_INTR_HIGH_SEL; 690 intr_mask |= DPSE_INTR_HIGH_SEL; 691 break; 692 } 693 694 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); 695 696 /* hold core PLL into reset */ 697 if (cfg->has_pll_override) { 698 qusb2_setbits(qphy->base, 699 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], 700 CORE_PLL_EN_FROM_RESET | CORE_RESET | 701 CORE_RESET_MUX); 702 } 703 704 /* enable phy auto-resume only if device is connected on bus */ 705 if (qphy->mode != PHY_MODE_INVALID) { 706 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], 707 cfg->autoresume_en); 708 /* Autoresume bit has to be toggled in order to enable it */ 709 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], 710 cfg->autoresume_en); 711 } 712 713 if (!qphy->has_se_clk_scheme) 714 clk_disable_unprepare(qphy->ref_clk); 715 716 clk_disable_unprepare(qphy->cfg_ahb_clk); 717 clk_disable_unprepare(qphy->iface_clk); 718 719 return 0; 720 } 721 722 static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev) 723 { 724 struct qusb2_phy *qphy = dev_get_drvdata(dev); 725 const struct qusb2_phy_cfg *cfg = qphy->cfg; 726 int ret; 727 728 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode); 729 730 if (!qphy->phy_initialized) { 731 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 732 return 0; 733 } 734 735 ret = clk_prepare_enable(qphy->iface_clk); 736 if (ret) { 737 dev_err(dev, "failed to enable iface_clk, %d\n", ret); 738 return ret; 739 } 740 741 ret = clk_prepare_enable(qphy->cfg_ahb_clk); 742 if (ret) { 743 dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret); 744 goto disable_iface_clk; 745 } 746 747 if (!qphy->has_se_clk_scheme) { 748 ret = clk_prepare_enable(qphy->ref_clk); 749 if (ret) { 750 dev_err(dev, "failed to enable ref clk, %d\n", ret); 751 goto disable_ahb_clk; 752 } 753 } 754 755 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); 756 757 /* bring core PLL out of reset */ 758 if (cfg->has_pll_override) { 759 qusb2_clrbits(qphy->base, 760 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], 761 CORE_RESET | CORE_RESET_MUX); 762 } 763 764 return 0; 765 766 disable_ahb_clk: 767 clk_disable_unprepare(qphy->cfg_ahb_clk); 768 disable_iface_clk: 769 clk_disable_unprepare(qphy->iface_clk); 770 771 return ret; 772 } 773 774 static int qusb2_phy_init(struct phy *phy) 775 { 776 struct qusb2_phy *qphy = phy_get_drvdata(phy); 777 const struct qusb2_phy_cfg *cfg = qphy->cfg; 778 unsigned int val = 0; 779 unsigned int clk_scheme; 780 int ret; 781 782 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__); 783 784 /* turn on regulator supplies */ 785 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 786 if (ret) 787 return ret; 788 789 ret = clk_prepare_enable(qphy->iface_clk); 790 if (ret) { 791 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret); 792 goto poweroff_phy; 793 } 794 795 /* enable ahb interface clock to program phy */ 796 ret = clk_prepare_enable(qphy->cfg_ahb_clk); 797 if (ret) { 798 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); 799 goto disable_iface_clk; 800 } 801 802 /* Perform phy reset */ 803 ret = reset_control_assert(qphy->phy_reset); 804 if (ret) { 805 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); 806 goto disable_ahb_clk; 807 } 808 809 /* 100 us delay to keep PHY in reset mode */ 810 usleep_range(100, 150); 811 812 ret = reset_control_deassert(qphy->phy_reset); 813 if (ret) { 814 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); 815 goto disable_ahb_clk; 816 } 817 818 /* Disable the PHY */ 819 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], 820 qphy->cfg->disable_ctrl); 821 822 if (cfg->has_pll_test) { 823 /* save reset value to override reference clock scheme later */ 824 val = readl(qphy->base + QUSB2PHY_PLL_TEST); 825 } 826 827 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, 828 cfg->tbl_num); 829 830 /* Override board specific PHY tuning values */ 831 qusb2_phy_override_phy_params(qphy); 832 833 /* Set efuse value for tuning the PHY */ 834 qusb2_phy_set_tune2_param(qphy); 835 836 /* Enable the PHY */ 837 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], 838 POWER_DOWN); 839 840 /* Required to get phy pll lock successfully */ 841 usleep_range(150, 160); 842 843 /* 844 * Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME 845 * register in the TCSR so, if there's none, use the default 846 * value hardcoded in the configuration. 847 */ 848 qphy->has_se_clk_scheme = cfg->se_clk_scheme_default; 849 850 /* 851 * read TCSR_PHY_CLK_SCHEME register to check if single-ended 852 * clock scheme is selected. If yes, then disable differential 853 * ref_clk and use single-ended clock, otherwise use differential 854 * ref_clk only. 855 */ 856 if (qphy->tcsr) { 857 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, 858 &clk_scheme); 859 if (ret) { 860 dev_err(&phy->dev, "failed to read clk scheme reg\n"); 861 goto assert_phy_reset; 862 } 863 864 /* is it a differential clock scheme ? */ 865 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) { 866 dev_vdbg(&phy->dev, "%s(): select differential clk\n", 867 __func__); 868 qphy->has_se_clk_scheme = false; 869 } else { 870 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n", 871 __func__); 872 } 873 } 874 875 if (!qphy->has_se_clk_scheme) { 876 ret = clk_prepare_enable(qphy->ref_clk); 877 if (ret) { 878 dev_err(&phy->dev, "failed to enable ref clk, %d\n", 879 ret); 880 goto assert_phy_reset; 881 } 882 } 883 884 if (cfg->has_pll_test) { 885 if (!qphy->has_se_clk_scheme) 886 val &= ~CLK_REF_SEL; 887 else 888 val |= CLK_REF_SEL; 889 890 writel(val, qphy->base + QUSB2PHY_PLL_TEST); 891 892 /* ensure above write is through */ 893 readl(qphy->base + QUSB2PHY_PLL_TEST); 894 } 895 896 /* Required to get phy pll lock successfully */ 897 usleep_range(100, 110); 898 899 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); 900 if (!(val & cfg->mask_core_ready)) { 901 dev_err(&phy->dev, 902 "QUSB2PHY pll lock failed: status reg = %x\n", val); 903 ret = -EBUSY; 904 goto disable_ref_clk; 905 } 906 qphy->phy_initialized = true; 907 908 return 0; 909 910 disable_ref_clk: 911 if (!qphy->has_se_clk_scheme) 912 clk_disable_unprepare(qphy->ref_clk); 913 assert_phy_reset: 914 reset_control_assert(qphy->phy_reset); 915 disable_ahb_clk: 916 clk_disable_unprepare(qphy->cfg_ahb_clk); 917 disable_iface_clk: 918 clk_disable_unprepare(qphy->iface_clk); 919 poweroff_phy: 920 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 921 922 return ret; 923 } 924 925 static int qusb2_phy_exit(struct phy *phy) 926 { 927 struct qusb2_phy *qphy = phy_get_drvdata(phy); 928 929 /* Disable the PHY */ 930 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], 931 qphy->cfg->disable_ctrl); 932 933 if (!qphy->has_se_clk_scheme) 934 clk_disable_unprepare(qphy->ref_clk); 935 936 reset_control_assert(qphy->phy_reset); 937 938 clk_disable_unprepare(qphy->cfg_ahb_clk); 939 clk_disable_unprepare(qphy->iface_clk); 940 941 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 942 943 qphy->phy_initialized = false; 944 945 return 0; 946 } 947 948 static const struct phy_ops qusb2_phy_gen_ops = { 949 .init = qusb2_phy_init, 950 .exit = qusb2_phy_exit, 951 .set_mode = qusb2_phy_set_mode, 952 .owner = THIS_MODULE, 953 }; 954 955 static const struct of_device_id qusb2_phy_of_match_table[] = { 956 { 957 .compatible = "qcom,ipq5424-qusb2-phy", 958 .data = &ipq5424_phy_cfg, 959 }, { 960 .compatible = "qcom,ipq6018-qusb2-phy", 961 .data = &ipq6018_phy_cfg, 962 }, { 963 .compatible = "qcom,ipq8074-qusb2-phy", 964 .data = &msm8996_phy_cfg, 965 }, { 966 .compatible = "qcom,ipq9574-qusb2-phy", 967 .data = &ipq6018_phy_cfg, 968 }, { 969 .compatible = "qcom,msm8953-qusb2-phy", 970 .data = &msm8996_phy_cfg, 971 }, { 972 .compatible = "qcom,msm8996-qusb2-phy", 973 .data = &msm8996_phy_cfg, 974 }, { 975 .compatible = "qcom,msm8998-qusb2-phy", 976 .data = &msm8998_phy_cfg, 977 }, { 978 .compatible = "qcom,qcs615-qusb2-phy", 979 .data = &qcs615_phy_cfg, 980 }, { 981 .compatible = "qcom,qcm2290-qusb2-phy", 982 .data = &sm6115_phy_cfg, 983 }, { 984 .compatible = "qcom,sdm660-qusb2-phy", 985 .data = &sdm660_phy_cfg, 986 }, { 987 .compatible = "qcom,sm4250-qusb2-phy", 988 .data = &sm6115_phy_cfg, 989 }, { 990 .compatible = "qcom,sm6115-qusb2-phy", 991 .data = &sm6115_phy_cfg, 992 }, { 993 /* 994 * Deprecated. Only here to support legacy device 995 * trees that didn't include "qcom,qusb2-v2-phy" 996 */ 997 .compatible = "qcom,sdm845-qusb2-phy", 998 .data = &qusb2_v2_phy_cfg, 999 }, { 1000 .compatible = "qcom,qusb2-v2-phy", 1001 .data = &qusb2_v2_phy_cfg, 1002 }, 1003 { }, 1004 }; 1005 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table); 1006 1007 static const struct dev_pm_ops qusb2_phy_pm_ops = { 1008 SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend, 1009 qusb2_phy_runtime_resume, NULL) 1010 }; 1011 1012 static int qusb2_phy_probe(struct platform_device *pdev) 1013 { 1014 struct device *dev = &pdev->dev; 1015 struct qusb2_phy *qphy; 1016 struct phy_provider *phy_provider; 1017 struct phy *generic_phy; 1018 int ret, i; 1019 int num; 1020 u32 value; 1021 struct override_params *or; 1022 1023 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 1024 if (!qphy) 1025 return -ENOMEM; 1026 or = &qphy->overrides; 1027 1028 qphy->base = devm_platform_ioremap_resource(pdev, 0); 1029 if (IS_ERR(qphy->base)) 1030 return PTR_ERR(qphy->base); 1031 1032 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); 1033 if (IS_ERR(qphy->cfg_ahb_clk)) 1034 return dev_err_probe(dev, PTR_ERR(qphy->cfg_ahb_clk), 1035 "failed to get cfg ahb clk\n"); 1036 1037 qphy->ref_clk = devm_clk_get(dev, "ref"); 1038 if (IS_ERR(qphy->ref_clk)) 1039 return dev_err_probe(dev, PTR_ERR(qphy->ref_clk), 1040 "failed to get ref clk\n"); 1041 1042 qphy->iface_clk = devm_clk_get_optional(dev, "iface"); 1043 if (IS_ERR(qphy->iface_clk)) 1044 return PTR_ERR(qphy->iface_clk); 1045 1046 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0); 1047 if (IS_ERR(qphy->phy_reset)) { 1048 dev_err(dev, "failed to get phy core reset\n"); 1049 return PTR_ERR(qphy->phy_reset); 1050 } 1051 1052 num = ARRAY_SIZE(qphy->vregs); 1053 for (i = 0; i < num; i++) 1054 qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; 1055 1056 ret = devm_regulator_bulk_get(dev, num, qphy->vregs); 1057 if (ret) 1058 return dev_err_probe(dev, ret, 1059 "failed to get regulator supplies\n"); 1060 1061 /* Get the specific init parameters of QMP phy */ 1062 qphy->cfg = of_device_get_match_data(dev); 1063 1064 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, 1065 "qcom,tcsr-syscon"); 1066 if (IS_ERR(qphy->tcsr)) { 1067 dev_dbg(dev, "failed to lookup TCSR regmap\n"); 1068 qphy->tcsr = NULL; 1069 } 1070 1071 qphy->cell = devm_nvmem_cell_get(dev, NULL); 1072 if (IS_ERR(qphy->cell)) { 1073 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER) 1074 return -EPROBE_DEFER; 1075 qphy->cell = NULL; 1076 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n"); 1077 } 1078 1079 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value", 1080 &value)) { 1081 or->imp_res_offset.value = (u8)value; 1082 or->imp_res_offset.override = true; 1083 } 1084 1085 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value", 1086 &value)) { 1087 or->bias_ctrl.value = (u8)value; 1088 or->bias_ctrl.override = true; 1089 } 1090 1091 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value", 1092 &value)) { 1093 or->charge_ctrl.value = (u8)value; 1094 or->charge_ctrl.override = true; 1095 } 1096 1097 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", 1098 &value)) { 1099 or->hstx_trim.value = (u8)value; 1100 or->hstx_trim.override = true; 1101 } 1102 1103 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level", 1104 &value)) { 1105 or->preemphasis.value = (u8)value; 1106 or->preemphasis.override = true; 1107 } 1108 1109 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width", 1110 &value)) { 1111 or->preemphasis_width.value = (u8)value; 1112 or->preemphasis_width.override = true; 1113 } 1114 1115 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value", 1116 &value)) { 1117 or->hsdisc_trim.value = (u8)value; 1118 or->hsdisc_trim.override = true; 1119 } 1120 1121 pm_runtime_set_active(dev); 1122 pm_runtime_enable(dev); 1123 /* 1124 * Prevent runtime pm from being ON by default. Users can enable 1125 * it using power/control in sysfs. 1126 */ 1127 pm_runtime_forbid(dev); 1128 1129 generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops); 1130 if (IS_ERR(generic_phy)) { 1131 ret = PTR_ERR(generic_phy); 1132 dev_err(dev, "failed to create phy, %d\n", ret); 1133 pm_runtime_disable(dev); 1134 return ret; 1135 } 1136 qphy->phy = generic_phy; 1137 1138 dev_set_drvdata(dev, qphy); 1139 phy_set_drvdata(generic_phy, qphy); 1140 1141 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1142 if (!IS_ERR(phy_provider)) 1143 dev_info(dev, "Registered Qcom-QUSB2 phy\n"); 1144 else 1145 pm_runtime_disable(dev); 1146 1147 return PTR_ERR_OR_ZERO(phy_provider); 1148 } 1149 1150 static struct platform_driver qusb2_phy_driver = { 1151 .probe = qusb2_phy_probe, 1152 .driver = { 1153 .name = "qcom-qusb2-phy", 1154 .pm = &qusb2_phy_pm_ops, 1155 .of_match_table = qusb2_phy_of_match_table, 1156 }, 1157 }; 1158 1159 module_platform_driver(qusb2_phy_driver); 1160 1161 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 1162 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver"); 1163 MODULE_LICENSE("GPL v2"); 1164