1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/export.h>
9 #include <linux/clk-provider.h>
10 #include <linux/regmap.h>
11 #include <linux/delay.h>
12
13 #include "clk-alpha-pll.h"
14 #include "common.h"
15
16 #define PLL_MODE(p) ((p)->offset + 0x0)
17 # define PLL_OUTCTRL BIT(0)
18 # define PLL_BYPASSNL BIT(1)
19 # define PLL_RESET_N BIT(2)
20 # define PLL_OFFLINE_REQ BIT(7)
21 # define PLL_LOCK_COUNT_SHIFT 8
22 # define PLL_LOCK_COUNT_MASK 0x3f
23 # define PLL_BIAS_COUNT_SHIFT 14
24 # define PLL_BIAS_COUNT_MASK 0x3f
25 # define PLL_VOTE_FSM_ENA BIT(20)
26 # define PLL_FSM_ENA BIT(20)
27 # define PLL_VOTE_FSM_RESET BIT(21)
28 # define PLL_UPDATE BIT(22)
29 # define PLL_UPDATE_BYPASS BIT(23)
30 # define PLL_FSM_LEGACY_MODE BIT(24)
31 # define PLL_OFFLINE_ACK BIT(28)
32 # define ALPHA_PLL_ACK_LATCH BIT(29)
33 # define PLL_ACTIVE_FLAG BIT(30)
34 # define PLL_LOCK_DET BIT(31)
35
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
40
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
42 # define PLL_POST_DIV_SHIFT 8
43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0)
44 # define PLL_ALPHA_MSB BIT(15)
45 # define PLL_ALPHA_EN BIT(24)
46 # define PLL_ALPHA_MODE BIT(25)
47 # define PLL_VCO_SHIFT 20
48 # define PLL_VCO_MASK 0x3
49
50 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
51 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
52
53 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
54 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
55 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
56 #define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2])
57 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
58 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
59 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
60 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
61 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
62 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
63 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
64
65 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
66 [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
67 [PLL_OFF_L_VAL] = 0x04,
68 [PLL_OFF_ALPHA_VAL] = 0x08,
69 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
70 [PLL_OFF_USER_CTL] = 0x10,
71 [PLL_OFF_USER_CTL_U] = 0x14,
72 [PLL_OFF_CONFIG_CTL] = 0x18,
73 [PLL_OFF_TEST_CTL] = 0x1c,
74 [PLL_OFF_TEST_CTL_U] = 0x20,
75 [PLL_OFF_STATUS] = 0x24,
76 },
77 [CLK_ALPHA_PLL_TYPE_HUAYRA] = {
78 [PLL_OFF_L_VAL] = 0x04,
79 [PLL_OFF_ALPHA_VAL] = 0x08,
80 [PLL_OFF_USER_CTL] = 0x10,
81 [PLL_OFF_CONFIG_CTL] = 0x14,
82 [PLL_OFF_CONFIG_CTL_U] = 0x18,
83 [PLL_OFF_TEST_CTL] = 0x1c,
84 [PLL_OFF_TEST_CTL_U] = 0x20,
85 [PLL_OFF_STATUS] = 0x24,
86 },
87 [CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = {
88 [PLL_OFF_L_VAL] = 0x08,
89 [PLL_OFF_ALPHA_VAL] = 0x10,
90 [PLL_OFF_USER_CTL] = 0x18,
91 [PLL_OFF_CONFIG_CTL] = 0x20,
92 [PLL_OFF_CONFIG_CTL_U] = 0x24,
93 [PLL_OFF_STATUS] = 0x28,
94 [PLL_OFF_TEST_CTL] = 0x30,
95 [PLL_OFF_TEST_CTL_U] = 0x34,
96 },
97 [CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = {
98 [PLL_OFF_L_VAL] = 0x04,
99 [PLL_OFF_ALPHA_VAL] = 0x08,
100 [PLL_OFF_USER_CTL] = 0x0c,
101 [PLL_OFF_CONFIG_CTL] = 0x10,
102 [PLL_OFF_CONFIG_CTL_U] = 0x14,
103 [PLL_OFF_CONFIG_CTL_U1] = 0x18,
104 [PLL_OFF_TEST_CTL] = 0x1c,
105 [PLL_OFF_TEST_CTL_U] = 0x20,
106 [PLL_OFF_TEST_CTL_U1] = 0x24,
107 [PLL_OFF_OPMODE] = 0x28,
108 [PLL_OFF_STATUS] = 0x38,
109 },
110 [CLK_ALPHA_PLL_TYPE_BRAMMO] = {
111 [PLL_OFF_L_VAL] = 0x04,
112 [PLL_OFF_ALPHA_VAL] = 0x08,
113 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
114 [PLL_OFF_USER_CTL] = 0x10,
115 [PLL_OFF_CONFIG_CTL] = 0x18,
116 [PLL_OFF_TEST_CTL] = 0x1c,
117 [PLL_OFF_STATUS] = 0x24,
118 },
119 [CLK_ALPHA_PLL_TYPE_FABIA] = {
120 [PLL_OFF_L_VAL] = 0x04,
121 [PLL_OFF_USER_CTL] = 0x0c,
122 [PLL_OFF_USER_CTL_U] = 0x10,
123 [PLL_OFF_CONFIG_CTL] = 0x14,
124 [PLL_OFF_CONFIG_CTL_U] = 0x18,
125 [PLL_OFF_TEST_CTL] = 0x1c,
126 [PLL_OFF_TEST_CTL_U] = 0x20,
127 [PLL_OFF_STATUS] = 0x24,
128 [PLL_OFF_OPMODE] = 0x2c,
129 [PLL_OFF_FRAC] = 0x38,
130 },
131 [CLK_ALPHA_PLL_TYPE_TRION] = {
132 [PLL_OFF_L_VAL] = 0x04,
133 [PLL_OFF_CAL_L_VAL] = 0x08,
134 [PLL_OFF_USER_CTL] = 0x0c,
135 [PLL_OFF_USER_CTL_U] = 0x10,
136 [PLL_OFF_USER_CTL_U1] = 0x14,
137 [PLL_OFF_CONFIG_CTL] = 0x18,
138 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
139 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
140 [PLL_OFF_TEST_CTL] = 0x24,
141 [PLL_OFF_TEST_CTL_U] = 0x28,
142 [PLL_OFF_TEST_CTL_U1] = 0x2c,
143 [PLL_OFF_STATUS] = 0x30,
144 [PLL_OFF_OPMODE] = 0x38,
145 [PLL_OFF_ALPHA_VAL] = 0x40,
146 },
147 [CLK_ALPHA_PLL_TYPE_AGERA] = {
148 [PLL_OFF_L_VAL] = 0x04,
149 [PLL_OFF_ALPHA_VAL] = 0x08,
150 [PLL_OFF_USER_CTL] = 0x0c,
151 [PLL_OFF_CONFIG_CTL] = 0x10,
152 [PLL_OFF_CONFIG_CTL_U] = 0x14,
153 [PLL_OFF_TEST_CTL] = 0x18,
154 [PLL_OFF_TEST_CTL_U] = 0x1c,
155 [PLL_OFF_STATUS] = 0x2c,
156 },
157 [CLK_ALPHA_PLL_TYPE_ZONDA] = {
158 [PLL_OFF_L_VAL] = 0x04,
159 [PLL_OFF_ALPHA_VAL] = 0x08,
160 [PLL_OFF_USER_CTL] = 0x0c,
161 [PLL_OFF_CONFIG_CTL] = 0x10,
162 [PLL_OFF_CONFIG_CTL_U] = 0x14,
163 [PLL_OFF_CONFIG_CTL_U1] = 0x18,
164 [PLL_OFF_TEST_CTL] = 0x1c,
165 [PLL_OFF_TEST_CTL_U] = 0x20,
166 [PLL_OFF_TEST_CTL_U1] = 0x24,
167 [PLL_OFF_OPMODE] = 0x28,
168 [PLL_OFF_STATUS] = 0x38,
169 },
170 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
171 [PLL_OFF_OPMODE] = 0x04,
172 [PLL_OFF_STATUS] = 0x0c,
173 [PLL_OFF_L_VAL] = 0x10,
174 [PLL_OFF_ALPHA_VAL] = 0x14,
175 [PLL_OFF_USER_CTL] = 0x18,
176 [PLL_OFF_USER_CTL_U] = 0x1c,
177 [PLL_OFF_CONFIG_CTL] = 0x20,
178 [PLL_OFF_CONFIG_CTL_U] = 0x24,
179 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
180 [PLL_OFF_TEST_CTL] = 0x2c,
181 [PLL_OFF_TEST_CTL_U] = 0x30,
182 [PLL_OFF_TEST_CTL_U1] = 0x34,
183 },
184 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
185 [PLL_OFF_OPMODE] = 0x04,
186 [PLL_OFF_STATE] = 0x08,
187 [PLL_OFF_STATUS] = 0x0c,
188 [PLL_OFF_L_VAL] = 0x10,
189 [PLL_OFF_ALPHA_VAL] = 0x14,
190 [PLL_OFF_USER_CTL] = 0x18,
191 [PLL_OFF_USER_CTL_U] = 0x1c,
192 [PLL_OFF_CONFIG_CTL] = 0x20,
193 [PLL_OFF_CONFIG_CTL_U] = 0x24,
194 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
195 [PLL_OFF_TEST_CTL] = 0x2c,
196 [PLL_OFF_TEST_CTL_U] = 0x30,
197 [PLL_OFF_TEST_CTL_U1] = 0x34,
198 [PLL_OFF_TEST_CTL_U2] = 0x38,
199 },
200 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
201 [PLL_OFF_OPMODE] = 0x04,
202 [PLL_OFF_STATUS] = 0x0c,
203 [PLL_OFF_L_VAL] = 0x10,
204 [PLL_OFF_USER_CTL] = 0x14,
205 [PLL_OFF_USER_CTL_U] = 0x18,
206 [PLL_OFF_CONFIG_CTL] = 0x1c,
207 [PLL_OFF_CONFIG_CTL_U] = 0x20,
208 [PLL_OFF_CONFIG_CTL_U1] = 0x24,
209 [PLL_OFF_TEST_CTL] = 0x28,
210 [PLL_OFF_TEST_CTL_U] = 0x2c,
211 },
212 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
213 [PLL_OFF_L_VAL] = 0x04,
214 [PLL_OFF_ALPHA_VAL] = 0x08,
215 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
216 [PLL_OFF_TEST_CTL] = 0x10,
217 [PLL_OFF_TEST_CTL_U] = 0x14,
218 [PLL_OFF_USER_CTL] = 0x18,
219 [PLL_OFF_USER_CTL_U] = 0x1c,
220 [PLL_OFF_CONFIG_CTL] = 0x20,
221 [PLL_OFF_STATUS] = 0x24,
222 },
223 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
224 [PLL_OFF_L_VAL] = 0x04,
225 [PLL_OFF_ALPHA_VAL] = 0x08,
226 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
227 [PLL_OFF_TEST_CTL] = 0x10,
228 [PLL_OFF_TEST_CTL_U] = 0x14,
229 [PLL_OFF_USER_CTL] = 0x18,
230 [PLL_OFF_CONFIG_CTL] = 0x1C,
231 [PLL_OFF_STATUS] = 0x20,
232 },
233 [CLK_ALPHA_PLL_TYPE_STROMER] = {
234 [PLL_OFF_L_VAL] = 0x08,
235 [PLL_OFF_ALPHA_VAL] = 0x10,
236 [PLL_OFF_ALPHA_VAL_U] = 0x14,
237 [PLL_OFF_USER_CTL] = 0x18,
238 [PLL_OFF_USER_CTL_U] = 0x1c,
239 [PLL_OFF_CONFIG_CTL] = 0x20,
240 [PLL_OFF_STATUS] = 0x28,
241 [PLL_OFF_TEST_CTL] = 0x30,
242 [PLL_OFF_TEST_CTL_U] = 0x34,
243 },
244 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
245 [PLL_OFF_L_VAL] = 0x04,
246 [PLL_OFF_USER_CTL] = 0x08,
247 [PLL_OFF_USER_CTL_U] = 0x0c,
248 [PLL_OFF_CONFIG_CTL] = 0x10,
249 [PLL_OFF_TEST_CTL] = 0x14,
250 [PLL_OFF_TEST_CTL_U] = 0x18,
251 [PLL_OFF_STATUS] = 0x1c,
252 [PLL_OFF_ALPHA_VAL] = 0x24,
253 [PLL_OFF_ALPHA_VAL_U] = 0x28,
254 },
255 [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = {
256 [PLL_OFF_L_VAL] = 0x04,
257 [PLL_OFF_ALPHA_VAL] = 0x08,
258 [PLL_OFF_USER_CTL] = 0x0c,
259 [PLL_OFF_USER_CTL_U] = 0x10,
260 [PLL_OFF_CONFIG_CTL] = 0x14,
261 [PLL_OFF_CONFIG_CTL_U] = 0x18,
262 [PLL_OFF_CONFIG_CTL_U1] = 0x1c,
263 [PLL_OFF_CONFIG_CTL_U2] = 0x20,
264 [PLL_OFF_TEST_CTL] = 0x24,
265 [PLL_OFF_TEST_CTL_U] = 0x28,
266 [PLL_OFF_TEST_CTL_U1] = 0x2c,
267 [PLL_OFF_OPMODE] = 0x30,
268 [PLL_OFF_STATUS] = 0x3c,
269 },
270 [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
271 [PLL_OFF_L_VAL] = 0x04,
272 [PLL_OFF_ALPHA_VAL] = 0x08,
273 [PLL_OFF_TEST_CTL] = 0x0c,
274 [PLL_OFF_TEST_CTL_U] = 0x10,
275 [PLL_OFF_USER_CTL] = 0x14,
276 [PLL_OFF_CONFIG_CTL] = 0x18,
277 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
278 [PLL_OFF_STATUS] = 0x20,
279 },
280
281 };
282 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
283
284 /*
285 * Even though 40 bits are present, use only 32 for ease of calculation.
286 */
287 #define ALPHA_REG_BITWIDTH 40
288 #define ALPHA_REG_16BIT_WIDTH 16
289 #define ALPHA_BITWIDTH 32U
290 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
291
292 #define ALPHA_PLL_STATUS_REG_SHIFT 8
293
294 #define PLL_HUAYRA_M_WIDTH 8
295 #define PLL_HUAYRA_M_SHIFT 8
296 #define PLL_HUAYRA_M_MASK 0xff
297 #define PLL_HUAYRA_N_SHIFT 0
298 #define PLL_HUAYRA_N_MASK 0xff
299 #define PLL_HUAYRA_ALPHA_WIDTH 16
300
301 #define PLL_STANDBY 0x0
302 #define PLL_RUN 0x1
303 #define PLL_OUT_MASK 0x7
304 #define PLL_RATE_MARGIN 500
305
306 /* TRION PLL specific settings and offsets */
307 #define TRION_PLL_CAL_VAL 0x44
308 #define TRION_PCAL_DONE BIT(26)
309
310 /* LUCID PLL specific settings and offsets */
311 #define LUCID_PCAL_DONE BIT(27)
312
313 /* LUCID 5LPE PLL specific settings and offsets */
314 #define LUCID_5LPE_PCAL_DONE BIT(11)
315 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13)
316 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
317 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
318
319 /* LUCID EVO PLL specific settings and offsets */
320 #define LUCID_EVO_PCAL_NOT_DONE BIT(8)
321 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
322 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
323 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
324 #define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24
325
326 /* ZONDA PLL specific */
327 #define ZONDA_PLL_OUT_MASK 0xf
328 #define ZONDA_STAY_IN_CFA BIT(16)
329 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
330
331 #define pll_alpha_width(p) \
332 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
333 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
334
335 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
336
337 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
338 struct clk_alpha_pll, clkr)
339
340 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
341 struct clk_alpha_pll_postdiv, clkr)
342
wait_for_pll(struct clk_alpha_pll * pll,u32 mask,bool inverse,const char * action)343 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
344 const char *action)
345 {
346 u32 val;
347 int count;
348 int ret;
349 const char *name = clk_hw_get_name(&pll->clkr.hw);
350
351 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
352 if (ret)
353 return ret;
354
355 for (count = 200; count > 0; count--) {
356 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
357 if (ret)
358 return ret;
359 if (inverse && !(val & mask))
360 return 0;
361 else if ((val & mask) == mask)
362 return 0;
363
364 udelay(1);
365 }
366
367 WARN(1, "%s failed to %s!\n", name, action);
368 return -ETIMEDOUT;
369 }
370
371 #define wait_for_pll_enable_active(pll) \
372 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
373
374 #define wait_for_pll_enable_lock(pll) \
375 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
376
377 #define wait_for_zonda_pll_freq_lock(pll) \
378 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
379
380 #define wait_for_pll_disable(pll) \
381 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
382
383 #define wait_for_pll_offline(pll) \
384 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
385
386 #define wait_for_pll_update(pll) \
387 wait_for_pll(pll, PLL_UPDATE, 1, "update")
388
389 #define wait_for_pll_update_ack_set(pll) \
390 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
391
392 #define wait_for_pll_update_ack_clear(pll) \
393 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
394
clk_alpha_pll_write_config(struct regmap * regmap,unsigned int reg,unsigned int val)395 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg,
396 unsigned int val)
397 {
398 if (val)
399 regmap_write(regmap, reg, val);
400 }
401
clk_alpha_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)402 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
403 const struct alpha_pll_config *config)
404 {
405 u32 val, mask;
406
407 regmap_write(regmap, PLL_L_VAL(pll), config->l);
408 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
409 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
410
411 if (pll_has_64bit_config(pll))
412 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
413 config->config_ctl_hi_val);
414
415 if (pll_alpha_width(pll) > 32)
416 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
417
418 val = config->main_output_mask;
419 val |= config->aux_output_mask;
420 val |= config->aux2_output_mask;
421 val |= config->early_output_mask;
422 val |= config->pre_div_val;
423 val |= config->post_div_val;
424 val |= config->vco_val;
425 val |= config->alpha_en_mask;
426 val |= config->alpha_mode_mask;
427
428 mask = config->main_output_mask;
429 mask |= config->aux_output_mask;
430 mask |= config->aux2_output_mask;
431 mask |= config->early_output_mask;
432 mask |= config->pre_div_mask;
433 mask |= config->post_div_mask;
434 mask |= config->vco_mask;
435
436 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
437
438 if (config->test_ctl_mask)
439 regmap_update_bits(regmap, PLL_TEST_CTL(pll),
440 config->test_ctl_mask,
441 config->test_ctl_val);
442 else
443 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
444 config->test_ctl_val);
445
446 if (config->test_ctl_hi_mask)
447 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll),
448 config->test_ctl_hi_mask,
449 config->test_ctl_hi_val);
450 else
451 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
452 config->test_ctl_hi_val);
453
454 if (pll->flags & SUPPORTS_FSM_MODE)
455 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
456 }
457 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
458
clk_alpha_pll_hwfsm_enable(struct clk_hw * hw)459 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
460 {
461 int ret;
462 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
463 u32 val;
464
465 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
466 if (ret)
467 return ret;
468
469 val |= PLL_FSM_ENA;
470
471 if (pll->flags & SUPPORTS_OFFLINE_REQ)
472 val &= ~PLL_OFFLINE_REQ;
473
474 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
475 if (ret)
476 return ret;
477
478 /* Make sure enable request goes through before waiting for update */
479 mb();
480
481 return wait_for_pll_enable_active(pll);
482 }
483
clk_alpha_pll_hwfsm_disable(struct clk_hw * hw)484 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
485 {
486 int ret;
487 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
488 u32 val;
489
490 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
491 if (ret)
492 return;
493
494 if (pll->flags & SUPPORTS_OFFLINE_REQ) {
495 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
496 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
497 if (ret)
498 return;
499
500 ret = wait_for_pll_offline(pll);
501 if (ret)
502 return;
503 }
504
505 /* Disable hwfsm */
506 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
507 PLL_FSM_ENA, 0);
508 if (ret)
509 return;
510
511 wait_for_pll_disable(pll);
512 }
513
pll_is_enabled(struct clk_hw * hw,u32 mask)514 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
515 {
516 int ret;
517 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
518 u32 val;
519
520 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
521 if (ret)
522 return ret;
523
524 return !!(val & mask);
525 }
526
clk_alpha_pll_hwfsm_is_enabled(struct clk_hw * hw)527 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
528 {
529 return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
530 }
531
clk_alpha_pll_is_enabled(struct clk_hw * hw)532 static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
533 {
534 return pll_is_enabled(hw, PLL_LOCK_DET);
535 }
536
clk_alpha_pll_enable(struct clk_hw * hw)537 static int clk_alpha_pll_enable(struct clk_hw *hw)
538 {
539 int ret;
540 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
541 u32 val, mask;
542
543 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
544 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
545 if (ret)
546 return ret;
547
548 /* If in FSM mode, just vote for it */
549 if (val & PLL_VOTE_FSM_ENA) {
550 ret = clk_enable_regmap(hw);
551 if (ret)
552 return ret;
553 return wait_for_pll_enable_active(pll);
554 }
555
556 /* Skip if already enabled */
557 if ((val & mask) == mask)
558 return 0;
559
560 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
561 PLL_BYPASSNL, PLL_BYPASSNL);
562 if (ret)
563 return ret;
564
565 /*
566 * H/W requires a 5us delay between disabling the bypass and
567 * de-asserting the reset.
568 */
569 mb();
570 udelay(5);
571
572 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
573 PLL_RESET_N, PLL_RESET_N);
574 if (ret)
575 return ret;
576
577 ret = wait_for_pll_enable_lock(pll);
578 if (ret)
579 return ret;
580
581 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
582 PLL_OUTCTRL, PLL_OUTCTRL);
583
584 /* Ensure that the write above goes through before returning. */
585 mb();
586 return ret;
587 }
588
clk_alpha_pll_disable(struct clk_hw * hw)589 static void clk_alpha_pll_disable(struct clk_hw *hw)
590 {
591 int ret;
592 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
593 u32 val, mask;
594
595 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
596 if (ret)
597 return;
598
599 /* If in FSM mode, just unvote it */
600 if (val & PLL_VOTE_FSM_ENA) {
601 clk_disable_regmap(hw);
602 return;
603 }
604
605 mask = PLL_OUTCTRL;
606 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
607
608 /* Delay of 2 output clock ticks required until output is disabled */
609 mb();
610 udelay(1);
611
612 mask = PLL_RESET_N | PLL_BYPASSNL;
613 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
614 }
615
616 static unsigned long
alpha_pll_calc_rate(u64 prate,u32 l,u32 a,u32 alpha_width)617 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
618 {
619 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
620 }
621
622 static unsigned long
alpha_pll_round_rate(unsigned long rate,unsigned long prate,u32 * l,u64 * a,u32 alpha_width)623 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
624 u32 alpha_width)
625 {
626 u64 remainder;
627 u64 quotient;
628
629 quotient = rate;
630 remainder = do_div(quotient, prate);
631 *l = quotient;
632
633 if (!remainder) {
634 *a = 0;
635 return rate;
636 }
637
638 /* Upper ALPHA_BITWIDTH bits of Alpha */
639 quotient = remainder << ALPHA_SHIFT(alpha_width);
640
641 remainder = do_div(quotient, prate);
642
643 if (remainder)
644 quotient++;
645
646 *a = quotient;
647 return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
648 }
649
650 static const struct pll_vco *
alpha_pll_find_vco(const struct clk_alpha_pll * pll,unsigned long rate)651 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
652 {
653 const struct pll_vco *v = pll->vco_table;
654 const struct pll_vco *end = v + pll->num_vco;
655
656 for (; v < end; v++)
657 if (rate >= v->min_freq && rate <= v->max_freq)
658 return v;
659
660 return NULL;
661 }
662
663 static unsigned long
clk_alpha_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)664 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
665 {
666 u32 l, low, high, ctl;
667 u64 a = 0, prate = parent_rate;
668 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
669 u32 alpha_width = pll_alpha_width(pll);
670
671 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
672
673 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
674 if (ctl & PLL_ALPHA_EN) {
675 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
676 if (alpha_width > 32) {
677 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
678 &high);
679 a = (u64)high << 32 | low;
680 } else {
681 a = low & GENMASK(alpha_width - 1, 0);
682 }
683
684 if (alpha_width > ALPHA_BITWIDTH)
685 a >>= alpha_width - ALPHA_BITWIDTH;
686 }
687
688 return alpha_pll_calc_rate(prate, l, a, alpha_width);
689 }
690
691
__clk_alpha_pll_update_latch(struct clk_alpha_pll * pll)692 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
693 {
694 int ret;
695 u32 mode;
696
697 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
698
699 /* Latch the input to the PLL */
700 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
701 PLL_UPDATE);
702
703 /* Wait for 2 reference cycle before checking ACK bit */
704 udelay(1);
705
706 /*
707 * PLL will latch the new L, Alpha and freq control word.
708 * PLL will respond by raising PLL_ACK_LATCH output when new programming
709 * has been latched in and PLL is being updated. When
710 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
711 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
712 */
713 if (mode & PLL_UPDATE_BYPASS) {
714 ret = wait_for_pll_update_ack_set(pll);
715 if (ret)
716 return ret;
717
718 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
719 } else {
720 ret = wait_for_pll_update(pll);
721 if (ret)
722 return ret;
723 }
724
725 ret = wait_for_pll_update_ack_clear(pll);
726 if (ret)
727 return ret;
728
729 /* Wait for PLL output to stabilize */
730 udelay(10);
731
732 return 0;
733 }
734
clk_alpha_pll_update_latch(struct clk_alpha_pll * pll,int (* is_enabled)(struct clk_hw *))735 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
736 int (*is_enabled)(struct clk_hw *))
737 {
738 if (!is_enabled(&pll->clkr.hw) ||
739 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
740 return 0;
741
742 return __clk_alpha_pll_update_latch(pll);
743 }
744
__clk_alpha_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate,int (* is_enabled)(struct clk_hw *))745 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
746 unsigned long prate,
747 int (*is_enabled)(struct clk_hw *))
748 {
749 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
750 const struct pll_vco *vco;
751 u32 l, alpha_width = pll_alpha_width(pll);
752 u64 a;
753
754 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
755 vco = alpha_pll_find_vco(pll, rate);
756 if (pll->vco_table && !vco) {
757 pr_err("%s: alpha pll not in a valid vco range\n",
758 clk_hw_get_name(hw));
759 return -EINVAL;
760 }
761
762 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
763
764 if (alpha_width > ALPHA_BITWIDTH)
765 a <<= alpha_width - ALPHA_BITWIDTH;
766
767 if (alpha_width > 32)
768 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
769
770 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
771
772 if (vco) {
773 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
774 PLL_VCO_MASK << PLL_VCO_SHIFT,
775 vco->val << PLL_VCO_SHIFT);
776 }
777
778 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
779 PLL_ALPHA_EN, PLL_ALPHA_EN);
780
781 return clk_alpha_pll_update_latch(pll, is_enabled);
782 }
783
clk_alpha_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)784 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
785 unsigned long prate)
786 {
787 return __clk_alpha_pll_set_rate(hw, rate, prate,
788 clk_alpha_pll_is_enabled);
789 }
790
clk_alpha_pll_hwfsm_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)791 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
792 unsigned long prate)
793 {
794 return __clk_alpha_pll_set_rate(hw, rate, prate,
795 clk_alpha_pll_hwfsm_is_enabled);
796 }
797
clk_alpha_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)798 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
799 unsigned long *prate)
800 {
801 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
802 u32 l, alpha_width = pll_alpha_width(pll);
803 u64 a;
804 unsigned long min_freq, max_freq;
805
806 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
807 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
808 return rate;
809
810 min_freq = pll->vco_table[0].min_freq;
811 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
812
813 return clamp(rate, min_freq, max_freq);
814 }
815
clk_huayra_2290_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)816 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
817 const struct alpha_pll_config *config)
818 {
819 u32 val;
820
821 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
822 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
823 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
824 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
825 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
826 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
827 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
828 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
829 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
830
831 /* Set PLL_BYPASSNL */
832 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
833 regmap_read(regmap, PLL_MODE(pll), &val);
834
835 /* Wait 5 us between setting BYPASS and deasserting reset */
836 udelay(5);
837
838 /* Take PLL out from reset state */
839 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
840 regmap_read(regmap, PLL_MODE(pll), &val);
841
842 /* Wait 50us for PLL_LOCK_DET bit to go high */
843 usleep_range(50, 55);
844
845 /* Enable PLL output */
846 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
847 }
848 EXPORT_SYMBOL_GPL(clk_huayra_2290_pll_configure);
849
850 static unsigned long
alpha_huayra_pll_calc_rate(u64 prate,u32 l,u32 a)851 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
852 {
853 /*
854 * a contains 16 bit alpha_val in two’s complement number in the range
855 * of [-0.5, 0.5).
856 */
857 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
858 l -= 1;
859
860 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
861 }
862
863 static unsigned long
alpha_huayra_pll_round_rate(unsigned long rate,unsigned long prate,u32 * l,u32 * a)864 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
865 u32 *l, u32 *a)
866 {
867 u64 remainder;
868 u64 quotient;
869
870 quotient = rate;
871 remainder = do_div(quotient, prate);
872 *l = quotient;
873
874 if (!remainder) {
875 *a = 0;
876 return rate;
877 }
878
879 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
880 remainder = do_div(quotient, prate);
881
882 if (remainder)
883 quotient++;
884
885 /*
886 * alpha_val should be in two’s complement number in the range
887 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
888 * since alpha value will be subtracted in this case.
889 */
890 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
891 *l += 1;
892
893 *a = quotient;
894 return alpha_huayra_pll_calc_rate(prate, *l, *a);
895 }
896
897 static unsigned long
alpha_pll_huayra_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)898 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
899 {
900 u64 rate = parent_rate, tmp;
901 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
902 u32 l, alpha = 0, ctl, alpha_m, alpha_n;
903
904 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
905 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
906
907 if (ctl & PLL_ALPHA_EN) {
908 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
909 /*
910 * Depending upon alpha_mode, it can be treated as M/N value or
911 * as a two’s complement number. When alpha_mode=1,
912 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
913 *
914 * Fout=FIN*(L+(M/N))
915 *
916 * M is a signed number (-128 to 127) and N is unsigned
917 * (0 to 255). M/N has to be within +/-0.5.
918 *
919 * When alpha_mode=0, it is a two’s complement number in the
920 * range [-0.5, 0.5).
921 *
922 * Fout=FIN*(L+(alpha_val)/2^16)
923 *
924 * where alpha_val is two’s complement number.
925 */
926 if (!(ctl & PLL_ALPHA_MODE))
927 return alpha_huayra_pll_calc_rate(rate, l, alpha);
928
929 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
930 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
931
932 rate *= l;
933 tmp = parent_rate;
934 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
935 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
936 tmp *= alpha_m;
937 do_div(tmp, alpha_n);
938 rate -= tmp;
939 } else {
940 tmp *= alpha_m;
941 do_div(tmp, alpha_n);
942 rate += tmp;
943 }
944
945 return rate;
946 }
947
948 return alpha_huayra_pll_calc_rate(rate, l, alpha);
949 }
950
alpha_pll_huayra_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)951 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
952 unsigned long prate)
953 {
954 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
955 u32 l, a, ctl, cur_alpha = 0;
956
957 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
958
959 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
960
961 if (ctl & PLL_ALPHA_EN)
962 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
963
964 /*
965 * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
966 * without having to go through the power on sequence.
967 */
968 if (clk_alpha_pll_is_enabled(hw)) {
969 if (cur_alpha != a) {
970 pr_err("%s: clock needs to be gated\n",
971 clk_hw_get_name(hw));
972 return -EBUSY;
973 }
974
975 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
976 /* Ensure that the write above goes to detect L val change. */
977 mb();
978 return wait_for_pll_enable_lock(pll);
979 }
980
981 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
982 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
983
984 if (a == 0)
985 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
986 PLL_ALPHA_EN, 0x0);
987 else
988 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
989 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
990
991 return 0;
992 }
993
alpha_pll_huayra_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)994 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
995 unsigned long *prate)
996 {
997 u32 l, a;
998
999 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
1000 }
1001
trion_pll_is_enabled(struct clk_alpha_pll * pll,struct regmap * regmap)1002 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
1003 struct regmap *regmap)
1004 {
1005 u32 mode_val, opmode_val;
1006 int ret;
1007
1008 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
1009 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1010 if (ret)
1011 return 0;
1012
1013 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
1014 }
1015
clk_trion_pll_is_enabled(struct clk_hw * hw)1016 static int clk_trion_pll_is_enabled(struct clk_hw *hw)
1017 {
1018 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1019
1020 return trion_pll_is_enabled(pll, pll->clkr.regmap);
1021 }
1022
clk_trion_pll_enable(struct clk_hw * hw)1023 static int clk_trion_pll_enable(struct clk_hw *hw)
1024 {
1025 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1026 struct regmap *regmap = pll->clkr.regmap;
1027 u32 val;
1028 int ret;
1029
1030 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1031 if (ret)
1032 return ret;
1033
1034 /* If in FSM mode, just vote for it */
1035 if (val & PLL_VOTE_FSM_ENA) {
1036 ret = clk_enable_regmap(hw);
1037 if (ret)
1038 return ret;
1039 return wait_for_pll_enable_active(pll);
1040 }
1041
1042 /* Set operation mode to RUN */
1043 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1044
1045 ret = wait_for_pll_enable_lock(pll);
1046 if (ret)
1047 return ret;
1048
1049 /* Enable the PLL outputs */
1050 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1051 PLL_OUT_MASK, PLL_OUT_MASK);
1052 if (ret)
1053 return ret;
1054
1055 /* Enable the global PLL outputs */
1056 return regmap_update_bits(regmap, PLL_MODE(pll),
1057 PLL_OUTCTRL, PLL_OUTCTRL);
1058 }
1059
clk_trion_pll_disable(struct clk_hw * hw)1060 static void clk_trion_pll_disable(struct clk_hw *hw)
1061 {
1062 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1063 struct regmap *regmap = pll->clkr.regmap;
1064 u32 val;
1065 int ret;
1066
1067 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1068 if (ret)
1069 return;
1070
1071 /* If in FSM mode, just unvote it */
1072 if (val & PLL_VOTE_FSM_ENA) {
1073 clk_disable_regmap(hw);
1074 return;
1075 }
1076
1077 /* Disable the global PLL output */
1078 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1079 if (ret)
1080 return;
1081
1082 /* Disable the PLL outputs */
1083 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1084 PLL_OUT_MASK, 0);
1085 if (ret)
1086 return;
1087
1088 /* Place the PLL mode in STANDBY */
1089 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1090 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1091 }
1092
1093 static unsigned long
clk_trion_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1094 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1095 {
1096 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1097 u32 l, frac, alpha_width = pll_alpha_width(pll);
1098
1099 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1100 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
1101
1102 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1103 }
1104
1105 const struct clk_ops clk_alpha_pll_fixed_ops = {
1106 .enable = clk_alpha_pll_enable,
1107 .disable = clk_alpha_pll_disable,
1108 .is_enabled = clk_alpha_pll_is_enabled,
1109 .recalc_rate = clk_alpha_pll_recalc_rate,
1110 };
1111 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
1112
1113 const struct clk_ops clk_alpha_pll_ops = {
1114 .enable = clk_alpha_pll_enable,
1115 .disable = clk_alpha_pll_disable,
1116 .is_enabled = clk_alpha_pll_is_enabled,
1117 .recalc_rate = clk_alpha_pll_recalc_rate,
1118 .round_rate = clk_alpha_pll_round_rate,
1119 .set_rate = clk_alpha_pll_set_rate,
1120 };
1121 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
1122
1123 const struct clk_ops clk_alpha_pll_huayra_ops = {
1124 .enable = clk_alpha_pll_enable,
1125 .disable = clk_alpha_pll_disable,
1126 .is_enabled = clk_alpha_pll_is_enabled,
1127 .recalc_rate = alpha_pll_huayra_recalc_rate,
1128 .round_rate = alpha_pll_huayra_round_rate,
1129 .set_rate = alpha_pll_huayra_set_rate,
1130 };
1131 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
1132
1133 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
1134 .enable = clk_alpha_pll_hwfsm_enable,
1135 .disable = clk_alpha_pll_hwfsm_disable,
1136 .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
1137 .recalc_rate = clk_alpha_pll_recalc_rate,
1138 .round_rate = clk_alpha_pll_round_rate,
1139 .set_rate = clk_alpha_pll_hwfsm_set_rate,
1140 };
1141 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
1142
1143 const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
1144 .enable = clk_trion_pll_enable,
1145 .disable = clk_trion_pll_disable,
1146 .is_enabled = clk_trion_pll_is_enabled,
1147 .recalc_rate = clk_trion_pll_recalc_rate,
1148 .round_rate = clk_alpha_pll_round_rate,
1149 };
1150 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
1151
1152 static unsigned long
clk_alpha_pll_postdiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1153 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1154 {
1155 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1156 u32 ctl;
1157
1158 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1159
1160 ctl >>= PLL_POST_DIV_SHIFT;
1161 ctl &= PLL_POST_DIV_MASK(pll);
1162
1163 return parent_rate >> fls(ctl);
1164 }
1165
1166 static const struct clk_div_table clk_alpha_div_table[] = {
1167 { 0x0, 1 },
1168 { 0x1, 2 },
1169 { 0x3, 4 },
1170 { 0x7, 8 },
1171 { 0xf, 16 },
1172 { }
1173 };
1174
1175 static const struct clk_div_table clk_alpha_2bit_div_table[] = {
1176 { 0x0, 1 },
1177 { 0x1, 2 },
1178 { 0x3, 4 },
1179 { }
1180 };
1181
1182 static long
clk_alpha_pll_postdiv_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1183 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1184 unsigned long *prate)
1185 {
1186 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1187 const struct clk_div_table *table;
1188
1189 if (pll->width == 2)
1190 table = clk_alpha_2bit_div_table;
1191 else
1192 table = clk_alpha_div_table;
1193
1194 return divider_round_rate(hw, rate, prate, table,
1195 pll->width, CLK_DIVIDER_POWER_OF_TWO);
1196 }
1197
1198 static long
clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1199 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
1200 unsigned long *prate)
1201 {
1202 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1203 u32 ctl, div;
1204
1205 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1206
1207 ctl >>= PLL_POST_DIV_SHIFT;
1208 ctl &= BIT(pll->width) - 1;
1209 div = 1 << fls(ctl);
1210
1211 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
1212 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
1213
1214 return DIV_ROUND_UP_ULL((u64)*prate, div);
1215 }
1216
clk_alpha_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1217 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1218 unsigned long parent_rate)
1219 {
1220 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1221 int div;
1222
1223 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
1224 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
1225
1226 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1227 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1228 div << PLL_POST_DIV_SHIFT);
1229 }
1230
1231 const struct clk_ops clk_alpha_pll_postdiv_ops = {
1232 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1233 .round_rate = clk_alpha_pll_postdiv_round_rate,
1234 .set_rate = clk_alpha_pll_postdiv_set_rate,
1235 };
1236 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
1237
1238 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
1239 .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
1240 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1241 };
1242 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
1243
clk_fabia_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1244 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1245 const struct alpha_pll_config *config)
1246 {
1247 u32 val, mask;
1248
1249 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1250 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha);
1251 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1252 config->config_ctl_val);
1253 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1254 config->config_ctl_hi_val);
1255 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1256 config->user_ctl_val);
1257 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1258 config->user_ctl_hi_val);
1259 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1260 config->test_ctl_val);
1261 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1262 config->test_ctl_hi_val);
1263
1264 if (config->post_div_mask) {
1265 mask = config->post_div_mask;
1266 val = config->post_div_val;
1267 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1268 }
1269
1270 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
1271 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
1272 PLL_FSM_LEGACY_MODE);
1273
1274 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1275 PLL_UPDATE_BYPASS);
1276
1277 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1278 }
1279 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
1280
alpha_pll_fabia_enable(struct clk_hw * hw)1281 static int alpha_pll_fabia_enable(struct clk_hw *hw)
1282 {
1283 int ret;
1284 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1285 u32 val, opmode_val;
1286 struct regmap *regmap = pll->clkr.regmap;
1287
1288 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1289 if (ret)
1290 return ret;
1291
1292 /* If in FSM mode, just vote for it */
1293 if (val & PLL_VOTE_FSM_ENA) {
1294 ret = clk_enable_regmap(hw);
1295 if (ret)
1296 return ret;
1297 return wait_for_pll_enable_active(pll);
1298 }
1299
1300 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1301 if (ret)
1302 return ret;
1303
1304 /* Skip If PLL is already running */
1305 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
1306 return 0;
1307
1308 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1309 if (ret)
1310 return ret;
1311
1312 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1313 if (ret)
1314 return ret;
1315
1316 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1317 PLL_RESET_N);
1318 if (ret)
1319 return ret;
1320
1321 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1322 if (ret)
1323 return ret;
1324
1325 ret = wait_for_pll_enable_lock(pll);
1326 if (ret)
1327 return ret;
1328
1329 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1330 PLL_OUT_MASK, PLL_OUT_MASK);
1331 if (ret)
1332 return ret;
1333
1334 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1335 PLL_OUTCTRL);
1336 }
1337
alpha_pll_fabia_disable(struct clk_hw * hw)1338 static void alpha_pll_fabia_disable(struct clk_hw *hw)
1339 {
1340 int ret;
1341 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1342 u32 val;
1343 struct regmap *regmap = pll->clkr.regmap;
1344
1345 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1346 if (ret)
1347 return;
1348
1349 /* If in FSM mode, just unvote it */
1350 if (val & PLL_FSM_ENA) {
1351 clk_disable_regmap(hw);
1352 return;
1353 }
1354
1355 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1356 if (ret)
1357 return;
1358
1359 /* Disable main outputs */
1360 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1361 if (ret)
1362 return;
1363
1364 /* Place the PLL in STANDBY */
1365 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1366 }
1367
alpha_pll_fabia_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1368 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
1369 unsigned long parent_rate)
1370 {
1371 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1372 u32 l, frac, alpha_width = pll_alpha_width(pll);
1373
1374 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1375 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1376
1377 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1378 }
1379
1380 /*
1381 * Due to limited number of bits for fractional rate programming, the
1382 * rounded up rate could be marginally higher than the requested rate.
1383 */
alpha_pll_check_rate_margin(struct clk_hw * hw,unsigned long rrate,unsigned long rate)1384 static int alpha_pll_check_rate_margin(struct clk_hw *hw,
1385 unsigned long rrate, unsigned long rate)
1386 {
1387 unsigned long rate_margin = rate + PLL_RATE_MARGIN;
1388
1389 if (rrate > rate_margin || rrate < rate) {
1390 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1391 clk_hw_get_name(hw), rrate, rate, rate_margin);
1392 return -EINVAL;
1393 }
1394
1395 return 0;
1396 }
1397
alpha_pll_fabia_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1398 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1399 unsigned long prate)
1400 {
1401 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1402 u32 l, alpha_width = pll_alpha_width(pll);
1403 unsigned long rrate;
1404 int ret;
1405 u64 a;
1406
1407 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1408
1409 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1410 if (ret < 0)
1411 return ret;
1412
1413 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1414 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1415
1416 return __clk_alpha_pll_update_latch(pll);
1417 }
1418
alpha_pll_fabia_prepare(struct clk_hw * hw)1419 static int alpha_pll_fabia_prepare(struct clk_hw *hw)
1420 {
1421 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1422 const struct pll_vco *vco;
1423 struct clk_hw *parent_hw;
1424 unsigned long cal_freq, rrate;
1425 u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1426 const char *name = clk_hw_get_name(hw);
1427 u64 a;
1428 int ret;
1429
1430 /* Check if calibration needs to be done i.e. PLL is in reset */
1431 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1432 if (ret)
1433 return ret;
1434
1435 /* Return early if calibration is not needed. */
1436 if (val & PLL_RESET_N)
1437 return 0;
1438
1439 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
1440 if (!vco) {
1441 pr_err("%s: alpha pll not in a valid vco range\n", name);
1442 return -EINVAL;
1443 }
1444
1445 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1446 pll->vco_table[0].max_freq) * 54, 100);
1447
1448 parent_hw = clk_hw_get_parent(hw);
1449 if (!parent_hw)
1450 return -EINVAL;
1451
1452 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw),
1453 &cal_l, &a, alpha_width);
1454
1455 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq);
1456 if (ret < 0)
1457 return ret;
1458
1459 /* Setup PLL for calibration frequency */
1460 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
1461
1462 /* Bringup the PLL at calibration frequency */
1463 ret = clk_alpha_pll_enable(hw);
1464 if (ret) {
1465 pr_err("%s: alpha pll calibration failed\n", name);
1466 return ret;
1467 }
1468
1469 clk_alpha_pll_disable(hw);
1470
1471 return 0;
1472 }
1473
1474 const struct clk_ops clk_alpha_pll_fabia_ops = {
1475 .prepare = alpha_pll_fabia_prepare,
1476 .enable = alpha_pll_fabia_enable,
1477 .disable = alpha_pll_fabia_disable,
1478 .is_enabled = clk_alpha_pll_is_enabled,
1479 .set_rate = alpha_pll_fabia_set_rate,
1480 .recalc_rate = alpha_pll_fabia_recalc_rate,
1481 .round_rate = clk_alpha_pll_round_rate,
1482 };
1483 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1484
1485 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1486 .enable = alpha_pll_fabia_enable,
1487 .disable = alpha_pll_fabia_disable,
1488 .is_enabled = clk_alpha_pll_is_enabled,
1489 .recalc_rate = alpha_pll_fabia_recalc_rate,
1490 .round_rate = clk_alpha_pll_round_rate,
1491 };
1492 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1493
clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1494 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1495 unsigned long parent_rate)
1496 {
1497 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1498 u32 i, div = 1, val;
1499 int ret;
1500
1501 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1502 if (ret)
1503 return ret;
1504
1505 val >>= pll->post_div_shift;
1506 val &= BIT(pll->width) - 1;
1507
1508 for (i = 0; i < pll->num_post_div; i++) {
1509 if (pll->post_div_table[i].val == val) {
1510 div = pll->post_div_table[i].div;
1511 break;
1512 }
1513 }
1514
1515 return (parent_rate / div);
1516 }
1517
1518 static unsigned long
clk_trion_pll_postdiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1519 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1520 {
1521 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1522 struct regmap *regmap = pll->clkr.regmap;
1523 u32 i, div = 1, val;
1524
1525 regmap_read(regmap, PLL_USER_CTL(pll), &val);
1526
1527 val >>= pll->post_div_shift;
1528 val &= PLL_POST_DIV_MASK(pll);
1529
1530 for (i = 0; i < pll->num_post_div; i++) {
1531 if (pll->post_div_table[i].val == val) {
1532 div = pll->post_div_table[i].div;
1533 break;
1534 }
1535 }
1536
1537 return (parent_rate / div);
1538 }
1539
1540 static long
clk_trion_pll_postdiv_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1541 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1542 unsigned long *prate)
1543 {
1544 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1545
1546 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1547 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1548 };
1549
1550 static int
clk_trion_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1551 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1552 unsigned long parent_rate)
1553 {
1554 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1555 struct regmap *regmap = pll->clkr.regmap;
1556 int i, val = 0, div;
1557
1558 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1559 for (i = 0; i < pll->num_post_div; i++) {
1560 if (pll->post_div_table[i].div == div) {
1561 val = pll->post_div_table[i].val;
1562 break;
1563 }
1564 }
1565
1566 return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1567 PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
1568 val << pll->post_div_shift);
1569 }
1570
1571 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
1572 .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1573 .round_rate = clk_trion_pll_postdiv_round_rate,
1574 .set_rate = clk_trion_pll_postdiv_set_rate,
1575 };
1576 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
1577
clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1578 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1579 unsigned long rate, unsigned long *prate)
1580 {
1581 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1582
1583 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1584 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1585 }
1586
clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1587 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1588 unsigned long rate, unsigned long parent_rate)
1589 {
1590 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1591 int i, val = 0, div, ret;
1592
1593 /*
1594 * If the PLL is in FSM mode, then treat set_rate callback as a
1595 * no-operation.
1596 */
1597 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1598 if (ret)
1599 return ret;
1600
1601 if (val & PLL_VOTE_FSM_ENA)
1602 return 0;
1603
1604 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1605 for (i = 0; i < pll->num_post_div; i++) {
1606 if (pll->post_div_table[i].div == div) {
1607 val = pll->post_div_table[i].val;
1608 break;
1609 }
1610 }
1611
1612 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1613 (BIT(pll->width) - 1) << pll->post_div_shift,
1614 val << pll->post_div_shift);
1615 }
1616
1617 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1618 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1619 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1620 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1621 };
1622 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1623
1624 /**
1625 * clk_trion_pll_configure - configure the trion pll
1626 *
1627 * @pll: clk alpha pll
1628 * @regmap: register map
1629 * @config: configuration to apply for pll
1630 */
clk_trion_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1631 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1632 const struct alpha_pll_config *config)
1633 {
1634 /*
1635 * If the bootloader left the PLL enabled it's likely that there are
1636 * RCGs that will lock up if we disable the PLL below.
1637 */
1638 if (trion_pll_is_enabled(pll, regmap)) {
1639 pr_debug("Trion PLL is already enabled, skipping configuration\n");
1640 return;
1641 }
1642
1643 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1644 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1645 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1646 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1647 config->config_ctl_val);
1648 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1649 config->config_ctl_hi_val);
1650 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1651 config->config_ctl_hi1_val);
1652 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1653 config->user_ctl_val);
1654 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1655 config->user_ctl_hi_val);
1656 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1657 config->user_ctl_hi1_val);
1658 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1659 config->test_ctl_val);
1660 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1661 config->test_ctl_hi_val);
1662 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1663 config->test_ctl_hi1_val);
1664
1665 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1666 PLL_UPDATE_BYPASS);
1667
1668 /* Disable PLL output */
1669 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1670
1671 /* Set operation mode to OFF */
1672 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1673
1674 /* Place the PLL in STANDBY mode */
1675 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1676 }
1677 EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
1678
1679 /*
1680 * The TRION PLL requires a power-on self-calibration which happens when the
1681 * PLL comes out of reset. Calibrate in case it is not completed.
1682 */
__alpha_pll_trion_prepare(struct clk_hw * hw,u32 pcal_done)1683 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
1684 {
1685 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1686 u32 val;
1687 int ret;
1688
1689 /* Return early if calibration is not needed. */
1690 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
1691 if (val & pcal_done)
1692 return 0;
1693
1694 /* On/off to calibrate */
1695 ret = clk_trion_pll_enable(hw);
1696 if (!ret)
1697 clk_trion_pll_disable(hw);
1698
1699 return ret;
1700 }
1701
alpha_pll_trion_prepare(struct clk_hw * hw)1702 static int alpha_pll_trion_prepare(struct clk_hw *hw)
1703 {
1704 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
1705 }
1706
alpha_pll_lucid_prepare(struct clk_hw * hw)1707 static int alpha_pll_lucid_prepare(struct clk_hw *hw)
1708 {
1709 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
1710 }
1711
__alpha_pll_trion_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate,u32 latch_bit,u32 latch_ack)1712 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1713 unsigned long prate, u32 latch_bit, u32 latch_ack)
1714 {
1715 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1716 unsigned long rrate;
1717 u32 val, l, alpha_width = pll_alpha_width(pll);
1718 u64 a;
1719 int ret;
1720
1721 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1722
1723 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1724 if (ret < 0)
1725 return ret;
1726
1727 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l);
1728 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1729
1730 /* Latch the PLL input */
1731 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
1732 if (ret)
1733 return ret;
1734
1735 /* Wait for 2 reference cycles before checking the ACK bit. */
1736 udelay(1);
1737 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1738 if (!(val & latch_ack)) {
1739 pr_err("Lucid PLL latch failed. Output may be unstable!\n");
1740 return -EINVAL;
1741 }
1742
1743 /* Return the latch input to 0 */
1744 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
1745 if (ret)
1746 return ret;
1747
1748 if (clk_hw_is_enabled(hw)) {
1749 ret = wait_for_pll_enable_lock(pll);
1750 if (ret)
1751 return ret;
1752 }
1753
1754 /* Wait for PLL output to stabilize */
1755 udelay(100);
1756 return 0;
1757 }
1758
alpha_pll_trion_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1759 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1760 unsigned long prate)
1761 {
1762 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
1763 }
1764
1765 const struct clk_ops clk_alpha_pll_trion_ops = {
1766 .prepare = alpha_pll_trion_prepare,
1767 .enable = clk_trion_pll_enable,
1768 .disable = clk_trion_pll_disable,
1769 .is_enabled = clk_trion_pll_is_enabled,
1770 .recalc_rate = clk_trion_pll_recalc_rate,
1771 .round_rate = clk_alpha_pll_round_rate,
1772 .set_rate = alpha_pll_trion_set_rate,
1773 };
1774 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
1775
1776 const struct clk_ops clk_alpha_pll_lucid_ops = {
1777 .prepare = alpha_pll_lucid_prepare,
1778 .enable = clk_trion_pll_enable,
1779 .disable = clk_trion_pll_disable,
1780 .is_enabled = clk_trion_pll_is_enabled,
1781 .recalc_rate = clk_trion_pll_recalc_rate,
1782 .round_rate = clk_alpha_pll_round_rate,
1783 .set_rate = alpha_pll_trion_set_rate,
1784 };
1785 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
1786
1787 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
1788 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1789 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1790 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1791 };
1792 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
1793
clk_agera_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1794 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1795 const struct alpha_pll_config *config)
1796 {
1797 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1798 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1799 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1800 config->user_ctl_val);
1801 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1802 config->config_ctl_val);
1803 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1804 config->config_ctl_hi_val);
1805 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1806 config->test_ctl_val);
1807 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1808 config->test_ctl_hi_val);
1809 }
1810 EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
1811
clk_alpha_pll_agera_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1812 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
1813 unsigned long prate)
1814 {
1815 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1816 u32 l, alpha_width = pll_alpha_width(pll);
1817 int ret;
1818 unsigned long rrate;
1819 u64 a;
1820
1821 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1822 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1823 if (ret < 0)
1824 return ret;
1825
1826 /* change L_VAL without having to go through the power on sequence */
1827 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1828 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1829
1830 if (clk_hw_is_enabled(hw))
1831 return wait_for_pll_enable_lock(pll);
1832
1833 return 0;
1834 }
1835
1836 const struct clk_ops clk_alpha_pll_agera_ops = {
1837 .enable = clk_alpha_pll_enable,
1838 .disable = clk_alpha_pll_disable,
1839 .is_enabled = clk_alpha_pll_is_enabled,
1840 .recalc_rate = alpha_pll_fabia_recalc_rate,
1841 .round_rate = clk_alpha_pll_round_rate,
1842 .set_rate = clk_alpha_pll_agera_set_rate,
1843 };
1844 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
1845
1846 /**
1847 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll
1848 *
1849 * @pll: clk alpha pll
1850 * @regmap: register map
1851 * @config: configuration to apply for pll
1852 */
clk_lucid_5lpe_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1853 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1854 const struct alpha_pll_config *config)
1855 {
1856 /*
1857 * If the bootloader left the PLL enabled it's likely that there are
1858 * RCGs that will lock up if we disable the PLL below.
1859 */
1860 if (trion_pll_is_enabled(pll, regmap)) {
1861 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n");
1862 return;
1863 }
1864
1865 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1866 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1867 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1868 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1869 config->config_ctl_val);
1870 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1871 config->config_ctl_hi_val);
1872 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1873 config->config_ctl_hi1_val);
1874 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1875 config->user_ctl_val);
1876 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1877 config->user_ctl_hi_val);
1878 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1879 config->user_ctl_hi1_val);
1880 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1881 config->test_ctl_val);
1882 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1883 config->test_ctl_hi_val);
1884 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1885 config->test_ctl_hi1_val);
1886
1887 /* Disable PLL output */
1888 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1889
1890 /* Set operation mode to OFF */
1891 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1892
1893 /* Place the PLL in STANDBY mode */
1894 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1895 }
1896 EXPORT_SYMBOL_GPL(clk_lucid_5lpe_pll_configure);
1897
alpha_pll_lucid_5lpe_enable(struct clk_hw * hw)1898 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
1899 {
1900 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1901 u32 val;
1902 int ret;
1903
1904 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1905 if (ret)
1906 return ret;
1907
1908 /* If in FSM mode, just vote for it */
1909 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1910 ret = clk_enable_regmap(hw);
1911 if (ret)
1912 return ret;
1913 return wait_for_pll_enable_lock(pll);
1914 }
1915
1916 /* Check if PLL is already enabled, return if enabled */
1917 if (trion_pll_is_enabled(pll, pll->clkr.regmap))
1918 return 0;
1919
1920 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1921 if (ret)
1922 return ret;
1923
1924 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
1925
1926 ret = wait_for_pll_enable_lock(pll);
1927 if (ret)
1928 return ret;
1929
1930 /* Enable the PLL outputs */
1931 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
1932 if (ret)
1933 return ret;
1934
1935 /* Enable the global PLL outputs */
1936 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1937 }
1938
alpha_pll_lucid_5lpe_disable(struct clk_hw * hw)1939 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
1940 {
1941 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1942 u32 val;
1943 int ret;
1944
1945 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1946 if (ret)
1947 return;
1948
1949 /* If in FSM mode, just unvote it */
1950 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1951 clk_disable_regmap(hw);
1952 return;
1953 }
1954
1955 /* Disable the global PLL output */
1956 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1957 if (ret)
1958 return;
1959
1960 /* Disable the PLL outputs */
1961 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1962 if (ret)
1963 return;
1964
1965 /* Place the PLL mode in STANDBY */
1966 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
1967 }
1968
1969 /*
1970 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1971 * when the PLL comes out of reset. Calibrate in case it is not completed.
1972 */
alpha_pll_lucid_5lpe_prepare(struct clk_hw * hw)1973 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
1974 {
1975 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1976 struct clk_hw *p;
1977 u32 val = 0;
1978 int ret;
1979
1980 /* Return early if calibration is not needed. */
1981 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1982 if (val & LUCID_5LPE_PCAL_DONE)
1983 return 0;
1984
1985 p = clk_hw_get_parent(hw);
1986 if (!p)
1987 return -EINVAL;
1988
1989 ret = alpha_pll_lucid_5lpe_enable(hw);
1990 if (ret)
1991 return ret;
1992
1993 alpha_pll_lucid_5lpe_disable(hw);
1994
1995 return 0;
1996 }
1997
alpha_pll_lucid_5lpe_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1998 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
1999 unsigned long prate)
2000 {
2001 return __alpha_pll_trion_set_rate(hw, rate, prate,
2002 LUCID_5LPE_PLL_LATCH_INPUT,
2003 LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
2004 }
2005
__clk_lucid_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate,unsigned long enable_vote_run)2006 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2007 unsigned long parent_rate,
2008 unsigned long enable_vote_run)
2009 {
2010 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
2011 struct regmap *regmap = pll->clkr.regmap;
2012 int i, val, div, ret;
2013 u32 mask;
2014
2015 /*
2016 * If the PLL is in FSM mode, then treat set_rate callback as a
2017 * no-operation.
2018 */
2019 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2020 if (ret)
2021 return ret;
2022
2023 if (val & enable_vote_run)
2024 return 0;
2025
2026 if (!pll->post_div_table) {
2027 pr_err("Missing the post_div_table for the %s PLL\n",
2028 clk_hw_get_name(&pll->clkr.hw));
2029 return -EINVAL;
2030 }
2031
2032 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
2033 for (i = 0; i < pll->num_post_div; i++) {
2034 if (pll->post_div_table[i].div == div) {
2035 val = pll->post_div_table[i].val;
2036 break;
2037 }
2038 }
2039
2040 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
2041 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2042 mask, val << pll->post_div_shift);
2043 }
2044
clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2045 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2046 unsigned long parent_rate)
2047 {
2048 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
2049 }
2050
2051 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
2052 .prepare = alpha_pll_lucid_5lpe_prepare,
2053 .enable = alpha_pll_lucid_5lpe_enable,
2054 .disable = alpha_pll_lucid_5lpe_disable,
2055 .is_enabled = clk_trion_pll_is_enabled,
2056 .recalc_rate = clk_trion_pll_recalc_rate,
2057 .round_rate = clk_alpha_pll_round_rate,
2058 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2059 };
2060 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
2061
2062 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
2063 .enable = alpha_pll_lucid_5lpe_enable,
2064 .disable = alpha_pll_lucid_5lpe_disable,
2065 .is_enabled = clk_trion_pll_is_enabled,
2066 .recalc_rate = clk_trion_pll_recalc_rate,
2067 .round_rate = clk_alpha_pll_round_rate,
2068 };
2069 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
2070
2071 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
2072 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2073 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2074 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
2075 };
2076 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
2077
clk_zonda_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2078 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2079 const struct alpha_pll_config *config)
2080 {
2081 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2082 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2083 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2084 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2085 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2086 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2087 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2088 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
2089 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2090 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2091 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2092
2093 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
2094
2095 /* Disable PLL output */
2096 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2097
2098 /* Set operation mode to OFF */
2099 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2100
2101 /* Place the PLL in STANDBY mode */
2102 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2103 }
2104 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);
2105
clk_zonda_pll_enable(struct clk_hw * hw)2106 static int clk_zonda_pll_enable(struct clk_hw *hw)
2107 {
2108 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2109 struct regmap *regmap = pll->clkr.regmap;
2110 u32 val;
2111 int ret;
2112
2113 regmap_read(regmap, PLL_MODE(pll), &val);
2114
2115 /* If in FSM mode, just vote for it */
2116 if (val & PLL_VOTE_FSM_ENA) {
2117 ret = clk_enable_regmap(hw);
2118 if (ret)
2119 return ret;
2120 return wait_for_pll_enable_active(pll);
2121 }
2122
2123 /* Get the PLL out of bypass mode */
2124 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
2125
2126 /*
2127 * H/W requires a 1us delay between disabling the bypass and
2128 * de-asserting the reset.
2129 */
2130 udelay(1);
2131
2132 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2133
2134 /* Set operation mode to RUN */
2135 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2136
2137 regmap_read(regmap, PLL_TEST_CTL(pll), &val);
2138
2139 /* If cfa mode then poll for freq lock */
2140 if (val & ZONDA_STAY_IN_CFA)
2141 ret = wait_for_zonda_pll_freq_lock(pll);
2142 else
2143 ret = wait_for_pll_enable_lock(pll);
2144 if (ret)
2145 return ret;
2146
2147 /* Enable the PLL outputs */
2148 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
2149
2150 /* Enable the global PLL outputs */
2151 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2152
2153 return 0;
2154 }
2155
clk_zonda_pll_disable(struct clk_hw * hw)2156 static void clk_zonda_pll_disable(struct clk_hw *hw)
2157 {
2158 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2159 struct regmap *regmap = pll->clkr.regmap;
2160 u32 val;
2161
2162 regmap_read(regmap, PLL_MODE(pll), &val);
2163
2164 /* If in FSM mode, just unvote it */
2165 if (val & PLL_VOTE_FSM_ENA) {
2166 clk_disable_regmap(hw);
2167 return;
2168 }
2169
2170 /* Disable the global PLL output */
2171 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2172
2173 /* Disable the PLL outputs */
2174 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
2175
2176 /* Put the PLL in bypass and reset */
2177 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
2178
2179 /* Place the PLL mode in OFF state */
2180 regmap_write(regmap, PLL_OPMODE(pll), 0x0);
2181 }
2182
zonda_pll_adjust_l_val(unsigned long rate,unsigned long prate,u32 * l)2183 static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l)
2184 {
2185 u64 remainder, quotient;
2186
2187 quotient = rate;
2188 remainder = do_div(quotient, prate);
2189
2190 *l = rate + (u32)(remainder * 2 >= prate);
2191 }
2192
clk_zonda_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2193 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
2194 unsigned long prate)
2195 {
2196 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2197 unsigned long rrate;
2198 u32 test_ctl_val;
2199 u32 l, alpha_width = pll_alpha_width(pll);
2200 u64 a;
2201 int ret;
2202
2203 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2204
2205 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
2206 if (ret < 0)
2207 return ret;
2208
2209 if (a & PLL_ALPHA_MSB)
2210 zonda_pll_adjust_l_val(rate, prate, &l);
2211
2212 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2213 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2214
2215 if (!clk_hw_is_enabled(hw))
2216 return 0;
2217
2218 /* Wait before polling for the frequency latch */
2219 udelay(5);
2220
2221 /* Read stay in cfa mode */
2222 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
2223
2224 /* If cfa mode then poll for freq lock */
2225 if (test_ctl_val & ZONDA_STAY_IN_CFA)
2226 ret = wait_for_zonda_pll_freq_lock(pll);
2227 else
2228 ret = wait_for_pll_enable_lock(pll);
2229 if (ret)
2230 return ret;
2231
2232 /* Wait for PLL output to stabilize */
2233 udelay(100);
2234 return 0;
2235 }
2236
2237 const struct clk_ops clk_alpha_pll_zonda_ops = {
2238 .enable = clk_zonda_pll_enable,
2239 .disable = clk_zonda_pll_disable,
2240 .is_enabled = clk_trion_pll_is_enabled,
2241 .recalc_rate = clk_trion_pll_recalc_rate,
2242 .round_rate = clk_alpha_pll_round_rate,
2243 .set_rate = clk_zonda_pll_set_rate,
2244 };
2245 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
2246
clk_lucid_evo_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2247 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2248 const struct alpha_pll_config *config)
2249 {
2250 u32 lval = config->l;
2251
2252 /*
2253 * If the bootloader left the PLL enabled it's likely that there are
2254 * RCGs that will lock up if we disable the PLL below.
2255 */
2256 if (trion_pll_is_enabled(pll, regmap)) {
2257 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n");
2258 return;
2259 }
2260
2261 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2262 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2263 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2264 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2265 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2266 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2267 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2268 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2269 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2270 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2271 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2272 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
2273
2274 /* Disable PLL output */
2275 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2276
2277 /* Set operation mode to STANDBY and de-assert the reset */
2278 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2279 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2280 }
2281 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
2282
clk_lucid_ole_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2283 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2284 const struct alpha_pll_config *config)
2285 {
2286 u32 lval = config->l;
2287
2288 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2289 lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT;
2290 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2291 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2292 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2293 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2294 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2295 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2296 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2297 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2298 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2299 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2300 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
2301
2302 /* Disable PLL output */
2303 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2304
2305 /* Set operation mode to STANDBY and de-assert the reset */
2306 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2307 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2308 }
2309 EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure);
2310
alpha_pll_lucid_evo_enable(struct clk_hw * hw)2311 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
2312 {
2313 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2314 struct regmap *regmap = pll->clkr.regmap;
2315 u32 val;
2316 int ret;
2317
2318 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2319 if (ret)
2320 return ret;
2321
2322 /* If in FSM mode, just vote for it */
2323 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2324 ret = clk_enable_regmap(hw);
2325 if (ret)
2326 return ret;
2327 return wait_for_pll_enable_lock(pll);
2328 }
2329
2330 /* Check if PLL is already enabled */
2331 if (trion_pll_is_enabled(pll, regmap))
2332 return 0;
2333
2334 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2335 if (ret)
2336 return ret;
2337
2338 /* Set operation mode to RUN */
2339 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2340
2341 ret = wait_for_pll_enable_lock(pll);
2342 if (ret)
2343 return ret;
2344
2345 /* Enable the PLL outputs */
2346 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
2347 if (ret)
2348 return ret;
2349
2350 /* Enable the global PLL outputs */
2351 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2352 if (ret)
2353 return ret;
2354
2355 /* Ensure that the write above goes through before returning. */
2356 mb();
2357 return ret;
2358 }
2359
_alpha_pll_lucid_evo_disable(struct clk_hw * hw,bool reset)2360 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset)
2361 {
2362 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2363 struct regmap *regmap = pll->clkr.regmap;
2364 u32 val;
2365 int ret;
2366
2367 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2368 if (ret)
2369 return;
2370
2371 /* If in FSM mode, just unvote it */
2372 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2373 clk_disable_regmap(hw);
2374 return;
2375 }
2376
2377 /* Disable the global PLL output */
2378 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2379 if (ret)
2380 return;
2381
2382 /* Disable the PLL outputs */
2383 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2384 if (ret)
2385 return;
2386
2387 /* Place the PLL mode in STANDBY */
2388 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2389
2390 if (reset)
2391 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0);
2392 }
2393
_alpha_pll_lucid_evo_prepare(struct clk_hw * hw,bool reset)2394 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset)
2395 {
2396 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2397 struct clk_hw *p;
2398 u32 val = 0;
2399 int ret;
2400
2401 /* Return early if calibration is not needed. */
2402 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
2403 if (!(val & LUCID_EVO_PCAL_NOT_DONE))
2404 return 0;
2405
2406 p = clk_hw_get_parent(hw);
2407 if (!p)
2408 return -EINVAL;
2409
2410 ret = alpha_pll_lucid_evo_enable(hw);
2411 if (ret)
2412 return ret;
2413
2414 _alpha_pll_lucid_evo_disable(hw, reset);
2415
2416 return 0;
2417 }
2418
alpha_pll_lucid_evo_disable(struct clk_hw * hw)2419 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
2420 {
2421 _alpha_pll_lucid_evo_disable(hw, false);
2422 }
2423
alpha_pll_lucid_evo_prepare(struct clk_hw * hw)2424 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
2425 {
2426 return _alpha_pll_lucid_evo_prepare(hw, false);
2427 }
2428
alpha_pll_reset_lucid_evo_disable(struct clk_hw * hw)2429 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw)
2430 {
2431 _alpha_pll_lucid_evo_disable(hw, true);
2432 }
2433
alpha_pll_reset_lucid_evo_prepare(struct clk_hw * hw)2434 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw)
2435 {
2436 return _alpha_pll_lucid_evo_prepare(hw, true);
2437 }
2438
alpha_pll_lucid_evo_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2439 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
2440 unsigned long parent_rate)
2441 {
2442 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2443 struct regmap *regmap = pll->clkr.regmap;
2444 u32 l, frac;
2445
2446 regmap_read(regmap, PLL_L_VAL(pll), &l);
2447 l &= LUCID_EVO_PLL_L_VAL_MASK;
2448 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
2449
2450 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
2451 }
2452
clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2453 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2454 unsigned long parent_rate)
2455 {
2456 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
2457 }
2458
2459 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
2460 .enable = alpha_pll_lucid_evo_enable,
2461 .disable = alpha_pll_lucid_evo_disable,
2462 .is_enabled = clk_trion_pll_is_enabled,
2463 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2464 .round_rate = clk_alpha_pll_round_rate,
2465 };
2466 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
2467
2468 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
2469 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2470 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2471 .set_rate = clk_lucid_evo_pll_postdiv_set_rate,
2472 };
2473 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
2474
2475 const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
2476 .prepare = alpha_pll_lucid_evo_prepare,
2477 .enable = alpha_pll_lucid_evo_enable,
2478 .disable = alpha_pll_lucid_evo_disable,
2479 .is_enabled = clk_trion_pll_is_enabled,
2480 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2481 .round_rate = clk_alpha_pll_round_rate,
2482 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2483 };
2484 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
2485
2486 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
2487 .prepare = alpha_pll_reset_lucid_evo_prepare,
2488 .enable = alpha_pll_lucid_evo_enable,
2489 .disable = alpha_pll_reset_lucid_evo_disable,
2490 .is_enabled = clk_trion_pll_is_enabled,
2491 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2492 .round_rate = clk_alpha_pll_round_rate,
2493 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2494 };
2495 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
2496
clk_rivian_evo_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2497 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2498 const struct alpha_pll_config *config)
2499 {
2500 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2501 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2502 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2503 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2504 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2505 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2506 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2507 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2508
2509 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2510
2511 regmap_update_bits(regmap, PLL_MODE(pll),
2512 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,
2513 PLL_RESET_N | PLL_BYPASSNL);
2514 }
2515 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);
2516
clk_rivian_evo_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2517 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
2518 unsigned long parent_rate)
2519 {
2520 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2521 u32 l;
2522
2523 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
2524
2525 return parent_rate * l;
2526 }
2527
clk_rivian_evo_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)2528 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2529 unsigned long *prate)
2530 {
2531 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2532 unsigned long min_freq, max_freq;
2533 u32 l;
2534 u64 a;
2535
2536 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
2537 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2538 return rate;
2539
2540 min_freq = pll->vco_table[0].min_freq;
2541 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
2542
2543 return clamp(rate, min_freq, max_freq);
2544 }
2545
2546 const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
2547 .enable = alpha_pll_lucid_5lpe_enable,
2548 .disable = alpha_pll_lucid_5lpe_disable,
2549 .is_enabled = clk_trion_pll_is_enabled,
2550 .recalc_rate = clk_rivian_evo_pll_recalc_rate,
2551 .round_rate = clk_rivian_evo_pll_round_rate,
2552 };
2553 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
2554
clk_stromer_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2555 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2556 const struct alpha_pll_config *config)
2557 {
2558 u32 val, val_u, mask, mask_u;
2559
2560 regmap_write(regmap, PLL_L_VAL(pll), config->l);
2561 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2562 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2563
2564 if (pll_has_64bit_config(pll))
2565 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
2566 config->config_ctl_hi_val);
2567
2568 if (pll_alpha_width(pll) > 32)
2569 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
2570
2571 val = config->main_output_mask;
2572 val |= config->aux_output_mask;
2573 val |= config->aux2_output_mask;
2574 val |= config->early_output_mask;
2575 val |= config->pre_div_val;
2576 val |= config->post_div_val;
2577 val |= config->vco_val;
2578 val |= config->alpha_en_mask;
2579 val |= config->alpha_mode_mask;
2580
2581 mask = config->main_output_mask;
2582 mask |= config->aux_output_mask;
2583 mask |= config->aux2_output_mask;
2584 mask |= config->early_output_mask;
2585 mask |= config->pre_div_mask;
2586 mask |= config->post_div_mask;
2587 mask |= config->vco_mask;
2588 mask |= config->alpha_en_mask;
2589 mask |= config->alpha_mode_mask;
2590
2591 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
2592
2593 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
2594 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT;
2595 val_u |= config->lock_det;
2596
2597 mask_u = config->status_mask;
2598 mask_u |= config->lock_det;
2599
2600 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
2601 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2602 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2603
2604 if (pll->flags & SUPPORTS_FSM_MODE)
2605 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
2606 }
2607 EXPORT_SYMBOL_GPL(clk_stromer_pll_configure);
2608
clk_alpha_pll_stromer_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)2609 static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
2610 struct clk_rate_request *req)
2611 {
2612 u32 l;
2613 u64 a;
2614
2615 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate,
2616 &l, &a, ALPHA_REG_BITWIDTH);
2617
2618 return 0;
2619 }
2620
clk_alpha_pll_stromer_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2621 static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
2622 unsigned long prate)
2623 {
2624 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2625 int ret;
2626 u32 l;
2627 u64 a;
2628
2629 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
2630
2631 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2632
2633 a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
2634 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2635 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2636 a >> ALPHA_BITWIDTH);
2637
2638 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2639 PLL_ALPHA_EN, PLL_ALPHA_EN);
2640
2641 if (!clk_hw_is_enabled(hw))
2642 return 0;
2643
2644 /*
2645 * Stromer PLL supports Dynamic programming.
2646 * It allows the PLL frequency to be changed on-the-fly without first
2647 * execution of a shutdown procedure followed by a bring up procedure.
2648 */
2649 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
2650 PLL_UPDATE);
2651
2652 ret = wait_for_pll_update(pll);
2653 if (ret)
2654 return ret;
2655
2656 return wait_for_pll_enable_lock(pll);
2657 }
2658
2659 const struct clk_ops clk_alpha_pll_stromer_ops = {
2660 .enable = clk_alpha_pll_enable,
2661 .disable = clk_alpha_pll_disable,
2662 .is_enabled = clk_alpha_pll_is_enabled,
2663 .recalc_rate = clk_alpha_pll_recalc_rate,
2664 .determine_rate = clk_alpha_pll_stromer_determine_rate,
2665 .set_rate = clk_alpha_pll_stromer_set_rate,
2666 };
2667 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
2668
clk_alpha_pll_stromer_plus_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2669 static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
2670 unsigned long rate,
2671 unsigned long prate)
2672 {
2673 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2674 u32 l, alpha_width = pll_alpha_width(pll);
2675 int ret, pll_mode;
2676 u64 a;
2677
2678 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2679
2680 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode);
2681 if (ret)
2682 return ret;
2683
2684 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0);
2685
2686 /* Delay of 2 output clock ticks required until output is disabled */
2687 udelay(1);
2688
2689 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2690
2691 if (alpha_width > ALPHA_BITWIDTH)
2692 a <<= alpha_width - ALPHA_BITWIDTH;
2693
2694 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2695 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2696 a >> ALPHA_BITWIDTH);
2697
2698 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2699 PLL_ALPHA_EN, PLL_ALPHA_EN);
2700
2701 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
2702
2703 /* Wait five micro seconds or more */
2704 udelay(5);
2705 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N,
2706 PLL_RESET_N);
2707
2708 /* The lock time should be less than 50 micro seconds worst case */
2709 usleep_range(50, 60);
2710
2711 ret = wait_for_pll_enable_lock(pll);
2712 if (ret) {
2713 pr_err("Wait for PLL enable lock failed [%s] %d\n",
2714 clk_hw_get_name(hw), ret);
2715 return ret;
2716 }
2717
2718 if (pll_mode & PLL_OUTCTRL)
2719 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL,
2720 PLL_OUTCTRL);
2721
2722 return 0;
2723 }
2724
2725 const struct clk_ops clk_alpha_pll_stromer_plus_ops = {
2726 .prepare = clk_alpha_pll_enable,
2727 .unprepare = clk_alpha_pll_disable,
2728 .is_enabled = clk_alpha_pll_is_enabled,
2729 .recalc_rate = clk_alpha_pll_recalc_rate,
2730 .determine_rate = clk_alpha_pll_stromer_determine_rate,
2731 .set_rate = clk_alpha_pll_stromer_plus_set_rate,
2732 };
2733 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);
2734
clk_regera_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2735 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2736 const struct alpha_pll_config *config)
2737 {
2738 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2739 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2740 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2741 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2742 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2743 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2744 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2745 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
2746 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2747 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2748 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2749
2750 /* Set operation mode to STANDBY */
2751 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2752 }
2753 EXPORT_SYMBOL_GPL(clk_regera_pll_configure);
2754
2755 const struct clk_ops clk_alpha_pll_regera_ops = {
2756 .enable = clk_zonda_pll_enable,
2757 .disable = clk_zonda_pll_disable,
2758 .is_enabled = clk_alpha_pll_is_enabled,
2759 .recalc_rate = clk_trion_pll_recalc_rate,
2760 .round_rate = clk_alpha_pll_round_rate,
2761 .set_rate = clk_zonda_pll_set_rate,
2762 };
2763 EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);
2764