1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Marvell PXA25x family clocks
4 *
5 * Copyright (C) 2014 Robert Jarzmik
6 *
7 * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
8 *
9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
10 * should go away.
11 */
12 #include <linux/clk-provider.h>
13 #include <linux/clk.h>
14 #include <linux/clk/pxa.h>
15 #include <linux/clkdev.h>
16 #include <linux/io.h>
17 #include <linux/of.h>
18 #include <linux/soc/pxa/smemc.h>
19 #include <linux/soc/pxa/cpu.h>
20
21 #include <dt-bindings/clock/pxa-clock.h>
22 #include "clk-pxa.h"
23 #include "clk-pxa2xx.h"
24
25 #define KHz 1000
26 #define MHz (1000 * 1000)
27
28 enum {
29 PXA_CORE_RUN = 0,
30 PXA_CORE_TURBO,
31 };
32
33 #define PXA25x_CLKCFG(T) \
34 (CLKCFG_FCS | \
35 ((T) ? CLKCFG_TURBO : 0))
36 #define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L)
37
38 /* Define the refresh period in mSec for the SDRAM and the number of rows */
39 #define SDRAM_TREF 64 /* standard 64ms SDRAM */
40
41 /*
42 * Various clock factors driven by the CCCR register.
43 */
44 static void __iomem *clk_regs;
45
46 /* Crystal Frequency to Memory Frequency Multiplier (L) */
47 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
48
49 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
50 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
51
52 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
53 /* Note: we store the value N * 2 here. */
54 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
55
56 static const char * const get_freq_khz[] = {
57 "core", "run", "cpll", "memory"
58 };
59
mdrefr_dri(unsigned int freq_khz)60 static u32 mdrefr_dri(unsigned int freq_khz)
61 {
62 u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();
63
64 return interval / 32;
65 }
66
67 /*
68 * Get the clock frequency as reflected by CCCR and the turbo flag.
69 * We assume these values have been applied via a fcs.
70 * If info is not 0 we also display the current settings.
71 */
pxa25x_get_clk_frequency_khz(int info)72 unsigned int pxa25x_get_clk_frequency_khz(int info)
73 {
74 struct clk *clk;
75 unsigned long clks[5];
76 int i;
77
78 for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) {
79 clk = clk_get(NULL, get_freq_khz[i]);
80 if (IS_ERR(clk)) {
81 clks[i] = 0;
82 } else {
83 clks[i] = clk_get_rate(clk);
84 clk_put(clk);
85 }
86 }
87
88 if (info) {
89 pr_info("Run Mode clock: %ld.%02ldMHz\n",
90 clks[1] / 1000000, (clks[1] % 1000000) / 10000);
91 pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
92 clks[2] / 1000000, (clks[2] % 1000000) / 10000);
93 pr_info("Memory clock: %ld.%02ldMHz\n",
94 clks[3] / 1000000, (clks[3] % 1000000) / 10000);
95 }
96
97 return (unsigned int)clks[0] / KHz;
98 }
99
clk_pxa25x_memory_get_rate(struct clk_hw * hw,unsigned long parent_rate)100 static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
101 unsigned long parent_rate)
102 {
103 unsigned long cccr = readl(clk_regs + CCCR);
104 unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];
105
106 return parent_rate / m;
107 }
108 PARENTS(clk_pxa25x_memory) = { "run" };
109 RATE_RO_OPS(clk_pxa25x_memory, "memory");
110
111 PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
112 PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
113 PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
114
115 #define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \
116 bit, is_lp, flags) \
117 PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \
118 is_lp, CKEN, CKEN_ ## bit, flags)
119 #define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
120 PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp, \
121 div_hp, bit, NULL, 0)
122 #define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\
123 PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp, \
124 div_hp, bit, NULL, 0)
125 #define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
126 PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp, \
127 div_hp, bit, NULL, 0)
128
129 #define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
130 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
131 CKEN, CKEN_ ## bit, 0)
132 #define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
133 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
134 CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
135
136 static struct desc_clk_cken pxa25x_clocks[] __initdata = {
137 PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
138 PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0),
139 PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0),
140 PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5),
141 PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1),
142 PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1),
143 PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1),
144 PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1),
145 PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0),
146 PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0),
147 PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0),
148 PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0),
149 PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0),
150 PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
151 PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0),
152
153 PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0),
154 PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
155 clk_pxa25x_memory_parents, 0),
156 };
157
158 /*
159 * In this table, PXA25x_CCCR(N2, M, L) has the following meaning, where :
160 * - freq_cpll = n * m * L * 3.6864 MHz
161 * - n = N2 / 2
162 * - m = 2^(M - 1), where 1 <= M <= 3
163 * - l = L_clk_mult[L], ie. { 0, 27, 32, 36, 40, 45, 0, }[L]
164 */
165 static struct pxa2xx_freq pxa25x_freqs[] = {
166 /* CPU MEMBUS CCCR DIV2 CCLKCFG */
167 { 99532800, 99500, PXA25x_CCCR(2, 1, 1), 1, PXA25x_CLKCFG(1)},
168 {199065600, 99500, PXA25x_CCCR(4, 1, 1), 0, PXA25x_CLKCFG(1)},
169 {298598400, 99500, PXA25x_CCCR(3, 2, 1), 0, PXA25x_CLKCFG(1)},
170 {398131200, 99500, PXA25x_CCCR(4, 2, 1), 0, PXA25x_CLKCFG(1)},
171 };
172
clk_pxa25x_core_get_parent(struct clk_hw * hw)173 static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
174 {
175 unsigned long clkcfg;
176 unsigned int t;
177
178 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
179 t = clkcfg & (1 << 0);
180 if (t)
181 return PXA_CORE_TURBO;
182 return PXA_CORE_RUN;
183 }
184
clk_pxa25x_core_set_parent(struct clk_hw * hw,u8 index)185 static int clk_pxa25x_core_set_parent(struct clk_hw *hw, u8 index)
186 {
187 if (index > PXA_CORE_TURBO)
188 return -EINVAL;
189
190 pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
191
192 return 0;
193 }
194
clk_pxa25x_core_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)195 static int clk_pxa25x_core_determine_rate(struct clk_hw *hw,
196 struct clk_rate_request *req)
197 {
198 return __clk_mux_determine_rate(hw, req);
199 }
200
201 PARENTS(clk_pxa25x_core) = { "run", "cpll" };
202 MUX_OPS(clk_pxa25x_core, "core", CLK_SET_RATE_PARENT);
203
clk_pxa25x_run_get_rate(struct clk_hw * hw,unsigned long parent_rate)204 static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
205 unsigned long parent_rate)
206 {
207 unsigned long cccr = readl(clk_regs + CCCR);
208 unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];
209
210 return (parent_rate / n2) * 2;
211 }
212 PARENTS(clk_pxa25x_run) = { "cpll" };
213 RATE_RO_OPS(clk_pxa25x_run, "run");
214
clk_pxa25x_cpll_get_rate(struct clk_hw * hw,unsigned long parent_rate)215 static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
216 unsigned long parent_rate)
217 {
218 unsigned long clkcfg, cccr = readl(clk_regs + CCCR);
219 unsigned int l, m, n2, t;
220
221 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
222 t = clkcfg & (1 << 0);
223 l = L_clk_mult[(cccr >> 0) & 0x1f];
224 m = M_clk_mult[(cccr >> 5) & 0x03];
225 n2 = N2_clk_mult[(cccr >> 7) & 0x07];
226
227 return m * l * n2 * parent_rate / 2;
228 }
229
clk_pxa25x_cpll_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)230 static int clk_pxa25x_cpll_determine_rate(struct clk_hw *hw,
231 struct clk_rate_request *req)
232 {
233 return pxa2xx_determine_rate(req, pxa25x_freqs,
234 ARRAY_SIZE(pxa25x_freqs));
235 }
236
clk_pxa25x_cpll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)237 static int clk_pxa25x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
238 unsigned long parent_rate)
239 {
240 int i;
241
242 pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
243 for (i = 0; i < ARRAY_SIZE(pxa25x_freqs); i++)
244 if (pxa25x_freqs[i].cpll == rate)
245 break;
246
247 if (i >= ARRAY_SIZE(pxa25x_freqs))
248 return -EINVAL;
249
250 pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, clk_regs + CCCR);
251
252 return 0;
253 }
254 PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
255 RATE_OPS(clk_pxa25x_cpll, "cpll");
256
pxa25x_register_core(void)257 static void __init pxa25x_register_core(void)
258 {
259 clkdev_pxa_register(CLK_NONE, "cpll", NULL,
260 clk_register_clk_pxa25x_cpll());
261 clkdev_pxa_register(CLK_NONE, "run", NULL,
262 clk_register_clk_pxa25x_run());
263 clkdev_pxa_register(CLK_CORE, "core", NULL,
264 clk_register_clk_pxa25x_core());
265 }
266
pxa25x_register_plls(void)267 static void __init pxa25x_register_plls(void)
268 {
269 clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
270 CLK_GET_RATE_NOCACHE, 3686400);
271 clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
272 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
273 CLK_GET_RATE_NOCACHE,
274 32768));
275 clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
276 clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
277 0, 26, 1);
278 clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
279 0, 40, 1);
280 }
281
pxa25x_base_clocks_init(void)282 static void __init pxa25x_base_clocks_init(void)
283 {
284 pxa25x_register_plls();
285 pxa25x_register_core();
286 clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
287 clk_register_clk_pxa25x_memory());
288 }
289
290 #define DUMMY_CLK(_con_id, _dev_id, _parent) \
291 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
292 struct dummy_clk {
293 const char *con_id;
294 const char *dev_id;
295 const char *parent;
296 };
297 static struct dummy_clk dummy_clks[] __initdata = {
298 DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"),
299 DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"),
300 DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
301 DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
302 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
303 DUMMY_CLK("OSTIMER0", NULL, "osc_3_6864mhz"),
304 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
305 };
306
pxa25x_dummy_clocks_init(void)307 static void __init pxa25x_dummy_clocks_init(void)
308 {
309 struct clk *clk;
310 struct dummy_clk *d;
311 const char *name;
312 int i;
313
314 /*
315 * All pinctrl logic has been wiped out of the clock driver, especially
316 * for gpio11 and gpio12 outputs. Machine code should ensure proper pin
317 * control (ie. pxa2xx_mfp_config() invocation).
318 */
319 for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
320 d = &dummy_clks[i];
321 name = d->dev_id ? d->dev_id : d->con_id;
322 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
323 clk_register_clkdev(clk, d->con_id, d->dev_id);
324 }
325 }
326
pxa25x_clocks_init(void __iomem * regs)327 int __init pxa25x_clocks_init(void __iomem *regs)
328 {
329 clk_regs = regs;
330 pxa25x_base_clocks_init();
331 pxa25x_dummy_clocks_init();
332 return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks), clk_regs);
333 }
334
pxa25x_dt_clocks_init(struct device_node * np)335 static void __init pxa25x_dt_clocks_init(struct device_node *np)
336 {
337 pxa25x_clocks_init(ioremap(0x41300000ul, 0x10));
338 clk_pxa_dt_common_init(np);
339 }
340 CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
341 pxa25x_dt_clocks_init);
342