1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for Allwinner A10 PS2 host controller
4 *
5 * Author: Vishnu Patekar <vishnupatekar0510@gmail.com>
6 * Aaron.maoye <leafy.myeh@newbietech.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/serio.h>
11 #include <linux/interrupt.h>
12 #include <linux/errno.h>
13 #include <linux/slab.h>
14 #include <linux/io.h>
15 #include <linux/clk.h>
16 #include <linux/platform_device.h>
17
18 #define DRIVER_NAME "sun4i-ps2"
19
20 /* register offset definitions */
21 #define PS2_REG_GCTL 0x00 /* PS2 Module Global Control Reg */
22 #define PS2_REG_DATA 0x04 /* PS2 Module Data Reg */
23 #define PS2_REG_LCTL 0x08 /* PS2 Module Line Control Reg */
24 #define PS2_REG_LSTS 0x0C /* PS2 Module Line Status Reg */
25 #define PS2_REG_FCTL 0x10 /* PS2 Module FIFO Control Reg */
26 #define PS2_REG_FSTS 0x14 /* PS2 Module FIFO Status Reg */
27 #define PS2_REG_CLKDR 0x18 /* PS2 Module Clock Divider Reg*/
28
29 /* PS2 GLOBAL CONTROL REGISTER PS2_GCTL */
30 #define PS2_GCTL_INTFLAG BIT(4)
31 #define PS2_GCTL_INTEN BIT(3)
32 #define PS2_GCTL_RESET BIT(2)
33 #define PS2_GCTL_MASTER BIT(1)
34 #define PS2_GCTL_BUSEN BIT(0)
35
36 /* PS2 LINE CONTROL REGISTER */
37 #define PS2_LCTL_NOACK BIT(18)
38 #define PS2_LCTL_TXDTOEN BIT(8)
39 #define PS2_LCTL_STOPERREN BIT(3)
40 #define PS2_LCTL_ACKERREN BIT(2)
41 #define PS2_LCTL_PARERREN BIT(1)
42 #define PS2_LCTL_RXDTOEN BIT(0)
43
44 /* PS2 LINE STATUS REGISTER */
45 #define PS2_LSTS_TXTDO BIT(8)
46 #define PS2_LSTS_STOPERR BIT(3)
47 #define PS2_LSTS_ACKERR BIT(2)
48 #define PS2_LSTS_PARERR BIT(1)
49 #define PS2_LSTS_RXTDO BIT(0)
50
51 #define PS2_LINE_ERROR_BIT \
52 (PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR | \
53 PS2_LSTS_PARERR | PS2_LSTS_RXTDO)
54
55 /* PS2 FIFO CONTROL REGISTER */
56 #define PS2_FCTL_TXRST BIT(17)
57 #define PS2_FCTL_RXRST BIT(16)
58 #define PS2_FCTL_TXUFIEN BIT(10)
59 #define PS2_FCTL_TXOFIEN BIT(9)
60 #define PS2_FCTL_TXRDYIEN BIT(8)
61 #define PS2_FCTL_RXUFIEN BIT(2)
62 #define PS2_FCTL_RXOFIEN BIT(1)
63 #define PS2_FCTL_RXRDYIEN BIT(0)
64
65 /* PS2 FIFO STATUS REGISTER */
66 #define PS2_FSTS_TXUF BIT(10)
67 #define PS2_FSTS_TXOF BIT(9)
68 #define PS2_FSTS_TXRDY BIT(8)
69 #define PS2_FSTS_RXUF BIT(2)
70 #define PS2_FSTS_RXOF BIT(1)
71 #define PS2_FSTS_RXRDY BIT(0)
72
73 #define PS2_FIFO_ERROR_BIT \
74 (PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_RXUF | PS2_FSTS_RXOF)
75
76 #define PS2_SAMPLE_CLK 1000000
77 #define PS2_SCLK 125000
78
79 struct sun4i_ps2data {
80 struct serio *serio;
81 struct device *dev;
82
83 /* IO mapping base */
84 void __iomem *reg_base;
85
86 /* clock management */
87 struct clk *clk;
88
89 /* irq */
90 spinlock_t lock;
91 int irq;
92 };
93
sun4i_ps2_interrupt(int irq,void * dev_id)94 static irqreturn_t sun4i_ps2_interrupt(int irq, void *dev_id)
95 {
96 struct sun4i_ps2data *drvdata = dev_id;
97 u32 intr_status;
98 u32 fifo_status;
99 unsigned char byte;
100 unsigned int rxflags = 0;
101 u32 rval;
102
103 guard(spinlock)(&drvdata->lock);
104
105 /* Get the PS/2 interrupts and clear them */
106 intr_status = readl(drvdata->reg_base + PS2_REG_LSTS);
107 fifo_status = readl(drvdata->reg_base + PS2_REG_FSTS);
108
109 /* Check line status register */
110 if (intr_status & PS2_LINE_ERROR_BIT) {
111 rxflags = (intr_status & PS2_LINE_ERROR_BIT) ? SERIO_FRAME : 0;
112 rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_PARITY : 0;
113 rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_TIMEOUT : 0;
114
115 rval = PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR |
116 PS2_LSTS_PARERR | PS2_LSTS_RXTDO;
117 writel(rval, drvdata->reg_base + PS2_REG_LSTS);
118 }
119
120 /* Check FIFO status register */
121 if (fifo_status & PS2_FIFO_ERROR_BIT) {
122 rval = PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_TXRDY |
123 PS2_FSTS_RXUF | PS2_FSTS_RXOF | PS2_FSTS_RXRDY;
124 writel(rval, drvdata->reg_base + PS2_REG_FSTS);
125 }
126
127 rval = (fifo_status >> 16) & 0x3;
128 while (rval--) {
129 byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff;
130 serio_interrupt(drvdata->serio, byte, rxflags);
131 }
132
133 writel(intr_status, drvdata->reg_base + PS2_REG_LSTS);
134 writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS);
135
136 return IRQ_HANDLED;
137 }
138
sun4i_ps2_open(struct serio * serio)139 static int sun4i_ps2_open(struct serio *serio)
140 {
141 struct sun4i_ps2data *drvdata = serio->port_data;
142 u32 src_clk = 0;
143 u32 clk_scdf;
144 u32 clk_pcdf;
145 u32 rval;
146
147 /* Set line control and enable interrupt */
148 rval = PS2_LCTL_STOPERREN | PS2_LCTL_ACKERREN
149 | PS2_LCTL_PARERREN | PS2_LCTL_RXDTOEN;
150 writel(rval, drvdata->reg_base + PS2_REG_LCTL);
151
152 /* Reset FIFO */
153 rval = PS2_FCTL_TXRST | PS2_FCTL_RXRST | PS2_FCTL_TXUFIEN
154 | PS2_FCTL_TXOFIEN | PS2_FCTL_RXUFIEN
155 | PS2_FCTL_RXOFIEN | PS2_FCTL_RXRDYIEN;
156
157 writel(rval, drvdata->reg_base + PS2_REG_FCTL);
158
159 src_clk = clk_get_rate(drvdata->clk);
160 /* Set clock divider register */
161 clk_scdf = src_clk / PS2_SAMPLE_CLK - 1;
162 clk_pcdf = PS2_SAMPLE_CLK / PS2_SCLK - 1;
163 rval = (clk_scdf << 8) | clk_pcdf;
164 writel(rval, drvdata->reg_base + PS2_REG_CLKDR);
165
166 /* Set global control register */
167 rval = PS2_GCTL_RESET | PS2_GCTL_INTEN | PS2_GCTL_MASTER
168 | PS2_GCTL_BUSEN;
169
170 guard(spinlock_irqsave)(&drvdata->lock);
171 writel(rval, drvdata->reg_base + PS2_REG_GCTL);
172
173 return 0;
174 }
175
sun4i_ps2_close(struct serio * serio)176 static void sun4i_ps2_close(struct serio *serio)
177 {
178 struct sun4i_ps2data *drvdata = serio->port_data;
179 u32 rval;
180
181 /* Shut off the interrupt */
182 rval = readl(drvdata->reg_base + PS2_REG_GCTL);
183 writel(rval & ~(PS2_GCTL_INTEN), drvdata->reg_base + PS2_REG_GCTL);
184
185 synchronize_irq(drvdata->irq);
186 }
187
sun4i_ps2_write(struct serio * serio,unsigned char val)188 static int sun4i_ps2_write(struct serio *serio, unsigned char val)
189 {
190 unsigned long expire = jiffies + msecs_to_jiffies(10000);
191 struct sun4i_ps2data *drvdata = serio->port_data;
192
193 do {
194 if (readl(drvdata->reg_base + PS2_REG_FSTS) & PS2_FSTS_TXRDY) {
195 writel(val, drvdata->reg_base + PS2_REG_DATA);
196 return 0;
197 }
198 } while (time_before(jiffies, expire));
199
200 return SERIO_TIMEOUT;
201 }
202
sun4i_ps2_probe(struct platform_device * pdev)203 static int sun4i_ps2_probe(struct platform_device *pdev)
204 {
205 struct resource *res; /* IO mem resources */
206 struct sun4i_ps2data *drvdata;
207 struct serio *serio;
208 struct device *dev = &pdev->dev;
209 int error;
210
211 drvdata = kzalloc_obj(*drvdata);
212 serio = kzalloc_obj(*serio);
213 if (!drvdata || !serio) {
214 error = -ENOMEM;
215 goto err_free_mem;
216 }
217
218 spin_lock_init(&drvdata->lock);
219
220 /* IO */
221 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
222 if (!res) {
223 dev_err(dev, "failed to locate registers\n");
224 error = -ENXIO;
225 goto err_free_mem;
226 }
227
228 drvdata->reg_base = ioremap(res->start, resource_size(res));
229 if (!drvdata->reg_base) {
230 dev_err(dev, "failed to map registers\n");
231 error = -ENOMEM;
232 goto err_free_mem;
233 }
234
235 drvdata->clk = clk_get(dev, NULL);
236 if (IS_ERR(drvdata->clk)) {
237 error = PTR_ERR(drvdata->clk);
238 dev_err(dev, "couldn't get clock %d\n", error);
239 goto err_ioremap;
240 }
241
242 error = clk_prepare_enable(drvdata->clk);
243 if (error) {
244 dev_err(dev, "failed to enable clock %d\n", error);
245 goto err_clk;
246 }
247
248 serio->id.type = SERIO_8042;
249 serio->write = sun4i_ps2_write;
250 serio->open = sun4i_ps2_open;
251 serio->close = sun4i_ps2_close;
252 serio->port_data = drvdata;
253 serio->dev.parent = dev;
254 strscpy(serio->name, dev_name(dev), sizeof(serio->name));
255 strscpy(serio->phys, dev_name(dev), sizeof(serio->phys));
256
257 /* shutoff interrupt */
258 writel(0, drvdata->reg_base + PS2_REG_GCTL);
259
260 /* Get IRQ for the device */
261 drvdata->irq = platform_get_irq(pdev, 0);
262 if (drvdata->irq < 0) {
263 error = drvdata->irq;
264 goto err_disable_clk;
265 }
266
267 drvdata->serio = serio;
268 drvdata->dev = dev;
269
270 error = request_irq(drvdata->irq, sun4i_ps2_interrupt, 0,
271 DRIVER_NAME, drvdata);
272 if (error) {
273 dev_err(drvdata->dev, "failed to allocate interrupt %d: %d\n",
274 drvdata->irq, error);
275 goto err_disable_clk;
276 }
277
278 serio_register_port(serio);
279 platform_set_drvdata(pdev, drvdata);
280
281 return 0; /* success */
282
283 err_disable_clk:
284 clk_disable_unprepare(drvdata->clk);
285 err_clk:
286 clk_put(drvdata->clk);
287 err_ioremap:
288 iounmap(drvdata->reg_base);
289 err_free_mem:
290 kfree(serio);
291 kfree(drvdata);
292 return error;
293 }
294
sun4i_ps2_remove(struct platform_device * pdev)295 static void sun4i_ps2_remove(struct platform_device *pdev)
296 {
297 struct sun4i_ps2data *drvdata = platform_get_drvdata(pdev);
298
299 serio_unregister_port(drvdata->serio);
300
301 free_irq(drvdata->irq, drvdata);
302
303 clk_disable_unprepare(drvdata->clk);
304 clk_put(drvdata->clk);
305
306 iounmap(drvdata->reg_base);
307
308 kfree(drvdata);
309 }
310
311 static const struct of_device_id sun4i_ps2_match[] = {
312 { .compatible = "allwinner,sun4i-a10-ps2", },
313 { },
314 };
315
316 MODULE_DEVICE_TABLE(of, sun4i_ps2_match);
317
318 static struct platform_driver sun4i_ps2_driver = {
319 .probe = sun4i_ps2_probe,
320 .remove = sun4i_ps2_remove,
321 .driver = {
322 .name = DRIVER_NAME,
323 .of_match_table = sun4i_ps2_match,
324 },
325 };
326 module_platform_driver(sun4i_ps2_driver);
327
328 MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
329 MODULE_AUTHOR("Aaron.maoye <leafy.myeh@newbietech.com>");
330 MODULE_DESCRIPTION("Allwinner A10/Sun4i PS/2 driver");
331 MODULE_LICENSE("GPL v2");
332