1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "core_types.h" 28 #include "dccg.h" 29 #include "clk_mgr_internal.h" 30 #include "dcn201_clk_mgr.h" 31 #include "dcn10/dcn10_clk_mgr.h" 32 #include "dcn20/dcn20_clk_mgr.h" 33 #include "dm_helpers.h" 34 #include "dm_services.h" 35 36 #include "cyan_skillfish_ip_offset.h" 37 #include "dcn/dcn_2_0_1_offset.h" 38 #include "dcn/dcn_2_0_1_sh_mask.h" 39 #include "clk/clk_11_0_1_offset.h" 40 #include "clk/clk_11_0_1_sh_mask.h" 41 42 #define REG(reg) \ 43 (clk_mgr->regs->reg) 44 45 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 46 47 #define BASE(seg) BASE_INNER(seg) 48 49 #define SR(reg_name)\ 50 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 51 mm ## reg_name 52 53 #define CLK_BASE_INNER(seg) \ 54 CLK_BASE__INST0_SEG ## seg 55 56 #undef FN 57 #define FN(reg_name, field_name) \ 58 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 59 60 #define CTX \ 61 clk_mgr->base.ctx 62 63 static const struct clk_mgr_registers clk_mgr_regs = { 64 CLK_COMMON_REG_LIST_DCN_201() 65 }; 66 67 static const struct clk_mgr_shift clk_mgr_shift = { 68 CLK_COMMON_MASK_SH_LIST_DCN201_BASE(__SHIFT) 69 }; 70 71 static const struct clk_mgr_mask clk_mgr_mask = { 72 CLK_COMMON_MASK_SH_LIST_DCN201_BASE(_MASK) 73 }; 74 75 static void dcn201_init_clocks(struct clk_mgr *clk_mgr) 76 { 77 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 78 clk_mgr->clks.p_state_change_support = true; 79 clk_mgr->clks.prev_p_state_change_support = true; 80 clk_mgr->clks.max_supported_dppclk_khz = 1200000; 81 clk_mgr->clks.max_supported_dispclk_khz = 1200000; 82 } 83 84 static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base, 85 struct dc_state *context, 86 bool safe_to_lower) 87 { 88 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 89 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 90 struct dc *dc = clk_mgr_base->ctx->dc; 91 bool update_dppclk = false; 92 bool update_dispclk = false; 93 bool dpp_clock_lowered = false; 94 bool force_reset = false; 95 bool p_state_change_support; 96 int total_plane_count; 97 98 if (dc->work_arounds.skip_clock_update) 99 return; 100 101 if (clk_mgr_base->clks.dispclk_khz == 0 || 102 dc->debug.force_clock_mode & 0x1) { 103 /* this is from resume or boot up, if forced_clock cfg option 104 * used, we bypass program dispclk and DPPCLK, but need set them 105 * for S3. 106 */ 107 108 force_reset = true; 109 /* force_clock_mode 0x1: force reset the clock even it is the 110 * same clock as long as it is in Passive level. 111 */ 112 113 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); 114 } 115 116 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) 117 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; 118 119 if (dc->debug.force_min_dcfclk_mhz > 0) 120 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? 121 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); 122 123 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) 124 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 125 126 if (should_set_clock(safe_to_lower, 127 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) 128 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 129 130 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) 131 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; 132 133 total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context); 134 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); 135 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { 136 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; 137 clk_mgr_base->clks.p_state_change_support = p_state_change_support; 138 } 139 140 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) 141 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; 142 143 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 144 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 145 dpp_clock_lowered = true; 146 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; 147 148 update_dppclk = true; 149 } 150 151 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 152 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 153 154 update_dispclk = true; 155 } 156 157 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { 158 if (dpp_clock_lowered) { 159 // if clock is being lowered, increase DTO before lowering refclk 160 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 161 dcn20_update_clocks_update_dentist(clk_mgr, context); 162 } else { 163 // if clock is being raised, increase refclk before lowering DTO 164 if (update_dppclk || update_dispclk) 165 dcn20_update_clocks_update_dentist(clk_mgr, context); 166 // always update dtos unless clock is lowered and not safe to lower 167 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 168 } 169 } 170 } 171 172 static struct clk_mgr_funcs dcn201_funcs = { 173 .get_dp_ref_clk_frequency = dcn10_get_dp_ref_freq_khz, 174 .update_clocks = dcn201_update_clocks, 175 .init_clocks = dcn201_init_clocks, 176 .get_clock = dcn2_get_clock, 177 }; 178 179 void dcn201_clk_mgr_construct(struct dc_context *ctx, 180 struct clk_mgr_internal *clk_mgr, 181 struct pp_smu_funcs *pp_smu, 182 struct dccg *dccg) 183 { 184 struct dc_debug_options *debug = &ctx->dc->debug; 185 struct dc_bios *bp = ctx->dc_bios; 186 clk_mgr->base.ctx = ctx; 187 clk_mgr->base.funcs = &dcn201_funcs; 188 clk_mgr->regs = &clk_mgr_regs; 189 clk_mgr->clk_mgr_shift = &clk_mgr_shift; 190 clk_mgr->clk_mgr_mask = &clk_mgr_mask; 191 192 clk_mgr->dccg = dccg; 193 194 clk_mgr->dfs_bypass_disp_clk = 0; 195 196 clk_mgr->dprefclk_ss_percentage = 0; 197 clk_mgr->dprefclk_ss_divider = 1000; 198 clk_mgr->ss_on_dprefclk = false; 199 200 clk_mgr->base.dprefclk_khz = REG_READ(CLK4_CLK2_CURRENT_CNT); 201 clk_mgr->base.dprefclk_khz *= 100; 202 203 if (clk_mgr->base.dprefclk_khz == 0) 204 clk_mgr->base.dprefclk_khz = 600000; 205 206 REG_GET(CLK4_CLK_PLL_REQ, FbMult_int, &clk_mgr->base.dentist_vco_freq_khz); 207 clk_mgr->base.dentist_vco_freq_khz *= 100000; 208 209 if (clk_mgr->base.dentist_vco_freq_khz == 0) 210 clk_mgr->base.dentist_vco_freq_khz = 3000000; 211 212 if (!debug->disable_dfs_bypass && bp->integrated_info) 213 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) 214 clk_mgr->dfs_bypass_enabled = true; 215 216 dcn10_clock_read_ss_info(clk_mgr); 217 } 218