1 /*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dal_asic_id.h"
27 #include "dc_types.h"
28 #include "dccg.h"
29 #include "clk_mgr_internal.h"
30 #include "dc_state_priv.h"
31 #include "link_service.h"
32
33 #include "dce100/dce_clk_mgr.h"
34 #include "dce110/dce110_clk_mgr.h"
35 #include "dce112/dce112_clk_mgr.h"
36 #include "dce120/dce120_clk_mgr.h"
37 #include "dcn10/rv1_clk_mgr.h"
38 #include "dcn10/rv2_clk_mgr.h"
39 #include "dcn20/dcn20_clk_mgr.h"
40 #include "dcn21/rn_clk_mgr.h"
41 #include "dcn201/dcn201_clk_mgr.h"
42 #include "dcn30/dcn30_clk_mgr.h"
43 #include "dcn301/vg_clk_mgr.h"
44 #include "dcn31/dcn31_clk_mgr.h"
45 #include "dcn314/dcn314_clk_mgr.h"
46 #include "dcn315/dcn315_clk_mgr.h"
47 #include "dcn316/dcn316_clk_mgr.h"
48 #include "dcn32/dcn32_clk_mgr.h"
49 #include "dcn35/dcn35_clk_mgr.h"
50 #include "dcn401/dcn401_clk_mgr.h"
51 #include "dcn42/dcn42_clk_mgr.h"
52
clk_mgr_helper_get_active_display_cnt(struct dc * dc,struct dc_state * context)53 int clk_mgr_helper_get_active_display_cnt(
54 struct dc *dc,
55 struct dc_state *context)
56 {
57 int i, display_count;
58
59 display_count = 0;
60 for (i = 0; i < context->stream_count; i++) {
61 const struct dc_stream_state *stream = context->streams[i];
62 const struct dc_stream_status *stream_status = &context->stream_status[i];
63
64 /* Don't count SubVP phantom pipes as part of active
65 * display count
66 */
67 if (dc_state_get_stream_subvp_type(context, stream) == SUBVP_PHANTOM)
68 continue;
69
70 if (!stream->dpms_off || dc->is_switch_in_progress_dest || (stream_status && stream_status->plane_count))
71 display_count++;
72 }
73
74 return display_count;
75 }
76
clk_mgr_helper_get_active_plane_cnt(struct dc * dc,struct dc_state * context)77 int clk_mgr_helper_get_active_plane_cnt(
78 struct dc *dc,
79 struct dc_state *context)
80 {
81 (void)dc;
82 int i, total_plane_count;
83
84 total_plane_count = 0;
85 for (i = 0; i < context->stream_count; i++) {
86 const struct dc_stream_status stream_status = context->stream_status[i];
87
88 /*
89 * Sum up plane_count for all streams ( active and virtual ).
90 */
91 total_plane_count += stream_status.plane_count;
92 }
93
94 return total_plane_count;
95 }
96
clk_mgr_exit_optimized_pwr_state(const struct dc * dc,struct clk_mgr * clk_mgr)97 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
98 {
99 struct dc_link *edp_links[MAX_NUM_EDP];
100 struct dc_link *edp_link = NULL;
101 unsigned int edp_num;
102 unsigned int panel_inst;
103
104 dc_get_edp_links(dc, edp_links, &edp_num);
105 if (dc->hwss.exit_optimized_pwr_state)
106 dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);
107
108 if (edp_num) {
109 for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
110 bool allow_active = false;
111
112 edp_link = edp_links[panel_inst];
113 if (!edp_link->psr_settings.psr_feature_enabled)
114 continue;
115 clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active;
116 dc->link_srv->edp_set_psr_allow_active(edp_link, &allow_active, false, false, NULL);
117 dc->link_srv->edp_set_replay_allow_active(edp_link, &allow_active, false, false, NULL);
118 }
119 }
120
121 }
122
clk_mgr_optimize_pwr_state(const struct dc * dc,struct clk_mgr * clk_mgr)123 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
124 {
125 struct dc_link *edp_links[MAX_NUM_EDP];
126 struct dc_link *edp_link = NULL;
127 unsigned int edp_num;
128 unsigned int panel_inst;
129
130 dc_get_edp_links(dc, edp_links, &edp_num);
131 if (edp_num) {
132 for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
133 edp_link = edp_links[panel_inst];
134 if (!edp_link->psr_settings.psr_feature_enabled)
135 continue;
136 dc->link_srv->edp_set_psr_allow_active(edp_link,
137 &clk_mgr->psr_allow_active_cache, false, false, NULL);
138 dc->link_srv->edp_set_replay_allow_active(edp_link,
139 &clk_mgr->psr_allow_active_cache, false, false, NULL);
140 }
141 }
142
143 if (dc->hwss.optimize_pwr_state)
144 dc->hwss.optimize_pwr_state(dc, dc->current_state);
145
146 }
147
dc_clk_mgr_create(struct dc_context * ctx,struct pp_smu_funcs * pp_smu,struct dccg * dccg)148 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)
149 {
150 struct hw_asic_id asic_id = ctx->asic_id;
151
152 switch (asic_id.chip_family) {
153 case FAMILY_SI:
154 case FAMILY_CI:
155 case FAMILY_KV: {
156 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
157
158 if (clk_mgr == NULL) {
159 BREAK_TO_DEBUGGER();
160 return NULL;
161 }
162 dce_clk_mgr_construct(ctx, clk_mgr);
163 return &clk_mgr->base;
164 }
165 case FAMILY_CZ: {
166 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
167
168 if (clk_mgr == NULL) {
169 BREAK_TO_DEBUGGER();
170 return NULL;
171 }
172 dce110_clk_mgr_construct(ctx, clk_mgr);
173 return &clk_mgr->base;
174 }
175 case FAMILY_VI: {
176 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
177
178 if (clk_mgr == NULL) {
179 BREAK_TO_DEBUGGER();
180 return NULL;
181 }
182 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
183 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
184 dce_clk_mgr_construct(ctx, clk_mgr);
185 return &clk_mgr->base;
186 }
187 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
188 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
189 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
190 dce112_clk_mgr_construct(ctx, clk_mgr);
191 return &clk_mgr->base;
192 }
193 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) {
194 dce112_clk_mgr_construct(ctx, clk_mgr);
195 return &clk_mgr->base;
196 }
197 return &clk_mgr->base;
198 }
199 case FAMILY_AI: {
200 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
201
202 if (clk_mgr == NULL) {
203 BREAK_TO_DEBUGGER();
204 return NULL;
205 }
206 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
207 dce121_clk_mgr_construct(ctx, clk_mgr);
208 else
209 dce120_clk_mgr_construct(ctx, clk_mgr);
210 return &clk_mgr->base;
211 }
212 #if defined(CONFIG_DRM_AMD_DC_FP)
213 case FAMILY_RV: {
214 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
215
216 if (clk_mgr == NULL) {
217 BREAK_TO_DEBUGGER();
218 return NULL;
219 }
220
221 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
222 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
223 return &clk_mgr->base;
224 }
225
226 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
227 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
228 return &clk_mgr->base;
229 }
230 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
231 rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
232 return &clk_mgr->base;
233 }
234 if (ASICREV_IS_RAVEN(asic_id.hw_internal_rev) ||
235 ASICREV_IS_PICASSO(asic_id.hw_internal_rev)) {
236 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);
237 return &clk_mgr->base;
238 }
239 return &clk_mgr->base;
240 }
241 case FAMILY_NV: {
242 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
243
244 if (clk_mgr == NULL) {
245 BREAK_TO_DEBUGGER();
246 return NULL;
247 }
248 if (ctx->dce_version == DCN_VERSION_2_01) {
249 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
250 return &clk_mgr->base;
251 }
252 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) {
253 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
254 return &clk_mgr->base;
255 }
256 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) {
257 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
258 return &clk_mgr->base;
259 }
260 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) {
261 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
262 return &clk_mgr->base;
263 }
264 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
265 return &clk_mgr->base;
266 }
267 case FAMILY_VGH:
268 if (ASICREV_IS_VANGOGH(asic_id.hw_internal_rev)) {
269 struct clk_mgr_vgh *clk_mgr = kzalloc_obj(*clk_mgr);
270
271 if (clk_mgr == NULL) {
272 BREAK_TO_DEBUGGER();
273 return NULL;
274 }
275 vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
276 return &clk_mgr->base.base;
277 }
278 break;
279
280 case FAMILY_YELLOW_CARP: {
281 struct clk_mgr_dcn31 *clk_mgr = kzalloc_obj(*clk_mgr);
282
283 if (clk_mgr == NULL) {
284 BREAK_TO_DEBUGGER();
285 return NULL;
286 }
287
288 dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
289 return &clk_mgr->base.base;
290 }
291 break;
292 case AMDGPU_FAMILY_GC_10_3_6: {
293 struct clk_mgr_dcn315 *clk_mgr = kzalloc_obj(*clk_mgr);
294
295 if (clk_mgr == NULL) {
296 BREAK_TO_DEBUGGER();
297 return NULL;
298 }
299
300 dcn315_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
301 return &clk_mgr->base.base;
302 }
303 break;
304 case AMDGPU_FAMILY_GC_10_3_7: {
305 struct clk_mgr_dcn316 *clk_mgr = kzalloc_obj(*clk_mgr);
306
307 if (clk_mgr == NULL) {
308 BREAK_TO_DEBUGGER();
309 return NULL;
310 }
311
312 dcn316_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
313 return &clk_mgr->base.base;
314 }
315 break;
316 case AMDGPU_FAMILY_GC_11_0_0: {
317 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
318
319 if (clk_mgr == NULL) {
320 BREAK_TO_DEBUGGER();
321 return NULL;
322 }
323 dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
324 return &clk_mgr->base;
325 }
326
327 case AMDGPU_FAMILY_GC_11_0_1: {
328 struct clk_mgr_dcn314 *clk_mgr = kzalloc_obj(*clk_mgr);
329
330 if (clk_mgr == NULL) {
331 BREAK_TO_DEBUGGER();
332 return NULL;
333 }
334
335 dcn314_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
336 return &clk_mgr->base.base;
337 }
338 break;
339
340 case AMDGPU_FAMILY_GC_11_5_0: {
341 struct clk_mgr_dcn35 *clk_mgr = kzalloc_obj(*clk_mgr);
342
343 if (clk_mgr == NULL) {
344 BREAK_TO_DEBUGGER();
345 return NULL;
346 }
347 if (ctx->dce_version == DCN_VERSION_3_51)
348 dcn351_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
349 else
350 dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
351
352 return &clk_mgr->base.base;
353 }
354 break;
355
356 case AMDGPU_FAMILY_GC_12_0_0: {
357 struct clk_mgr_internal *clk_mgr = dcn401_clk_mgr_construct(ctx, dccg);
358
359 if (clk_mgr == NULL) {
360 BREAK_TO_DEBUGGER();
361 return NULL;
362 }
363
364 return &clk_mgr->base;
365 }
366 break;
367 case AMDGPU_FAMILY_GC_11_5_4: {
368 struct clk_mgr_dcn42 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
369
370 if (clk_mgr == NULL) {
371 BREAK_TO_DEBUGGER();
372 return NULL;
373 }
374
375 dcn42_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
376 return &clk_mgr->base.base;
377 }
378 break;
379 #endif /* CONFIG_DRM_AMD_DC_FP */
380 default:
381 ASSERT(0); /* Unknown Asic */
382 break;
383 }
384
385 return NULL;
386 }
387
dc_destroy_clk_mgr(struct clk_mgr * clk_mgr_base)388 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
389 {
390 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
391
392 #ifdef CONFIG_DRM_AMD_DC_FP
393 switch (clk_mgr_base->ctx->asic_id.chip_family) {
394 case FAMILY_NV:
395 if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
396 dcn3_clk_mgr_destroy(clk_mgr);
397 } else if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
398 dcn3_clk_mgr_destroy(clk_mgr);
399 }
400 if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
401 dcn3_clk_mgr_destroy(clk_mgr);
402 }
403 break;
404
405 case FAMILY_VGH:
406 if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev))
407 vg_clk_mgr_destroy(clk_mgr);
408 break;
409
410 case FAMILY_YELLOW_CARP:
411 dcn31_clk_mgr_destroy(clk_mgr);
412 break;
413
414 case AMDGPU_FAMILY_GC_10_3_6:
415 dcn315_clk_mgr_destroy(clk_mgr);
416 break;
417
418 case AMDGPU_FAMILY_GC_10_3_7:
419 dcn316_clk_mgr_destroy(clk_mgr);
420 break;
421
422 case AMDGPU_FAMILY_GC_11_0_0:
423 dcn32_clk_mgr_destroy(clk_mgr);
424 break;
425
426 case AMDGPU_FAMILY_GC_11_0_1:
427 dcn314_clk_mgr_destroy(clk_mgr);
428 break;
429
430 case AMDGPU_FAMILY_GC_11_5_0:
431 dcn35_clk_mgr_destroy(clk_mgr);
432 break;
433 case AMDGPU_FAMILY_GC_12_0_0:
434 dcn401_clk_mgr_destroy(clk_mgr);
435 break;
436 case AMDGPU_FAMILY_GC_11_5_4:
437 dcn42_clk_mgr_destroy(clk_mgr);
438 break;
439
440 default:
441 break;
442 }
443 #endif /* CONFIG_DRM_AMD_DC_FP */
444
445 kfree(clk_mgr);
446 }
447
448