1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 */
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
8
9 #include <dt-bindings/clock/clock.h>
10 #include <linux/of.h>
11 #include <linux/of_clk.h>
12
13 /**
14 * DOC: clk framework flags
15 *
16 * Flags used across common struct clk. These flags should only affect the
17 * top-level framework. Custom flags for dealing with hardware specifics
18 * belong in struct clk_foo.
19 *
20 * * CLK_SET_RATE_GATE - must be gated across rate change
21 * * CLK_SET_PARENT_GATE - must be gated across re-parent
22 * * CLK_SET_RATE_PARENT - propagate rate change up one level
23 * * CLK_IGNORE_UNUSED - do not gate even if unused
24 * * CLK_GET_RATE_NOCACHE - do not use the cached clk rate
25 * * CLK_SET_RATE_NO_REPARENT - don't re-parent on rate change
26 * * CLK_GET_ACCURACY_NOCACHE - do not use the cached clk accuracy
27 * * CLK_RECALC_NEW_RATES - recalc rates after notifications
28 * * CLK_SET_RATE_UNGATE - clock needs to run to set rate
29 * * CLK_IS_CRITICAL - do not gate, ever
30 * * CLK_OPS_PARENT_ENABLE - parents need enable during gate/ungate, set rate and re-parent
31 * * CLK_DUTY_CYCLE_PARENT - duty cycle call may be forwarded to the parent clock
32 */
33 /* Please update clk_flags[] in drivers/clk/clk.c when making changes here! */
34 #define CLK_SET_RATE_GATE BIT(0)
35 #define CLK_SET_PARENT_GATE BIT(1)
36 #define CLK_SET_RATE_PARENT BIT(2)
37 #define CLK_IGNORE_UNUSED BIT(3)
38 /* unused */
39 /* unused */
40 #define CLK_GET_RATE_NOCACHE BIT(6)
41 #define CLK_SET_RATE_NO_REPARENT BIT(7)
42 #define CLK_GET_ACCURACY_NOCACHE BIT(8)
43 #define CLK_RECALC_NEW_RATES BIT(9)
44 #define CLK_SET_RATE_UNGATE BIT(10)
45 #define CLK_IS_CRITICAL BIT(11)
46 #define CLK_OPS_PARENT_ENABLE BIT(12)
47 #define CLK_DUTY_CYCLE_PARENT BIT(13)
48
49 struct clk;
50 struct clk_hw;
51 struct clk_core;
52 struct dentry;
53
54 /**
55 * struct clk_rate_request - Structure encoding the clk constraints that
56 * a clock user might require.
57 *
58 * Should be initialized by calling clk_hw_init_rate_request().
59 *
60 * @core: Pointer to the struct clk_core affected by this request
61 * @rate: Requested clock rate. This field will be adjusted by
62 * clock drivers according to hardware capabilities.
63 * @min_rate: Minimum rate imposed by clk users.
64 * @max_rate: Maximum rate imposed by clk users.
65 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
66 * requested constraints.
67 * @best_parent_hw: The most appropriate parent clock that fulfills the
68 * requested constraints.
69 *
70 */
71 struct clk_rate_request {
72 struct clk_core *core;
73 unsigned long rate;
74 unsigned long min_rate;
75 unsigned long max_rate;
76 unsigned long best_parent_rate;
77 struct clk_hw *best_parent_hw;
78 };
79
80 void clk_hw_init_rate_request(const struct clk_hw *hw,
81 struct clk_rate_request *req,
82 unsigned long rate);
83 void clk_hw_forward_rate_request(const struct clk_hw *core,
84 const struct clk_rate_request *old_req,
85 const struct clk_hw *parent,
86 struct clk_rate_request *req,
87 unsigned long parent_rate);
88
89 /**
90 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
91 *
92 * @num: Numerator of the duty cycle ratio
93 * @den: Denominator of the duty cycle ratio
94 */
95 struct clk_duty {
96 unsigned int num;
97 unsigned int den;
98 };
99
100 enum clk_ssc_method {
101 CLK_SPREAD_NO = CLK_SSC_NO_SPREAD,
102 CLK_SPREAD_CENTER = CLK_SSC_CENTER_SPREAD,
103 CLK_SPREAD_UP = CLK_SSC_UP_SPREAD,
104 CLK_SPREAD_DOWN = CLK_SSC_DOWN_SPREAD,
105 };
106
107 /**
108 * struct clk_spread_spectrum - Structure encoding spread spectrum of a clock
109 *
110 * @modfreq_hz: Modulation frequency
111 * @spread_bp: Modulation percent in permyriad
112 * @method: Modulation method
113 */
114 struct clk_spread_spectrum {
115 u32 modfreq_hz;
116 u32 spread_bp;
117 enum clk_ssc_method method;
118 };
119
120 /**
121 * struct clk_ops - Callback operations for hardware clocks; these are to
122 * be provided by the clock implementation, and will be called by drivers
123 * through the clk_* api.
124 *
125 * @prepare: Prepare the clock for enabling. This must not return until
126 * the clock is fully prepared, and it's safe to call clk_enable.
127 * This callback is intended to allow clock implementations to
128 * do any initialisation that may sleep. Called with
129 * prepare_lock held.
130 *
131 * @unprepare: Release the clock from its prepared state. This will typically
132 * undo any work done in the @prepare callback. Called with
133 * prepare_lock held.
134 *
135 * @is_prepared: Queries the hardware to determine if the clock is prepared.
136 * This function is allowed to sleep. Optional, if this op is not
137 * set then the prepare count will be used.
138 *
139 * @unprepare_unused: Unprepare the clock atomically. Only called from
140 * clk_disable_unused for prepare clocks with special needs.
141 * Called with prepare mutex held. This function may sleep.
142 *
143 * @enable: Enable the clock atomically. This must not return until the
144 * clock is generating a valid clock signal, usable by consumer
145 * devices. Called with enable_lock held. This function must not
146 * sleep.
147 *
148 * @disable: Disable the clock atomically. Called with enable_lock held.
149 * This function must not sleep.
150 *
151 * @is_enabled: Queries the hardware to determine if the clock is enabled.
152 * This function must not sleep. Optional, if this op is not
153 * set then the enable count will be used.
154 *
155 * @disable_unused: Disable the clock atomically. Only called from
156 * clk_disable_unused for gate clocks with special needs.
157 * Called with enable_lock held. This function must not
158 * sleep.
159 *
160 * @save_context: Save the context of the clock in prepration for poweroff.
161 *
162 * @restore_context: Restore the context of the clock after a restoration
163 * of power.
164 *
165 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The
166 * parent rate is an input parameter. It is up to the caller to
167 * ensure that the prepare_mutex is held across this call. If the
168 * driver cannot figure out a rate for this clock, it must return
169 * 0. Returns the calculated rate. Optional, but recommended - if
170 * this op is not set then clock rate will be initialized to 0.
171 *
172 * @determine_rate: Given a target rate as input, returns the closest rate
173 * actually supported by the clock, and optionally the parent clock
174 * that should be used to provide the clock rate.
175 *
176 * @set_parent: Change the input source of this clock; for clocks with multiple
177 * possible parents specify a new parent by passing in the index
178 * as a u8 corresponding to the parent in either the .parent_names
179 * or .parents arrays. This function in affect translates an
180 * array index into the value programmed into the hardware.
181 * Returns 0 on success, -EERROR otherwise.
182 *
183 * @get_parent: Queries the hardware to determine the parent of a clock. The
184 * return value is a u8 which specifies the index corresponding to
185 * the parent clock. This index can be applied to either the
186 * .parent_names or .parents arrays. In short, this function
187 * translates the parent value read from hardware into an array
188 * index. Currently only called when the clock is initialized by
189 * __clk_init. This callback is mandatory for clocks with
190 * multiple parents. It is optional (and unnecessary) for clocks
191 * with 0 or 1 parents.
192 *
193 * @set_rate: Change the rate of this clock. The requested rate is specified
194 * by the second argument, which should typically be the return
195 * of .determine_rate call. The third argument gives the parent
196 * rate which is likely helpful for most .set_rate implementation.
197 * Returns 0 on success, -EERROR otherwise.
198 *
199 * @set_rate_and_parent: Change the rate and the parent of this clock. The
200 * requested rate is specified by the second argument, which
201 * should typically be the return of clk_round_rate() call. The
202 * third argument gives the parent rate which is likely helpful
203 * for most .set_rate_and_parent implementation. The fourth
204 * argument gives the parent index. This callback is optional (and
205 * unnecessary) for clocks with 0 or 1 parents as well as
206 * for clocks that can tolerate switching the rate and the parent
207 * separately via calls to .set_parent and .set_rate.
208 * Returns 0 on success, -EERROR otherwise.
209 *
210 * @set_spread_spectrum: Optional callback used to configure the spread
211 * spectrum modulation frequency, percentage, and method
212 * to reduce EMI by spreading the clock frequency over a
213 * wider range.
214 * Returns 0 on success, -EERROR otherwise.
215 *
216 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
217 * is expressed in ppb (parts per billion). The parent accuracy is
218 * an input parameter.
219 * Returns the calculated accuracy. Optional - if this op is not
220 * set then clock accuracy will be initialized to parent accuracy
221 * or 0 (perfect clock) if clock has no parent.
222 *
223 * @get_phase: Queries the hardware to get the current phase of a clock.
224 * Returned values are 0-359 degrees on success, negative
225 * error codes on failure.
226 *
227 * @set_phase: Shift the phase this clock signal in degrees specified
228 * by the second argument. Valid values for degrees are
229 * 0-359. Return 0 on success, otherwise -EERROR.
230 *
231 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
232 * of a clock. Returned values denominator cannot be 0 and must be
233 * superior or equal to the numerator.
234 *
235 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
236 * the numerator (2nd argurment) and denominator (3rd argument).
237 * Argument must be a valid ratio (denominator > 0
238 * and >= numerator) Return 0 on success, otherwise -EERROR.
239 *
240 * @init: Perform platform-specific initialization magic.
241 * This is not used by any of the basic clock types.
242 * This callback exist for HW which needs to perform some
243 * initialisation magic for CCF to get an accurate view of the
244 * clock. It may also be used dynamic resource allocation is
245 * required. It shall not used to deal with clock parameters,
246 * such as rate or parents.
247 * Returns 0 on success, -EERROR otherwise.
248 *
249 * @terminate: Free any resource allocated by init.
250 *
251 * @debug_init: Set up type-specific debugfs entries for this clock. This
252 * is called once, after the debugfs directory entry for this
253 * clock has been created. The dentry pointer representing that
254 * directory is provided as an argument. Called with
255 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
256 *
257 *
258 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
259 * implementations to split any work between atomic (enable) and sleepable
260 * (prepare) contexts. If enabling a clock requires code that might sleep,
261 * this must be done in clk_prepare. Clock enable code that will never be
262 * called in a sleepable context may be implemented in clk_enable.
263 *
264 * Typically, drivers will call clk_prepare when a clock may be needed later
265 * (eg. when a device is opened), and clk_enable when the clock is actually
266 * required (eg. from an interrupt). Note that clk_prepare MUST have been
267 * called before clk_enable.
268 */
269 struct clk_ops {
270 int (*prepare)(struct clk_hw *hw);
271 void (*unprepare)(struct clk_hw *hw);
272 int (*is_prepared)(struct clk_hw *hw);
273 void (*unprepare_unused)(struct clk_hw *hw);
274 int (*enable)(struct clk_hw *hw);
275 void (*disable)(struct clk_hw *hw);
276 int (*is_enabled)(struct clk_hw *hw);
277 void (*disable_unused)(struct clk_hw *hw);
278 int (*save_context)(struct clk_hw *hw);
279 void (*restore_context)(struct clk_hw *hw);
280 unsigned long (*recalc_rate)(struct clk_hw *hw,
281 unsigned long parent_rate);
282 int (*determine_rate)(struct clk_hw *hw,
283 struct clk_rate_request *req);
284 int (*set_parent)(struct clk_hw *hw, u8 index);
285 u8 (*get_parent)(struct clk_hw *hw);
286 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
287 unsigned long parent_rate);
288 int (*set_rate_and_parent)(struct clk_hw *hw,
289 unsigned long rate,
290 unsigned long parent_rate, u8 index);
291 int (*set_spread_spectrum)(struct clk_hw *hw,
292 const struct clk_spread_spectrum *ss_conf);
293 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
294 unsigned long parent_accuracy);
295 int (*get_phase)(struct clk_hw *hw);
296 int (*set_phase)(struct clk_hw *hw, int degrees);
297 int (*get_duty_cycle)(struct clk_hw *hw,
298 struct clk_duty *duty);
299 int (*set_duty_cycle)(struct clk_hw *hw,
300 struct clk_duty *duty);
301 int (*init)(struct clk_hw *hw);
302 void (*terminate)(struct clk_hw *hw);
303 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
304 };
305
306 /**
307 * struct clk_parent_data - clk parent information
308 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
309 * @fw_name: parent name local to provider registering clk
310 * @name: globally unique parent name (used as a fallback)
311 * @index: parent index local to provider registering clk (if @fw_name absent)
312 */
313 struct clk_parent_data {
314 const struct clk_hw *hw;
315 const char *fw_name;
316 const char *name;
317 int index;
318 };
319
320 /**
321 * struct clk_init_data - holds init data that's common to all clocks and is
322 * shared between the clock provider and the common clock framework.
323 *
324 * @name: clock name
325 * @ops: operations this clock supports
326 * @parent_names: array of string names for all possible parents
327 * @parent_data: array of parent data for all possible parents (when some
328 * parents are external to the clk controller)
329 * @parent_hws: array of pointers to all possible parents (when all parents
330 * are internal to the clk controller)
331 * @num_parents: number of possible parents
332 * @flags: framework-level hints and quirks
333 */
334 struct clk_init_data {
335 const char *name;
336 const struct clk_ops *ops;
337 /* Only one of the following three should be assigned */
338 const char * const *parent_names;
339 const struct clk_parent_data *parent_data;
340 const struct clk_hw **parent_hws;
341 u8 num_parents;
342 unsigned long flags;
343 };
344
345 /**
346 * struct clk_hw - handle for traversing from a struct clk to its corresponding
347 * hardware-specific structure. struct clk_hw should be declared within struct
348 * clk_foo and then referenced by the struct clk instance that uses struct
349 * clk_foo's clk_ops
350 *
351 * @core: pointer to the struct clk_core instance that points back to this
352 * struct clk_hw instance
353 *
354 * @clk: pointer to the per-user struct clk instance that can be used to call
355 * into the clk API
356 *
357 * @init: pointer to struct clk_init_data that contains the init data shared
358 * with the common clock framework. This pointer will be set to NULL once
359 * a clk_register() variant is called on this clk_hw pointer.
360 */
361 struct clk_hw {
362 struct clk_core *core;
363 struct clk *clk;
364 const struct clk_init_data *init;
365 };
366
367 /*
368 * DOC: Basic clock implementations common to many platforms
369 *
370 * Each basic clock hardware type is comprised of a structure describing the
371 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
372 * unique flags for that hardware type, a registration function and an
373 * alternative macro for static initialization
374 */
375
376 /**
377 * struct clk_fixed_rate - fixed-rate clock
378 * @hw: handle between common and hardware-specific interfaces
379 * @fixed_rate: constant frequency of clock
380 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
381 * @flags: hardware specific flags
382 *
383 * Flags:
384 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
385 * instead of what's set in @fixed_accuracy.
386 */
387 struct clk_fixed_rate {
388 struct clk_hw hw;
389 unsigned long fixed_rate;
390 unsigned long fixed_accuracy;
391 unsigned long flags;
392 };
393
394 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
395
396 extern const struct clk_ops clk_fixed_rate_ops;
397 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
398 struct device_node *np, const char *name,
399 const char *parent_name, const struct clk_hw *parent_hw,
400 const struct clk_parent_data *parent_data, unsigned long flags,
401 unsigned long fixed_rate, unsigned long fixed_accuracy,
402 unsigned long clk_fixed_flags, bool devm);
403 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
404 const char *parent_name, unsigned long flags,
405 unsigned long fixed_rate);
406 /**
407 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
408 * framework
409 * @dev: device that is registering this clock
410 * @name: name of this clock
411 * @parent_name: name of clock's parent
412 * @flags: framework-specific flags
413 * @fixed_rate: non-adjustable clock rate
414 */
415 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
416 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
417 NULL, (flags), (fixed_rate), 0, 0, false)
418
419 /**
420 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
421 * framework
422 * @dev: device that is registering this clock
423 * @name: name of this clock
424 * @parent_name: name of clock's parent
425 * @flags: framework-specific flags
426 * @fixed_rate: non-adjustable clock rate
427 */
428 #define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
429 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
430 NULL, (flags), (fixed_rate), 0, 0, true)
431 /**
432 * devm_clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
433 * the clock framework
434 * @dev: device that is registering this clock
435 * @name: name of this clock
436 * @parent_data: parent clk data
437 * @flags: framework-specific flags
438 * @fixed_rate: non-adjustable clock rate
439 */
440 #define devm_clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \
441 fixed_rate) \
442 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
443 (parent_data), (flags), (fixed_rate), 0, \
444 0, true)
445 /**
446 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
447 * the clock framework
448 * @dev: device that is registering this clock
449 * @name: name of this clock
450 * @parent_hw: pointer to parent clk
451 * @flags: framework-specific flags
452 * @fixed_rate: non-adjustable clock rate
453 */
454 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
455 fixed_rate) \
456 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
457 NULL, (flags), (fixed_rate), 0, 0, false)
458 /**
459 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
460 * the clock framework
461 * @dev: device that is registering this clock
462 * @name: name of this clock
463 * @parent_data: parent clk data
464 * @flags: framework-specific flags
465 * @fixed_rate: non-adjustable clock rate
466 */
467 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \
468 fixed_rate) \
469 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
470 (parent_data), (flags), (fixed_rate), 0, \
471 0, false)
472 /**
473 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
474 * the clock framework
475 * @dev: device that is registering this clock
476 * @name: name of this clock
477 * @parent_name: name of clock's parent
478 * @flags: framework-specific flags
479 * @fixed_rate: non-adjustable clock rate
480 * @fixed_accuracy: non-adjustable clock accuracy
481 */
482 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
483 flags, fixed_rate, \
484 fixed_accuracy) \
485 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
486 NULL, NULL, (flags), (fixed_rate), \
487 (fixed_accuracy), 0, false)
488 /**
489 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
490 * clock with the clock framework
491 * @dev: device that is registering this clock
492 * @name: name of this clock
493 * @parent_hw: pointer to parent clk
494 * @flags: framework-specific flags
495 * @fixed_rate: non-adjustable clock rate
496 * @fixed_accuracy: non-adjustable clock accuracy
497 */
498 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
499 parent_hw, flags, fixed_rate, fixed_accuracy) \
500 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
501 NULL, (flags), (fixed_rate), \
502 (fixed_accuracy), 0, false)
503 /**
504 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
505 * clock with the clock framework
506 * @dev: device that is registering this clock
507 * @name: name of this clock
508 * @parent_data: name of clock's parent
509 * @flags: framework-specific flags
510 * @fixed_rate: non-adjustable clock rate
511 * @fixed_accuracy: non-adjustable clock accuracy
512 */
513 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
514 parent_data, flags, fixed_rate, fixed_accuracy) \
515 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
516 (parent_data), NULL, (flags), \
517 (fixed_rate), (fixed_accuracy), 0, false)
518 /**
519 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
520 * the clock framework
521 * @dev: device that is registering this clock
522 * @name: name of this clock
523 * @parent_data: name of clock's parent
524 * @flags: framework-specific flags
525 * @fixed_rate: non-adjustable clock rate
526 */
527 #define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \
528 flags, fixed_rate) \
529 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
530 (parent_data), (flags), (fixed_rate), 0, \
531 CLK_FIXED_RATE_PARENT_ACCURACY, false)
532
533 void clk_unregister_fixed_rate(struct clk *clk);
534 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
535
536 void of_fixed_clk_setup(struct device_node *np);
537
538 /**
539 * struct clk_gate - gating clock
540 *
541 * @hw: handle between common and hardware-specific interfaces
542 * @reg: register controlling gate
543 * @bit_idx: single bit controlling gate
544 * @flags: hardware-specific flags
545 * @lock: register lock
546 *
547 * Clock which can gate its output. Implements .enable & .disable
548 *
549 * Flags:
550 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
551 * enable the clock. Setting this flag does the opposite: setting the bit
552 * disable the clock and clearing it enables the clock
553 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
554 * of this register, and mask of gate bits are in higher 16-bit of this
555 * register. While setting the gate bits, higher 16-bit should also be
556 * updated to indicate changing gate bits.
557 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
558 * the gate register. Setting this flag makes the register accesses big
559 * endian.
560 */
561 struct clk_gate {
562 struct clk_hw hw;
563 void __iomem *reg;
564 u8 bit_idx;
565 u8 flags;
566 spinlock_t *lock;
567 };
568
569 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
570
571 #define CLK_GATE_SET_TO_DISABLE BIT(0)
572 #define CLK_GATE_HIWORD_MASK BIT(1)
573 #define CLK_GATE_BIG_ENDIAN BIT(2)
574
575 extern const struct clk_ops clk_gate_ops;
576 struct clk_hw *__clk_hw_register_gate(struct device *dev,
577 struct device_node *np, const char *name,
578 const char *parent_name, const struct clk_hw *parent_hw,
579 const struct clk_parent_data *parent_data,
580 unsigned long flags,
581 void __iomem *reg, u8 bit_idx,
582 u8 clk_gate_flags, spinlock_t *lock);
583 struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
584 struct device_node *np, const char *name,
585 const char *parent_name, const struct clk_hw *parent_hw,
586 const struct clk_parent_data *parent_data,
587 unsigned long flags,
588 void __iomem *reg, u8 bit_idx,
589 u8 clk_gate_flags, spinlock_t *lock);
590 struct clk *clk_register_gate(struct device *dev, const char *name,
591 const char *parent_name, unsigned long flags,
592 void __iomem *reg, u8 bit_idx,
593 u8 clk_gate_flags, spinlock_t *lock);
594 /**
595 * clk_hw_register_gate - register a gate clock with the clock framework
596 * @dev: device that is registering this clock
597 * @name: name of this clock
598 * @parent_name: name of this clock's parent
599 * @flags: framework-specific flags for this clock
600 * @reg: register address to control gating of this clock
601 * @bit_idx: which bit in the register controls gating of this clock
602 * @clk_gate_flags: gate-specific flags for this clock
603 * @lock: shared register lock for this clock
604 */
605 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
606 clk_gate_flags, lock) \
607 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
608 NULL, (flags), (reg), (bit_idx), \
609 (clk_gate_flags), (lock))
610 /**
611 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
612 * framework
613 * @dev: device that is registering this clock
614 * @name: name of this clock
615 * @parent_hw: pointer to parent clk
616 * @flags: framework-specific flags for this clock
617 * @reg: register address to control gating of this clock
618 * @bit_idx: which bit in the register controls gating of this clock
619 * @clk_gate_flags: gate-specific flags for this clock
620 * @lock: shared register lock for this clock
621 */
622 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
623 bit_idx, clk_gate_flags, lock) \
624 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
625 NULL, (flags), (reg), (bit_idx), \
626 (clk_gate_flags), (lock))
627 /**
628 * clk_hw_register_gate_parent_data - register a gate clock with the clock
629 * framework
630 * @dev: device that is registering this clock
631 * @name: name of this clock
632 * @parent_data: parent clk data
633 * @flags: framework-specific flags for this clock
634 * @reg: register address to control gating of this clock
635 * @bit_idx: which bit in the register controls gating of this clock
636 * @clk_gate_flags: gate-specific flags for this clock
637 * @lock: shared register lock for this clock
638 */
639 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
640 bit_idx, clk_gate_flags, lock) \
641 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
642 (flags), (reg), (bit_idx), \
643 (clk_gate_flags), (lock))
644 /**
645 * devm_clk_hw_register_gate - register a gate clock with the clock framework
646 * @dev: device that is registering this clock
647 * @name: name of this clock
648 * @parent_name: name of this clock's parent
649 * @flags: framework-specific flags for this clock
650 * @reg: register address to control gating of this clock
651 * @bit_idx: which bit in the register controls gating of this clock
652 * @clk_gate_flags: gate-specific flags for this clock
653 * @lock: shared register lock for this clock
654 */
655 #define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\
656 clk_gate_flags, lock) \
657 __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
658 NULL, (flags), (reg), (bit_idx), \
659 (clk_gate_flags), (lock))
660 /**
661 * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock
662 * framework
663 * @dev: device that is registering this clock
664 * @name: name of this clock
665 * @parent_hw: pointer to parent clk
666 * @flags: framework-specific flags for this clock
667 * @reg: register address to control gating of this clock
668 * @bit_idx: which bit in the register controls gating of this clock
669 * @clk_gate_flags: gate-specific flags for this clock
670 * @lock: shared register lock for this clock
671 */
672 #define devm_clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, \
673 reg, bit_idx, clk_gate_flags, \
674 lock) \
675 __devm_clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
676 NULL, (flags), (reg), (bit_idx), \
677 (clk_gate_flags), (lock))
678 /**
679 * devm_clk_hw_register_gate_parent_data - register a gate clock with the
680 * clock framework
681 * @dev: device that is registering this clock
682 * @name: name of this clock
683 * @parent_data: parent clk data
684 * @flags: framework-specific flags for this clock
685 * @reg: register address to control gating of this clock
686 * @bit_idx: which bit in the register controls gating of this clock
687 * @clk_gate_flags: gate-specific flags for this clock
688 * @lock: shared register lock for this clock
689 */
690 #define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \
691 reg, bit_idx, clk_gate_flags, \
692 lock) \
693 __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \
694 (parent_data), (flags), (reg), (bit_idx), \
695 (clk_gate_flags), (lock))
696
697 void clk_unregister_gate(struct clk *clk);
698 void clk_hw_unregister_gate(struct clk_hw *hw);
699 int clk_gate_is_enabled(struct clk_hw *hw);
700
701 struct clk_div_table {
702 unsigned int val;
703 unsigned int div;
704 };
705
706 /**
707 * struct clk_divider - adjustable divider clock
708 *
709 * @hw: handle between common and hardware-specific interfaces
710 * @reg: register containing the divider
711 * @shift: shift to the divider bit field
712 * @width: width of the divider bit field
713 * @table: array of value/divider pairs, last entry should have div = 0
714 * @lock: register lock
715 *
716 * Clock with an adjustable divider affecting its output frequency. Implements
717 * .recalc_rate, .set_rate and .determine_rate
718 *
719 * @flags:
720 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
721 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
722 * the raw value read from the register, with the value of zero considered
723 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
724 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
725 * the hardware register
726 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
727 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
728 * Some hardware implementations gracefully handle this case and allow a
729 * zero divisor by not modifying their input clock
730 * (divide by one / bypass).
731 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
732 * of this register, and mask of divider bits are in higher 16-bit of this
733 * register. While setting the divider bits, higher 16-bit should also be
734 * updated to indicate changing divider bits.
735 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
736 * to the closest integer instead of the up one.
737 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
738 * not be changed by the clock framework.
739 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
740 * except when the value read from the register is zero, the divisor is
741 * 2^width of the field.
742 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
743 * for the divider register. Setting this flag makes the register accesses
744 * big endian.
745 * CLK_DIVIDER_EVEN_INTEGERS - clock divisor is 2, 4, 6, 8, 10, etc.
746 * Formula is 2 * (value read from hardware + 1).
747 */
748 struct clk_divider {
749 struct clk_hw hw;
750 void __iomem *reg;
751 u8 shift;
752 u8 width;
753 u16 flags;
754 const struct clk_div_table *table;
755 spinlock_t *lock;
756 };
757
758 #define clk_div_mask(width) ((1 << (width)) - 1)
759 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
760
761 #define CLK_DIVIDER_ONE_BASED BIT(0)
762 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
763 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
764 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
765 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
766 #define CLK_DIVIDER_READ_ONLY BIT(5)
767 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
768 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
769 #define CLK_DIVIDER_EVEN_INTEGERS BIT(8)
770
771 extern const struct clk_ops clk_divider_ops;
772 extern const struct clk_ops clk_divider_ro_ops;
773
774 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
775 unsigned int val, const struct clk_div_table *table,
776 unsigned long flags, unsigned long width);
777 int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
778 const struct clk_div_table *table, u8 width,
779 unsigned long flags);
780 int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
781 const struct clk_div_table *table, u8 width,
782 unsigned long flags, unsigned int val);
783 int divider_get_val(unsigned long rate, unsigned long parent_rate,
784 const struct clk_div_table *table, u8 width,
785 unsigned long flags);
786
787 struct clk_hw *__clk_hw_register_divider(struct device *dev,
788 struct device_node *np, const char *name,
789 const char *parent_name, const struct clk_hw *parent_hw,
790 const struct clk_parent_data *parent_data, unsigned long flags,
791 void __iomem *reg, u8 shift, u8 width,
792 unsigned long clk_divider_flags,
793 const struct clk_div_table *table, spinlock_t *lock);
794 struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
795 struct device_node *np, const char *name,
796 const char *parent_name, const struct clk_hw *parent_hw,
797 const struct clk_parent_data *parent_data, unsigned long flags,
798 void __iomem *reg, u8 shift, u8 width,
799 unsigned long clk_divider_flags,
800 const struct clk_div_table *table, spinlock_t *lock);
801 struct clk *clk_register_divider_table(struct device *dev, const char *name,
802 const char *parent_name, unsigned long flags,
803 void __iomem *reg, u8 shift, u8 width,
804 unsigned long clk_divider_flags,
805 const struct clk_div_table *table, spinlock_t *lock);
806 /**
807 * clk_register_divider - register a divider clock with the clock framework
808 * @dev: device registering this clock
809 * @name: name of this clock
810 * @parent_name: name of clock's parent
811 * @flags: framework-specific flags
812 * @reg: register address to adjust divider
813 * @shift: number of bits to shift the bitfield
814 * @width: width of the bitfield
815 * @clk_divider_flags: divider-specific flags for this clock
816 * @lock: shared register lock for this clock
817 */
818 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
819 clk_divider_flags, lock) \
820 clk_register_divider_table((dev), (name), (parent_name), (flags), \
821 (reg), (shift), (width), \
822 (clk_divider_flags), NULL, (lock))
823 /**
824 * clk_hw_register_divider - register a divider clock with the clock framework
825 * @dev: device registering this clock
826 * @name: name of this clock
827 * @parent_name: name of clock's parent
828 * @flags: framework-specific flags
829 * @reg: register address to adjust divider
830 * @shift: number of bits to shift the bitfield
831 * @width: width of the bitfield
832 * @clk_divider_flags: divider-specific flags for this clock
833 * @lock: shared register lock for this clock
834 */
835 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
836 width, clk_divider_flags, lock) \
837 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
838 NULL, (flags), (reg), (shift), (width), \
839 (clk_divider_flags), NULL, (lock))
840 /**
841 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
842 * framework
843 * @dev: device registering this clock
844 * @name: name of this clock
845 * @parent_hw: pointer to parent clk
846 * @flags: framework-specific flags
847 * @reg: register address to adjust divider
848 * @shift: number of bits to shift the bitfield
849 * @width: width of the bitfield
850 * @clk_divider_flags: divider-specific flags for this clock
851 * @lock: shared register lock for this clock
852 */
853 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
854 shift, width, clk_divider_flags, \
855 lock) \
856 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
857 NULL, (flags), (reg), (shift), (width), \
858 (clk_divider_flags), NULL, (lock))
859 /**
860 * clk_hw_register_divider_parent_data - register a divider clock with the clock
861 * framework
862 * @dev: device registering this clock
863 * @name: name of this clock
864 * @parent_data: parent clk data
865 * @flags: framework-specific flags
866 * @reg: register address to adjust divider
867 * @shift: number of bits to shift the bitfield
868 * @width: width of the bitfield
869 * @clk_divider_flags: divider-specific flags for this clock
870 * @lock: shared register lock for this clock
871 */
872 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
873 reg, shift, width, \
874 clk_divider_flags, lock) \
875 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
876 (parent_data), (flags), (reg), (shift), \
877 (width), (clk_divider_flags), NULL, (lock))
878 /**
879 * clk_hw_register_divider_table - register a table based divider clock with
880 * the clock framework
881 * @dev: device registering this clock
882 * @name: name of this clock
883 * @parent_name: name of clock's parent
884 * @flags: framework-specific flags
885 * @reg: register address to adjust divider
886 * @shift: number of bits to shift the bitfield
887 * @width: width of the bitfield
888 * @clk_divider_flags: divider-specific flags for this clock
889 * @table: array of divider/value pairs ending with a div set to 0
890 * @lock: shared register lock for this clock
891 */
892 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
893 shift, width, clk_divider_flags, table, \
894 lock) \
895 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
896 NULL, (flags), (reg), (shift), (width), \
897 (clk_divider_flags), (table), (lock))
898 /**
899 * clk_hw_register_divider_table_parent_hw - register a table based divider
900 * clock with the clock framework
901 * @dev: device registering this clock
902 * @name: name of this clock
903 * @parent_hw: pointer to parent clk
904 * @flags: framework-specific flags
905 * @reg: register address to adjust divider
906 * @shift: number of bits to shift the bitfield
907 * @width: width of the bitfield
908 * @clk_divider_flags: divider-specific flags for this clock
909 * @table: array of divider/value pairs ending with a div set to 0
910 * @lock: shared register lock for this clock
911 */
912 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
913 reg, shift, width, \
914 clk_divider_flags, table, \
915 lock) \
916 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
917 NULL, (flags), (reg), (shift), (width), \
918 (clk_divider_flags), (table), (lock))
919 /**
920 * clk_hw_register_divider_table_parent_data - register a table based divider
921 * clock with the clock framework
922 * @dev: device registering this clock
923 * @name: name of this clock
924 * @parent_data: parent clk data
925 * @flags: framework-specific flags
926 * @reg: register address to adjust divider
927 * @shift: number of bits to shift the bitfield
928 * @width: width of the bitfield
929 * @clk_divider_flags: divider-specific flags for this clock
930 * @table: array of divider/value pairs ending with a div set to 0
931 * @lock: shared register lock for this clock
932 */
933 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
934 flags, reg, shift, width, \
935 clk_divider_flags, table, \
936 lock) \
937 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
938 (parent_data), (flags), (reg), (shift), \
939 (width), (clk_divider_flags), (table), \
940 (lock))
941 /**
942 * devm_clk_hw_register_divider - register a divider clock with the clock framework
943 * @dev: device registering this clock
944 * @name: name of this clock
945 * @parent_name: name of clock's parent
946 * @flags: framework-specific flags
947 * @reg: register address to adjust divider
948 * @shift: number of bits to shift the bitfield
949 * @width: width of the bitfield
950 * @clk_divider_flags: divider-specific flags for this clock
951 * @lock: shared register lock for this clock
952 */
953 #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
954 width, clk_divider_flags, lock) \
955 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
956 NULL, (flags), (reg), (shift), (width), \
957 (clk_divider_flags), NULL, (lock))
958 /**
959 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
960 * @dev: device registering this clock
961 * @name: name of this clock
962 * @parent_hw: pointer to parent clk
963 * @flags: framework-specific flags
964 * @reg: register address to adjust divider
965 * @shift: number of bits to shift the bitfield
966 * @width: width of the bitfield
967 * @clk_divider_flags: divider-specific flags for this clock
968 * @lock: shared register lock for this clock
969 */
970 #define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \
971 reg, shift, width, \
972 clk_divider_flags, lock) \
973 __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \
974 (parent_hw), NULL, (flags), (reg), \
975 (shift), (width), (clk_divider_flags), \
976 NULL, (lock))
977 /**
978 * devm_clk_hw_register_divider_parent_data - register a divider clock with the
979 * clock framework
980 * @dev: device registering this clock
981 * @name: name of this clock
982 * @parent_data: parent clk data
983 * @flags: framework-specific flags
984 * @reg: register address to adjust divider
985 * @shift: number of bits to shift the bitfield
986 * @width: width of the bitfield
987 * @clk_divider_flags: divider-specific flags for this clock
988 * @lock: shared register lock for this clock
989 */
990 #define devm_clk_hw_register_divider_parent_data(dev, name, parent_data, \
991 flags, reg, shift, width, \
992 clk_divider_flags, lock) \
993 __devm_clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
994 (parent_data), (flags), (reg), (shift), \
995 (width), (clk_divider_flags), NULL, \
996 (lock))
997 /**
998 * devm_clk_hw_register_divider_table - register a table based divider clock
999 * with the clock framework (devres variant)
1000 * @dev: device registering this clock
1001 * @name: name of this clock
1002 * @parent_name: name of clock's parent
1003 * @flags: framework-specific flags
1004 * @reg: register address to adjust divider
1005 * @shift: number of bits to shift the bitfield
1006 * @width: width of the bitfield
1007 * @clk_divider_flags: divider-specific flags for this clock
1008 * @table: array of divider/value pairs ending with a div set to 0
1009 * @lock: shared register lock for this clock
1010 */
1011 #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \
1012 reg, shift, width, \
1013 clk_divider_flags, table, lock) \
1014 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \
1015 NULL, NULL, (flags), (reg), (shift), \
1016 (width), (clk_divider_flags), (table), \
1017 (lock))
1018
1019 void clk_unregister_divider(struct clk *clk);
1020 void clk_hw_unregister_divider(struct clk_hw *hw);
1021
1022 /**
1023 * struct clk_mux - multiplexer clock
1024 *
1025 * @hw: handle between common and hardware-specific interfaces
1026 * @reg: register controlling multiplexer
1027 * @table: array of register values corresponding to the parent index
1028 * @shift: shift to multiplexer bit field
1029 * @mask: mask of mutliplexer bit field
1030 * @flags: hardware-specific flags
1031 * @lock: register lock
1032 *
1033 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
1034 * and .recalc_rate
1035 *
1036 * Flags:
1037 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
1038 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
1039 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
1040 * register, and mask of mux bits are in higher 16-bit of this register.
1041 * While setting the mux bits, higher 16-bit should also be updated to
1042 * indicate changing mux bits.
1043 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
1044 * .get_parent clk_op.
1045 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
1046 * frequency.
1047 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
1048 * the mux register. Setting this flag makes the register accesses big
1049 * endian.
1050 */
1051 struct clk_mux {
1052 struct clk_hw hw;
1053 void __iomem *reg;
1054 const u32 *table;
1055 u32 mask;
1056 u8 shift;
1057 u8 flags;
1058 spinlock_t *lock;
1059 };
1060
1061 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
1062
1063 #define CLK_MUX_INDEX_ONE BIT(0)
1064 #define CLK_MUX_INDEX_BIT BIT(1)
1065 #define CLK_MUX_HIWORD_MASK BIT(2)
1066 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
1067 #define CLK_MUX_ROUND_CLOSEST BIT(4)
1068 #define CLK_MUX_BIG_ENDIAN BIT(5)
1069
1070 extern const struct clk_ops clk_mux_ops;
1071 extern const struct clk_ops clk_mux_ro_ops;
1072
1073 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
1074 const char *name, u8 num_parents,
1075 const char * const *parent_names,
1076 const struct clk_hw **parent_hws,
1077 const struct clk_parent_data *parent_data,
1078 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1079 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
1080 struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
1081 const char *name, u8 num_parents,
1082 const char * const *parent_names,
1083 const struct clk_hw **parent_hws,
1084 const struct clk_parent_data *parent_data,
1085 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1086 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
1087 struct clk *clk_register_mux_table(struct device *dev, const char *name,
1088 const char * const *parent_names, u8 num_parents,
1089 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1090 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
1091
1092 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1093 shift, width, clk_mux_flags, lock) \
1094 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
1095 (flags), (reg), (shift), BIT((width)) - 1, \
1096 (clk_mux_flags), NULL, (lock))
1097 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
1098 flags, reg, shift, mask, clk_mux_flags, \
1099 table, lock) \
1100 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1101 (parent_names), NULL, NULL, (flags), (reg), \
1102 (shift), (mask), (clk_mux_flags), (table), \
1103 (lock))
1104 #define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \
1105 num_parents, flags, reg, shift, mask, \
1106 clk_mux_flags, table, lock) \
1107 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1108 NULL, NULL, (parent_data), (flags), (reg), \
1109 (shift), (mask), (clk_mux_flags), (table), \
1110 (lock))
1111 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1112 shift, width, clk_mux_flags, lock) \
1113 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1114 (parent_names), NULL, NULL, (flags), (reg), \
1115 (shift), BIT((width)) - 1, (clk_mux_flags), \
1116 NULL, (lock))
1117 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
1118 reg, shift, width, clk_mux_flags, lock) \
1119 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1120 (parent_hws), NULL, (flags), (reg), (shift), \
1121 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1122 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
1123 flags, reg, shift, width, \
1124 clk_mux_flags, lock) \
1125 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
1126 (parent_data), (flags), (reg), (shift), \
1127 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1128 #define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
1129 num_parents, flags, reg, shift, \
1130 width, clk_mux_flags, table, \
1131 lock) \
1132 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
1133 (parent_data), (flags), (reg), (shift), \
1134 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1135 #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1136 shift, width, clk_mux_flags, lock) \
1137 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1138 (parent_names), NULL, NULL, (flags), (reg), \
1139 (shift), BIT((width)) - 1, (clk_mux_flags), \
1140 NULL, (lock))
1141 #define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \
1142 num_parents, flags, reg, shift, \
1143 width, clk_mux_flags, lock) \
1144 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1145 (parent_hws), NULL, (flags), (reg), \
1146 (shift), BIT((width)) - 1, \
1147 (clk_mux_flags), NULL, (lock))
1148 #define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
1149 num_parents, flags, reg, shift, \
1150 width, clk_mux_flags, table, \
1151 lock) \
1152 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1153 NULL, (parent_data), (flags), (reg), (shift), \
1154 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1155
1156 int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
1157 unsigned int val);
1158 unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index);
1159
1160 void clk_unregister_mux(struct clk *clk);
1161 void clk_hw_unregister_mux(struct clk_hw *hw);
1162
1163 void of_fixed_factor_clk_setup(struct device_node *node);
1164
1165 /**
1166 * struct clk_fixed_factor - fixed multiplier and divider clock
1167 *
1168 * @hw: handle between common and hardware-specific interfaces
1169 * @mult: multiplier
1170 * @div: divider
1171 * @acc: fixed accuracy in ppb
1172 * @flags: behavior modifying flags
1173 *
1174 * Clock with a fixed multiplier and divider. The output frequency is the
1175 * parent clock rate divided by div and multiplied by mult.
1176 * Implements .recalc_rate, .set_rate, .determine_rate and .recalc_accuracy
1177 *
1178 * Flags:
1179 * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the
1180 * parent clk accuracy.
1181 */
1182
1183 struct clk_fixed_factor {
1184 struct clk_hw hw;
1185 unsigned int mult;
1186 unsigned int div;
1187 unsigned long acc;
1188 unsigned int flags;
1189 };
1190
1191 #define CLK_FIXED_FACTOR_FIXED_ACCURACY BIT(0)
1192
1193 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
1194
1195 extern const struct clk_ops clk_fixed_factor_ops;
1196 struct clk_hw *
1197 __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
1198 const char *name, const char *parent_name,
1199 const struct clk_hw *parent_hw, const struct clk_parent_data *pdata,
1200 unsigned long flags, unsigned int mult, unsigned int div,
1201 unsigned long acc, unsigned int fixflags, bool devm);
1202 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
1203 const char *parent_name, unsigned long flags,
1204 unsigned int mult, unsigned int div);
1205 void clk_unregister_fixed_factor(struct clk *clk);
1206 struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
1207 struct device_node *np, const char *name, const char *fw_name,
1208 unsigned long flags, unsigned int mult, unsigned int div);
1209 struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,
1210 struct device_node *np, const char *name, const char *fw_name,
1211 unsigned long flags, unsigned int mult, unsigned int div,
1212 unsigned long acc);
1213 struct clk_hw *clk_hw_register_fixed_factor_index(struct device *dev,
1214 const char *name, unsigned int index, unsigned long flags,
1215 unsigned int mult, unsigned int div);
1216 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
1217 struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,
1218 struct device_node *np, const char *name, const char *fw_name,
1219 unsigned long flags, unsigned int mult, unsigned int div);
1220 struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,
1221 struct device_node *np, const char *name, const char *fw_name,
1222 unsigned long flags, unsigned int mult, unsigned int div,
1223 unsigned long acc);
1224 struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
1225 const char *name, unsigned int index, unsigned long flags,
1226 unsigned int mult, unsigned int div);
1227
1228 #define clk_hw_register_fixed_factor(dev, name, parent_name, \
1229 flags, mult, div) \
1230 __clk_hw_register_fixed_factor((dev), NULL, (name), (parent_name), \
1231 NULL, NULL, (flags), (mult), (div), \
1232 0, 0, false)
1233 #define clk_hw_register_fixed_factor_pdata(dev, np, name, pdata, \
1234 flags, mult, div, acc, fixflags) \
1235 __clk_hw_register_fixed_factor((dev), (np), (name), NULL, NULL, \
1236 (pdata), (flags), (mult), (div), \
1237 (acc), (fixflags), false)
1238 #define devm_clk_hw_register_fixed_factor(dev, name, parent_name, flags, \
1239 mult, div) \
1240 __clk_hw_register_fixed_factor((dev), NULL, (name), (parent_name), \
1241 NULL, NULL, (flags), (mult), (div), 0, \
1242 0, true)
1243 /**
1244 * devm_clk_hw_register_fixed_factor_parent_hw - Register a fixed factor clock with
1245 * pointer to parent clock
1246 * @dev: device that is registering this clock
1247 * @name: name of this clock
1248 * @parent_hw: pointer to parent clk
1249 * @flags: fixed factor flags
1250 * @mult: multiplier
1251 * @div: divider
1252 *
1253 * Return: Pointer to fixed factor clk_hw structure that was registered or
1254 * an error pointer.
1255 */
1256 #define devm_clk_hw_register_fixed_factor_parent_hw(dev, name, parent_hw, \
1257 flags, mult, div) \
1258 __clk_hw_register_fixed_factor((dev), NULL, (name), NULL, \
1259 (parent_hw), NULL, (flags), (mult), \
1260 (div), 0, 0, true)
1261
1262 #define clk_hw_register_fixed_factor_parent_hw(dev, name, parent_hw, flags, \
1263 mult, div) \
1264 __clk_hw_register_fixed_factor((dev), NULL, (name), NULL, \
1265 (parent_hw), NULL, (flags), (mult), \
1266 (div), 0, 0, false)
1267 /**
1268 * struct clk_fractional_divider - adjustable fractional divider clock
1269 *
1270 * @hw: handle between common and hardware-specific interfaces
1271 * @reg: register containing the divider
1272 * @mshift: shift to the numerator bit field
1273 * @mwidth: width of the numerator bit field
1274 * @nshift: shift to the denominator bit field
1275 * @nwidth: width of the denominator bit field
1276 * @approximation: clk driver's callback for calculating the divider clock
1277 * @lock: register lock
1278 *
1279 * Clock with adjustable fractional divider affecting its output frequency.
1280 *
1281 * @flags:
1282 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1283 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
1284 * is set then the numerator and denominator are both the value read
1285 * plus one.
1286 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1287 * used for the divider register. Setting this flag makes the register
1288 * accesses big endian.
1289 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1290 * be saturated and the caller will get quite far from the good enough
1291 * approximation. Instead the caller may require, by setting this flag,
1292 * to shift left by a few bits in case, when the asked one is quite small
1293 * to satisfy the desired range of denominator. It assumes that on the
1294 * caller's side the power-of-two capable prescaler exists.
1295 */
1296 struct clk_fractional_divider {
1297 struct clk_hw hw;
1298 void __iomem *reg;
1299 u8 mshift;
1300 u8 mwidth;
1301 u8 nshift;
1302 u8 nwidth;
1303 u8 flags;
1304 void (*approximation)(struct clk_hw *hw,
1305 unsigned long rate, unsigned long *parent_rate,
1306 unsigned long *m, unsigned long *n);
1307 spinlock_t *lock;
1308 };
1309
1310 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
1311
1312 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
1313 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
1314 #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2)
1315
1316 struct clk *clk_register_fractional_divider(struct device *dev,
1317 const char *name, const char *parent_name, unsigned long flags,
1318 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1319 u8 clk_divider_flags, spinlock_t *lock);
1320 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1321 const char *name, const char *parent_name, unsigned long flags,
1322 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1323 u8 clk_divider_flags, spinlock_t *lock);
1324 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
1325
1326 /**
1327 * struct clk_multiplier - adjustable multiplier clock
1328 *
1329 * @hw: handle between common and hardware-specific interfaces
1330 * @reg: register containing the multiplier
1331 * @shift: shift to the multiplier bit field
1332 * @width: width of the multiplier bit field
1333 * @lock: register lock
1334 *
1335 * Clock with an adjustable multiplier affecting its output frequency.
1336 * Implements .recalc_rate, .set_rate and .determine_rate
1337 *
1338 * @flags:
1339 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1340 * from the register, with 0 being a valid value effectively
1341 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1342 * set, then a null multiplier will be considered as a bypass,
1343 * leaving the parent rate unmodified.
1344 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1345 * rounded to the closest integer instead of the down one.
1346 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1347 * used for the multiplier register. Setting this flag makes the register
1348 * accesses big endian.
1349 */
1350 struct clk_multiplier {
1351 struct clk_hw hw;
1352 void __iomem *reg;
1353 u8 shift;
1354 u8 width;
1355 u8 flags;
1356 spinlock_t *lock;
1357 };
1358
1359 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1360
1361 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1362 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1363 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1364
1365 extern const struct clk_ops clk_multiplier_ops;
1366
1367 /***
1368 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1369 *
1370 * @hw: handle between common and hardware-specific interfaces
1371 * @mux_hw: handle between composite and hardware-specific mux clock
1372 * @rate_hw: handle between composite and hardware-specific rate clock
1373 * @gate_hw: handle between composite and hardware-specific gate clock
1374 * @mux_ops: clock ops for mux
1375 * @rate_ops: clock ops for rate
1376 * @gate_ops: clock ops for gate
1377 */
1378 struct clk_composite {
1379 struct clk_hw hw;
1380 struct clk_ops ops;
1381
1382 struct clk_hw *mux_hw;
1383 struct clk_hw *rate_hw;
1384 struct clk_hw *gate_hw;
1385
1386 const struct clk_ops *mux_ops;
1387 const struct clk_ops *rate_ops;
1388 const struct clk_ops *gate_ops;
1389 };
1390
1391 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1392
1393 struct clk *clk_register_composite(struct device *dev, const char *name,
1394 const char * const *parent_names, int num_parents,
1395 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1396 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1397 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1398 unsigned long flags);
1399 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1400 const struct clk_parent_data *parent_data, int num_parents,
1401 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1402 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1403 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1404 unsigned long flags);
1405 void clk_unregister_composite(struct clk *clk);
1406 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1407 const char * const *parent_names, int num_parents,
1408 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1409 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1410 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1411 unsigned long flags);
1412 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1413 const char *name,
1414 const struct clk_parent_data *parent_data, int num_parents,
1415 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1416 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1417 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1418 unsigned long flags);
1419 struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1420 const char *name, const struct clk_parent_data *parent_data,
1421 int num_parents,
1422 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1423 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1424 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1425 unsigned long flags);
1426 void clk_hw_unregister_composite(struct clk_hw *hw);
1427
1428 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1429 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1430
1431 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1432 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1433 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1434
1435 void clk_unregister(struct clk *clk);
1436
1437 void clk_hw_unregister(struct clk_hw *hw);
1438
1439 /* helper functions */
1440 const char *__clk_get_name(const struct clk *clk);
1441 const char *clk_hw_get_name(const struct clk_hw *hw);
1442
1443 /**
1444 * clk_hw_get_dev() - get device from an hardware clock.
1445 * @hw: the clk_hw pointer to get the struct device from
1446 *
1447 * This is a helper to get the struct device associated with a hardware
1448 * clock. Some clock controllers, such as the one registered with
1449 * CLK_OF_DECLARE(), may have not provided a device pointer while
1450 * registering the clock.
1451 *
1452 * Return: the struct device associated with the clock, or NULL if there
1453 * is none.
1454 */
1455 struct device *clk_hw_get_dev(const struct clk_hw *hw);
1456
1457 /**
1458 * clk_hw_get_of_node() - get device_node from a hardware clock.
1459 * @hw: the clk_hw pointer to get the struct device_node from
1460 *
1461 * This is a helper to get the struct device_node associated with a
1462 * hardware clock.
1463 *
1464 * Return: the struct device_node associated with the clock, or NULL
1465 * if there is none.
1466 */
1467 struct device_node *clk_hw_get_of_node(const struct clk_hw *hw);
1468 #ifdef CONFIG_COMMON_CLK
1469 struct clk_hw *__clk_get_hw(struct clk *clk);
1470 #else
__clk_get_hw(struct clk * clk)1471 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1472 {
1473 return (struct clk_hw *)clk;
1474 }
1475 #endif
1476
1477 struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1478 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1479 const char *con_id);
1480
1481 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1482 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1483 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1484 unsigned int index);
1485 int clk_hw_get_parent_index(struct clk_hw *hw);
1486 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1487 unsigned int __clk_get_enable_count(struct clk *clk);
1488 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1489 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1490 #define clk_hw_can_set_rate_parent(hw) \
1491 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1492
1493 bool clk_hw_is_prepared(const struct clk_hw *hw);
1494 bool clk_hw_is_enabled(const struct clk_hw *hw);
1495 bool __clk_is_enabled(struct clk *clk);
1496 struct clk *__clk_lookup(const char *name);
1497 int __clk_mux_determine_rate(struct clk_hw *hw,
1498 struct clk_rate_request *req);
1499 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1500 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1501 struct clk_rate_request *req);
1502 int clk_mux_determine_rate_flags(struct clk_hw *hw,
1503 struct clk_rate_request *req,
1504 unsigned long flags);
1505 int clk_hw_determine_rate_no_reparent(struct clk_hw *hw,
1506 struct clk_rate_request *req);
1507 int clk_determine_rate_noop(struct clk_hw *hw, struct clk_rate_request *req);
1508 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1509 void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate,
1510 unsigned long *max_rate);
1511 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1512 unsigned long max_rate);
1513 int clk_hw_set_spread_spectrum(struct clk_hw *hw,
1514 const struct clk_spread_spectrum *ss_conf);
1515
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)1516 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1517 {
1518 dst->clk = src->clk;
1519 dst->core = src->core;
1520 }
1521
1522 /*
1523 * FIXME clock api without lock protection
1524 */
1525 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1526
1527 struct clk_onecell_data {
1528 struct clk **clks;
1529 unsigned int clk_num;
1530 };
1531
1532 struct clk_hw_onecell_data {
1533 unsigned int num;
1534 struct clk_hw *hws[] __counted_by(num);
1535 };
1536
1537 #define CLK_OF_DECLARE(name, compat, fn) \
1538 static void __init __##name##_of_clk_init_declare(struct device_node *np) \
1539 { \
1540 fn(np); \
1541 fwnode_dev_initialized(of_fwnode_handle(np), true); \
1542 } \
1543 OF_DECLARE_1(clk, name, compat, __##name##_of_clk_init_declare)
1544
1545 /*
1546 * Use this macro when you have a driver that requires two initialization
1547 * routines, one at of_clk_init(), and one at platform device probe
1548 */
1549 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1550 static void __init name##_of_clk_init_driver(struct device_node *np) \
1551 { \
1552 of_node_clear_flag(np, OF_POPULATED); \
1553 fn(np); \
1554 } \
1555 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1556
1557 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1558 (&(struct clk_init_data) { \
1559 .flags = _flags, \
1560 .name = _name, \
1561 .parent_names = (const char *[]) { _parent }, \
1562 .num_parents = 1, \
1563 .ops = _ops, \
1564 })
1565
1566 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1567 (&(struct clk_init_data) { \
1568 .flags = _flags, \
1569 .name = _name, \
1570 .parent_hws = (const struct clk_hw*[]) { _parent }, \
1571 .num_parents = 1, \
1572 .ops = _ops, \
1573 })
1574
1575 /*
1576 * This macro is intended for drivers to be able to share the otherwise
1577 * individual struct clk_hw[] compound literals created by the compiler
1578 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1579 */
1580 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1581 (&(struct clk_init_data) { \
1582 .flags = _flags, \
1583 .name = _name, \
1584 .parent_hws = _parent, \
1585 .num_parents = 1, \
1586 .ops = _ops, \
1587 })
1588
1589 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1590 (&(struct clk_init_data) { \
1591 .flags = _flags, \
1592 .name = _name, \
1593 .parent_data = (const struct clk_parent_data[]) { \
1594 { .fw_name = _parent }, \
1595 }, \
1596 .num_parents = 1, \
1597 .ops = _ops, \
1598 })
1599
1600 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1601 (&(struct clk_init_data) { \
1602 .flags = _flags, \
1603 .name = _name, \
1604 .parent_names = _parents, \
1605 .num_parents = ARRAY_SIZE(_parents), \
1606 .ops = _ops, \
1607 })
1608
1609 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1610 (&(struct clk_init_data) { \
1611 .flags = _flags, \
1612 .name = _name, \
1613 .parent_hws = _parents, \
1614 .num_parents = ARRAY_SIZE(_parents), \
1615 .ops = _ops, \
1616 })
1617
1618 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1619 (&(struct clk_init_data) { \
1620 .flags = _flags, \
1621 .name = _name, \
1622 .parent_data = _parents, \
1623 .num_parents = ARRAY_SIZE(_parents), \
1624 .ops = _ops, \
1625 })
1626
1627 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1628 (&(struct clk_init_data) { \
1629 .flags = _flags, \
1630 .name = _name, \
1631 .parent_names = NULL, \
1632 .num_parents = 0, \
1633 .ops = _ops, \
1634 })
1635
1636 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1637 _div, _mult, _flags) \
1638 struct clk_fixed_factor _struct = { \
1639 .div = _div, \
1640 .mult = _mult, \
1641 .hw.init = CLK_HW_INIT(_name, \
1642 _parent, \
1643 &clk_fixed_factor_ops, \
1644 _flags), \
1645 }
1646
1647 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1648 _div, _mult, _flags) \
1649 struct clk_fixed_factor _struct = { \
1650 .div = _div, \
1651 .mult = _mult, \
1652 .hw.init = CLK_HW_INIT_HW(_name, \
1653 _parent, \
1654 &clk_fixed_factor_ops, \
1655 _flags), \
1656 }
1657
1658 /*
1659 * This macro allows the driver to reuse the _parent array for multiple
1660 * fixed factor clk declarations.
1661 */
1662 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1663 _div, _mult, _flags) \
1664 struct clk_fixed_factor _struct = { \
1665 .div = _div, \
1666 .mult = _mult, \
1667 .hw.init = CLK_HW_INIT_HWS(_name, \
1668 _parent, \
1669 &clk_fixed_factor_ops, \
1670 _flags), \
1671 }
1672
1673 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1674 _div, _mult, _flags) \
1675 struct clk_fixed_factor _struct = { \
1676 .div = _div, \
1677 .mult = _mult, \
1678 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1679 _parent, \
1680 &clk_fixed_factor_ops, \
1681 _flags), \
1682 }
1683
1684 #ifdef CONFIG_OF
1685 int of_clk_add_provider(struct device_node *np,
1686 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1687 void *data),
1688 void *data);
1689 int of_clk_add_hw_provider(struct device_node *np,
1690 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1691 void *data),
1692 void *data);
1693 int devm_of_clk_add_hw_provider(struct device *dev,
1694 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1695 void *data),
1696 void *data);
1697 void of_clk_del_provider(struct device_node *np);
1698
1699 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1700 void *data);
1701 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1702 void *data);
1703 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1704 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1705 void *data);
1706 int of_clk_parent_fill(struct device_node *np, const char **parents,
1707 unsigned int size);
1708 int of_clk_detect_critical(struct device_node *np, int index,
1709 unsigned long *flags);
1710
1711 #else /* !CONFIG_OF */
1712
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)1713 static inline int of_clk_add_provider(struct device_node *np,
1714 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1715 void *data),
1716 void *data)
1717 {
1718 return 0;
1719 }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1720 static inline int of_clk_add_hw_provider(struct device_node *np,
1721 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1722 void *data),
1723 void *data)
1724 {
1725 return 0;
1726 }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1727 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1728 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1729 void *data),
1730 void *data)
1731 {
1732 return 0;
1733 }
of_clk_del_provider(struct device_node * np)1734 static inline void of_clk_del_provider(struct device_node *np) {}
1735
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)1736 static inline struct clk *of_clk_src_simple_get(
1737 struct of_phandle_args *clkspec, void *data)
1738 {
1739 return ERR_PTR(-ENOENT);
1740 }
1741 static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)1742 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1743 {
1744 return ERR_PTR(-ENOENT);
1745 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)1746 static inline struct clk *of_clk_src_onecell_get(
1747 struct of_phandle_args *clkspec, void *data)
1748 {
1749 return ERR_PTR(-ENOENT);
1750 }
1751 static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)1752 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1753 {
1754 return ERR_PTR(-ENOENT);
1755 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)1756 static inline int of_clk_parent_fill(struct device_node *np,
1757 const char **parents, unsigned int size)
1758 {
1759 return 0;
1760 }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)1761 static inline int of_clk_detect_critical(struct device_node *np, int index,
1762 unsigned long *flags)
1763 {
1764 return 0;
1765 }
1766 #endif /* CONFIG_OF */
1767
1768 void clk_gate_restore_context(struct clk_hw *hw);
1769
1770 #endif /* CLK_PROVIDER_H */
1771