xref: /linux/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi (revision ec71f661a572a770d7c861cd52a50cbbb0e1a8d1) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Copyright (c) 2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Alexander Stein
6 */
7
8/dts-v1/;
9
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12#include <dt-bindings/usb/pd.h>
13#include "imx95.dtsi"
14
15/ {
16	aliases {
17		ethernet0 = &enetc_port0;
18		ethernet1 = &enetc_port1;
19	};
20
21	memory@80000000 {
22		device_type = "memory";
23		/*
24		 * DRAM base addr, size : 2048 MiB DRAM
25		 * should be corrected by bootloader
26		 */
27		reg = <0 0x80000000 0 0x80000000>;
28	};
29
30	reserved-memory {
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34
35		linux_cma: linux,cma {
36			compatible = "shared-dma-pool";
37			reusable;
38			size = <0 0x28000000>;
39			alloc-ranges = <0 0x80000000 0 0x80000000>;
40			linux,cma-default;
41		};
42
43		vpu_boot: vpu_boot@a0000000 {
44			reg = <0 0xa0000000 0 0x100000>;
45			no-map;
46		};
47	};
48
49	clk_dp: clk-dp {
50		compatible = "fixed-clock";
51		#clock-cells = <0>;
52		clock-frequency = <26000000>;
53	};
54
55	clk_xtal25: clk-xtal25 {
56		compatible = "fixed-clock";
57		#clock-cells = <0>;
58		clock-frequency = <25000000>;
59	};
60
61	reg_1v8: regulator-1v8 {
62		compatible = "regulator-fixed";
63		regulator-name = "V_1V8";
64		regulator-min-microvolt = <1800000>;
65		regulator-max-microvolt = <1800000>;
66		regulator-always-on;
67	};
68
69	reg_3v3: regulator-3v3 {
70		compatible = "regulator-fixed";
71		regulator-name = "V_3V3";
72		regulator-min-microvolt = <3300000>;
73		regulator-max-microvolt = <3300000>;
74		regulator-always-on;
75	};
76
77	/* Controlled by system manager */
78	reg_sdvmmc: regulator-sdvmmc {
79		compatible = "regulator-fixed";
80		pinctrl-names = "default";
81		pinctrl-0 = <&pinctrl_sdvmmc>;
82		regulator-name = "SDIO_PWR_EN";
83		regulator-min-microvolt = <3300000>;
84		regulator-max-microvolt = <3300000>;
85		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
86		enable-active-high;
87		status = "disabled";
88	};
89};
90
91&enetc_port0 {
92	pinctrl-names = "default";
93	pinctrl-0 = <&pinctrl_enetc0>;
94	phy-handle = <&ethphy0>;
95	phy-mode = "rgmii-id";
96};
97
98&enetc_port1 {
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_enetc1>;
101	phy-handle = <&ethphy3>;
102	phy-mode = "rgmii-id";
103};
104
105&netc_timer {
106	status = "okay";
107};
108
109&flexspi1 {
110	pinctrl-names = "default", "sleep";
111	pinctrl-0 = <&pinctrl_flexspi1>;
112	pinctrl-1 = <&pinctrl_flexspi1>;
113	status = "okay";
114
115	flash0: flash@0 {
116		compatible = "jedec,spi-nor";
117		reg = <0>;
118		spi-max-frequency = <80000000>;
119		spi-tx-bus-width = <4>;
120		spi-rx-bus-width = <4>;
121		vcc-supply = <&reg_1v8>;
122
123		partitions {
124			compatible = "fixed-partitions";
125			#address-cells = <1>;
126			#size-cells = <1>;
127		};
128	};
129};
130
131&gpio1 {
132	pinctrl-names = "default";
133	pinctrl-0 = <&pinctrl_gpio1>;
134	gpio-line-names = "", "", "", "",
135			  "", "", "", "",
136			  "", "", "GPIO7", "GPIO8",
137			  "", "GPIO9", "", "",
138			  "", "", "", "",
139			  "", "", "", "",
140			  "", "", "", "",
141			  "", "", "", "";
142};
143
144&gpio2 {
145	pinctrl-names = "default";
146	pinctrl-0 = <&pinctrl_gpio2>;
147	gpio-line-names = "", "", "", "",
148			  "", "", "", "",
149			  "", "", "", "",
150			  "", "", "", "",
151			  "", "", "SLEEP", "GPIO5",
152			  "", "", "GPIO6", "",
153			  "", "", "", "",
154			  "", "", "", "";
155};
156
157&lpi2c1 {
158	clock-frequency = <400000>;
159	pinctrl-names = "default", "sleep";
160	pinctrl-0 = <&pinctrl_lpi2c1>;
161	pinctrl-1 = <&pinctrl_lpi2c1>;
162	status = "okay";
163
164	tmp1075: temperature-sensor@4a {
165		compatible = "ti,tmp1075";
166		reg = <0x4a>;
167		vs-supply = <&reg_1v8>;
168	};
169
170	eeprom_smarc: eeprom@50 {
171		compatible = "atmel,24c64";
172		reg = <0x50>;
173		pagesize = <32>;
174		vcc-supply = <&reg_1v8>;
175	};
176
177	pcf85063: rtc@51 {
178		compatible = "nxp,pcf85063a";
179		reg = <0x51>;
180		quartz-load-femtofarads = <7000>;
181		pinctrl-names = "default";
182		pinctrl-0 = <&pinctrl_pcf85063>;
183		interrupt-parent = <&gpio2>;
184		interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
185	};
186
187	m24c64: eeprom@54 {
188		compatible = "atmel,24c64";
189		reg = <0x54>;
190		pagesize = <32>;
191		vcc-supply = <&reg_1v8>;
192	};
193
194	/* protectable identification memory (part of M24C64-D @50) */
195	eeprom@58 {
196		compatible = "atmel,24c64d-wl";
197		reg = <0x58>;
198		vcc-supply = <&reg_1v8>;
199	};
200
201	/* protectable identification memory (part of M24C64-D @54) */
202	eeprom@5c {
203		compatible = "atmel,24c64d-wl";
204		reg = <0x5c>;
205		vcc-supply = <&reg_1v8>;
206	};
207
208	pcieclk: clock-generator@6a {
209		compatible = "renesas,9fgv0441";
210		reg = <0x6a>;
211		clocks = <&clk_xtal25>;
212		#clock-cells = <1>;
213	};
214
215	imu@6b {
216		compatible = "st,ism330dhcx";
217		reg = <0x6b>;
218		vdd-supply = <&reg_3v3>;
219		vddio-supply = <&reg_3v3>;
220	};
221
222	/* D23 */
223	expander2: gpio@74 {
224		compatible = "ti,tca9539";
225		reg = <0x74>;
226		vcc-supply = <&reg_1v8>;
227		gpio-controller;
228		#gpio-cells = <2>;
229		gpio-line-names = "GPIO4", "LCD0_BLKT_EN", "LCD0_VDD_EN", "LCD1_BLKT_EN",
230				  "LCD1_VDD_EN", "ENET1_RESET#", "ENET2_RESET#", "GBE0_SDP_DIR",
231				  "GBE1_SDP_DIR", "PCIE1_RST#", "PCIE2_RST#", "DP_BRIDGE_EN",
232				  "HUB_RST#", "QSPI_RESET#", "PCIE1_CLK_EN", "PCIE2_CLK_EN";
233	};
234
235	/* D21 */
236	expander1: gpio@75 {
237		compatible = "ti,tca9539";
238		reg = <0x75>;
239		vcc-supply = <&reg_1v8>;
240		pinctrl-names = "default";
241		pinctrl-0 = <&pinctrl_expander1>;
242		gpio-controller;
243		#gpio-cells = <2>;
244		interrupt-controller;
245		#interrupt-cells = <2>;
246		interrupt-parent = <&gpio3>;
247		interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
248		gpio-line-names = "GPIO10", "GPIO11", "GPIO12", "GPIO13",
249				  "CHG_PRSNT#", "CHARGING", "LID", "BATLOW#",
250				  "TEMP_EVENT#", "PGOOD_ARM", "PGOOD_SOC", "PCIE_WAKE#_1V8",
251				  "GPIO0", "GPIO1", "GPIO2", "GPIO3";
252	};
253};
254
255/* I2C_CAM0 */
256&lpi2c3 {
257	clock-frequency = <400000>;
258	pinctrl-names = "default", "sleep";
259	pinctrl-0 = <&pinctrl_lpi2c3>;
260	pinctrl-1 = <&pinctrl_lpi2c3>;
261	status = "okay";
262
263	dp_bridge: dp-bridge@f {
264		compatible = "toshiba,tc9595", "toshiba,tc358767";
265		reg = <0x0f>;
266		pinctrl-names = "default";
267		pinctrl-0 = <&pinctrl_tc9595>;
268		clock-names = "ref";
269		clocks = <&clk_dp>;
270		reset-gpios = <&expander2 11 GPIO_ACTIVE_HIGH>;
271		interrupt-parent = <&gpio2>;
272		interrupts = <25 IRQ_TYPE_EDGE_RISING>;
273		toshiba,hpd-pin = <0>;
274		status = "disabled";
275
276		ports {
277			#address-cells = <1>;
278			#size-cells = <0>;
279
280			port@0 {
281				reg = <0>;
282
283				dp_dsi_in: endpoint {
284					/* TODO: DSI out */
285					data-lanes = <1 2 3 4>;
286				};
287			};
288		};
289	};
290};
291
292/* I2C_CAM1 */
293&lpi2c4 {
294	clock-frequency = <400000>;
295	pinctrl-names = "default", "sleep";
296	pinctrl-0 = <&pinctrl_lpi2c4>;
297	pinctrl-1 = <&pinctrl_lpi2c4>;
298	status = "okay";
299};
300
301/* I2C_LCD */
302&lpi2c6 {
303	clock-frequency = <400000>;
304	pinctrl-names = "default", "sleep";
305	pinctrl-0 = <&pinctrl_lpi2c6>;
306	pinctrl-1 = <&pinctrl_lpi2c6>;
307	status = "okay";
308};
309
310/* SER0 */
311&lpuart1 {
312	pinctrl-names = "default";
313	pinctrl-0 = <&pinctrl_lpuart1>;
314};
315
316/* SER3 */
317&lpuart5 {
318	pinctrl-names = "default";
319	pinctrl-0 = <&pinctrl_lpuart5>;
320};
321
322/* SER1 */
323&lpuart7 {
324	pinctrl-names = "default";
325	pinctrl-0 = <&pinctrl_lpuart7>;
326};
327
328/* SER2 */
329&lpuart8 {
330	pinctrl-names = "default";
331	pinctrl-0 = <&pinctrl_lpuart8>;
332};
333
334&netc_blk_ctrl {
335	status = "okay";
336};
337
338&netc_emdio {
339	pinctrl-names = "default";
340	pinctrl-0 = <&pinctrl_mdio>;
341	status = "okay";
342
343	ethphy0: ethernet-phy@0 {
344		compatible = "ethernet-phy-ieee802.3-c22";
345		reg = <0>;
346		pinctrl-names = "default";
347		pinctrl-0 = <&pinctrl_ethphy0>;
348		reset-gpios = <&expander2 5 GPIO_ACTIVE_LOW>;
349		reset-assert-us = <500000>;
350		reset-deassert-us = <50000>;
351		interrupt-parent = <&gpio5>;
352		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
353		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
354		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
355		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
356		ti,dp83867-rxctrl-strap-quirk;
357		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
358	};
359
360	ethphy3: ethernet-phy@3 {
361		compatible = "ethernet-phy-ieee802.3-c22";
362		reg = <3>;
363		pinctrl-names = "default";
364		pinctrl-0 = <&pinctrl_ethphy3>;
365		reset-gpios = <&expander2 6 GPIO_ACTIVE_LOW>;
366		reset-assert-us = <500000>;
367		reset-deassert-us = <50000>;
368		interrupt-parent = <&gpio5>;
369		interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
370		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
371		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
372		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
373		ti,dp83867-rxctrl-strap-quirk;
374		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
375	};
376};
377
378&scmi_bbm {
379	linux,code = <KEY_POWER>;
380};
381
382&tpm3 {
383	pinctrl-names = "default";
384	pinctrl-0 = <&pinctrl_tpm3>;
385};
386
387&tpm4 {
388	pinctrl-names = "default";
389	pinctrl-0 = <&pinctrl_tpm4>;
390};
391
392&tpm5 {
393	pinctrl-names = "default";
394	pinctrl-0 = <&pinctrl_tpm5>;
395};
396
397&usb3 {
398	status = "okay";
399};
400
401&usb3_dwc3 {
402	dr_mode = "host";
403	#address-cells = <1>;
404	#size-cells = <0>;
405
406	hub_2_0: hub@1 {
407		compatible = "usb451,8142";
408		reg = <1>;
409		peer-hub = <&hub_3_0>;
410		reset-gpios = <&expander2 12 GPIO_ACTIVE_LOW>;
411		vdd-supply = <&reg_3v3>;
412	};
413
414	hub_3_0: hub@2 {
415		compatible = "usb451,8140";
416		reg = <2>;
417		peer-hub = <&hub_2_0>;
418		reset-gpios = <&expander2 12 GPIO_ACTIVE_LOW>;
419		vdd-supply = <&reg_3v3>;
420	};
421};
422
423&usb3_phy {
424	status = "okay";
425};
426
427&usdhc1 {
428	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
429	pinctrl-0 = <&pinctrl_usdhc1>;
430	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
431	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
432	pinctrl-3 = <&pinctrl_usdhc1>;
433	bus-width = <8>;
434	non-removable;
435	no-sdio;
436	no-sd;
437	status = "okay";
438};
439
440&wdog3 {
441	status = "okay";
442};
443
444&scmi_iomuxc {
445	pinctrl_ethphy0: ethphy0grp {
446		fsl,pins = <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13				0x1100>;
447	};
448
449	pinctrl_ethphy3: ethphy3grp {
450		fsl,pins = <IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14				0x1100>;
451	};
452
453	pinctrl_enetc0: enetc0grp {
454		fsl,pins = <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x1100>,
455			   <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x1100>,
456			   <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x1100>,
457			   <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x1100>,
458			   <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK		0x1100>,
459			   <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x1100>,
460			   <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x11e>,
461			   <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x11e>,
462			   <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x11e>,
463			   <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x11e>,
464			   <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK		0x11e>,
465			   <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x11e>,
466			   <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23				0x51e>;
467	};
468
469	pinctrl_enetc1: enetc1grp {
470		fsl,pins = <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0		0x1100>,
471			   <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1		0x1100>,
472			   <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2		0x1100>,
473			   <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3		0x1100>,
474			   <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK		0x1100>,
475			   <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL	0x1100>,
476			   <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0		0x11e>,
477			   <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1		0x11e>,
478			   <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2		0x11e>,
479			   <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3		0x11e>,
480			   <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK		0x11e>,
481			   <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL	0x11e>,
482			   <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24				0x51e>;
483	};
484
485	pinctrl_expander1: expander1grp {
486		fsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27				0x1100>;
487	};
488
489	pinctrl_flexcan1: flexcan1grp {
490		fsl,pins = <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX	0x1300>,
491			   <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX		0x31e>;
492	};
493
494	pinctrl_flexcan3: flexcan3grp {
495		fsl,pins = <IMX95_PAD_CCM_CLKO3__CAN3_TX		0x31e>,
496			   <IMX95_PAD_CCM_CLKO4__CAN3_RX		0x1300>;
497	};
498
499	pinctrl_flexspi1: flexspi1grp {
500		fsl,pins = <IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK		0x11e>,
501			   <IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B		0x11e>,
502			   <IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0	0x11e>,
503			   <IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1	0x11e>,
504			   <IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2	0x11e>,
505			   <IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3	0x11e>;
506	};
507
508	pinctrl_gpio1: gpio1grp {
509		fsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10	0x111e>,
510			   <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13		0x111e>,
511			   <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11		0x111e>;
512	};
513
514	pinctrl_gpio2: gpio2grp {
515		fsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18		0x1100>,
516			   <IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19		0x111e>,
517			   <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22		0x111e>;
518	};
519
520	pinctrl_lpi2c1: lpi2c1grp {
521		fsl,pins = <IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL		0x4000191e>,
522			   <IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA		0x4000191e>;
523	};
524
525	pinctrl_lpi2c3: lpi2c3grp {
526		fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA			0x4000191e>,
527			   <IMX95_PAD_GPIO_IO29__LPI2C3_SCL			0x4000191e>;
528	};
529
530	pinctrl_lpi2c4: lpi2c4grp {
531		fsl,pins = <IMX95_PAD_GPIO_IO30__LPI2C4_SDA             0x4000191e>,
532			   <IMX95_PAD_GPIO_IO31__LPI2C4_SCL             0x4000191e>;
533	};
534
535	pinctrl_lpi2c6: lpi2c6grp {
536		fsl,pins = <IMX95_PAD_GPIO_IO02__LPI2C6_SDA             0x4000191e>,
537			   <IMX95_PAD_GPIO_IO03__LPI2C6_SCL             0x4000191e>;
538	};
539
540	pinctrl_lpspi3: lpspi3grp {
541		fsl,pins = <IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7		0x51e>,
542			   <IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8		0x51e>,
543			   <IMX95_PAD_GPIO_IO09__LPSPI3_SIN		0x51e>,
544			   <IMX95_PAD_GPIO_IO10__LPSPI3_SOUT		0x51e>,
545			   <IMX95_PAD_GPIO_IO11__LPSPI3_SCK		0x51e>;
546	};
547
548	pinctrl_lpuart1: lpuart1grp {
549		fsl,pins = <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX		0x1300>,
550			   <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX		0x31e>,
551			   <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B	0x1300>,
552			   <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B	0x31e>;
553	};
554
555	pinctrl_lpuart5: lpuart5grp {
556		fsl,pins = <IMX95_PAD_GPIO_IO00__LPUART5_TX			0x31e>,
557			   <IMX95_PAD_GPIO_IO01__LPUART5_RX			0x1300>;
558	};
559
560	pinctrl_lpuart7: lpuart7grp {
561		fsl,pins = <IMX95_PAD_GPIO_IO36__LPUART7_TX			0x31e>,
562			   <IMX95_PAD_GPIO_IO37__LPUART7_RX			0x1300>;
563	};
564
565	pinctrl_lpuart8: lpuart8grp {
566		fsl,pins = <IMX95_PAD_GPIO_IO12__LPUART8_TX			0x31e>,
567			   <IMX95_PAD_GPIO_IO13__LPUART8_RX			0x1300>,
568			   <IMX95_PAD_GPIO_IO14__LPUART8_CTS_B			0x31e>,
569			   <IMX95_PAD_GPIO_IO15__LPUART8_RTS_B			0x1300>;
570	};
571
572	pinctrl_mdio: mdiogrp {
573		fsl,pins = <IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC		0x51e>,
574			   <IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO		0x51e>;
575	};
576
577	pinctrl_pcf85063: pcf85063grp {
578		fsl,pins = <IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27			0x1100>;
579	};
580
581	pinctrl_pcie0: pcie0grp {
582		fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B	0x111e>;
583	};
584
585	pinctrl_pcie1: pcie1grp {
586		fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B	0x111e>;
587	};
588
589	pinctrl_sai3: sai3grp {
590		fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK			0x51e>,
591			   <IMX95_PAD_GPIO_IO17__SAI3_MCLK			0x51e>,
592			   <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0		0x1300>,
593			   <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0		0x51e>,
594			   <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC			0x51e>;
595	};
596
597	pinctrl_sai5: sai5grp {
598		fsl,pins = <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0		0x51e>,
599			   <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC			0x51e>,
600			   <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK			0x51e>,
601			   <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0		0x1300>;
602	};
603
604	pinctrl_sdvmmc: sdvmmcgrp {
605		fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7		0x11e>;
606	};
607
608	pinctrl_tc9595: tc9595grp {
609		fsl,pins = <IMX95_PAD_GPIO_IO25__GPIO2_IO_BIT25			0x1500>;
610	};
611
612	pinctrl_tpm3: tpm3grp {
613		fsl,pins = <IMX95_PAD_GPIO_IO04__TPM3_CH0			0x51e>;
614	};
615
616	pinctrl_tpm4: tpm4grp {
617		fsl,pins = <IMX95_PAD_GPIO_IO05__TPM4_CH0			0x51e>;
618	};
619
620	pinctrl_tpm5: tpm4grp {
621		fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0			0x51e>;
622	};
623
624	pinctrl_usdhc1: usdhc1grp {
625		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK	0x158e>,
626			   <IMX95_PAD_SD1_CMD__USDHC1_CMD	0x138e>,
627			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x138e>,
628			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x138e>,
629			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x138e>,
630			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x138e>,
631			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x138e>,
632			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x138e>,
633			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x138e>,
634			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x138e>,
635			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x158e>;
636	};
637
638	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
639		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK	0x158e>,
640			   <IMX95_PAD_SD1_CMD__USDHC1_CMD	0x138e>,
641			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x138e>,
642			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x138e>,
643			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x138e>,
644			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x138e>,
645			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x138e>,
646			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x138e>,
647			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x138e>,
648			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x138e>,
649			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x158e>;
650	};
651
652	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
653		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK	0x15fe>,
654			   <IMX95_PAD_SD1_CMD__USDHC1_CMD	0x13fe>,
655			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe>,
656			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe>,
657			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe>,
658			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe>,
659			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe>,
660			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe>,
661			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe>,
662			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe>,
663			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe>;
664	};
665
666	pinctrl_usdhc2: usdhc2grp {
667		fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0			0x1100>,
668			   <IMX95_PAD_SD2_CLK__USDHC2_CLK			0x51e>,
669			   <IMX95_PAD_SD2_CMD__USDHC2_CMD			0x31e>,
670			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x131e>,
671			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x131e>,
672			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x131e>,
673			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x131e>,
674			   <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e>;
675	};
676
677	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
678		fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0			0x1100>,
679			   <IMX95_PAD_SD2_CLK__USDHC2_CLK			0x158e>,
680			   <IMX95_PAD_SD2_CMD__USDHC2_CMD			0x138e>,
681			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e>,
682			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e>,
683			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e>,
684			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e>,
685			   <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e>;
686	};
687
688	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
689		fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0			0x1100>,
690			   <IMX95_PAD_SD2_CLK__USDHC2_CLK			0x15fe>,
691			   <IMX95_PAD_SD2_CMD__USDHC2_CMD			0x13fe>,
692			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x13fe>,
693			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x13fe>,
694			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x13fe>,
695			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x13fe>,
696			   <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e>;
697	};
698};
699