1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer 4 * 5 * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/device.h> 12 #include <linux/ethtool.h> 13 #include <linux/io.h> 14 #include <linux/ioport.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_net.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/platform_device.h> 20 #include <linux/stmmac.h> 21 22 #include "stmmac_platform.h" 23 24 #define PRG_ETH0 0x0 25 26 #define PRG_ETH0_RGMII_MODE BIT(0) 27 28 #define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) 29 30 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ 31 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) 32 33 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one 34 * cycle of the 125MHz RGMII TX clock): 35 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3 36 */ 37 #define PRG_ETH0_TXDLY_MASK GENMASK(6, 5) 38 39 /* divider for the result of m250_sel */ 40 #define PRG_ETH0_CLK_M250_DIV_SHIFT 7 41 #define PRG_ETH0_CLK_M250_DIV_WIDTH 3 42 43 #define PRG_ETH0_RGMII_TX_CLK_EN 10 44 45 #define PRG_ETH0_INVERTED_RMII_CLK BIT(11) 46 #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) 47 48 /* Bypass (= 0, the signal from the GPIO input directly connects to the 49 * internal sampling) or enable (= 1) the internal logic for RXEN and RXD[3:0] 50 * timing tuning. 51 */ 52 #define PRG_ETH0_ADJ_ENABLE BIT(13) 53 /* Controls whether the RXEN and RXD[3:0] signals should be aligned with the 54 * input RX rising/falling edge and sent to the Ethernet internals. This sets 55 * the automatically delay and skew automatically (internally). 56 */ 57 #define PRG_ETH0_ADJ_SETUP BIT(14) 58 /* An internal counter based on the "timing-adjustment" clock. The counter is 59 * cleared on both, the falling and rising edge of the RX_CLK. This selects the 60 * delay (= the counter value) when to start sampling RXEN and RXD[3:0]. 61 */ 62 #define PRG_ETH0_ADJ_DELAY GENMASK(19, 15) 63 /* Adjusts the skew between each bit of RXEN and RXD[3:0]. If a signal has a 64 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1, 65 * ...) can be configured to be 1 to compensate for a delay of about 1ns. 66 */ 67 #define PRG_ETH0_ADJ_SKEW GENMASK(24, 20) 68 69 #define PRG_ETH1 0x4 70 71 /* Defined for adding a delay to the input RX_CLK for better timing. 72 * Each step is 200ps. These bits are used with external RGMII PHYs 73 * because RGMII RX only has the small window. cfg_rxclk_dly can 74 * adjust the window between RX_CLK and RX_DATA and improve the stability 75 * of "rx data valid". 76 */ 77 #define PRG_ETH1_CFG_RXCLK_DLY GENMASK(19, 16) 78 79 struct meson8b_dwmac; 80 81 struct meson8b_dwmac_data { 82 int (*set_phy_mode)(struct meson8b_dwmac *dwmac); 83 bool has_prg_eth1_rgmii_rx_delay; 84 }; 85 86 struct meson8b_dwmac { 87 struct device *dev; 88 void __iomem *regs; 89 90 const struct meson8b_dwmac_data *data; 91 phy_interface_t phy_mode; 92 struct clk *rgmii_tx_clk; 93 u32 tx_delay_ns; 94 u32 rx_delay_ps; 95 struct clk *timing_adj_clk; 96 }; 97 98 struct meson8b_dwmac_clk_configs { 99 struct clk_mux m250_mux; 100 struct clk_divider m250_div; 101 struct clk_fixed_factor fixed_div2; 102 struct clk_gate rgmii_tx_en; 103 }; 104 105 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, 106 u32 mask, u32 value) 107 { 108 u32 data; 109 110 data = readl(dwmac->regs + reg); 111 data &= ~mask; 112 data |= (value & mask); 113 114 writel(data, dwmac->regs + reg); 115 } 116 117 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, 118 const char *name_suffix, 119 const struct clk_parent_data *parents, 120 int num_parents, 121 const struct clk_ops *ops, 122 struct clk_hw *hw) 123 { 124 struct clk_init_data init = { }; 125 char clk_name[32]; 126 127 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev), 128 name_suffix); 129 130 init.name = clk_name; 131 init.ops = ops; 132 init.flags = CLK_SET_RATE_PARENT; 133 init.parent_data = parents; 134 init.num_parents = num_parents; 135 136 hw->init = &init; 137 138 return devm_clk_register(dwmac->dev, hw); 139 } 140 141 static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) 142 { 143 struct clk *clk; 144 struct device *dev = dwmac->dev; 145 static const struct clk_parent_data mux_parents[] = { 146 { .fw_name = "clkin0", }, 147 { .index = -1, }, 148 }; 149 static const struct clk_div_table div_table[] = { 150 { .div = 2, .val = 2, }, 151 { .div = 3, .val = 3, }, 152 { .div = 4, .val = 4, }, 153 { .div = 5, .val = 5, }, 154 { .div = 6, .val = 6, }, 155 { .div = 7, .val = 7, }, 156 { /* end of array */ } 157 }; 158 struct meson8b_dwmac_clk_configs *clk_configs; 159 struct clk_parent_data parent_data = { }; 160 161 clk_configs = devm_kzalloc(dev, sizeof(*clk_configs), GFP_KERNEL); 162 if (!clk_configs) 163 return -ENOMEM; 164 165 clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0; 166 clk_configs->m250_mux.shift = __ffs(PRG_ETH0_CLK_M250_SEL_MASK); 167 clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK >> 168 clk_configs->m250_mux.shift; 169 clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parents, 170 ARRAY_SIZE(mux_parents), &clk_mux_ops, 171 &clk_configs->m250_mux.hw); 172 if (WARN_ON(IS_ERR(clk))) 173 return PTR_ERR(clk); 174 175 parent_data.hw = &clk_configs->m250_mux.hw; 176 clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0; 177 clk_configs->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT; 178 clk_configs->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH; 179 clk_configs->m250_div.table = div_table; 180 clk_configs->m250_div.flags = CLK_DIVIDER_ALLOW_ZERO | 181 CLK_DIVIDER_ROUND_CLOSEST; 182 clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_data, 1, 183 &clk_divider_ops, 184 &clk_configs->m250_div.hw); 185 if (WARN_ON(IS_ERR(clk))) 186 return PTR_ERR(clk); 187 188 parent_data.hw = &clk_configs->m250_div.hw; 189 clk_configs->fixed_div2.mult = 1; 190 clk_configs->fixed_div2.div = 2; 191 clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_data, 1, 192 &clk_fixed_factor_ops, 193 &clk_configs->fixed_div2.hw); 194 if (WARN_ON(IS_ERR(clk))) 195 return PTR_ERR(clk); 196 197 parent_data.hw = &clk_configs->fixed_div2.hw; 198 clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0; 199 clk_configs->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN; 200 clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_data, 1, 201 &clk_gate_ops, 202 &clk_configs->rgmii_tx_en.hw); 203 if (WARN_ON(IS_ERR(clk))) 204 return PTR_ERR(clk); 205 206 dwmac->rgmii_tx_clk = clk; 207 208 return 0; 209 } 210 211 static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac) 212 { 213 switch (dwmac->phy_mode) { 214 case PHY_INTERFACE_MODE_RGMII: 215 case PHY_INTERFACE_MODE_RGMII_RXID: 216 case PHY_INTERFACE_MODE_RGMII_ID: 217 case PHY_INTERFACE_MODE_RGMII_TXID: 218 /* enable RGMII mode */ 219 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 220 PRG_ETH0_RGMII_MODE, 221 PRG_ETH0_RGMII_MODE); 222 break; 223 case PHY_INTERFACE_MODE_RMII: 224 /* disable RGMII mode -> enables RMII mode */ 225 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 226 PRG_ETH0_RGMII_MODE, 0); 227 break; 228 default: 229 dev_err(dwmac->dev, "fail to set phy-mode %s\n", 230 phy_modes(dwmac->phy_mode)); 231 return -EINVAL; 232 } 233 234 return 0; 235 } 236 237 static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac) 238 { 239 int phy_intf_sel; 240 241 phy_intf_sel = stmmac_get_phy_intf_sel(dwmac->phy_mode); 242 if (phy_intf_sel != PHY_INTF_SEL_RGMII && 243 phy_intf_sel != PHY_INTF_SEL_RMII) { 244 dev_err(dwmac->dev, "fail to set phy-mode %s\n", 245 phy_modes(dwmac->phy_mode)); 246 return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; 247 } 248 249 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_EXT_PHY_MODE_MASK, 250 FIELD_PREP(PRG_ETH0_EXT_PHY_MODE_MASK, 251 phy_intf_sel)); 252 253 return 0; 254 } 255 256 static void meson8b_clk_disable_unprepare(void *data) 257 { 258 clk_disable_unprepare(data); 259 } 260 261 static int meson8b_devm_clk_prepare_enable(struct meson8b_dwmac *dwmac, 262 struct clk *clk) 263 { 264 int ret; 265 266 ret = clk_prepare_enable(clk); 267 if (ret) 268 return ret; 269 270 return devm_add_action_or_reset(dwmac->dev, 271 meson8b_clk_disable_unprepare, clk); 272 } 273 274 static int meson8b_init_rgmii_delays(struct meson8b_dwmac *dwmac) 275 { 276 u32 tx_dly_config, rx_adj_config, cfg_rxclk_dly, delay_config; 277 int ret; 278 279 rx_adj_config = 0; 280 cfg_rxclk_dly = 0; 281 tx_dly_config = FIELD_PREP(PRG_ETH0_TXDLY_MASK, 282 dwmac->tx_delay_ns >> 1); 283 284 if (dwmac->data->has_prg_eth1_rgmii_rx_delay) 285 cfg_rxclk_dly = FIELD_PREP(PRG_ETH1_CFG_RXCLK_DLY, 286 dwmac->rx_delay_ps / 200); 287 else if (dwmac->rx_delay_ps == 2000) 288 rx_adj_config = PRG_ETH0_ADJ_ENABLE | PRG_ETH0_ADJ_SETUP; 289 290 switch (dwmac->phy_mode) { 291 case PHY_INTERFACE_MODE_RGMII: 292 delay_config = tx_dly_config | rx_adj_config; 293 break; 294 case PHY_INTERFACE_MODE_RGMII_RXID: 295 delay_config = tx_dly_config; 296 cfg_rxclk_dly = 0; 297 break; 298 case PHY_INTERFACE_MODE_RGMII_TXID: 299 delay_config = rx_adj_config; 300 break; 301 case PHY_INTERFACE_MODE_RGMII_ID: 302 case PHY_INTERFACE_MODE_RMII: 303 delay_config = 0; 304 cfg_rxclk_dly = 0; 305 break; 306 default: 307 dev_err(dwmac->dev, "unsupported phy-mode %s\n", 308 phy_modes(dwmac->phy_mode)); 309 return -EINVAL; 310 } 311 312 if (delay_config & PRG_ETH0_ADJ_ENABLE) { 313 if (!dwmac->timing_adj_clk) { 314 dev_err(dwmac->dev, 315 "The timing-adjustment clock is mandatory for the RX delay re-timing\n"); 316 return -EINVAL; 317 } 318 319 /* The timing adjustment logic is driven by a separate clock */ 320 ret = meson8b_devm_clk_prepare_enable(dwmac, 321 dwmac->timing_adj_clk); 322 if (ret) { 323 dev_err(dwmac->dev, 324 "Failed to enable the timing-adjustment clock\n"); 325 return ret; 326 } 327 } 328 329 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK | 330 PRG_ETH0_ADJ_ENABLE | PRG_ETH0_ADJ_SETUP | 331 PRG_ETH0_ADJ_DELAY | PRG_ETH0_ADJ_SKEW, 332 delay_config); 333 334 meson8b_dwmac_mask_bits(dwmac, PRG_ETH1, PRG_ETH1_CFG_RXCLK_DLY, 335 cfg_rxclk_dly); 336 337 return 0; 338 } 339 340 static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) 341 { 342 int ret; 343 344 if (phy_interface_mode_is_rgmii(dwmac->phy_mode)) { 345 /* only relevant for RMII mode -> disable in RGMII mode */ 346 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 347 PRG_ETH0_INVERTED_RMII_CLK, 0); 348 349 /* Configure the 125MHz RGMII TX clock, the IP block changes 350 * the output automatically (= without us having to configure 351 * a register) based on the line-speed (125MHz for Gbit speeds, 352 * 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s). 353 */ 354 ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000); 355 if (ret) { 356 dev_err(dwmac->dev, 357 "failed to set RGMII TX clock\n"); 358 return ret; 359 } 360 361 ret = meson8b_devm_clk_prepare_enable(dwmac, 362 dwmac->rgmii_tx_clk); 363 if (ret) { 364 dev_err(dwmac->dev, 365 "failed to enable the RGMII TX clock\n"); 366 return ret; 367 } 368 } else { 369 /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ 370 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 371 PRG_ETH0_INVERTED_RMII_CLK, 372 PRG_ETH0_INVERTED_RMII_CLK); 373 } 374 375 /* enable TX_CLK and PHY_REF_CLK generator */ 376 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK, 377 PRG_ETH0_TX_AND_PHY_REF_CLK); 378 379 return 0; 380 } 381 382 static int meson8b_dwmac_probe(struct platform_device *pdev) 383 { 384 struct plat_stmmacenet_data *plat_dat; 385 struct stmmac_resources stmmac_res; 386 struct meson8b_dwmac *dwmac; 387 int ret; 388 389 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 390 if (ret) 391 return ret; 392 393 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 394 if (IS_ERR(plat_dat)) 395 return PTR_ERR(plat_dat); 396 397 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 398 if (!dwmac) 399 return -ENOMEM; 400 401 dwmac->data = (const struct meson8b_dwmac_data *) 402 of_device_get_match_data(&pdev->dev); 403 if (!dwmac->data) 404 return -EINVAL; 405 dwmac->regs = devm_platform_ioremap_resource(pdev, 1); 406 if (IS_ERR(dwmac->regs)) 407 return PTR_ERR(dwmac->regs); 408 409 dwmac->dev = &pdev->dev; 410 dwmac->phy_mode = plat_dat->phy_interface; 411 412 /* use 2ns as fallback since this value was previously hardcoded */ 413 if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns", 414 &dwmac->tx_delay_ns)) 415 dwmac->tx_delay_ns = 2; 416 417 /* RX delay defaults to 0ps since this is what many boards use */ 418 if (of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps", 419 &dwmac->rx_delay_ps)) { 420 if (!of_property_read_u32(pdev->dev.of_node, 421 "amlogic,rx-delay-ns", 422 &dwmac->rx_delay_ps)) 423 /* convert ns to ps */ 424 dwmac->rx_delay_ps *= 1000; 425 } 426 427 if (dwmac->data->has_prg_eth1_rgmii_rx_delay) { 428 if (dwmac->rx_delay_ps > 3000 || dwmac->rx_delay_ps % 200) { 429 dev_err(dwmac->dev, 430 "The RGMII RX delay range is 0..3000ps in 200ps steps"); 431 return -EINVAL; 432 } 433 } else { 434 if (dwmac->rx_delay_ps != 0 && dwmac->rx_delay_ps != 2000) { 435 dev_err(dwmac->dev, 436 "The only allowed RGMII RX delays values are: 0ps, 2000ps"); 437 return -EINVAL; 438 } 439 } 440 441 dwmac->timing_adj_clk = devm_clk_get_optional(dwmac->dev, 442 "timing-adjustment"); 443 if (IS_ERR(dwmac->timing_adj_clk)) 444 return PTR_ERR(dwmac->timing_adj_clk); 445 446 ret = meson8b_init_rgmii_delays(dwmac); 447 if (ret) 448 return ret; 449 450 ret = meson8b_init_rgmii_tx_clk(dwmac); 451 if (ret) 452 return ret; 453 454 ret = dwmac->data->set_phy_mode(dwmac); 455 if (ret) 456 return ret; 457 458 ret = meson8b_init_prg_eth(dwmac); 459 if (ret) 460 return ret; 461 462 plat_dat->bsp_priv = dwmac; 463 464 return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 465 } 466 467 static const struct meson8b_dwmac_data meson8b_dwmac_data = { 468 .set_phy_mode = meson8b_set_phy_mode, 469 .has_prg_eth1_rgmii_rx_delay = false, 470 }; 471 472 static const struct meson8b_dwmac_data meson_axg_dwmac_data = { 473 .set_phy_mode = meson_axg_set_phy_mode, 474 .has_prg_eth1_rgmii_rx_delay = false, 475 }; 476 477 static const struct meson8b_dwmac_data meson_g12a_dwmac_data = { 478 .set_phy_mode = meson_axg_set_phy_mode, 479 .has_prg_eth1_rgmii_rx_delay = true, 480 }; 481 482 static const struct of_device_id meson8b_dwmac_match[] = { 483 { 484 .compatible = "amlogic,meson8b-dwmac", 485 .data = &meson8b_dwmac_data, 486 }, 487 { 488 .compatible = "amlogic,meson8m2-dwmac", 489 .data = &meson8b_dwmac_data, 490 }, 491 { 492 .compatible = "amlogic,meson-gxbb-dwmac", 493 .data = &meson8b_dwmac_data, 494 }, 495 { 496 .compatible = "amlogic,meson-axg-dwmac", 497 .data = &meson_axg_dwmac_data, 498 }, 499 { 500 .compatible = "amlogic,meson-g12a-dwmac", 501 .data = &meson_g12a_dwmac_data, 502 }, 503 { } 504 }; 505 MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); 506 507 static struct platform_driver meson8b_dwmac_driver = { 508 .probe = meson8b_dwmac_probe, 509 .remove = stmmac_pltfr_remove, 510 .driver = { 511 .name = "meson8b-dwmac", 512 .pm = &stmmac_pltfr_pm_ops, 513 .of_match_table = meson8b_dwmac_match, 514 }, 515 }; 516 module_platform_driver(meson8b_dwmac_driver); 517 518 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); 519 MODULE_DESCRIPTION("Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer"); 520 MODULE_LICENSE("GPL v2"); 521