1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/pinctrl/rockchip.h> 7#include "rockchip-pinconf.dtsi" 8 9/* 10 * This file is auto generated by pin2dts tool, please keep these code 11 * by adding changes at end of this file. 12 */ 13&pinctrl { 14 cam { 15 /omit-if-no-ref/ 16 camm0_clk0_out: camm0-clk0-out { 17 rockchip,pins = 18 /* camm0_clk0_out */ 19 <3 RK_PB2 2 &pcfg_pull_none>; 20 }; 21 22 /omit-if-no-ref/ 23 camm0_clk1_out: camm0-clk1-out { 24 rockchip,pins = 25 /* camm0_clk1_out */ 26 <3 RK_PB3 2 &pcfg_pull_none>; 27 }; 28 29 /omit-if-no-ref/ 30 camm1_clk0_out: camm1-clk0-out { 31 rockchip,pins = 32 /* camm1_clk0_out */ 33 <4 RK_PB1 3 &pcfg_pull_none>; 34 }; 35 36 /omit-if-no-ref/ 37 camm1_clk1_out: camm1-clk1-out { 38 rockchip,pins = 39 /* camm1_clk1_out */ 40 <4 RK_PB7 3 &pcfg_pull_none>; 41 }; 42 43 /omit-if-no-ref/ 44 cam_clk2_out: cam-clk2-out { 45 rockchip,pins = 46 /* cam_clk2_out */ 47 <3 RK_PB4 2 &pcfg_pull_none>; 48 }; 49 50 /omit-if-no-ref/ 51 cam_clk3_out: cam-clk3-out { 52 rockchip,pins = 53 /* cam_clk3_out */ 54 <3 RK_PB5 2 &pcfg_pull_none>; 55 }; 56 }; 57 58 can0 { 59 /omit-if-no-ref/ 60 can0m0_pins: can0m0-pins { 61 rockchip,pins = 62 /* can0_rx_m0 */ 63 <3 RK_PA1 4 &pcfg_pull_none>, 64 /* can0_tx_m0 */ 65 <3 RK_PA0 4 &pcfg_pull_none>; 66 }; 67 68 /omit-if-no-ref/ 69 can0m1_pins: can0m1-pins { 70 rockchip,pins = 71 /* can0_rx_m1 */ 72 <3 RK_PB7 6 &pcfg_pull_none>, 73 /* can0_tx_m1 */ 74 <3 RK_PB6 6 &pcfg_pull_none>; 75 }; 76 77 /omit-if-no-ref/ 78 can0m2_pins: can0m2-pins { 79 rockchip,pins = 80 /* can0_rx_m2 */ 81 <0 RK_PC7 2 &pcfg_pull_none>, 82 /* can0_tx_m2 */ 83 <0 RK_PC6 2 &pcfg_pull_none>; 84 }; 85 }; 86 87 can1 { 88 /omit-if-no-ref/ 89 can1m0_pins: can1m0-pins { 90 rockchip,pins = 91 /* can1_rx_m0 */ 92 <1 RK_PB7 4 &pcfg_pull_none>, 93 /* can1_tx_m0 */ 94 <1 RK_PC0 5 &pcfg_pull_none>; 95 }; 96 97 /omit-if-no-ref/ 98 can1m1_pins: can1m1-pins { 99 rockchip,pins = 100 /* can1_rx_m1 */ 101 <0 RK_PC1 4 &pcfg_pull_none>, 102 /* can1_tx_m1 */ 103 <0 RK_PC0 4 &pcfg_pull_none>; 104 }; 105 }; 106 107 clk { 108 /omit-if-no-ref/ 109 clk_32k_in: clk-32k-in { 110 rockchip,pins = 111 /* clk_32k_in */ 112 <0 RK_PB0 1 &pcfg_pull_none>; 113 }; 114 }; 115 116 clk0 { 117 /omit-if-no-ref/ 118 clk0_32k_out: clk0-32k-out { 119 rockchip,pins = 120 /* clk0_32k_out */ 121 <0 RK_PB0 2 &pcfg_pull_none>; 122 }; 123 }; 124 125 clk1 { 126 /omit-if-no-ref/ 127 clk1_32k_out: clk1-32k-out { 128 rockchip,pins = 129 /* clk1_32k_out */ 130 <2 RK_PA1 3 &pcfg_pull_none>; 131 }; 132 }; 133 134 cpu { 135 /omit-if-no-ref/ 136 cpu_pins: cpu-pins { 137 rockchip,pins = 138 /* cpu_avs */ 139 <0 RK_PB7 3 &pcfg_pull_none>; 140 }; 141 }; 142 143 dsm { 144 /omit-if-no-ref/ 145 dsm_pins: dsm-pins { 146 rockchip,pins = 147 /* dsm_aud_ln */ 148 <1 RK_PB4 5 &pcfg_pull_none>, 149 /* dsm_aud_lp */ 150 <1 RK_PB3 5 &pcfg_pull_none>, 151 /* dsm_aud_rn */ 152 <1 RK_PB6 6 &pcfg_pull_none>, 153 /* dsm_aud_rp */ 154 <1 RK_PB5 6 &pcfg_pull_none>; 155 }; 156 }; 157 158 emmc { 159 /omit-if-no-ref/ 160 emmc_bus8: emmc-bus8 { 161 rockchip,pins = 162 /* emmc_d0 */ 163 <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, 164 /* emmc_d1 */ 165 <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, 166 /* emmc_d2 */ 167 <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, 168 /* emmc_d3 */ 169 <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>, 170 /* emmc_d4 */ 171 <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, 172 /* emmc_d5 */ 173 <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, 174 /* emmc_d6 */ 175 <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, 176 /* emmc_d7 */ 177 <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; 178 }; 179 180 /omit-if-no-ref/ 181 emmc_clk: emmc-clk { 182 rockchip,pins = 183 /* emmc_clk */ 184 <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; 185 }; 186 187 /omit-if-no-ref/ 188 emmc_cmd: emmc-cmd { 189 rockchip,pins = 190 /* emmc_cmd */ 191 <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; 192 }; 193 194 /omit-if-no-ref/ 195 emmc_strb: emmc-strb { 196 rockchip,pins = 197 /* emmc_strb */ 198 <1 RK_PB2 1 &pcfg_pull_none>; 199 }; 200 }; 201 202 eth { 203 /omit-if-no-ref/ 204 ethm0_pins: ethm0-pins { 205 rockchip,pins = 206 /* eth_clk_25m_out_m0 */ 207 <4 RK_PB1 2 &pcfg_pull_none>; 208 }; 209 210 /omit-if-no-ref/ 211 ethm1_pins: ethm1-pins { 212 rockchip,pins = 213 /* eth_clk_25m_out_m1 */ 214 <2 RK_PA1 2 &pcfg_pull_none>; 215 }; 216 }; 217 218 fspi { 219 /omit-if-no-ref/ 220 fspi_pins: fspi-pins { 221 rockchip,pins = 222 /* fspi_clk */ 223 <1 RK_PB1 2 &pcfg_pull_none>, 224 /* fspi_d0 */ 225 <1 RK_PA0 2 &pcfg_pull_none>, 226 /* fspi_d1 */ 227 <1 RK_PA1 2 &pcfg_pull_none>, 228 /* fspi_d2 */ 229 <1 RK_PA2 2 &pcfg_pull_none>, 230 /* fspi_d3 */ 231 <1 RK_PA3 2 &pcfg_pull_none>; 232 }; 233 234 /omit-if-no-ref/ 235 fspi_csn0: fspi-csn0 { 236 rockchip,pins = 237 /* fspi_csn0 */ 238 <1 RK_PB0 2 &pcfg_pull_none>; 239 }; 240 /omit-if-no-ref/ 241 fspi_csn1: fspi-csn1 { 242 rockchip,pins = 243 /* fspi_csn1 */ 244 <1 RK_PB2 2 &pcfg_pull_none>; 245 }; 246 }; 247 248 gpu { 249 /omit-if-no-ref/ 250 gpu_pins: gpu-pins { 251 rockchip,pins = 252 /* gpu_avs */ 253 <0 RK_PC0 3 &pcfg_pull_none>; 254 }; 255 }; 256 257 i2c0 { 258 /omit-if-no-ref/ 259 i2c0_xfer: i2c0-xfer { 260 rockchip,pins = 261 /* i2c0_scl */ 262 <0 RK_PB1 1 &pcfg_pull_none_smt>, 263 /* i2c0_sda */ 264 <0 RK_PB2 1 &pcfg_pull_none_smt>; 265 }; 266 }; 267 268 i2c1 { 269 /omit-if-no-ref/ 270 i2c1m0_xfer: i2c1m0-xfer { 271 rockchip,pins = 272 /* i2c1_scl_m0 */ 273 <0 RK_PB3 1 &pcfg_pull_none_smt>, 274 /* i2c1_sda_m0 */ 275 <0 RK_PB4 1 &pcfg_pull_none_smt>; 276 }; 277 278 /omit-if-no-ref/ 279 i2c1m1_xfer: i2c1m1-xfer { 280 rockchip,pins = 281 /* i2c1_scl_m1 */ 282 <4 RK_PB4 5 &pcfg_pull_none_smt>, 283 /* i2c1_sda_m1 */ 284 <4 RK_PB5 5 &pcfg_pull_none_smt>; 285 }; 286 }; 287 288 i2c2 { 289 /omit-if-no-ref/ 290 i2c2m0_xfer: i2c2m0-xfer { 291 rockchip,pins = 292 /* i2c2_scl_m0 */ 293 <0 RK_PB5 1 &pcfg_pull_none_smt>, 294 /* i2c2_sda_m0 */ 295 <0 RK_PB6 1 &pcfg_pull_none_smt>; 296 }; 297 298 /omit-if-no-ref/ 299 i2c2m1_xfer: i2c2m1-xfer { 300 rockchip,pins = 301 /* i2c2_scl_m1 */ 302 <3 RK_PD2 5 &pcfg_pull_none_smt>, 303 /* i2c2_sda_m1 */ 304 <3 RK_PD3 5 &pcfg_pull_none_smt>; 305 }; 306 }; 307 308 i2c3 { 309 /omit-if-no-ref/ 310 i2c3m0_xfer: i2c3m0-xfer { 311 rockchip,pins = 312 /* i2c3_scl_m0 */ 313 <3 RK_PA0 1 &pcfg_pull_none_smt>, 314 /* i2c3_sda_m0 */ 315 <3 RK_PA1 1 &pcfg_pull_none_smt>; 316 }; 317 318 /omit-if-no-ref/ 319 i2c3m1_xfer: i2c3m1-xfer { 320 rockchip,pins = 321 /* i2c3_scl_m1 */ 322 <4 RK_PA5 5 &pcfg_pull_none_smt>, 323 /* i2c3_sda_m1 */ 324 <4 RK_PA6 5 &pcfg_pull_none_smt>; 325 }; 326 }; 327 328 i2c4 { 329 /omit-if-no-ref/ 330 i2c4m0_xfer: i2c4m0-xfer { 331 rockchip,pins = 332 /* i2c4_scl_m0 */ 333 <3 RK_PB6 5 &pcfg_pull_none_smt>, 334 /* i2c4_sda_m0 */ 335 <3 RK_PB7 5 &pcfg_pull_none_smt>; 336 }; 337 338 /omit-if-no-ref/ 339 i2c4m1_xfer: i2c4m1-xfer { 340 rockchip,pins = 341 /* i2c4_scl_m1 */ 342 <0 RK_PA5 2 &pcfg_pull_none_smt>, 343 /* i2c4_sda_m1 */ 344 <0 RK_PA4 2 &pcfg_pull_none_smt>; 345 }; 346 }; 347 348 i2c5 { 349 /omit-if-no-ref/ 350 i2c5m0_xfer: i2c5m0-xfer { 351 rockchip,pins = 352 /* i2c5_scl_m0 */ 353 <3 RK_PC2 1 &pcfg_pull_none_smt>, 354 /* i2c5_sda_m0 */ 355 <3 RK_PC3 1 &pcfg_pull_none_smt>; 356 }; 357 358 /omit-if-no-ref/ 359 i2c5m1_xfer: i2c5m1-xfer { 360 rockchip,pins = 361 /* i2c5_scl_m1 */ 362 <1 RK_PC7 4 &pcfg_pull_none_smt>, 363 /* i2c5_sda_m1 */ 364 <1 RK_PD0 4 &pcfg_pull_none_smt>; 365 }; 366 }; 367 368 i2s0 { 369 /omit-if-no-ref/ 370 i2s0m0_lrck: i2s0m0-lrck { 371 rockchip,pins = 372 /* i2s0_lrck_m0 */ 373 <3 RK_PA4 1 &pcfg_pull_none_smt>; 374 }; 375 376 /omit-if-no-ref/ 377 i2s0m0_mclk: i2s0m0-mclk { 378 rockchip,pins = 379 /* i2s0_mclk_m0 */ 380 <3 RK_PA2 1 &pcfg_pull_none_smt>; 381 }; 382 383 /omit-if-no-ref/ 384 i2s0m0_sclk: i2s0m0-sclk { 385 rockchip,pins = 386 /* i2s0_sclk_m0 */ 387 <3 RK_PA3 1 &pcfg_pull_none_smt>; 388 }; 389 390 /omit-if-no-ref/ 391 i2s0m0_sdi0: i2s0m0-sdi0 { 392 rockchip,pins = 393 /* i2s0_sdi0_m0 */ 394 <3 RK_PB1 1 &pcfg_pull_none>; 395 }; 396 397 /omit-if-no-ref/ 398 i2s0m0_sdi1: i2s0m0-sdi1 { 399 rockchip,pins = 400 /* i2s0_sdi1_m0 */ 401 <3 RK_PB0 2 &pcfg_pull_none>; 402 }; 403 404 /omit-if-no-ref/ 405 i2s0m0_sdi2: i2s0m0-sdi2 { 406 rockchip,pins = 407 /* i2s0_sdi2_m0 */ 408 <3 RK_PA7 2 &pcfg_pull_none>; 409 }; 410 411 /omit-if-no-ref/ 412 i2s0m0_sdi3: i2s0m0-sdi3 { 413 rockchip,pins = 414 /* i2s0_sdi3_m0 */ 415 <3 RK_PA6 2 &pcfg_pull_none>; 416 }; 417 418 /omit-if-no-ref/ 419 i2s0m0_sdo0: i2s0m0-sdo0 { 420 rockchip,pins = 421 /* i2s0_sdo0_m0 */ 422 <3 RK_PA5 1 &pcfg_pull_none>; 423 }; 424 425 /omit-if-no-ref/ 426 i2s0m0_sdo1: i2s0m0-sdo1 { 427 rockchip,pins = 428 /* i2s0_sdo1_m0 */ 429 <3 RK_PA6 1 &pcfg_pull_none>; 430 }; 431 432 /omit-if-no-ref/ 433 i2s0m0_sdo2: i2s0m0-sdo2 { 434 rockchip,pins = 435 /* i2s0_sdo2_m0 */ 436 <3 RK_PA7 1 &pcfg_pull_none>; 437 }; 438 439 /omit-if-no-ref/ 440 i2s0m0_sdo3: i2s0m0-sdo3 { 441 rockchip,pins = 442 /* i2s0_sdo3_m0 */ 443 <3 RK_PB0 1 &pcfg_pull_none>; 444 }; 445 446 /omit-if-no-ref/ 447 i2s0m1_lrck: i2s0m1-lrck { 448 rockchip,pins = 449 /* i2s0_lrck_m1 */ 450 <1 RK_PC4 3 &pcfg_pull_none_smt>; 451 }; 452 453 /omit-if-no-ref/ 454 i2s0m1_mclk: i2s0m1-mclk { 455 rockchip,pins = 456 /* i2s0_mclk_m1 */ 457 <1 RK_PC6 3 &pcfg_pull_none_smt>; 458 }; 459 460 /omit-if-no-ref/ 461 i2s0m1_sclk: i2s0m1-sclk { 462 rockchip,pins = 463 /* i2s0_sclk_m1 */ 464 <1 RK_PC5 3 &pcfg_pull_none_smt>; 465 }; 466 467 /omit-if-no-ref/ 468 i2s0m1_sdi0: i2s0m1-sdi0 { 469 rockchip,pins = 470 /* i2s0_sdi0_m1 */ 471 <1 RK_PC1 3 &pcfg_pull_none>; 472 }; 473 474 /omit-if-no-ref/ 475 i2s0m1_sdi1: i2s0m1-sdi1 { 476 rockchip,pins = 477 /* i2s0_sdi1_m1 */ 478 <1 RK_PC2 3 &pcfg_pull_none>; 479 }; 480 481 /omit-if-no-ref/ 482 i2s0m1_sdi2: i2s0m1-sdi2 { 483 rockchip,pins = 484 /* i2s0_sdi2_m1 */ 485 <1 RK_PD3 3 &pcfg_pull_none>; 486 }; 487 488 /omit-if-no-ref/ 489 i2s0m1_sdi3: i2s0m1-sdi3 { 490 rockchip,pins = 491 /* i2s0_sdi3_m1 */ 492 <1 RK_PD4 3 &pcfg_pull_none>; 493 }; 494 495 /omit-if-no-ref/ 496 i2s0m1_sdo0: i2s0m1-sdo0 { 497 rockchip,pins = 498 /* i2s0_sdo0_m1 */ 499 <1 RK_PC3 3 &pcfg_pull_none>; 500 }; 501 502 /omit-if-no-ref/ 503 i2s0m1_sdo1: i2s0m1-sdo1 { 504 rockchip,pins = 505 /* i2s0_sdo1_m1 */ 506 <1 RK_PD1 3 &pcfg_pull_none>; 507 }; 508 509 /omit-if-no-ref/ 510 i2s0m1_sdo2: i2s0m1-sdo2 { 511 rockchip,pins = 512 /* i2s0_sdo2_m1 */ 513 <1 RK_PD2 3 &pcfg_pull_none>; 514 }; 515 516 /omit-if-no-ref/ 517 i2s0m1_sdo3: i2s0m1-sdo3 { 518 rockchip,pins = 519 /* i2s0_sdo3_m1 */ 520 <2 RK_PA1 5 &pcfg_pull_none>; 521 }; 522 }; 523 524 i2s1 { 525 /omit-if-no-ref/ 526 i2s1m0_lrck: i2s1m0-lrck { 527 rockchip,pins = 528 /* i2s1_lrck_m0 */ 529 <3 RK_PC6 2 &pcfg_pull_none_smt>; 530 }; 531 532 /omit-if-no-ref/ 533 i2s1m0_mclk: i2s1m0-mclk { 534 rockchip,pins = 535 /* i2s1_mclk_m0 */ 536 <3 RK_PC4 2 &pcfg_pull_none_smt>; 537 }; 538 539 /omit-if-no-ref/ 540 i2s1m0_sclk: i2s1m0-sclk { 541 rockchip,pins = 542 /* i2s1_sclk_m0 */ 543 <3 RK_PC5 2 &pcfg_pull_none_smt>; 544 }; 545 546 /omit-if-no-ref/ 547 i2s1m0_sdi0: i2s1m0-sdi0 { 548 rockchip,pins = 549 /* i2s1_sdi0_m0 */ 550 <3 RK_PD0 2 &pcfg_pull_none>; 551 }; 552 553 /omit-if-no-ref/ 554 i2s1m0_sdi1: i2s1m0-sdi1 { 555 rockchip,pins = 556 /* i2s1_sdi1_m0 */ 557 <3 RK_PD1 2 &pcfg_pull_none>; 558 }; 559 560 /omit-if-no-ref/ 561 i2s1m0_sdi2: i2s1m0-sdi2 { 562 rockchip,pins = 563 /* i2s1_sdi2_m0 */ 564 <3 RK_PD2 2 &pcfg_pull_none>; 565 }; 566 567 /omit-if-no-ref/ 568 i2s1m0_sdi3: i2s1m0-sdi3 { 569 rockchip,pins = 570 /* i2s1_sdi3_m0 */ 571 <3 RK_PD3 2 &pcfg_pull_none>; 572 }; 573 574 /omit-if-no-ref/ 575 i2s1m0_sdo0: i2s1m0-sdo0 { 576 rockchip,pins = 577 /* i2s1_sdo0_m0 */ 578 <3 RK_PC7 2 &pcfg_pull_none>; 579 }; 580 581 /omit-if-no-ref/ 582 i2s1m0_sdo1: i2s1m0-sdo1 { 583 rockchip,pins = 584 /* i2s1_sdo1_m0 */ 585 <4 RK_PB4 2 &pcfg_pull_none>; 586 }; 587 588 /omit-if-no-ref/ 589 i2s1m0_sdo2: i2s1m0-sdo2 { 590 rockchip,pins = 591 /* i2s1_sdo2_m0 */ 592 <4 RK_PB5 2 &pcfg_pull_none>; 593 }; 594 595 /omit-if-no-ref/ 596 i2s1m0_sdo3: i2s1m0-sdo3 { 597 rockchip,pins = 598 /* i2s1_sdo3_m0 */ 599 <4 RK_PB6 2 &pcfg_pull_none>; 600 }; 601 602 /omit-if-no-ref/ 603 i2s1m1_lrck: i2s1m1-lrck { 604 rockchip,pins = 605 /* i2s1_lrck_m1 */ 606 <3 RK_PB4 1 &pcfg_pull_none_smt>; 607 }; 608 609 /omit-if-no-ref/ 610 i2s1m1_mclk: i2s1m1-mclk { 611 rockchip,pins = 612 /* i2s1_mclk_m1 */ 613 <3 RK_PB2 1 &pcfg_pull_none_smt>; 614 }; 615 616 /omit-if-no-ref/ 617 i2s1m1_sclk: i2s1m1-sclk { 618 rockchip,pins = 619 /* i2s1_sclk_m1 */ 620 <3 RK_PB3 1 &pcfg_pull_none_smt>; 621 }; 622 623 /omit-if-no-ref/ 624 i2s1m1_sdi0: i2s1m1-sdi0 { 625 rockchip,pins = 626 /* i2s1_sdi0_m1 */ 627 <3 RK_PC1 1 &pcfg_pull_none>; 628 }; 629 630 /omit-if-no-ref/ 631 i2s1m1_sdi1: i2s1m1-sdi1 { 632 rockchip,pins = 633 /* i2s1_sdi1_m1 */ 634 <3 RK_PC0 2 &pcfg_pull_none>; 635 }; 636 637 /omit-if-no-ref/ 638 i2s1m1_sdi2: i2s1m1-sdi2 { 639 rockchip,pins = 640 /* i2s1_sdi2_m1 */ 641 <3 RK_PB7 2 &pcfg_pull_none>; 642 }; 643 644 /omit-if-no-ref/ 645 i2s1m1_sdi3: i2s1m1-sdi3 { 646 rockchip,pins = 647 /* i2s1_sdi3_m1 */ 648 <3 RK_PB6 2 &pcfg_pull_none>; 649 }; 650 651 /omit-if-no-ref/ 652 i2s1m1_sdo0: i2s1m1-sdo0 { 653 rockchip,pins = 654 /* i2s1_sdo0_m1 */ 655 <3 RK_PB5 1 &pcfg_pull_none>; 656 }; 657 658 /omit-if-no-ref/ 659 i2s1m1_sdo1: i2s1m1-sdo1 { 660 rockchip,pins = 661 /* i2s1_sdo1_m1 */ 662 <3 RK_PB6 1 &pcfg_pull_none>; 663 }; 664 665 /omit-if-no-ref/ 666 i2s1m1_sdo2: i2s1m1-sdo2 { 667 rockchip,pins = 668 /* i2s1_sdo2_m1 */ 669 <3 RK_PB7 1 &pcfg_pull_none>; 670 }; 671 672 /omit-if-no-ref/ 673 i2s1m1_sdo3: i2s1m1-sdo3 { 674 rockchip,pins = 675 /* i2s1_sdo3_m1 */ 676 <3 RK_PC0 1 &pcfg_pull_none>; 677 }; 678 }; 679 680 i2s2 { 681 /omit-if-no-ref/ 682 i2s2m0_lrck: i2s2m0-lrck { 683 rockchip,pins = 684 /* i2s2_lrck_m0 */ 685 <1 RK_PD6 1 &pcfg_pull_none_smt>; 686 }; 687 688 /omit-if-no-ref/ 689 i2s2m0_mclk: i2s2m0-mclk { 690 rockchip,pins = 691 /* i2s2_mclk_m0 */ 692 <2 RK_PA1 1 &pcfg_pull_none_smt>; 693 }; 694 695 /omit-if-no-ref/ 696 i2s2m0_sclk: i2s2m0-sclk { 697 rockchip,pins = 698 /* i2s2_sclk_m0 */ 699 <1 RK_PD5 1 &pcfg_pull_none_smt>; 700 }; 701 702 /omit-if-no-ref/ 703 i2s2m0_sdi: i2s2m0-sdi { 704 rockchip,pins = 705 /* i2s2_sdi_m0 */ 706 <2 RK_PA0 1 &pcfg_pull_none>; 707 }; 708 709 /omit-if-no-ref/ 710 i2s2m0_sdo: i2s2m0-sdo { 711 rockchip,pins = 712 /* i2s2_sdo_m0 */ 713 <1 RK_PD7 1 &pcfg_pull_none>; 714 }; 715 716 /omit-if-no-ref/ 717 i2s2m1_lrck: i2s2m1-lrck { 718 rockchip,pins = 719 /* i2s2_lrck_m1 */ 720 <4 RK_PA1 3 &pcfg_pull_none_smt>; 721 }; 722 723 /omit-if-no-ref/ 724 i2s2m1_mclk: i2s2m1-mclk { 725 rockchip,pins = 726 /* i2s2_mclk_m1 */ 727 <3 RK_PD6 3 &pcfg_pull_none_smt>; 728 }; 729 730 /omit-if-no-ref/ 731 i2s2m1_sclk: i2s2m1-sclk { 732 rockchip,pins = 733 /* i2s2_sclk_m1 */ 734 <4 RK_PB1 4 &pcfg_pull_none_smt>; 735 }; 736 737 /omit-if-no-ref/ 738 i2s2m1_sdi: i2s2m1-sdi { 739 rockchip,pins = 740 /* i2s2_sdi_m1 */ 741 <3 RK_PD4 4 &pcfg_pull_none>; 742 }; 743 744 /omit-if-no-ref/ 745 i2s2m1_sdo: i2s2m1-sdo { 746 rockchip,pins = 747 /* i2s2_sdo_m1 */ 748 <3 RK_PD5 4 &pcfg_pull_none>; 749 }; 750 }; 751 752 isp { 753 /omit-if-no-ref/ 754 isp_pins: isp-pins { 755 rockchip,pins = 756 /* isp_flash_trigin */ 757 <3 RK_PC1 2 &pcfg_pull_none>, 758 /* isp_flash_trigout */ 759 <3 RK_PC3 2 &pcfg_pull_none>, 760 /* isp_prelight_trigout */ 761 <3 RK_PC2 2 &pcfg_pull_none>; 762 }; 763 }; 764 765 jtag { 766 /omit-if-no-ref/ 767 jtagm0_pins: jtagm0-pins { 768 rockchip,pins = 769 /* jtag_cpu_mcu_tck_m0 */ 770 <0 RK_PD1 2 &pcfg_pull_none>, 771 /* jtag_cpu_mcu_tms_m0 */ 772 <0 RK_PD0 2 &pcfg_pull_none>; 773 }; 774 775 /omit-if-no-ref/ 776 jtagm1_pins: jtagm1-pins { 777 rockchip,pins = 778 /* jtag_cpu_mcu_tck_m1 */ 779 <1 RK_PB5 2 &pcfg_pull_none>, 780 /* jtag_cpu_mcu_tms_m1 */ 781 <1 RK_PB6 2 &pcfg_pull_none>; 782 }; 783 }; 784 785 npu { 786 /omit-if-no-ref/ 787 npu_pins: npu-pins { 788 rockchip,pins = 789 /* npu_avs */ 790 <0 RK_PC1 3 &pcfg_pull_none>; 791 }; 792 }; 793 794 pcie20 { 795 /omit-if-no-ref/ 796 pcie20m0_pins: pcie20m0-pins { 797 rockchip,pins = 798 /* pcie20_clkreqn_m0 */ 799 <0 RK_PA6 1 &pcfg_pull_none>, 800 /* pcie20_perstn_m0 */ 801 <0 RK_PB5 2 &pcfg_pull_none>, 802 /* pcie20_waken_m0 */ 803 <0 RK_PB6 2 &pcfg_pull_none>; 804 }; 805 806 /omit-if-no-ref/ 807 pcie20m1_pins: pcie20m1-pins { 808 rockchip,pins = 809 /* pcie20_clkreqn_m1 */ 810 <3 RK_PA6 4 &pcfg_pull_none>, 811 /* pcie20_perstn_m1 */ 812 <3 RK_PB0 4 &pcfg_pull_none>, 813 /* pcie20_waken_m1 */ 814 <3 RK_PA7 4 &pcfg_pull_none>; 815 }; 816 817 /omit-if-no-ref/ 818 pcie20_buttonrstn: pcie20-buttonrstn { 819 rockchip,pins = 820 /* pcie20_buttonrstn */ 821 <0 RK_PB0 3 &pcfg_pull_none>; 822 }; 823 }; 824 825 pdm { 826 /omit-if-no-ref/ 827 pdmm0_clk0: pdmm0-clk0 { 828 rockchip,pins = 829 /* pdm_clk0_m0 */ 830 <3 RK_PA6 3 &pcfg_pull_none>; 831 }; 832 833 /omit-if-no-ref/ 834 pdmm0_clk1: pdmm0-clk1 { 835 rockchip,pins = 836 /* pdm_clk1_m0 */ 837 <3 RK_PA2 3 &pcfg_pull_none>; 838 }; 839 840 /omit-if-no-ref/ 841 pdmm0_sdi0: pdmm0-sdi0 { 842 rockchip,pins = 843 /* pdm_sdi0_m0 */ 844 <3 RK_PB1 2 &pcfg_pull_none>; 845 }; 846 847 /omit-if-no-ref/ 848 pdmm0_sdi1: pdmm0-sdi1 { 849 rockchip,pins = 850 /* pdm_sdi1_m0 */ 851 <3 RK_PB0 3 &pcfg_pull_none>; 852 }; 853 854 /omit-if-no-ref/ 855 pdmm0_sdi2: pdmm0-sdi2 { 856 rockchip,pins = 857 /* pdm_sdi2_m0 */ 858 <3 RK_PA7 3 &pcfg_pull_none>; 859 }; 860 861 /omit-if-no-ref/ 862 pdmm0_sdi3: pdmm0-sdi3 { 863 rockchip,pins = 864 /* pdm_sdi3_m0 */ 865 <3 RK_PA0 3 &pcfg_pull_none>; 866 }; 867 868 /omit-if-no-ref/ 869 pdmm1_clk0: pdmm1-clk0 { 870 rockchip,pins = 871 /* pdm_clk0_m1 */ 872 <4 RK_PB7 4 &pcfg_pull_none>; 873 }; 874 875 /omit-if-no-ref/ 876 pdmm1_clk1: pdmm1-clk1 { 877 rockchip,pins = 878 /* pdm_clk1_m1 */ 879 <4 RK_PB1 5 &pcfg_pull_none>; 880 }; 881 882 /omit-if-no-ref/ 883 pdmm1_sdi0: pdmm1-sdi0 { 884 rockchip,pins = 885 /* pdm_sdi0_m1 */ 886 <4 RK_PA7 4 &pcfg_pull_none>; 887 }; 888 889 /omit-if-no-ref/ 890 pdmm1_sdi1: pdmm1-sdi1 { 891 rockchip,pins = 892 /* pdm_sdi1_m1 */ 893 <4 RK_PB0 4 &pcfg_pull_none>; 894 }; 895 896 /omit-if-no-ref/ 897 pdmm1_sdi2: pdmm1-sdi2 { 898 rockchip,pins = 899 /* pdm_sdi2_m1 */ 900 <4 RK_PA5 4 &pcfg_pull_none>; 901 }; 902 903 /omit-if-no-ref/ 904 pdmm1_sdi3: pdmm1-sdi3 { 905 rockchip,pins = 906 /* pdm_sdi3_m1 */ 907 <4 RK_PA6 4 &pcfg_pull_none>; 908 }; 909 }; 910 911 pmic { 912 /omit-if-no-ref/ 913 pmic_int: pmic-int { 914 rockchip,pins = 915 <0 RK_PA3 0 &pcfg_pull_up>; 916 }; 917 918 /omit-if-no-ref/ 919 soc_slppin_gpio: soc-slppin-gpio { 920 rockchip,pins = 921 <0 RK_PA2 0 &pcfg_output_low>; 922 }; 923 924 /omit-if-no-ref/ 925 soc_slppin_slp: soc-slppin-slp { 926 rockchip,pins = 927 <0 RK_PA2 1 &pcfg_pull_none>; 928 }; 929 }; 930 931 pmu { 932 /omit-if-no-ref/ 933 pmu_pins: pmu-pins { 934 rockchip,pins = 935 /* pmu_debug */ 936 <0 RK_PA5 3 &pcfg_pull_none>; 937 }; 938 }; 939 940 pwm0 { 941 /omit-if-no-ref/ 942 pwm0m0_pins: pwm0m0-pins { 943 rockchip,pins = 944 /* pwm0_m0 */ 945 <0 RK_PC3 2 &pcfg_pull_none_drv_level_1>; 946 }; 947 948 /omit-if-no-ref/ 949 pwm0m1_pins: pwm0m1-pins { 950 rockchip,pins = 951 /* pwm0_m1 */ 952 <1 RK_PC5 4 &pcfg_pull_none_drv_level_1>; 953 }; 954 }; 955 956 pwm1 { 957 /omit-if-no-ref/ 958 pwm1m0_pins: pwm1m0-pins { 959 rockchip,pins = 960 /* pwm1_m0 */ 961 <0 RK_PC4 2 &pcfg_pull_none_drv_level_1>; 962 }; 963 964 /omit-if-no-ref/ 965 pwm1m1_pins: pwm1m1-pins { 966 rockchip,pins = 967 /* pwm1_m1 */ 968 <1 RK_PC6 4 &pcfg_pull_none_drv_level_1>; 969 }; 970 }; 971 972 pwm2 { 973 /omit-if-no-ref/ 974 pwm2m0_pins: pwm2m0-pins { 975 rockchip,pins = 976 /* pwm2_m0 */ 977 <0 RK_PC5 2 &pcfg_pull_none_drv_level_1>; 978 }; 979 980 /omit-if-no-ref/ 981 pwm2m1_pins: pwm2m1-pins { 982 rockchip,pins = 983 /* pwm2_m1 */ 984 <1 RK_PC7 3 &pcfg_pull_none_drv_level_1>; 985 }; 986 }; 987 988 pwm3 { 989 /omit-if-no-ref/ 990 pwm3m0_pins: pwm3m0-pins { 991 rockchip,pins = 992 /* pwm3_m0 */ 993 <0 RK_PA7 1 &pcfg_pull_none_drv_level_1>; 994 }; 995 996 /omit-if-no-ref/ 997 pwm3m1_pins: pwm3m1-pins { 998 rockchip,pins = 999 /* pwm3_m1 */ 1000 <1 RK_PD0 3 &pcfg_pull_none_drv_level_1>; 1001 }; 1002 }; 1003 1004 pwm4 { 1005 /omit-if-no-ref/ 1006 pwm4m0_pins: pwm4m0-pins { 1007 rockchip,pins = 1008 /* pwm4_m0 */ 1009 <0 RK_PB7 2 &pcfg_pull_none_drv_level_1>; 1010 }; 1011 1012 /omit-if-no-ref/ 1013 pwm4m1_pins: pwm4m1-pins { 1014 rockchip,pins = 1015 /* pwm4_m1 */ 1016 <1 RK_PD1 4 &pcfg_pull_none_drv_level_1>; 1017 }; 1018 }; 1019 1020 pwm5 { 1021 /omit-if-no-ref/ 1022 pwm5m0_pins: pwm5m0-pins { 1023 rockchip,pins = 1024 /* pwm5_m0 */ 1025 <0 RK_PC2 2 &pcfg_pull_none_drv_level_1>; 1026 }; 1027 1028 /omit-if-no-ref/ 1029 pwm5m1_pins: pwm5m1-pins { 1030 rockchip,pins = 1031 /* pwm5_m1 */ 1032 <1 RK_PD2 4 &pcfg_pull_none_drv_level_1>; 1033 }; 1034 }; 1035 1036 pwm6 { 1037 /omit-if-no-ref/ 1038 pwm6m0_pins: pwm6m0-pins { 1039 rockchip,pins = 1040 /* pwm6_m0 */ 1041 <0 RK_PC1 2 &pcfg_pull_none_drv_level_1>; 1042 }; 1043 1044 /omit-if-no-ref/ 1045 pwm6m1_pins: pwm6m1-pins { 1046 rockchip,pins = 1047 /* pwm6_m1 */ 1048 <1 RK_PD3 4 &pcfg_pull_none_drv_level_1>; 1049 }; 1050 }; 1051 1052 pwm7 { 1053 /omit-if-no-ref/ 1054 pwm7m0_pins: pwm7m0-pins { 1055 rockchip,pins = 1056 /* pwm7_m0 */ 1057 <0 RK_PC0 2 &pcfg_pull_none_drv_level_1>; 1058 }; 1059 1060 /omit-if-no-ref/ 1061 pwm7m1_pins: pwm7m1-pins { 1062 rockchip,pins = 1063 /* pwm7_m1 */ 1064 <1 RK_PD4 4 &pcfg_pull_none_drv_level_1>; 1065 }; 1066 }; 1067 1068 pwm8 { 1069 /omit-if-no-ref/ 1070 pwm8m0_pins: pwm8m0-pins { 1071 rockchip,pins = 1072 /* pwm8_m0 */ 1073 <3 RK_PA4 2 &pcfg_pull_none_drv_level_1>; 1074 }; 1075 1076 /omit-if-no-ref/ 1077 pwm8m1_pins: pwm8m1-pins { 1078 rockchip,pins = 1079 /* pwm8_m1 */ 1080 <1 RK_PC1 4 &pcfg_pull_none_drv_level_1>; 1081 }; 1082 }; 1083 1084 pwm9 { 1085 /omit-if-no-ref/ 1086 pwm9m0_pins: pwm9m0-pins { 1087 rockchip,pins = 1088 /* pwm9_m0 */ 1089 <3 RK_PA5 2 &pcfg_pull_none_drv_level_1>; 1090 }; 1091 1092 /omit-if-no-ref/ 1093 pwm9m1_pins: pwm9m1-pins { 1094 rockchip,pins = 1095 /* pwm9_m1 */ 1096 <1 RK_PC2 4 &pcfg_pull_none_drv_level_1>; 1097 }; 1098 }; 1099 1100 pwm10 { 1101 /omit-if-no-ref/ 1102 pwm10m0_pins: pwm10m0-pins { 1103 rockchip,pins = 1104 /* pwm10_m0 */ 1105 <1 RK_PB5 5 &pcfg_pull_none_drv_level_1>; 1106 }; 1107 1108 /omit-if-no-ref/ 1109 pwm10m1_pins: pwm10m1-pins { 1110 rockchip,pins = 1111 /* pwm10_m1 */ 1112 <1 RK_PC3 4 &pcfg_pull_none_drv_level_1>; 1113 }; 1114 }; 1115 1116 pwm11 { 1117 /omit-if-no-ref/ 1118 pwm11m0_pins: pwm11m0-pins { 1119 rockchip,pins = 1120 /* pwm11_m0 */ 1121 <1 RK_PB6 5 &pcfg_pull_none_drv_level_1>; 1122 }; 1123 1124 /omit-if-no-ref/ 1125 pwm11m1_pins: pwm11m1-pins { 1126 rockchip,pins = 1127 /* pwm11_m1 */ 1128 <1 RK_PC4 4 &pcfg_pull_none_drv_level_1>; 1129 }; 1130 }; 1131 1132 pwm12 { 1133 /omit-if-no-ref/ 1134 pwm12m0_pins: pwm12m0-pins { 1135 rockchip,pins = 1136 /* pwm12_m0 */ 1137 <4 RK_PA1 4 &pcfg_pull_none_drv_level_1>; 1138 }; 1139 1140 /omit-if-no-ref/ 1141 pwm12m1_pins: pwm12m1-pins { 1142 rockchip,pins = 1143 /* pwm12_m1 */ 1144 <3 RK_PB4 5 &pcfg_pull_none_drv_level_1>; 1145 }; 1146 }; 1147 1148 pwm13 { 1149 /omit-if-no-ref/ 1150 pwm13m0_pins: pwm13m0-pins { 1151 rockchip,pins = 1152 /* pwm13_m0 */ 1153 <4 RK_PA4 3 &pcfg_pull_none_drv_level_1>; 1154 }; 1155 1156 /omit-if-no-ref/ 1157 pwm13m1_pins: pwm13m1-pins { 1158 rockchip,pins = 1159 /* pwm13_m1 */ 1160 <3 RK_PB5 5 &pcfg_pull_none_drv_level_1>; 1161 }; 1162 }; 1163 1164 pwm14 { 1165 /omit-if-no-ref/ 1166 pwm14m0_pins: pwm14m0-pins { 1167 rockchip,pins = 1168 /* pwm14_m0 */ 1169 <3 RK_PC5 4 &pcfg_pull_none_drv_level_1>; 1170 }; 1171 1172 /omit-if-no-ref/ 1173 pwm14m1_pins: pwm14m1-pins { 1174 rockchip,pins = 1175 /* pwm14_m1 */ 1176 <1 RK_PD7 5 &pcfg_pull_none_drv_level_1>; 1177 }; 1178 }; 1179 1180 pwm15 { 1181 /omit-if-no-ref/ 1182 pwm15m0_pins: pwm15m0-pins { 1183 rockchip,pins = 1184 /* pwm15_m0 */ 1185 <3 RK_PC6 4 &pcfg_pull_none_drv_level_1>; 1186 }; 1187 1188 /omit-if-no-ref/ 1189 pwm15m1_pins: pwm15m1-pins { 1190 rockchip,pins = 1191 /* pwm15_m1 */ 1192 <2 RK_PA0 5 &pcfg_pull_none_drv_level_1>; 1193 }; 1194 }; 1195 1196 pwr { 1197 /omit-if-no-ref/ 1198 pwr_pins: pwr-pins { 1199 rockchip,pins = 1200 /* pwr_ctrl0 */ 1201 <0 RK_PA2 1 &pcfg_pull_none>, 1202 /* pwr_ctrl1 */ 1203 <0 RK_PA3 1 &pcfg_pull_none>; 1204 }; 1205 }; 1206 1207 ref { 1208 /omit-if-no-ref/ 1209 ref_pins: ref-pins { 1210 rockchip,pins = 1211 /* ref_clk_out */ 1212 <0 RK_PA0 1 &pcfg_pull_none>; 1213 }; 1214 }; 1215 1216 rgmii { 1217 /omit-if-no-ref/ 1218 rgmiim0_miim: rgmiim0-miim { 1219 rockchip,pins = 1220 /* rgmii_mdc_m0 */ 1221 <4 RK_PB2 2 &pcfg_pull_none>, 1222 /* rgmii_mdio_m0 */ 1223 <4 RK_PB3 2 &pcfg_pull_none>; 1224 }; 1225 1226 /omit-if-no-ref/ 1227 rgmiim0_rx_er: rgmiim0-rx_er { 1228 rockchip,pins = 1229 /* rgmii_rxer_m0 */ 1230 <4 RK_PB0 2 &pcfg_pull_none>; 1231 }; 1232 1233 /omit-if-no-ref/ 1234 rgmiim0_rx_bus2: rgmiim0-rx_bus2 { 1235 rockchip,pins = 1236 /* rgmii_rxd0_m0 */ 1237 <4 RK_PA5 2 &pcfg_pull_none>, 1238 /* rgmii_rxd1_m0 */ 1239 <4 RK_PA6 2 &pcfg_pull_none>, 1240 /* rgmii_rxdv_m0 */ 1241 <4 RK_PA7 2 &pcfg_pull_none>; 1242 }; 1243 1244 /omit-if-no-ref/ 1245 rgmiim0_tx_bus2: rgmiim0-tx_bus2 { 1246 rockchip,pins = 1247 /* rgmii_txd0_m0 */ 1248 <4 RK_PA2 2 &pcfg_pull_none>, 1249 /* rgmii_txd1_m0 */ 1250 <4 RK_PA3 2 &pcfg_pull_none>, 1251 /* rgmii_txen_m0 */ 1252 <4 RK_PA4 2 &pcfg_pull_none>; 1253 }; 1254 1255 /omit-if-no-ref/ 1256 rgmiim0_rgmii_clk: rgmiim0-rgmii_clk { 1257 rockchip,pins = 1258 /* rgmii_rxclk_m0 */ 1259 <4 RK_PA1 2 &pcfg_pull_none>, 1260 /* rgmii_txclk_m0 */ 1261 <3 RK_PD6 2 &pcfg_pull_none>; 1262 }; 1263 1264 /omit-if-no-ref/ 1265 rgmiim0_rgmii_bus: rgmiim0-rgmii_bus { 1266 rockchip,pins = 1267 /* rgmii_rxd2_m0 */ 1268 <3 RK_PD7 2 &pcfg_pull_none>, 1269 /* rgmii_rxd3_m0 */ 1270 <4 RK_PA0 2 &pcfg_pull_none>, 1271 /* rgmii_txd2_m0 */ 1272 <3 RK_PD4 2 &pcfg_pull_none>, 1273 /* rgmii_txd3_m0 */ 1274 <3 RK_PD5 2 &pcfg_pull_none>; 1275 }; 1276 1277 /omit-if-no-ref/ 1278 rgmiim0_clk: rgmiim0-clk { 1279 rockchip,pins = 1280 /* rgmiim0_clk */ 1281 <4 RK_PB7 2 &pcfg_pull_none>; 1282 }; 1283 1284 /omit-if-no-ref/ 1285 rgmiim1_miim: rgmiim1-miim { 1286 rockchip,pins = 1287 /* rgmii_mdc_m1 */ 1288 <1 RK_PC7 2 &pcfg_pull_none>, 1289 /* rgmii_mdio_m1 */ 1290 <1 RK_PD0 2 &pcfg_pull_none>; 1291 }; 1292 1293 /omit-if-no-ref/ 1294 rgmiim1_rx_er: rgmiim1-rx_er { 1295 rockchip,pins = 1296 /* rgmii_rxer_m1 */ 1297 <2 RK_PA0 2 &pcfg_pull_none>; 1298 }; 1299 1300 /omit-if-no-ref/ 1301 rgmiim1_rx_bus2: rgmiim1-rx_bus2 { 1302 rockchip,pins = 1303 /* rgmii_rxd0_m1 */ 1304 <1 RK_PD4 2 &pcfg_pull_none>, 1305 /* rgmii_rxd1_m1 */ 1306 <1 RK_PD7 2 &pcfg_pull_none>, 1307 /* rgmii_rxdv_m1 */ 1308 <1 RK_PD6 2 &pcfg_pull_none>; 1309 }; 1310 1311 /omit-if-no-ref/ 1312 rgmiim1_tx_bus2: rgmiim1-tx_bus2 { 1313 rockchip,pins = 1314 /* rgmii_txd0_m1 */ 1315 <1 RK_PD1 2 &pcfg_pull_none>, 1316 /* rgmii_txd1_m1 */ 1317 <1 RK_PD2 2 &pcfg_pull_none>, 1318 /* rgmii_txen_m1 */ 1319 <1 RK_PD3 2 &pcfg_pull_none>; 1320 }; 1321 1322 /omit-if-no-ref/ 1323 rgmiim1_rgmii_clk: rgmiim1-rgmii_clk { 1324 rockchip,pins = 1325 /* rgmii_rxclk_m1 */ 1326 <1 RK_PC6 2 &pcfg_pull_none>, 1327 /* rgmii_txclk_m1 */ 1328 <1 RK_PC3 2 &pcfg_pull_none>; 1329 }; 1330 1331 /omit-if-no-ref/ 1332 rgmiim1_rgmii_bus: rgmiim1-rgmii_bus { 1333 rockchip,pins = 1334 /* rgmii_rxd2_m1 */ 1335 <1 RK_PC4 2 &pcfg_pull_none>, 1336 /* rgmii_rxd3_m1 */ 1337 <1 RK_PC5 2 &pcfg_pull_none>, 1338 /* rgmii_txd2_m1 */ 1339 <1 RK_PC1 2 &pcfg_pull_none>, 1340 /* rgmii_txd3_m1 */ 1341 <1 RK_PC2 2 &pcfg_pull_none>; 1342 }; 1343 1344 /omit-if-no-ref/ 1345 rgmiim1_clk: rgmiim1-clk { 1346 rockchip,pins = 1347 /* rgmiim1_clk */ 1348 <1 RK_PD5 2 &pcfg_pull_none>; 1349 }; 1350 }; 1351 1352 rmii { 1353 /omit-if-no-ref/ 1354 rmii_pins: rmii-pins { 1355 rockchip,pins = 1356 /* rmii_clk */ 1357 <1 RK_PD5 5 &pcfg_pull_none>, 1358 /* rmii_mdc */ 1359 <1 RK_PC7 5 &pcfg_pull_none>, 1360 /* rmii_mdio */ 1361 <1 RK_PD0 5 &pcfg_pull_none>, 1362 /* rmii_rxd0 */ 1363 <1 RK_PD4 5 &pcfg_pull_none>, 1364 /* rmii_rxd1 */ 1365 <1 RK_PD7 6 &pcfg_pull_none>, 1366 /* rmii_rxdv_crs */ 1367 <1 RK_PD6 5 &pcfg_pull_none>, 1368 /* rmii_rxer */ 1369 <2 RK_PA0 6 &pcfg_pull_none>, 1370 /* rmii_txd0 */ 1371 <1 RK_PD1 5 &pcfg_pull_none>, 1372 /* rmii_txd1 */ 1373 <1 RK_PD2 5 &pcfg_pull_none>, 1374 /* rmii_txen */ 1375 <1 RK_PD3 5 &pcfg_pull_none>; 1376 }; 1377 }; 1378 1379 sdmmc0 { 1380 /omit-if-no-ref/ 1381 sdmmc0_bus4: sdmmc0-bus4 { 1382 rockchip,pins = 1383 /* sdmmc0_d0 */ 1384 <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>, 1385 /* sdmmc0_d1 */ 1386 <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, 1387 /* sdmmc0_d2 */ 1388 <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, 1389 /* sdmmc0_d3 */ 1390 <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>; 1391 }; 1392 1393 /omit-if-no-ref/ 1394 sdmmc0_clk: sdmmc0-clk { 1395 rockchip,pins = 1396 /* sdmmc0_clk */ 1397 <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>; 1398 }; 1399 1400 /omit-if-no-ref/ 1401 sdmmc0_cmd: sdmmc0-cmd { 1402 rockchip,pins = 1403 /* sdmmc0_cmd */ 1404 <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; 1405 }; 1406 1407 /omit-if-no-ref/ 1408 sdmmc0_det: sdmmc0-det { 1409 rockchip,pins = 1410 /* sdmmc0_detn */ 1411 <0 RK_PA4 1 &pcfg_pull_up>; 1412 }; 1413 1414 /omit-if-no-ref/ 1415 sdmmc0_pwren: sdmmc0-pwren { 1416 rockchip,pins = 1417 /* sdmmc0_pwren */ 1418 <0 RK_PA5 1 &pcfg_pull_none>; 1419 }; 1420 }; 1421 1422 sdmmc1 { 1423 /omit-if-no-ref/ 1424 sdmmc1_bus4: sdmmc1-bus4 { 1425 rockchip,pins = 1426 /* sdmmc1_d0 */ 1427 <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, 1428 /* sdmmc1_d1 */ 1429 <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, 1430 /* sdmmc1_d2 */ 1431 <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>, 1432 /* sdmmc1_d3 */ 1433 <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; 1434 }; 1435 1436 /omit-if-no-ref/ 1437 sdmmc1_clk: sdmmc1-clk { 1438 rockchip,pins = 1439 /* sdmmc1_clk */ 1440 <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>; 1441 }; 1442 1443 /omit-if-no-ref/ 1444 sdmmc1_cmd: sdmmc1-cmd { 1445 rockchip,pins = 1446 /* sdmmc1_cmd */ 1447 <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; 1448 }; 1449 1450 /omit-if-no-ref/ 1451 sdmmc1_det: sdmmc1-det { 1452 rockchip,pins = 1453 /* sdmmc1_detn */ 1454 <1 RK_PD0 1 &pcfg_pull_up>; 1455 }; 1456 1457 /omit-if-no-ref/ 1458 sdmmc1_pwren: sdmmc1-pwren { 1459 rockchip,pins = 1460 /* sdmmc1_pwren */ 1461 <1 RK_PC7 1 &pcfg_pull_none>; 1462 }; 1463 }; 1464 1465 spdif { 1466 /omit-if-no-ref/ 1467 spdifm0_pins: spdifm0-pins { 1468 rockchip,pins = 1469 /* spdif_tx_m0 */ 1470 <3 RK_PA1 3 &pcfg_pull_none>; 1471 }; 1472 1473 /omit-if-no-ref/ 1474 spdifm1_pins: spdifm1-pins { 1475 rockchip,pins = 1476 /* spdif_tx_m1 */ 1477 <0 RK_PB7 4 &pcfg_pull_none>; 1478 }; 1479 1480 /omit-if-no-ref/ 1481 spdifm2_pins: spdifm2-pins { 1482 rockchip,pins = 1483 /* spdif_tx_m2 */ 1484 <1 RK_PB7 2 &pcfg_pull_none>; 1485 }; 1486 }; 1487 1488 spi0 { 1489 /omit-if-no-ref/ 1490 spi0m0_pins: spi0m0-pins { 1491 rockchip,pins = 1492 /* spi0_clk_m0 */ 1493 <0 RK_PC3 3 &pcfg_pull_none_drv_level_3>, 1494 /* spi0_miso_m0 */ 1495 <0 RK_PC5 3 &pcfg_pull_none_drv_level_3>, 1496 /* spi0_mosi_m0 */ 1497 <0 RK_PC4 3 &pcfg_pull_none_drv_level_3>; 1498 }; 1499 1500 /omit-if-no-ref/ 1501 spi0m0_csn0: spi0m0-csn0 { 1502 rockchip,pins = 1503 /* spi0m0_csn0 */ 1504 <0 RK_PC2 3 &pcfg_pull_none_drv_level_3>; 1505 }; 1506 /omit-if-no-ref/ 1507 spi0m0_csn1: spi0m0-csn1 { 1508 rockchip,pins = 1509 /* spi0m0_csn1 */ 1510 <0 RK_PB7 1 &pcfg_pull_none_drv_level_3>; 1511 }; 1512 1513 /omit-if-no-ref/ 1514 spi0m1_pins: spi0m1-pins { 1515 rockchip,pins = 1516 /* spi0_clk_m1 */ 1517 <3 RK_PB5 4 &pcfg_pull_none_drv_level_3>, 1518 /* spi0_miso_m1 */ 1519 <3 RK_PC0 4 &pcfg_pull_none_drv_level_3>, 1520 /* spi0_mosi_m1 */ 1521 <3 RK_PB4 4 &pcfg_pull_none_drv_level_3>; 1522 }; 1523 1524 /omit-if-no-ref/ 1525 spi0m1_csn0: spi0m1-csn0 { 1526 rockchip,pins = 1527 /* spi0m1_csn0 */ 1528 <3 RK_PB7 4 &pcfg_pull_none_drv_level_3>; 1529 }; 1530 /omit-if-no-ref/ 1531 spi0m1_csn1: spi0m1-csn1 { 1532 rockchip,pins = 1533 /* spi0m1_csn1 */ 1534 <3 RK_PB6 4 &pcfg_pull_none_drv_level_3>; 1535 }; 1536 }; 1537 1538 spi1 { 1539 /omit-if-no-ref/ 1540 spi1m0_pins: spi1m0-pins { 1541 rockchip,pins = 1542 /* spi1_clk_m0 */ 1543 <3 RK_PD6 4 &pcfg_pull_none_drv_level_3>, 1544 /* spi1_miso_m0 */ 1545 <4 RK_PA3 4 &pcfg_pull_none_drv_level_3>, 1546 /* spi1_mosi_m0 */ 1547 <4 RK_PA2 4 &pcfg_pull_none_drv_level_3>; 1548 }; 1549 1550 /omit-if-no-ref/ 1551 spi1m0_csn0: spi1m0-csn0 { 1552 rockchip,pins = 1553 /* spi1m0_csn0 */ 1554 <3 RK_PD7 4 &pcfg_pull_none_drv_level_3>; 1555 }; 1556 /omit-if-no-ref/ 1557 spi1m0_csn1: spi1m0-csn1 { 1558 rockchip,pins = 1559 /* spi1m0_csn1 */ 1560 <4 RK_PA0 4 &pcfg_pull_none_drv_level_3>; 1561 }; 1562 1563 /omit-if-no-ref/ 1564 spi1m1_pins: spi1m1-pins { 1565 rockchip,pins = 1566 /* spi1_clk_m1 */ 1567 <1 RK_PC0 4 &pcfg_pull_none_drv_level_3>, 1568 /* spi1_miso_m1 */ 1569 <1 RK_PB4 4 &pcfg_pull_none_drv_level_3>, 1570 /* spi1_mosi_m1 */ 1571 <1 RK_PB3 4 &pcfg_pull_none_drv_level_3>; 1572 }; 1573 1574 /omit-if-no-ref/ 1575 spi1m1_csn0: spi1m1-csn0 { 1576 rockchip,pins = 1577 /* spi1m1_csn0 */ 1578 <1 RK_PB6 4 &pcfg_pull_none_drv_level_3>; 1579 }; 1580 /omit-if-no-ref/ 1581 spi1m1_csn1: spi1m1-csn1 { 1582 rockchip,pins = 1583 /* spi1m1_csn1 */ 1584 <1 RK_PB5 4 &pcfg_pull_none_drv_level_3>; 1585 }; 1586 }; 1587 1588 spi2 { 1589 /omit-if-no-ref/ 1590 spi2m0_pins: spi2m0-pins { 1591 rockchip,pins = 1592 /* spi2_clk_m0 */ 1593 <4 RK_PB6 4 &pcfg_pull_none_drv_level_3>, 1594 /* spi2_miso_m0 */ 1595 <3 RK_PD2 4 &pcfg_pull_none_drv_level_3>, 1596 /* spi2_mosi_m0 */ 1597 <3 RK_PD3 4 &pcfg_pull_none_drv_level_3>; 1598 }; 1599 1600 /omit-if-no-ref/ 1601 spi2m0_csn0: spi2m0-csn0 { 1602 rockchip,pins = 1603 /* spi2m0_csn0 */ 1604 <4 RK_PB5 4 &pcfg_pull_none_drv_level_3>; 1605 }; 1606 /omit-if-no-ref/ 1607 spi2m0_csn1: spi2m0-csn1 { 1608 rockchip,pins = 1609 /* spi2m0_csn1 */ 1610 <4 RK_PB4 4 &pcfg_pull_none_drv_level_3>; 1611 }; 1612 1613 /omit-if-no-ref/ 1614 spi2m1_pins: spi2m1-pins { 1615 rockchip,pins = 1616 /* spi2_clk_m1 */ 1617 <2 RK_PA1 4 &pcfg_pull_none_drv_level_3>, 1618 /* spi2_miso_m1 */ 1619 <2 RK_PA0 4 &pcfg_pull_none_drv_level_3>, 1620 /* spi2_mosi_m1 */ 1621 <1 RK_PD7 4 &pcfg_pull_none_drv_level_3>; 1622 }; 1623 1624 /omit-if-no-ref/ 1625 spi2m1_csn0: spi2m1-csn0 { 1626 rockchip,pins = 1627 /* spi2m1_csn0 */ 1628 <1 RK_PD6 4 &pcfg_pull_none_drv_level_3>; 1629 }; 1630 /omit-if-no-ref/ 1631 spi2m1_csn1: spi2m1-csn1 { 1632 rockchip,pins = 1633 /* spi2m1_csn1 */ 1634 <1 RK_PD5 4 &pcfg_pull_none_drv_level_3>; 1635 }; 1636 }; 1637 1638 tsadc { 1639 /omit-if-no-ref/ 1640 tsadcm0_pins: tsadcm0-pins { 1641 rockchip,pins = 1642 /* tsadc_shut_m0 */ 1643 <0 RK_PA1 1 &pcfg_pull_none>; 1644 }; 1645 1646 /omit-if-no-ref/ 1647 tsadcm1_pins: tsadcm1-pins { 1648 rockchip,pins = 1649 /* tsadc_shut_m1 */ 1650 <0 RK_PA2 2 &pcfg_pull_none>; 1651 }; 1652 1653 /omit-if-no-ref/ 1654 tsadc_shut_org: tsadc-shut-org { 1655 rockchip,pins = 1656 /* tsadc_shut_org */ 1657 <0 RK_PA1 2 &pcfg_pull_none>; 1658 }; 1659 }; 1660 1661 uart0 { 1662 /omit-if-no-ref/ 1663 uart0m0_xfer: uart0m0-xfer { 1664 rockchip,pins = 1665 /* uart0_rx_m0 */ 1666 <0 RK_PD0 1 &pcfg_pull_up>, 1667 /* uart0_tx_m0 */ 1668 <0 RK_PD1 1 &pcfg_pull_up>; 1669 }; 1670 1671 /omit-if-no-ref/ 1672 uart0m1_xfer: uart0m1-xfer { 1673 rockchip,pins = 1674 /* uart0_rx_m1 */ 1675 <1 RK_PB3 2 &pcfg_pull_up>, 1676 /* uart0_tx_m1 */ 1677 <1 RK_PB4 2 &pcfg_pull_up>; 1678 }; 1679 }; 1680 1681 uart1 { 1682 /omit-if-no-ref/ 1683 uart1m0_xfer: uart1m0-xfer { 1684 rockchip,pins = 1685 /* uart1_rx_m0 */ 1686 <1 RK_PD1 1 &pcfg_pull_up>, 1687 /* uart1_tx_m0 */ 1688 <1 RK_PD2 1 &pcfg_pull_up>; 1689 }; 1690 1691 /omit-if-no-ref/ 1692 uart1m0_ctsn: uart1m0-ctsn { 1693 rockchip,pins = 1694 /* uart1m0_ctsn */ 1695 <1 RK_PD4 1 &pcfg_pull_none>; 1696 }; 1697 /omit-if-no-ref/ 1698 uart1m0_rtsn: uart1m0-rtsn { 1699 rockchip,pins = 1700 /* uart1m0_rtsn */ 1701 <1 RK_PD3 1 &pcfg_pull_none>; 1702 }; 1703 1704 /omit-if-no-ref/ 1705 uart1m1_xfer: uart1m1-xfer { 1706 rockchip,pins = 1707 /* uart1_rx_m1 */ 1708 <4 RK_PA6 3 &pcfg_pull_up>, 1709 /* uart1_tx_m1 */ 1710 <4 RK_PA5 3 &pcfg_pull_up>; 1711 }; 1712 1713 /omit-if-no-ref/ 1714 uart1m1_ctsn: uart1m1-ctsn { 1715 rockchip,pins = 1716 /* uart1m1_ctsn */ 1717 <4 RK_PB0 3 &pcfg_pull_none>; 1718 }; 1719 /omit-if-no-ref/ 1720 uart1m1_rtsn: uart1m1-rtsn { 1721 rockchip,pins = 1722 /* uart1m1_rtsn */ 1723 <4 RK_PA7 3 &pcfg_pull_none>; 1724 }; 1725 }; 1726 1727 uart2 { 1728 /omit-if-no-ref/ 1729 uart2m0_xfer: uart2m0-xfer { 1730 rockchip,pins = 1731 /* uart2_rx_m0 */ 1732 <0 RK_PC1 1 &pcfg_pull_up>, 1733 /* uart2_tx_m0 */ 1734 <0 RK_PC0 1 &pcfg_pull_up>; 1735 }; 1736 1737 /omit-if-no-ref/ 1738 uart2m0_ctsn: uart2m0-ctsn { 1739 rockchip,pins = 1740 /* uart2m0_ctsn */ 1741 <0 RK_PC2 1 &pcfg_pull_none>; 1742 }; 1743 /omit-if-no-ref/ 1744 uart2m0_rtsn: uart2m0-rtsn { 1745 rockchip,pins = 1746 /* uart2m0_rtsn */ 1747 <0 RK_PC3 1 &pcfg_pull_none>; 1748 }; 1749 1750 /omit-if-no-ref/ 1751 uart2m1_xfer: uart2m1-xfer { 1752 rockchip,pins = 1753 /* uart2_rx_m1 */ 1754 <3 RK_PA1 2 &pcfg_pull_up>, 1755 /* uart2_tx_m1 */ 1756 <3 RK_PA0 2 &pcfg_pull_up>; 1757 }; 1758 1759 /omit-if-no-ref/ 1760 uart2m1_ctsn: uart2m1-ctsn { 1761 rockchip,pins = 1762 /* uart2m1_ctsn */ 1763 <3 RK_PA2 2 &pcfg_pull_none>; 1764 }; 1765 /omit-if-no-ref/ 1766 uart2m1_rtsn: uart2m1-rtsn { 1767 rockchip,pins = 1768 /* uart2m1_rtsn */ 1769 <3 RK_PA3 2 &pcfg_pull_none>; 1770 }; 1771 }; 1772 1773 uart3 { 1774 /omit-if-no-ref/ 1775 uart3m0_xfer: uart3m0-xfer { 1776 rockchip,pins = 1777 /* uart3_rx_m0 */ 1778 <4 RK_PB5 6 &pcfg_pull_up>, 1779 /* uart3_tx_m0 */ 1780 <4 RK_PB4 6 &pcfg_pull_up>; 1781 }; 1782 1783 /omit-if-no-ref/ 1784 uart3m0_ctsn: uart3m0-ctsn { 1785 rockchip,pins = 1786 /* uart3m0_ctsn */ 1787 <4 RK_PB6 3 &pcfg_pull_none>; 1788 }; 1789 /omit-if-no-ref/ 1790 uart3m0_rtsn: uart3m0-rtsn { 1791 rockchip,pins = 1792 /* uart3m0_rtsn */ 1793 <3 RK_PD1 4 &pcfg_pull_none>; 1794 }; 1795 1796 /omit-if-no-ref/ 1797 uart3m1_xfer: uart3m1-xfer { 1798 rockchip,pins = 1799 /* uart3_rx_m1 */ 1800 <3 RK_PC0 3 &pcfg_pull_up>, 1801 /* uart3_tx_m1 */ 1802 <3 RK_PB7 3 &pcfg_pull_up>; 1803 }; 1804 1805 /omit-if-no-ref/ 1806 uart3m1_ctsn: uart3m1-ctsn { 1807 rockchip,pins = 1808 /* uart3m1_ctsn */ 1809 <3 RK_PB6 3 &pcfg_pull_none>; 1810 }; 1811 /omit-if-no-ref/ 1812 uart3m1_rtsn: uart3m1-rtsn { 1813 rockchip,pins = 1814 /* uart3m1_rtsn */ 1815 <3 RK_PC1 3 &pcfg_pull_none>; 1816 }; 1817 }; 1818 1819 uart4 { 1820 /omit-if-no-ref/ 1821 uart4m0_xfer: uart4m0-xfer { 1822 rockchip,pins = 1823 /* uart4_rx_m0 */ 1824 <3 RK_PD1 3 &pcfg_pull_up>, 1825 /* uart4_tx_m0 */ 1826 <3 RK_PD0 3 &pcfg_pull_up>; 1827 }; 1828 1829 /omit-if-no-ref/ 1830 uart4m0_ctsn: uart4m0-ctsn { 1831 rockchip,pins = 1832 /* uart4m0_ctsn */ 1833 <3 RK_PC5 3 &pcfg_pull_none>; 1834 }; 1835 /omit-if-no-ref/ 1836 uart4m0_rtsn: uart4m0-rtsn { 1837 rockchip,pins = 1838 /* uart4m0_rtsn */ 1839 <3 RK_PC6 3 &pcfg_pull_none>; 1840 }; 1841 1842 /omit-if-no-ref/ 1843 uart4m1_xfer: uart4m1-xfer { 1844 rockchip,pins = 1845 /* uart4_rx_m1 */ 1846 <1 RK_PD5 3 &pcfg_pull_up>, 1847 /* uart4_tx_m1 */ 1848 <1 RK_PD6 3 &pcfg_pull_up>; 1849 }; 1850 1851 /omit-if-no-ref/ 1852 uart4m1_ctsn: uart4m1-ctsn { 1853 rockchip,pins = 1854 /* uart4m1_ctsn */ 1855 <2 RK_PA0 3 &pcfg_pull_none>; 1856 }; 1857 /omit-if-no-ref/ 1858 uart4m1_rtsn: uart4m1-rtsn { 1859 rockchip,pins = 1860 /* uart4m1_rtsn */ 1861 <1 RK_PD7 3 &pcfg_pull_none>; 1862 }; 1863 }; 1864 1865 uart5 { 1866 /omit-if-no-ref/ 1867 uart5m0_xfer: uart5m0-xfer { 1868 rockchip,pins = 1869 /* uart5_rx_m0 */ 1870 <1 RK_PB7 3 &pcfg_pull_up>, 1871 /* uart5_tx_m0 */ 1872 <1 RK_PC0 3 &pcfg_pull_up>; 1873 }; 1874 1875 /omit-if-no-ref/ 1876 uart5m0_ctsn: uart5m0-ctsn { 1877 rockchip,pins = 1878 /* uart5m0_ctsn */ 1879 <1 RK_PB5 3 &pcfg_pull_none>; 1880 }; 1881 /omit-if-no-ref/ 1882 uart5m0_rtsn: uart5m0-rtsn { 1883 rockchip,pins = 1884 /* uart5m0_rtsn */ 1885 <1 RK_PB6 3 &pcfg_pull_none>; 1886 }; 1887 1888 /omit-if-no-ref/ 1889 uart5m1_xfer: uart5m1-xfer { 1890 rockchip,pins = 1891 /* uart5_rx_m1 */ 1892 <3 RK_PA7 5 &pcfg_pull_up>, 1893 /* uart5_tx_m1 */ 1894 <3 RK_PA6 5 &pcfg_pull_up>; 1895 }; 1896 1897 /omit-if-no-ref/ 1898 uart5m1_ctsn: uart5m1-ctsn { 1899 rockchip,pins = 1900 /* uart5m1_ctsn */ 1901 <3 RK_PA0 5 &pcfg_pull_none>; 1902 }; 1903 /omit-if-no-ref/ 1904 uart5m1_rtsn: uart5m1-rtsn { 1905 rockchip,pins = 1906 /* uart5m1_rtsn */ 1907 <3 RK_PA1 5 &pcfg_pull_none>; 1908 }; 1909 }; 1910 1911 uart6 { 1912 /omit-if-no-ref/ 1913 uart6m0_xfer: uart6m0-xfer { 1914 rockchip,pins = 1915 /* uart6_rx_m0 */ 1916 <0 RK_PC7 1 &pcfg_pull_up>, 1917 /* uart6_tx_m0 */ 1918 <0 RK_PC6 1 &pcfg_pull_up>; 1919 }; 1920 1921 /omit-if-no-ref/ 1922 uart6m0_ctsn: uart6m0-ctsn { 1923 rockchip,pins = 1924 /* uart6m0_ctsn */ 1925 <0 RK_PC4 1 &pcfg_pull_none>; 1926 }; 1927 /omit-if-no-ref/ 1928 uart6m0_rtsn: uart6m0-rtsn { 1929 rockchip,pins = 1930 /* uart6m0_rtsn */ 1931 <0 RK_PC5 1 &pcfg_pull_none>; 1932 }; 1933 1934 /omit-if-no-ref/ 1935 uart6m1_xfer: uart6m1-xfer { 1936 rockchip,pins = 1937 /* uart6_rx_m1 */ 1938 <4 RK_PB0 5 &pcfg_pull_up>, 1939 /* uart6_tx_m1 */ 1940 <4 RK_PA7 5 &pcfg_pull_up>; 1941 }; 1942 1943 /omit-if-no-ref/ 1944 uart6m1_ctsn: uart6m1-ctsn { 1945 rockchip,pins = 1946 /* uart6m1_ctsn */ 1947 <4 RK_PA2 3 &pcfg_pull_none>; 1948 }; 1949 /omit-if-no-ref/ 1950 uart6m1_rtsn: uart6m1-rtsn { 1951 rockchip,pins = 1952 /* uart6m1_rtsn */ 1953 <4 RK_PA3 3 &pcfg_pull_none>; 1954 }; 1955 }; 1956 1957 uart7 { 1958 /omit-if-no-ref/ 1959 uart7m0_xfer: uart7m0-xfer { 1960 rockchip,pins = 1961 /* uart7_rx_m0 */ 1962 <3 RK_PC7 3 &pcfg_pull_up>, 1963 /* uart7_tx_m0 */ 1964 <3 RK_PC4 3 &pcfg_pull_up>; 1965 }; 1966 1967 /omit-if-no-ref/ 1968 uart7m0_ctsn: uart7m0-ctsn { 1969 rockchip,pins = 1970 /* uart7m0_ctsn */ 1971 <3 RK_PD2 3 &pcfg_pull_none>; 1972 }; 1973 /omit-if-no-ref/ 1974 uart7m0_rtsn: uart7m0-rtsn { 1975 rockchip,pins = 1976 /* uart7m0_rtsn */ 1977 <3 RK_PD3 3 &pcfg_pull_none>; 1978 }; 1979 1980 /omit-if-no-ref/ 1981 uart7m1_xfer: uart7m1-xfer { 1982 rockchip,pins = 1983 /* uart7_rx_m1 */ 1984 <1 RK_PB3 3 &pcfg_pull_up>, 1985 /* uart7_tx_m1 */ 1986 <1 RK_PB4 3 &pcfg_pull_up>; 1987 }; 1988 }; 1989 1990 uart8 { 1991 /omit-if-no-ref/ 1992 uart8m0_xfer: uart8m0-xfer { 1993 rockchip,pins = 1994 /* uart8_rx_m0 */ 1995 <3 RK_PB3 3 &pcfg_pull_up>, 1996 /* uart8_tx_m0 */ 1997 <3 RK_PB2 3 &pcfg_pull_up>; 1998 }; 1999 2000 /omit-if-no-ref/ 2001 uart8m0_ctsn: uart8m0-ctsn { 2002 rockchip,pins = 2003 /* uart8m0_ctsn */ 2004 <3 RK_PB4 3 &pcfg_pull_none>; 2005 }; 2006 /omit-if-no-ref/ 2007 uart8m0_rtsn: uart8m0-rtsn { 2008 rockchip,pins = 2009 /* uart8m0_rtsn */ 2010 <3 RK_PB5 3 &pcfg_pull_none>; 2011 }; 2012 2013 /omit-if-no-ref/ 2014 uart8m1_xfer: uart8m1-xfer { 2015 rockchip,pins = 2016 /* uart8_rx_m1 */ 2017 <3 RK_PD5 3 &pcfg_pull_up>, 2018 /* uart8_tx_m1 */ 2019 <3 RK_PD4 3 &pcfg_pull_up>; 2020 }; 2021 2022 /omit-if-no-ref/ 2023 uart8m1_ctsn: uart8m1-ctsn { 2024 rockchip,pins = 2025 /* uart8m1_ctsn */ 2026 <3 RK_PD7 3 &pcfg_pull_none>; 2027 }; 2028 /omit-if-no-ref/ 2029 uart8m1_rtsn: uart8m1-rtsn { 2030 rockchip,pins = 2031 /* uart8m1_rtsn */ 2032 <4 RK_PA0 3 &pcfg_pull_none>; 2033 }; 2034 }; 2035 2036 uart9 { 2037 /omit-if-no-ref/ 2038 uart9m0_xfer: uart9m0-xfer { 2039 rockchip,pins = 2040 /* uart9_rx_m0 */ 2041 <4 RK_PB3 3 &pcfg_pull_up>, 2042 /* uart9_tx_m0 */ 2043 <4 RK_PB2 3 &pcfg_pull_up>; 2044 }; 2045 2046 /omit-if-no-ref/ 2047 uart9m0_ctsn: uart9m0-ctsn { 2048 rockchip,pins = 2049 /* uart9m0_ctsn */ 2050 <4 RK_PB4 3 &pcfg_pull_none>; 2051 }; 2052 /omit-if-no-ref/ 2053 uart9m0_rtsn: uart9m0-rtsn { 2054 rockchip,pins = 2055 /* uart9m0_rtsn */ 2056 <4 RK_PB5 3 &pcfg_pull_none>; 2057 }; 2058 2059 /omit-if-no-ref/ 2060 uart9m1_xfer: uart9m1-xfer { 2061 rockchip,pins = 2062 /* uart9_rx_m1 */ 2063 <3 RK_PC3 3 &pcfg_pull_up>, 2064 /* uart9_tx_m1 */ 2065 <3 RK_PC2 3 &pcfg_pull_up>; 2066 }; 2067 }; 2068 2069 vo { 2070 /omit-if-no-ref/ 2071 vo_pins: vo-pins { 2072 rockchip,pins = 2073 /* vo_lcdc_clk */ 2074 <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, 2075 /* vo_lcdc_d0 */ 2076 <4 RK_PA4 1 &pcfg_pull_none_drv_level_3>, 2077 /* vo_lcdc_d1 */ 2078 <4 RK_PA5 1 &pcfg_pull_none_drv_level_3>, 2079 /* vo_lcdc_d2 */ 2080 <4 RK_PB2 1 &pcfg_pull_none_drv_level_3>, 2081 /* vo_lcdc_d3 */ 2082 <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, 2083 /* vo_lcdc_d4 */ 2084 <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, 2085 /* vo_lcdc_d5 */ 2086 <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, 2087 /* vo_lcdc_d6 */ 2088 <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, 2089 /* vo_lcdc_d7 */ 2090 <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, 2091 /* vo_lcdc_d8 */ 2092 <4 RK_PA6 1 &pcfg_pull_none_drv_level_3>, 2093 /* vo_lcdc_d9 */ 2094 <4 RK_PA7 1 &pcfg_pull_none_drv_level_3>, 2095 /* vo_lcdc_d10 */ 2096 <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, 2097 /* vo_lcdc_d11 */ 2098 <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, 2099 /* vo_lcdc_d12 */ 2100 <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, 2101 /* vo_lcdc_d13 */ 2102 <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, 2103 /* vo_lcdc_d14 */ 2104 <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, 2105 /* vo_lcdc_d15 */ 2106 <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, 2107 /* vo_lcdc_d16 */ 2108 <4 RK_PB0 1 &pcfg_pull_none_drv_level_3>, 2109 /* vo_lcdc_d17 */ 2110 <4 RK_PB1 1 &pcfg_pull_none_drv_level_3>, 2111 /* vo_lcdc_d18 */ 2112 <4 RK_PB3 1 &pcfg_pull_none_drv_level_3>, 2113 /* vo_lcdc_d19 */ 2114 <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, 2115 /* vo_lcdc_d20 */ 2116 <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, 2117 /* vo_lcdc_d21 */ 2118 <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, 2119 /* vo_lcdc_d22 */ 2120 <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, 2121 /* vo_lcdc_d23 */ 2122 <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, 2123 /* vo_lcdc_den */ 2124 <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, 2125 /* vo_lcdc_hsync */ 2126 <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, 2127 /* vo_lcdc_vsync */ 2128 <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; 2129 }; 2130 }; 2131}; 2132 2133/* 2134 * This part is edited handly. 2135 */ 2136&pinctrl { 2137 vo { 2138 /omit-if-no-ref/ 2139 bt1120_pins: bt1120-pins { 2140 rockchip,pins = 2141 /* vo_lcdc_clk */ 2142 <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, 2143 /* vo_lcdc_d3 */ 2144 <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, 2145 /* vo_lcdc_d4 */ 2146 <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, 2147 /* vo_lcdc_d5 */ 2148 <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, 2149 /* vo_lcdc_d6 */ 2150 <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, 2151 /* vo_lcdc_d7 */ 2152 <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, 2153 /* vo_lcdc_d10 */ 2154 <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, 2155 /* vo_lcdc_d11 */ 2156 <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, 2157 /* vo_lcdc_d12 */ 2158 <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, 2159 /* vo_lcdc_d13 */ 2160 <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, 2161 /* vo_lcdc_d14 */ 2162 <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, 2163 /* vo_lcdc_d15 */ 2164 <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, 2165 /* vo_lcdc_d19 */ 2166 <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, 2167 /* vo_lcdc_d20 */ 2168 <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, 2169 /* vo_lcdc_d21 */ 2170 <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, 2171 /* vo_lcdc_d22 */ 2172 <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, 2173 /* vo_lcdc_d23 */ 2174 <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>; 2175 }; 2176 2177 /omit-if-no-ref/ 2178 bt656_pins: bt656-pins { 2179 rockchip,pins = 2180 /* vo_lcdc_clk */ 2181 <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, 2182 /* vo_lcdc_d3 */ 2183 <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, 2184 /* vo_lcdc_d4 */ 2185 <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, 2186 /* vo_lcdc_d5 */ 2187 <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, 2188 /* vo_lcdc_d6 */ 2189 <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, 2190 /* vo_lcdc_d7 */ 2191 <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, 2192 /* vo_lcdc_d10 */ 2193 <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, 2194 /* vo_lcdc_d11 */ 2195 <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, 2196 /* vo_lcdc_d12 */ 2197 <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>; 2198 }; 2199 2200 /omit-if-no-ref/ 2201 rgb3x8_pins_m0: rgb3x8-pins-m0 { 2202 rockchip,pins = 2203 /* vo_lcdc_clk */ 2204 <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, 2205 /* vo_lcdc_d3 */ 2206 <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, 2207 /* vo_lcdc_d4 */ 2208 <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, 2209 /* vo_lcdc_d5 */ 2210 <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, 2211 /* vo_lcdc_d6 */ 2212 <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, 2213 /* vo_lcdc_d7 */ 2214 <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, 2215 /* vo_lcdc_d10 */ 2216 <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, 2217 /* vo_lcdc_d11 */ 2218 <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, 2219 /* vo_lcdc_d12 */ 2220 <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, 2221 /* vo_lcdc_den */ 2222 <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, 2223 /* vo_lcdc_hsync */ 2224 <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, 2225 /* vo_lcdc_vsync */ 2226 <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; 2227 }; 2228 2229 /omit-if-no-ref/ 2230 rgb3x8_pins_m1: rgb3x8-pins-m1 { 2231 rockchip,pins = 2232 /* vo_lcdc_clk */ 2233 <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, 2234 /* vo_lcdc_d13 */ 2235 <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, 2236 /* vo_lcdc_d14 */ 2237 <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, 2238 /* vo_lcdc_d15 */ 2239 <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, 2240 /* vo_lcdc_d19 */ 2241 <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, 2242 /* vo_lcdc_d20 */ 2243 <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, 2244 /* vo_lcdc_d21 */ 2245 <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, 2246 /* vo_lcdc_d22 */ 2247 <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, 2248 /* vo_lcdc_d23 */ 2249 <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, 2250 /* vo_lcdc_den */ 2251 <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, 2252 /* vo_lcdc_hsync */ 2253 <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, 2254 /* vo_lcdc_vsync */ 2255 <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; 2256 }; 2257 2258 /omit-if-no-ref/ 2259 rgb565_pins: rgb565-pins { 2260 rockchip,pins = 2261 /* vo_lcdc_clk */ 2262 <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, 2263 /* vo_lcdc_d3 */ 2264 <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, 2265 /* vo_lcdc_d4 */ 2266 <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, 2267 /* vo_lcdc_d5 */ 2268 <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, 2269 /* vo_lcdc_d6 */ 2270 <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, 2271 /* vo_lcdc_d7 */ 2272 <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, 2273 /* vo_lcdc_d10 */ 2274 <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, 2275 /* vo_lcdc_d11 */ 2276 <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, 2277 /* vo_lcdc_d12 */ 2278 <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, 2279 /* vo_lcdc_d13 */ 2280 <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, 2281 /* vo_lcdc_d14 */ 2282 <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, 2283 /* vo_lcdc_d15 */ 2284 <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, 2285 /* vo_lcdc_d19 */ 2286 <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, 2287 /* vo_lcdc_d20 */ 2288 <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, 2289 /* vo_lcdc_d21 */ 2290 <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, 2291 /* vo_lcdc_d22 */ 2292 <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, 2293 /* vo_lcdc_d23 */ 2294 <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, 2295 /* vo_lcdc_den */ 2296 <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, 2297 /* vo_lcdc_hsync */ 2298 <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, 2299 /* vo_lcdc_vsync */ 2300 <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; 2301 }; 2302 2303 /omit-if-no-ref/ 2304 rgb666_pins: rgb666-pins { 2305 rockchip,pins = 2306 /* vo_lcdc_clk */ 2307 <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, 2308 /* vo_lcdc_d2 */ 2309 <4 RK_PB2 1 &pcfg_pull_none_drv_level_3>, 2310 /* vo_lcdc_d3 */ 2311 <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, 2312 /* vo_lcdc_d4 */ 2313 <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, 2314 /* vo_lcdc_d5 */ 2315 <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, 2316 /* vo_lcdc_d6 */ 2317 <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, 2318 /* vo_lcdc_d7 */ 2319 <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, 2320 /* vo_lcdc_d10 */ 2321 <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, 2322 /* vo_lcdc_d11 */ 2323 <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, 2324 /* vo_lcdc_d12 */ 2325 <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, 2326 /* vo_lcdc_d13 */ 2327 <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, 2328 /* vo_lcdc_d14 */ 2329 <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, 2330 /* vo_lcdc_d15 */ 2331 <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, 2332 /* vo_lcdc_d18 */ 2333 <4 RK_PB3 1 &pcfg_pull_none_drv_level_3>, 2334 /* vo_lcdc_d19 */ 2335 <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, 2336 /* vo_lcdc_d20 */ 2337 <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, 2338 /* vo_lcdc_d21 */ 2339 <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, 2340 /* vo_lcdc_d22 */ 2341 <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, 2342 /* vo_lcdc_d23 */ 2343 <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, 2344 /* vo_lcdc_den */ 2345 <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, 2346 /* vo_lcdc_hsync */ 2347 <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, 2348 /* vo_lcdc_vsync */ 2349 <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; 2350 }; 2351 }; 2352}; 2353