xref: /linux/arch/s390/include/asm/processor.h (revision 3fd6c59042dbba50391e30862beac979491145fe)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  *  S390 version
4  *    Copyright IBM Corp. 1999
5  *    Author(s): Hartmut Penner (hp@de.ibm.com),
6  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
7  *
8  *  Derived from "include/asm-i386/processor.h"
9  *    Copyright (C) 1994, Linus Torvalds
10  */
11 
12 #ifndef __ASM_S390_PROCESSOR_H
13 #define __ASM_S390_PROCESSOR_H
14 
15 #include <linux/bits.h>
16 
17 #define CIF_NOHZ_DELAY		2	/* delay HZ disable for a tick */
18 #define CIF_ENABLED_WAIT	5	/* in enabled wait state */
19 #define CIF_MCCK_GUEST		6	/* machine check happening in guest */
20 #define CIF_DEDICATED_CPU	7	/* this CPU is dedicated */
21 
22 #define _CIF_NOHZ_DELAY		BIT(CIF_NOHZ_DELAY)
23 #define _CIF_ENABLED_WAIT	BIT(CIF_ENABLED_WAIT)
24 #define _CIF_MCCK_GUEST		BIT(CIF_MCCK_GUEST)
25 #define _CIF_DEDICATED_CPU	BIT(CIF_DEDICATED_CPU)
26 
27 #define RESTART_FLAG_CTLREGS	_AC(1 << 0, U)
28 
29 #ifndef __ASSEMBLY__
30 
31 #include <linux/cpumask.h>
32 #include <linux/linkage.h>
33 #include <linux/irqflags.h>
34 #include <asm/fpu-types.h>
35 #include <asm/cpu.h>
36 #include <asm/page.h>
37 #include <asm/ptrace.h>
38 #include <asm/setup.h>
39 #include <asm/runtime_instr.h>
40 #include <asm/irqflags.h>
41 #include <asm/alternative.h>
42 #include <asm/fault.h>
43 
44 struct pcpu {
45 	unsigned long ec_mask;		/* bit mask for ec_xxx functions */
46 	unsigned long ec_clk;		/* sigp timestamp for ec_xxx */
47 	unsigned long flags;		/* per CPU flags */
48 	unsigned long capacity;		/* cpu capacity for scheduler */
49 	signed char state;		/* physical cpu state */
50 	signed char polarization;	/* physical polarization */
51 	u16 address;			/* physical cpu address */
52 };
53 
54 DECLARE_PER_CPU(struct pcpu, pcpu_devices);
55 
56 typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
57 
this_pcpu(void)58 static __always_inline struct pcpu *this_pcpu(void)
59 {
60 	return (struct pcpu *)(get_lowcore()->pcpu);
61 }
62 
set_cpu_flag(int flag)63 static __always_inline void set_cpu_flag(int flag)
64 {
65 	this_pcpu()->flags |= (1UL << flag);
66 }
67 
clear_cpu_flag(int flag)68 static __always_inline void clear_cpu_flag(int flag)
69 {
70 	this_pcpu()->flags &= ~(1UL << flag);
71 }
72 
test_cpu_flag(int flag)73 static __always_inline bool test_cpu_flag(int flag)
74 {
75 	return this_pcpu()->flags & (1UL << flag);
76 }
77 
test_and_set_cpu_flag(int flag)78 static __always_inline bool test_and_set_cpu_flag(int flag)
79 {
80 	if (test_cpu_flag(flag))
81 		return true;
82 	set_cpu_flag(flag);
83 	return false;
84 }
85 
test_and_clear_cpu_flag(int flag)86 static __always_inline bool test_and_clear_cpu_flag(int flag)
87 {
88 	if (!test_cpu_flag(flag))
89 		return false;
90 	clear_cpu_flag(flag);
91 	return true;
92 }
93 
94 /*
95  * Test CIF flag of another CPU. The caller needs to ensure that
96  * CPU hotplug can not happen, e.g. by disabling preemption.
97  */
test_cpu_flag_of(int flag,int cpu)98 static __always_inline bool test_cpu_flag_of(int flag, int cpu)
99 {
100 	return per_cpu(pcpu_devices, cpu).flags & (1UL << flag);
101 }
102 
103 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
104 
get_cpu_id(struct cpuid * ptr)105 static inline void get_cpu_id(struct cpuid *ptr)
106 {
107 	asm volatile("stidp %0" : "=Q" (*ptr));
108 }
109 
get_cpu_timer(void)110 static __always_inline unsigned long get_cpu_timer(void)
111 {
112 	unsigned long timer;
113 
114 	asm volatile("stpt	%[timer]" : [timer] "=Q" (timer));
115 	return timer;
116 }
117 
118 void s390_adjust_jiffies(void);
119 void s390_update_cpu_mhz(void);
120 void cpu_detect_mhz_feature(void);
121 
122 extern const struct seq_operations cpuinfo_op;
123 extern void execve_tail(void);
124 unsigned long vdso_text_size(void);
125 unsigned long vdso_size(void);
126 
127 /*
128  * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
129  */
130 
131 #define TASK_SIZE		(test_thread_flag(TIF_31BIT) ? \
132 					_REGION3_SIZE : TASK_SIZE_MAX)
133 #define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_31BIT) ? \
134 					(_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1))
135 #define TASK_SIZE_MAX		(-PAGE_SIZE)
136 
137 #define VDSO_BASE		(STACK_TOP + PAGE_SIZE)
138 #define VDSO_LIMIT		(test_thread_flag(TIF_31BIT) ? _REGION3_SIZE : _REGION2_SIZE)
139 #define STACK_TOP		(VDSO_LIMIT - vdso_size() - PAGE_SIZE)
140 #define STACK_TOP_MAX		(_REGION2_SIZE - vdso_size() - PAGE_SIZE)
141 
142 #define HAVE_ARCH_PICK_MMAP_LAYOUT
143 
144 #define __stackleak_poison __stackleak_poison
__stackleak_poison(unsigned long erase_low,unsigned long erase_high,unsigned long poison)145 static __always_inline void __stackleak_poison(unsigned long erase_low,
146 					       unsigned long erase_high,
147 					       unsigned long poison)
148 {
149 	unsigned long tmp, count;
150 
151 	count = erase_high - erase_low;
152 	if (!count)
153 		return;
154 	asm volatile(
155 		"	cghi	%[count],8\n"
156 		"	je	2f\n"
157 		"	aghi	%[count],-(8+1)\n"
158 		"	srlg	%[tmp],%[count],8\n"
159 		"	ltgr	%[tmp],%[tmp]\n"
160 		"	jz	1f\n"
161 		"0:	stg	%[poison],0(%[addr])\n"
162 		"	mvc	8(256-8,%[addr]),0(%[addr])\n"
163 		"	la	%[addr],256(%[addr])\n"
164 		"	brctg	%[tmp],0b\n"
165 		"1:	stg	%[poison],0(%[addr])\n"
166 		"	larl	%[tmp],3f\n"
167 		"	ex	%[count],0(%[tmp])\n"
168 		"	j	4f\n"
169 		"2:	stg	%[poison],0(%[addr])\n"
170 		"	j	4f\n"
171 		"3:	mvc	8(1,%[addr]),0(%[addr])\n"
172 		"4:\n"
173 		: [addr] "+&a" (erase_low), [count] "+&d" (count), [tmp] "=&a" (tmp)
174 		: [poison] "d" (poison)
175 		: "memory", "cc"
176 		);
177 }
178 
179 /*
180  * Thread structure
181  */
182 struct thread_struct {
183 	unsigned int  acrs[NUM_ACRS];
184 	unsigned long ksp;			/* kernel stack pointer */
185 	unsigned long user_timer;		/* task cputime in user space */
186 	unsigned long guest_timer;		/* task cputime in kvm guest */
187 	unsigned long system_timer;		/* task cputime in kernel space */
188 	unsigned long hardirq_timer;		/* task cputime in hardirq context */
189 	unsigned long softirq_timer;		/* task cputime in softirq context */
190 	const sys_call_ptr_t *sys_call_table;	/* system call table address */
191 	union teid gmap_teid;			/* address and flags of last gmap fault */
192 	unsigned int gmap_int_code;		/* int code of last gmap fault */
193 	int ufpu_flags;				/* user fpu flags */
194 	int kfpu_flags;				/* kernel fpu flags */
195 
196 	/* Per-thread information related to debugging */
197 	struct per_regs per_user;		/* User specified PER registers */
198 	struct per_event per_event;		/* Cause of the last PER trap */
199 	unsigned long per_flags;		/* Flags to control debug behavior */
200 	unsigned int system_call;		/* system call number in signal */
201 	unsigned long last_break;		/* last breaking-event-address. */
202 	/* pfault_wait is used to block the process on a pfault event */
203 	unsigned long pfault_wait;
204 	struct list_head list;
205 	/* cpu runtime instrumentation */
206 	struct runtime_instr_cb *ri_cb;
207 	struct gs_cb *gs_cb;			/* Current guarded storage cb */
208 	struct gs_cb *gs_bc_cb;			/* Broadcast guarded storage cb */
209 	struct pgm_tdb trap_tdb;		/* Transaction abort diagnose block */
210 	struct fpu ufpu;			/* User FP and VX register save area */
211 	struct fpu kfpu;			/* Kernel FP and VX register save area */
212 };
213 
214 /* Flag to disable transactions. */
215 #define PER_FLAG_NO_TE			1UL
216 /* Flag to enable random transaction aborts. */
217 #define PER_FLAG_TE_ABORT_RAND		2UL
218 /* Flag to specify random transaction abort mode:
219  * - abort each transaction at a random instruction before TEND if set.
220  * - abort random transactions at a random instruction if cleared.
221  */
222 #define PER_FLAG_TE_ABORT_RAND_TEND	4UL
223 
224 typedef struct thread_struct thread_struct;
225 
226 #define ARCH_MIN_TASKALIGN	8
227 
228 #define INIT_THREAD {							\
229 	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
230 	.last_break = 1,						\
231 }
232 
233 /*
234  * Do necessary setup to start up a new thread.
235  */
236 #define start_thread(regs, new_psw, new_stackp) do {			\
237 	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;	\
238 	regs->psw.addr	= new_psw;					\
239 	regs->gprs[15]	= new_stackp;					\
240 	execve_tail();							\
241 } while (0)
242 
243 #define start_thread31(regs, new_psw, new_stackp) do {			\
244 	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_BA;			\
245 	regs->psw.addr	= new_psw;					\
246 	regs->gprs[15]	= new_stackp;					\
247 	execve_tail();							\
248 } while (0)
249 
250 struct task_struct;
251 struct mm_struct;
252 struct seq_file;
253 struct pt_regs;
254 
255 void show_registers(struct pt_regs *regs);
256 void show_cacheinfo(struct seq_file *m);
257 
258 /* Free guarded storage control block */
259 void guarded_storage_release(struct task_struct *tsk);
260 void gs_load_bc_cb(struct pt_regs *regs);
261 
262 unsigned long __get_wchan(struct task_struct *p);
263 #define task_pt_regs(tsk) ((struct pt_regs *) \
264         (task_stack_page(tsk) + THREAD_SIZE) - 1)
265 #define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
266 #define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])
267 
268 /* Has task runtime instrumentation enabled ? */
269 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
270 
271 /* avoid using global register due to gcc bug in versions < 8.4 */
272 #define current_stack_pointer (__current_stack_pointer())
273 
__current_stack_pointer(void)274 static __always_inline unsigned long __current_stack_pointer(void)
275 {
276 	unsigned long sp;
277 
278 	asm volatile("lgr %0,15" : "=d" (sp));
279 	return sp;
280 }
281 
on_thread_stack(void)282 static __always_inline bool on_thread_stack(void)
283 {
284 	unsigned long ksp = get_lowcore()->kernel_stack;
285 
286 	return !((ksp ^ current_stack_pointer) & ~(THREAD_SIZE - 1));
287 }
288 
stap(void)289 static __always_inline unsigned short stap(void)
290 {
291 	unsigned short cpu_address;
292 
293 	asm volatile("stap %0" : "=Q" (cpu_address));
294 	return cpu_address;
295 }
296 
297 #define cpu_relax() barrier()
298 
299 #define ECAG_CACHE_ATTRIBUTE	0
300 #define ECAG_CPU_ATTRIBUTE	1
301 
__ecag(unsigned int asi,unsigned char parm)302 static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
303 {
304 	unsigned long val;
305 
306 	asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm));
307 	return val;
308 }
309 
psw_set_key(unsigned int key)310 static inline void psw_set_key(unsigned int key)
311 {
312 	asm volatile("spka 0(%0)" : : "d" (key));
313 }
314 
315 /*
316  * Set PSW to specified value.
317  */
__load_psw(psw_t psw)318 static inline void __load_psw(psw_t psw)
319 {
320 	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
321 }
322 
323 /*
324  * Set PSW mask to specified value, while leaving the
325  * PSW addr pointing to the next instruction.
326  */
__load_psw_mask(unsigned long mask)327 static __always_inline void __load_psw_mask(unsigned long mask)
328 {
329 	psw_t psw __uninitialized;
330 	unsigned long addr;
331 
332 	psw.mask = mask;
333 
334 	asm volatile(
335 		"	larl	%0,1f\n"
336 		"	stg	%0,%1\n"
337 		"	lpswe	%2\n"
338 		"1:"
339 		: "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
340 }
341 
342 /*
343  * Extract current PSW mask
344  */
__extract_psw(void)345 static inline unsigned long __extract_psw(void)
346 {
347 	unsigned int reg1, reg2;
348 
349 	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
350 	return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
351 }
352 
__local_mcck_save(void)353 static inline unsigned long __local_mcck_save(void)
354 {
355 	unsigned long mask = __extract_psw();
356 
357 	__load_psw_mask(mask & ~PSW_MASK_MCHECK);
358 	return mask & PSW_MASK_MCHECK;
359 }
360 
361 #define local_mcck_save(mflags)			\
362 do {						\
363 	typecheck(unsigned long, mflags);	\
364 	mflags = __local_mcck_save();		\
365 } while (0)
366 
local_mcck_restore(unsigned long mflags)367 static inline void local_mcck_restore(unsigned long mflags)
368 {
369 	unsigned long mask = __extract_psw();
370 
371 	mask &= ~PSW_MASK_MCHECK;
372 	__load_psw_mask(mask | mflags);
373 }
374 
local_mcck_disable(void)375 static inline void local_mcck_disable(void)
376 {
377 	__local_mcck_save();
378 }
379 
local_mcck_enable(void)380 static inline void local_mcck_enable(void)
381 {
382 	__load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
383 }
384 
385 /*
386  * Rewind PSW instruction address by specified number of bytes.
387  */
__rewind_psw(psw_t psw,unsigned long ilc)388 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
389 {
390 	unsigned long mask;
391 
392 	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
393 	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
394 					  (1UL << 24) - 1;
395 	return (psw.addr - ilc) & mask;
396 }
397 
398 /*
399  * Function to drop a processor into disabled wait state
400  */
disabled_wait(void)401 static __always_inline void __noreturn disabled_wait(void)
402 {
403 	psw_t psw;
404 
405 	psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
406 	psw.addr = _THIS_IP_;
407 	__load_psw(psw);
408 	while (1);
409 }
410 
411 #define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL
412 
regs_irqs_disabled(struct pt_regs * regs)413 static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
414 {
415 	return arch_irqs_disabled_flags(regs->psw.mask);
416 }
417 
bpon(void)418 static __always_inline void bpon(void)
419 {
420 	asm volatile(ALTERNATIVE("nop", ".insn	rrf,0xb2e80000,0,0,13,0", ALT_SPEC(82)));
421 }
422 
423 #endif /* __ASSEMBLY__ */
424 
425 #endif /* __ASM_S390_PROCESSOR_H */
426