1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/delay.h> 5 #include <linux/mutex.h> 6 #include <linux/spinlock_types.h> 7 #include <linux/workqueue.h> 8 9 #include <drm/drm_encoder.h> 10 #include <drm/drm_gem.h> 11 #include <drm/drm_gem_shmem_helper.h> 12 #include <drm/gpu_scheduler.h> 13 14 #include "v3d_performance_counters.h" 15 16 #include "uapi/drm/v3d_drm.h" 17 18 struct clk; 19 struct platform_device; 20 struct reset_control; 21 22 #define V3D_MMU_PAGE_SHIFT 12 23 #define V3D_PAGE_FACTOR (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT) 24 25 #define V3D_MAX_QUEUES (V3D_CPU + 1) 26 27 static inline char *v3d_queue_to_string(enum v3d_queue queue) 28 { 29 switch (queue) { 30 case V3D_BIN: return "bin"; 31 case V3D_RENDER: return "render"; 32 case V3D_TFU: return "tfu"; 33 case V3D_CSD: return "csd"; 34 case V3D_CACHE_CLEAN: return "cache_clean"; 35 case V3D_CPU: return "cpu"; 36 } 37 return "UNKNOWN"; 38 } 39 40 struct v3d_stats { 41 u64 start_ns; 42 u64 enabled_ns; 43 u64 jobs_completed; 44 45 /* 46 * This seqcount is used to protect the access to the GPU stats 47 * variables. It must be used as, while we are reading the stats, 48 * IRQs can happen and the stats can be updated. 49 */ 50 seqcount_t lock; 51 }; 52 53 struct v3d_queue_state { 54 struct drm_gpu_scheduler sched; 55 56 u64 fence_context; 57 u64 emit_seqno; 58 59 /* Stores the GPU stats for this queue in the global context. */ 60 struct v3d_stats stats; 61 62 /* Currently active job for this queue */ 63 struct v3d_job *active_job; 64 spinlock_t queue_lock; 65 /* Protect dma fence for signalling job completion */ 66 spinlock_t fence_lock; 67 }; 68 69 /* Performance monitor object. The perform lifetime is controlled by userspace 70 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 71 * request, and when this is the case, HW perf counters will be activated just 72 * before the submit_cl is submitted to the GPU and disabled when the job is 73 * done. This way, only events related to a specific job will be counted. 74 */ 75 struct v3d_perfmon { 76 /* Tracks the number of users of the perfmon, when this counter reaches 77 * zero the perfmon is destroyed. 78 */ 79 refcount_t refcnt; 80 81 /* Protects perfmon stop, as it can be invoked from multiple places. */ 82 struct mutex lock; 83 84 /* Number of counters activated in this perfmon instance 85 * (should be less than DRM_V3D_MAX_PERF_COUNTERS). 86 */ 87 u8 ncounters; 88 89 /* Events counted by the HW perf counters. */ 90 u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 91 92 /* Storage for counter values. Counters are incremented by the 93 * HW perf counter values every time the perfmon is attached 94 * to a GPU job. This way, perfmon users don't have to 95 * retrieve the results after each job if they want to track 96 * events covering several submissions. Note that counter 97 * values can't be reset, but you can fake a reset by 98 * destroying the perfmon and creating a new one. 99 */ 100 u64 values[] __counted_by(ncounters); 101 }; 102 103 enum v3d_gen { 104 V3D_GEN_33 = 33, 105 V3D_GEN_41 = 41, 106 V3D_GEN_42 = 42, 107 V3D_GEN_71 = 71, 108 }; 109 110 enum v3d_irq { 111 V3D_CORE_IRQ, 112 V3D_HUB_IRQ, 113 V3D_MAX_IRQS, 114 }; 115 116 struct v3d_dev { 117 struct drm_device drm; 118 119 /* Short representation (e.g. 33, 41) of the V3D tech version */ 120 enum v3d_gen ver; 121 122 /* Short representation (e.g. 5, 6) of the V3D tech revision */ 123 int rev; 124 125 bool single_irq_line; 126 127 int irq[V3D_MAX_IRQS]; 128 129 struct v3d_perfmon_info perfmon_info; 130 131 void __iomem *hub_regs; 132 void __iomem *core_regs[3]; 133 void __iomem *bridge_regs; 134 void __iomem *gca_regs; 135 void __iomem *sms_regs; 136 struct clk *clk; 137 struct reset_control *reset; 138 139 /* Virtual and DMA addresses of the single shared page table. */ 140 volatile u32 *pt; 141 dma_addr_t pt_paddr; 142 143 /* Virtual and DMA addresses of the MMU's scratch page. When 144 * a read or write is invalid in the MMU, it will be 145 * redirected here. 146 */ 147 void *mmu_scratch; 148 dma_addr_t mmu_scratch_paddr; 149 /* virtual address bits from V3D to the MMU. */ 150 int va_width; 151 152 /* Number of V3D cores. */ 153 u32 cores; 154 155 /* Allocator managing the address space. All units are in 156 * number of pages. 157 */ 158 struct drm_mm mm; 159 spinlock_t mm_lock; 160 161 struct work_struct overflow_mem_work; 162 163 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 164 165 /* Used to track the active perfmon if any. */ 166 struct v3d_perfmon *active_perfmon; 167 168 /* Protects bo_stats */ 169 struct mutex bo_lock; 170 171 /* Lock taken when resetting the GPU, to keep multiple 172 * processes from trying to park the scheduler threads and 173 * reset at once. 174 */ 175 struct mutex reset_lock; 176 177 /* Lock taken when creating and pushing the GPU scheduler 178 * jobs, to keep the sched-fence seqnos in order. 179 */ 180 struct mutex sched_lock; 181 182 /* Lock taken during a cache clean and when initiating an L2 183 * flush, to keep L2 flushes from interfering with the 184 * synchronous L2 cleans. 185 */ 186 struct mutex cache_clean_lock; 187 188 struct { 189 u32 num_allocated; 190 u32 pages_allocated; 191 } bo_stats; 192 193 /* To support a performance analysis tool in user space, we require 194 * a single, globally configured performance monitor (perfmon) for 195 * all jobs. 196 */ 197 struct v3d_perfmon *global_perfmon; 198 199 /* Global reset counter. The counter must be incremented when 200 * a GPU reset happens. It must be protected by @reset_lock. 201 */ 202 unsigned int reset_counter; 203 }; 204 205 static inline struct v3d_dev * 206 to_v3d_dev(struct drm_device *dev) 207 { 208 return container_of(dev, struct v3d_dev, drm); 209 } 210 211 static inline bool 212 v3d_has_csd(struct v3d_dev *v3d) 213 { 214 return v3d->ver >= V3D_GEN_41; 215 } 216 217 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev) 218 219 /* The per-fd struct, which tracks the MMU mappings. */ 220 struct v3d_file_priv { 221 struct v3d_dev *v3d; 222 223 struct { 224 struct idr idr; 225 struct mutex lock; 226 } perfmon; 227 228 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 229 230 /* Stores the GPU stats for a specific queue for this fd. */ 231 struct v3d_stats stats[V3D_MAX_QUEUES]; 232 233 /* Per-fd reset counter, must be incremented when a job submitted 234 * by this fd causes a GPU reset. It must be protected by 235 * &struct v3d_dev->reset_lock. 236 */ 237 unsigned int reset_counter; 238 }; 239 240 struct v3d_bo { 241 struct drm_gem_shmem_object base; 242 243 struct drm_mm_node node; 244 245 /* List entry for the BO's position in 246 * v3d_render_job->unref_list 247 */ 248 struct list_head unref_head; 249 250 void *vaddr; 251 }; 252 253 static inline struct v3d_bo * 254 to_v3d_bo(struct drm_gem_object *bo) 255 { 256 return (struct v3d_bo *)bo; 257 } 258 259 struct v3d_fence { 260 struct dma_fence base; 261 struct drm_device *dev; 262 /* v3d seqno for signaled() test */ 263 u64 seqno; 264 enum v3d_queue queue; 265 }; 266 267 static inline struct v3d_fence * 268 to_v3d_fence(struct dma_fence *fence) 269 { 270 return (struct v3d_fence *)fence; 271 } 272 273 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 274 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 275 276 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 277 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 278 279 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 280 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 281 282 #define V3D_SMS_IDLE 0x0 283 #define V3D_SMS_ISOLATING_FOR_RESET 0xa 284 #define V3D_SMS_RESETTING 0xb 285 #define V3D_SMS_ISOLATING_FOR_POWER_OFF 0xc 286 #define V3D_SMS_POWER_OFF_STATE 0xd 287 288 #define V3D_SMS_READ(offset) readl(v3d->sms_regs + (offset)) 289 #define V3D_SMS_WRITE(offset, val) writel(val, v3d->sms_regs + (offset)) 290 291 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 292 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 293 294 struct v3d_job { 295 struct drm_sched_job base; 296 297 struct kref refcount; 298 299 struct v3d_dev *v3d; 300 301 /* This is the array of BOs that were looked up at the start 302 * of submission. 303 */ 304 struct drm_gem_object **bo; 305 u32 bo_count; 306 307 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 308 struct dma_fence *irq_fence; 309 310 /* scheduler fence for when the job is considered complete and 311 * the BO reservations can be released. 312 */ 313 struct dma_fence *done_fence; 314 315 /* Pointer to a performance monitor object if the user requested it, 316 * NULL otherwise. 317 */ 318 struct v3d_perfmon *perfmon; 319 320 /* File descriptor of the process that submitted the job that could be used 321 * to collect per-process information about the GPU. 322 */ 323 struct v3d_file_priv *file_priv; 324 325 /* Callback for the freeing of the job on refcount going to 0. */ 326 void (*free)(struct kref *ref); 327 }; 328 329 struct v3d_bin_job { 330 struct v3d_job base; 331 332 /* GPU virtual addresses of the start/end of the CL job. */ 333 u32 start, end; 334 335 u32 timedout_ctca, timedout_ctra; 336 337 /* Corresponding render job, for attaching our overflow memory. */ 338 struct v3d_render_job *render; 339 340 /* Submitted tile memory allocation start/size, tile state. */ 341 u32 qma, qms, qts; 342 }; 343 344 struct v3d_render_job { 345 struct v3d_job base; 346 347 /* GPU virtual addresses of the start/end of the CL job. */ 348 u32 start, end; 349 350 u32 timedout_ctca, timedout_ctra; 351 352 /* List of overflow BOs used in the job that need to be 353 * released once the job is complete. 354 */ 355 struct list_head unref_list; 356 }; 357 358 struct v3d_tfu_job { 359 struct v3d_job base; 360 361 struct drm_v3d_submit_tfu args; 362 }; 363 364 struct v3d_csd_job { 365 struct v3d_job base; 366 367 u32 timedout_batches; 368 369 struct drm_v3d_submit_csd args; 370 }; 371 372 enum v3d_cpu_job_type { 373 V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1, 374 V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY, 375 V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY, 376 V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY, 377 V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY, 378 V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY, 379 }; 380 381 struct v3d_timestamp_query { 382 /* Offset of this query in the timestamp BO for its value. */ 383 u32 offset; 384 385 /* Syncobj that indicates the timestamp availability */ 386 struct drm_syncobj *syncobj; 387 }; 388 389 struct v3d_performance_query { 390 /* Performance monitor IDs for this query */ 391 u32 *kperfmon_ids; 392 393 /* Syncobj that indicates the query availability */ 394 struct drm_syncobj *syncobj; 395 }; 396 397 struct v3d_indirect_csd_info { 398 /* Indirect CSD */ 399 struct v3d_csd_job *job; 400 401 /* Clean cache job associated to the Indirect CSD job */ 402 struct v3d_job *clean_job; 403 404 /* Offset within the BO where the workgroup counts are stored */ 405 u32 offset; 406 407 /* Workgroups size */ 408 u32 wg_size; 409 410 /* Indices of the uniforms with the workgroup dispatch counts 411 * in the uniform stream. 412 */ 413 u32 wg_uniform_offsets[3]; 414 415 /* Indirect BO */ 416 struct drm_gem_object *indirect; 417 418 /* Context of the Indirect CSD job */ 419 struct ww_acquire_ctx acquire_ctx; 420 }; 421 422 struct v3d_timestamp_query_info { 423 struct v3d_timestamp_query *queries; 424 425 u32 count; 426 }; 427 428 struct v3d_performance_query_info { 429 struct v3d_performance_query *queries; 430 431 /* Number of performance queries */ 432 u32 count; 433 434 /* Number of performance monitors related to that query pool */ 435 u32 nperfmons; 436 437 /* Number of performance counters related to that query pool */ 438 u32 ncounters; 439 }; 440 441 struct v3d_copy_query_results_info { 442 /* Define if should write to buffer using 64 or 32 bits */ 443 bool do_64bit; 444 445 /* Define if it can write to buffer even if the query is not available */ 446 bool do_partial; 447 448 /* Define if it should write availability bit to buffer */ 449 bool availability_bit; 450 451 /* Offset of the copy buffer in the BO */ 452 u32 offset; 453 454 /* Stride of the copy buffer in the BO */ 455 u32 stride; 456 }; 457 458 struct v3d_cpu_job { 459 struct v3d_job base; 460 461 enum v3d_cpu_job_type job_type; 462 463 struct v3d_indirect_csd_info indirect_csd; 464 465 struct v3d_timestamp_query_info timestamp_query; 466 467 struct v3d_copy_query_results_info copy; 468 469 struct v3d_performance_query_info performance_query; 470 }; 471 472 typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *); 473 474 struct v3d_submit_outsync { 475 struct drm_syncobj *syncobj; 476 }; 477 478 struct v3d_submit_ext { 479 u32 flags; 480 u32 wait_stage; 481 482 u32 in_sync_count; 483 u64 in_syncs; 484 485 u32 out_sync_count; 486 struct v3d_submit_outsync *out_syncs; 487 }; 488 489 /** 490 * __wait_for - magic wait macro 491 * 492 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 493 * important that we check the condition again after having timed out, since the 494 * timeout could be due to preemption or similar and we've never had a chance to 495 * check the condition before the timeout. 496 */ 497 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 498 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 499 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 500 int ret__; \ 501 might_sleep(); \ 502 for (;;) { \ 503 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 504 OP; \ 505 /* Guarantee COND check prior to timeout */ \ 506 barrier(); \ 507 if (COND) { \ 508 ret__ = 0; \ 509 break; \ 510 } \ 511 if (expired__) { \ 512 ret__ = -ETIMEDOUT; \ 513 break; \ 514 } \ 515 usleep_range(wait__, wait__ * 2); \ 516 if (wait__ < (Wmax)) \ 517 wait__ <<= 1; \ 518 } \ 519 ret__; \ 520 }) 521 522 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 523 (Wmax)) 524 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 525 526 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 527 { 528 /* nsecs_to_jiffies64() does not guard against overflow */ 529 if ((NSEC_PER_SEC % HZ) != 0 && 530 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 531 return MAX_JIFFY_OFFSET; 532 533 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 534 } 535 536 /* v3d_bo.c */ 537 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size); 538 void v3d_free_object(struct drm_gem_object *gem_obj); 539 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 540 size_t size); 541 void v3d_get_bo_vaddr(struct v3d_bo *bo); 542 void v3d_put_bo_vaddr(struct v3d_bo *bo); 543 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 544 struct drm_file *file_priv); 545 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 546 struct drm_file *file_priv); 547 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 548 struct drm_file *file_priv); 549 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 550 struct drm_file *file_priv); 551 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 552 struct dma_buf_attachment *attach, 553 struct sg_table *sgt); 554 555 /* v3d_debugfs.c */ 556 void v3d_debugfs_init(struct drm_minor *minor); 557 558 /* v3d_drv.c */ 559 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 560 u64 *active_runtime, u64 *jobs_completed); 561 562 /* v3d_fence.c */ 563 extern const struct dma_fence_ops v3d_fence_ops; 564 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue q); 565 566 /* v3d_gem.c */ 567 extern bool super_pages; 568 int v3d_gem_init(struct drm_device *dev); 569 void v3d_gem_destroy(struct drm_device *dev); 570 void v3d_reset_sms(struct v3d_dev *v3d); 571 void v3d_reset(struct v3d_dev *v3d); 572 void v3d_invalidate_caches(struct v3d_dev *v3d); 573 void v3d_clean_caches(struct v3d_dev *v3d); 574 575 /* v3d_submit.c */ 576 void v3d_job_cleanup(struct v3d_job *job); 577 void v3d_job_put(struct v3d_job *job); 578 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 579 struct drm_file *file_priv); 580 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data, 581 struct drm_file *file_priv); 582 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data, 583 struct drm_file *file_priv); 584 int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data, 585 struct drm_file *file_priv); 586 587 /* v3d_irq.c */ 588 int v3d_irq_init(struct v3d_dev *v3d); 589 void v3d_irq_enable(struct v3d_dev *v3d); 590 void v3d_irq_disable(struct v3d_dev *v3d); 591 void v3d_irq_reset(struct v3d_dev *v3d); 592 593 /* v3d_mmu.c */ 594 int v3d_mmu_flush_all(struct v3d_dev *v3d); 595 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 596 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 597 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 598 599 /* v3d_sched.c */ 600 void v3d_timestamp_query_info_free(struct v3d_timestamp_query_info *query_info, 601 unsigned int count); 602 void v3d_performance_query_info_free(struct v3d_performance_query_info *query_info, 603 unsigned int count); 604 void v3d_job_update_stats(struct v3d_job *job, enum v3d_queue q); 605 int v3d_sched_init(struct v3d_dev *v3d); 606 void v3d_sched_fini(struct v3d_dev *v3d); 607 608 /* v3d_perfmon.c */ 609 void v3d_perfmon_init(struct v3d_dev *v3d); 610 void v3d_perfmon_get(struct v3d_perfmon *perfmon); 611 void v3d_perfmon_put(struct v3d_perfmon *perfmon); 612 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon); 613 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 614 bool capture); 615 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id); 616 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv); 617 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv); 618 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data, 619 struct drm_file *file_priv); 620 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 621 struct drm_file *file_priv); 622 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 623 struct drm_file *file_priv); 624 int v3d_perfmon_get_counter_ioctl(struct drm_device *dev, void *data, 625 struct drm_file *file_priv); 626 int v3d_perfmon_set_global_ioctl(struct drm_device *dev, void *data, 627 struct drm_file *file_priv); 628 629 /* v3d_sysfs.c */ 630 int v3d_sysfs_init(struct device *dev); 631 void v3d_sysfs_destroy(struct device *dev); 632