1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7 #include <linux/cleanup.h> 8 #include <linux/module.h> 9 #include <linux/err.h> 10 #include <linux/debugfs.h> 11 #include <linux/string.h> 12 #include <linux/kernel.h> 13 #include <linux/list.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 #include <linux/bitops.h> 17 #include <linux/slab.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_domain.h> 21 #include <linux/pm_opp.h> 22 #include <linux/interrupt.h> 23 #include <linux/regmap.h> 24 #include <linux/mfd/syscon.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/clk.h> 27 #include <linux/nvmem-consumer.h> 28 29 /* Register Offsets for RB-CPR and Bit Definitions */ 30 31 /* RBCPR Version Register */ 32 #define REG_RBCPR_VERSION 0 33 #define RBCPR_VER_2 0x02 34 #define FLAGS_IGNORE_1ST_IRQ_STATUS BIT(0) 35 36 /* RBCPR Gate Count and Target Registers */ 37 #define REG_RBCPR_GCNT_TARGET(n) (0x60 + 4 * (n)) 38 39 #define RBCPR_GCNT_TARGET_TARGET_SHIFT 0 40 #define RBCPR_GCNT_TARGET_TARGET_MASK GENMASK(11, 0) 41 #define RBCPR_GCNT_TARGET_GCNT_SHIFT 12 42 #define RBCPR_GCNT_TARGET_GCNT_MASK GENMASK(9, 0) 43 44 /* RBCPR Timer Control */ 45 #define REG_RBCPR_TIMER_INTERVAL 0x44 46 #define REG_RBIF_TIMER_ADJUST 0x4c 47 48 #define RBIF_TIMER_ADJ_CONS_UP_MASK GENMASK(3, 0) 49 #define RBIF_TIMER_ADJ_CONS_UP_SHIFT 0 50 #define RBIF_TIMER_ADJ_CONS_DOWN_MASK GENMASK(3, 0) 51 #define RBIF_TIMER_ADJ_CONS_DOWN_SHIFT 4 52 #define RBIF_TIMER_ADJ_CLAMP_INT_MASK GENMASK(7, 0) 53 #define RBIF_TIMER_ADJ_CLAMP_INT_SHIFT 8 54 55 /* RBCPR Config Register */ 56 #define REG_RBIF_LIMIT 0x48 57 #define RBIF_LIMIT_CEILING_MASK GENMASK(5, 0) 58 #define RBIF_LIMIT_CEILING_SHIFT 6 59 #define RBIF_LIMIT_FLOOR_BITS 6 60 #define RBIF_LIMIT_FLOOR_MASK GENMASK(5, 0) 61 62 #define RBIF_LIMIT_CEILING_DEFAULT RBIF_LIMIT_CEILING_MASK 63 #define RBIF_LIMIT_FLOOR_DEFAULT 0 64 65 #define REG_RBIF_SW_VLEVEL 0x94 66 #define RBIF_SW_VLEVEL_DEFAULT 0x20 67 68 #define REG_RBCPR_STEP_QUOT 0x80 69 #define RBCPR_STEP_QUOT_STEPQUOT_MASK GENMASK(7, 0) 70 #define RBCPR_STEP_QUOT_IDLE_CLK_MASK GENMASK(3, 0) 71 #define RBCPR_STEP_QUOT_IDLE_CLK_SHIFT 8 72 73 /* RBCPR Control Register */ 74 #define REG_RBCPR_CTL 0x90 75 76 #define RBCPR_CTL_LOOP_EN BIT(0) 77 #define RBCPR_CTL_TIMER_EN BIT(3) 78 #define RBCPR_CTL_SW_AUTO_CONT_ACK_EN BIT(5) 79 #define RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN BIT(6) 80 #define RBCPR_CTL_COUNT_MODE BIT(10) 81 #define RBCPR_CTL_UP_THRESHOLD_MASK GENMASK(3, 0) 82 #define RBCPR_CTL_UP_THRESHOLD_SHIFT 24 83 #define RBCPR_CTL_DN_THRESHOLD_MASK GENMASK(3, 0) 84 #define RBCPR_CTL_DN_THRESHOLD_SHIFT 28 85 86 /* RBCPR Ack/Nack Response */ 87 #define REG_RBIF_CONT_ACK_CMD 0x98 88 #define REG_RBIF_CONT_NACK_CMD 0x9c 89 90 /* RBCPR Result status Register */ 91 #define REG_RBCPR_RESULT_0 0xa0 92 93 #define RBCPR_RESULT0_BUSY_SHIFT 19 94 #define RBCPR_RESULT0_BUSY_MASK BIT(RBCPR_RESULT0_BUSY_SHIFT) 95 #define RBCPR_RESULT0_ERROR_LT0_SHIFT 18 96 #define RBCPR_RESULT0_ERROR_SHIFT 6 97 #define RBCPR_RESULT0_ERROR_MASK GENMASK(11, 0) 98 #define RBCPR_RESULT0_ERROR_STEPS_SHIFT 2 99 #define RBCPR_RESULT0_ERROR_STEPS_MASK GENMASK(3, 0) 100 #define RBCPR_RESULT0_STEP_UP_SHIFT 1 101 102 /* RBCPR Interrupt Control Register */ 103 #define REG_RBIF_IRQ_EN(n) (0x100 + 4 * (n)) 104 #define REG_RBIF_IRQ_CLEAR 0x110 105 #define REG_RBIF_IRQ_STATUS 0x114 106 107 #define CPR_INT_DONE BIT(0) 108 #define CPR_INT_MIN BIT(1) 109 #define CPR_INT_DOWN BIT(2) 110 #define CPR_INT_MID BIT(3) 111 #define CPR_INT_UP BIT(4) 112 #define CPR_INT_MAX BIT(5) 113 #define CPR_INT_CLAMP BIT(6) 114 #define CPR_INT_ALL (CPR_INT_DONE | CPR_INT_MIN | CPR_INT_DOWN | \ 115 CPR_INT_MID | CPR_INT_UP | CPR_INT_MAX | CPR_INT_CLAMP) 116 #define CPR_INT_DEFAULT (CPR_INT_UP | CPR_INT_DOWN) 117 118 #define CPR_NUM_RING_OSC 8 119 120 /* CPR eFuse parameters */ 121 #define CPR_FUSE_TARGET_QUOT_BITS_MASK GENMASK(11, 0) 122 123 #define CPR_FUSE_MIN_QUOT_DIFF 50 124 125 #define FUSE_REVISION_UNKNOWN (-1) 126 127 enum voltage_change_dir { 128 NO_CHANGE, 129 DOWN, 130 UP, 131 }; 132 133 struct cpr_fuse { 134 char *ring_osc; 135 char *init_voltage; 136 char *quotient; 137 char *quotient_offset; 138 }; 139 140 struct fuse_corner_data { 141 int ref_uV; 142 int max_uV; 143 int min_uV; 144 int max_volt_scale; 145 int max_quot_scale; 146 /* fuse quot */ 147 int quot_offset; 148 int quot_scale; 149 int quot_adjust; 150 /* fuse quot_offset */ 151 int quot_offset_scale; 152 int quot_offset_adjust; 153 }; 154 155 struct cpr_fuses { 156 int init_voltage_step; 157 int init_voltage_width; 158 struct fuse_corner_data *fuse_corner_data; 159 }; 160 161 struct corner_data { 162 unsigned int fuse_corner; 163 unsigned long freq; 164 }; 165 166 struct cpr_desc { 167 unsigned int num_fuse_corners; 168 int min_diff_quot; 169 int *step_quot; 170 171 unsigned int timer_delay_us; 172 unsigned int timer_cons_up; 173 unsigned int timer_cons_down; 174 unsigned int up_threshold; 175 unsigned int down_threshold; 176 unsigned int idle_clocks; 177 unsigned int gcnt_us; 178 unsigned int vdd_apc_step_up_limit; 179 unsigned int vdd_apc_step_down_limit; 180 unsigned int clamp_timer_interval; 181 182 struct cpr_fuses cpr_fuses; 183 bool reduce_to_fuse_uV; 184 bool reduce_to_corner_uV; 185 }; 186 187 struct acc_desc { 188 unsigned int enable_reg; 189 u32 enable_mask; 190 191 struct reg_sequence *config; 192 struct reg_sequence *settings; 193 int num_regs_per_fuse; 194 }; 195 196 struct cpr_acc_desc { 197 const struct cpr_desc *cpr_desc; 198 const struct acc_desc *acc_desc; 199 }; 200 201 struct fuse_corner { 202 int min_uV; 203 int max_uV; 204 int uV; 205 int quot; 206 int step_quot; 207 const struct reg_sequence *accs; 208 int num_accs; 209 unsigned long max_freq; 210 u8 ring_osc_idx; 211 }; 212 213 struct corner { 214 int min_uV; 215 int max_uV; 216 int uV; 217 int last_uV; 218 int quot_adjust; 219 u32 save_ctl; 220 u32 save_irq; 221 unsigned long freq; 222 struct fuse_corner *fuse_corner; 223 }; 224 225 struct cpr_drv { 226 unsigned int num_corners; 227 unsigned int ref_clk_khz; 228 229 struct generic_pm_domain pd; 230 struct device *dev; 231 struct device *attached_cpu_dev; 232 struct mutex lock; 233 void __iomem *base; 234 struct corner *corner; 235 struct regulator *vdd_apc; 236 struct clk *cpu_clk; 237 struct regmap *tcsr; 238 bool loop_disabled; 239 u32 gcnt; 240 unsigned long flags; 241 242 struct corner *corners; 243 244 const struct cpr_desc *desc; 245 const struct acc_desc *acc_desc; 246 const struct cpr_fuse *cpr_fuses; 247 248 struct dentry *debugfs; 249 250 struct fuse_corner fuse_corners[]; 251 }; 252 253 static bool cpr_is_allowed(struct cpr_drv *drv) 254 { 255 return !drv->loop_disabled; 256 } 257 258 static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value) 259 { 260 writel_relaxed(value, drv->base + offset); 261 } 262 263 static u32 cpr_read(struct cpr_drv *drv, u32 offset) 264 { 265 return readl_relaxed(drv->base + offset); 266 } 267 268 static void 269 cpr_masked_write(struct cpr_drv *drv, u32 offset, u32 mask, u32 value) 270 { 271 u32 val; 272 273 val = readl_relaxed(drv->base + offset); 274 val &= ~mask; 275 val |= value & mask; 276 writel_relaxed(val, drv->base + offset); 277 } 278 279 static void cpr_irq_clr(struct cpr_drv *drv) 280 { 281 cpr_write(drv, REG_RBIF_IRQ_CLEAR, CPR_INT_ALL); 282 } 283 284 static void cpr_irq_clr_nack(struct cpr_drv *drv) 285 { 286 cpr_irq_clr(drv); 287 cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1); 288 } 289 290 static void cpr_irq_clr_ack(struct cpr_drv *drv) 291 { 292 cpr_irq_clr(drv); 293 cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1); 294 } 295 296 static void cpr_irq_set(struct cpr_drv *drv, u32 int_bits) 297 { 298 cpr_write(drv, REG_RBIF_IRQ_EN(0), int_bits); 299 } 300 301 static void cpr_ctl_modify(struct cpr_drv *drv, u32 mask, u32 value) 302 { 303 cpr_masked_write(drv, REG_RBCPR_CTL, mask, value); 304 } 305 306 static void cpr_ctl_enable(struct cpr_drv *drv, struct corner *corner) 307 { 308 u32 val, mask; 309 const struct cpr_desc *desc = drv->desc; 310 311 /* Program Consecutive Up & Down */ 312 val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT; 313 val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT; 314 mask = RBIF_TIMER_ADJ_CONS_UP_MASK | RBIF_TIMER_ADJ_CONS_DOWN_MASK; 315 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val); 316 cpr_masked_write(drv, REG_RBCPR_CTL, 317 RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN | 318 RBCPR_CTL_SW_AUTO_CONT_ACK_EN, 319 corner->save_ctl); 320 cpr_irq_set(drv, corner->save_irq); 321 322 if (cpr_is_allowed(drv) && corner->max_uV > corner->min_uV) 323 val = RBCPR_CTL_LOOP_EN; 324 else 325 val = 0; 326 cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, val); 327 } 328 329 static void cpr_ctl_disable(struct cpr_drv *drv) 330 { 331 cpr_irq_set(drv, 0); 332 cpr_ctl_modify(drv, RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN | 333 RBCPR_CTL_SW_AUTO_CONT_ACK_EN, 0); 334 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, 335 RBIF_TIMER_ADJ_CONS_UP_MASK | 336 RBIF_TIMER_ADJ_CONS_DOWN_MASK, 0); 337 cpr_irq_clr(drv); 338 cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1); 339 cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1); 340 cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, 0); 341 } 342 343 static bool cpr_ctl_is_enabled(struct cpr_drv *drv) 344 { 345 u32 reg_val; 346 347 reg_val = cpr_read(drv, REG_RBCPR_CTL); 348 return reg_val & RBCPR_CTL_LOOP_EN; 349 } 350 351 static bool cpr_ctl_is_busy(struct cpr_drv *drv) 352 { 353 u32 reg_val; 354 355 reg_val = cpr_read(drv, REG_RBCPR_RESULT_0); 356 return reg_val & RBCPR_RESULT0_BUSY_MASK; 357 } 358 359 static void cpr_corner_save(struct cpr_drv *drv, struct corner *corner) 360 { 361 corner->save_ctl = cpr_read(drv, REG_RBCPR_CTL); 362 corner->save_irq = cpr_read(drv, REG_RBIF_IRQ_EN(0)); 363 } 364 365 static void cpr_corner_restore(struct cpr_drv *drv, struct corner *corner) 366 { 367 u32 gcnt, ctl, irq, ro_sel, step_quot; 368 struct fuse_corner *fuse = corner->fuse_corner; 369 const struct cpr_desc *desc = drv->desc; 370 int i; 371 372 ro_sel = fuse->ring_osc_idx; 373 gcnt = drv->gcnt; 374 gcnt |= fuse->quot - corner->quot_adjust; 375 376 /* Program the step quotient and idle clocks */ 377 step_quot = desc->idle_clocks << RBCPR_STEP_QUOT_IDLE_CLK_SHIFT; 378 step_quot |= fuse->step_quot & RBCPR_STEP_QUOT_STEPQUOT_MASK; 379 cpr_write(drv, REG_RBCPR_STEP_QUOT, step_quot); 380 381 /* Clear the target quotient value and gate count of all ROs */ 382 for (i = 0; i < CPR_NUM_RING_OSC; i++) 383 cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0); 384 385 cpr_write(drv, REG_RBCPR_GCNT_TARGET(ro_sel), gcnt); 386 ctl = corner->save_ctl; 387 cpr_write(drv, REG_RBCPR_CTL, ctl); 388 irq = corner->save_irq; 389 cpr_irq_set(drv, irq); 390 dev_dbg(drv->dev, "gcnt = %#08x, ctl = %#08x, irq = %#08x\n", gcnt, 391 ctl, irq); 392 } 393 394 static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f, 395 struct fuse_corner *end) 396 { 397 if (f == end) 398 return; 399 400 if (f < end) { 401 for (f += 1; f <= end; f++) 402 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); 403 } else { 404 for (f -= 1; f >= end; f--) 405 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); 406 } 407 } 408 409 static int cpr_pre_voltage(struct cpr_drv *drv, 410 struct fuse_corner *fuse_corner, 411 enum voltage_change_dir dir) 412 { 413 struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner; 414 415 if (drv->tcsr && dir == DOWN) 416 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); 417 418 return 0; 419 } 420 421 static int cpr_post_voltage(struct cpr_drv *drv, 422 struct fuse_corner *fuse_corner, 423 enum voltage_change_dir dir) 424 { 425 struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner; 426 427 if (drv->tcsr && dir == UP) 428 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); 429 430 return 0; 431 } 432 433 static int cpr_scale_voltage(struct cpr_drv *drv, struct corner *corner, 434 int new_uV, enum voltage_change_dir dir) 435 { 436 int ret; 437 struct fuse_corner *fuse_corner = corner->fuse_corner; 438 439 ret = cpr_pre_voltage(drv, fuse_corner, dir); 440 if (ret) 441 return ret; 442 443 ret = regulator_set_voltage(drv->vdd_apc, new_uV, new_uV); 444 if (ret) { 445 dev_err_ratelimited(drv->dev, "failed to set apc voltage %d\n", 446 new_uV); 447 return ret; 448 } 449 450 ret = cpr_post_voltage(drv, fuse_corner, dir); 451 if (ret) 452 return ret; 453 454 return 0; 455 } 456 457 static unsigned int cpr_get_cur_perf_state(struct cpr_drv *drv) 458 { 459 return drv->corner ? drv->corner - drv->corners + 1 : 0; 460 } 461 462 static int cpr_scale(struct cpr_drv *drv, enum voltage_change_dir dir) 463 { 464 u32 val, error_steps, reg_mask; 465 int last_uV, new_uV, step_uV, ret; 466 struct corner *corner; 467 const struct cpr_desc *desc = drv->desc; 468 469 if (dir != UP && dir != DOWN) 470 return 0; 471 472 step_uV = regulator_get_linear_step(drv->vdd_apc); 473 if (!step_uV) 474 return -EINVAL; 475 476 corner = drv->corner; 477 478 val = cpr_read(drv, REG_RBCPR_RESULT_0); 479 480 error_steps = val >> RBCPR_RESULT0_ERROR_STEPS_SHIFT; 481 error_steps &= RBCPR_RESULT0_ERROR_STEPS_MASK; 482 last_uV = corner->last_uV; 483 484 if (dir == UP) { 485 if (desc->clamp_timer_interval && 486 error_steps < desc->up_threshold) { 487 /* 488 * Handle the case where another measurement started 489 * after the interrupt was triggered due to a core 490 * exiting from power collapse. 491 */ 492 error_steps = max(desc->up_threshold, 493 desc->vdd_apc_step_up_limit); 494 } 495 496 if (last_uV >= corner->max_uV) { 497 cpr_irq_clr_nack(drv); 498 499 /* Maximize the UP threshold */ 500 reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK; 501 reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT; 502 val = reg_mask; 503 cpr_ctl_modify(drv, reg_mask, val); 504 505 /* Disable UP interrupt */ 506 cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_UP); 507 508 return 0; 509 } 510 511 if (error_steps > desc->vdd_apc_step_up_limit) 512 error_steps = desc->vdd_apc_step_up_limit; 513 514 /* Calculate new voltage */ 515 new_uV = last_uV + error_steps * step_uV; 516 new_uV = min(new_uV, corner->max_uV); 517 518 dev_dbg(drv->dev, 519 "UP: -> new_uV: %d last_uV: %d perf state: %u\n", 520 new_uV, last_uV, cpr_get_cur_perf_state(drv)); 521 } else { 522 if (desc->clamp_timer_interval && 523 error_steps < desc->down_threshold) { 524 /* 525 * Handle the case where another measurement started 526 * after the interrupt was triggered due to a core 527 * exiting from power collapse. 528 */ 529 error_steps = max(desc->down_threshold, 530 desc->vdd_apc_step_down_limit); 531 } 532 533 if (last_uV <= corner->min_uV) { 534 cpr_irq_clr_nack(drv); 535 536 /* Enable auto nack down */ 537 reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN; 538 val = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN; 539 540 cpr_ctl_modify(drv, reg_mask, val); 541 542 /* Disable DOWN interrupt */ 543 cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_DOWN); 544 545 return 0; 546 } 547 548 if (error_steps > desc->vdd_apc_step_down_limit) 549 error_steps = desc->vdd_apc_step_down_limit; 550 551 /* Calculate new voltage */ 552 new_uV = last_uV - error_steps * step_uV; 553 new_uV = max(new_uV, corner->min_uV); 554 555 dev_dbg(drv->dev, 556 "DOWN: -> new_uV: %d last_uV: %d perf state: %u\n", 557 new_uV, last_uV, cpr_get_cur_perf_state(drv)); 558 } 559 560 ret = cpr_scale_voltage(drv, corner, new_uV, dir); 561 if (ret) { 562 cpr_irq_clr_nack(drv); 563 return ret; 564 } 565 drv->corner->last_uV = new_uV; 566 567 if (dir == UP) { 568 /* Disable auto nack down */ 569 reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN; 570 val = 0; 571 } else { 572 /* Restore default threshold for UP */ 573 reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK; 574 reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT; 575 val = desc->up_threshold; 576 val <<= RBCPR_CTL_UP_THRESHOLD_SHIFT; 577 } 578 579 cpr_ctl_modify(drv, reg_mask, val); 580 581 /* Re-enable default interrupts */ 582 cpr_irq_set(drv, CPR_INT_DEFAULT); 583 584 /* Ack */ 585 cpr_irq_clr_ack(drv); 586 587 return 0; 588 } 589 590 static irqreturn_t cpr_irq_handler(int irq, void *dev) 591 { 592 struct cpr_drv *drv = dev; 593 const struct cpr_desc *desc = drv->desc; 594 irqreturn_t ret = IRQ_HANDLED; 595 u32 val; 596 597 mutex_lock(&drv->lock); 598 599 val = cpr_read(drv, REG_RBIF_IRQ_STATUS); 600 if (drv->flags & FLAGS_IGNORE_1ST_IRQ_STATUS) 601 val = cpr_read(drv, REG_RBIF_IRQ_STATUS); 602 603 dev_dbg(drv->dev, "IRQ_STATUS = %#02x\n", val); 604 605 if (!cpr_ctl_is_enabled(drv)) { 606 dev_dbg(drv->dev, "CPR is disabled\n"); 607 ret = IRQ_NONE; 608 } else if (cpr_ctl_is_busy(drv) && !desc->clamp_timer_interval) { 609 dev_dbg(drv->dev, "CPR measurement is not ready\n"); 610 } else if (!cpr_is_allowed(drv)) { 611 val = cpr_read(drv, REG_RBCPR_CTL); 612 dev_err_ratelimited(drv->dev, 613 "Interrupt broken? RBCPR_CTL = %#02x\n", 614 val); 615 ret = IRQ_NONE; 616 } else { 617 /* 618 * Following sequence of handling is as per each IRQ's 619 * priority 620 */ 621 if (val & CPR_INT_UP) { 622 cpr_scale(drv, UP); 623 } else if (val & CPR_INT_DOWN) { 624 cpr_scale(drv, DOWN); 625 } else if (val & CPR_INT_MIN) { 626 cpr_irq_clr_nack(drv); 627 } else if (val & CPR_INT_MAX) { 628 cpr_irq_clr_nack(drv); 629 } else if (val & CPR_INT_MID) { 630 /* RBCPR_CTL_SW_AUTO_CONT_ACK_EN is enabled */ 631 dev_dbg(drv->dev, "IRQ occurred for Mid Flag\n"); 632 } else { 633 dev_dbg(drv->dev, 634 "IRQ occurred for unknown flag (%#08x)\n", val); 635 } 636 637 /* Save register values for the corner */ 638 cpr_corner_save(drv, drv->corner); 639 } 640 641 mutex_unlock(&drv->lock); 642 643 return ret; 644 } 645 646 static int cpr_enable(struct cpr_drv *drv) 647 { 648 int ret; 649 650 ret = regulator_enable(drv->vdd_apc); 651 if (ret) 652 return ret; 653 654 mutex_lock(&drv->lock); 655 656 if (cpr_is_allowed(drv) && drv->corner) { 657 cpr_irq_clr(drv); 658 cpr_corner_restore(drv, drv->corner); 659 cpr_ctl_enable(drv, drv->corner); 660 } 661 662 mutex_unlock(&drv->lock); 663 664 return 0; 665 } 666 667 static int cpr_disable(struct cpr_drv *drv) 668 { 669 mutex_lock(&drv->lock); 670 671 if (cpr_is_allowed(drv)) { 672 cpr_ctl_disable(drv); 673 cpr_irq_clr(drv); 674 } 675 676 mutex_unlock(&drv->lock); 677 678 return regulator_disable(drv->vdd_apc); 679 } 680 681 static int cpr_config(struct cpr_drv *drv) 682 { 683 int i; 684 u32 val, gcnt; 685 struct corner *corner; 686 const struct cpr_desc *desc = drv->desc; 687 688 /* Disable interrupt and CPR */ 689 cpr_write(drv, REG_RBIF_IRQ_EN(0), 0); 690 cpr_write(drv, REG_RBCPR_CTL, 0); 691 692 /* Program the default HW ceiling, floor and vlevel */ 693 val = (RBIF_LIMIT_CEILING_DEFAULT & RBIF_LIMIT_CEILING_MASK) 694 << RBIF_LIMIT_CEILING_SHIFT; 695 val |= RBIF_LIMIT_FLOOR_DEFAULT & RBIF_LIMIT_FLOOR_MASK; 696 cpr_write(drv, REG_RBIF_LIMIT, val); 697 cpr_write(drv, REG_RBIF_SW_VLEVEL, RBIF_SW_VLEVEL_DEFAULT); 698 699 /* 700 * Clear the target quotient value and gate count of all 701 * ring oscillators 702 */ 703 for (i = 0; i < CPR_NUM_RING_OSC; i++) 704 cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0); 705 706 /* Init and save gcnt */ 707 gcnt = (drv->ref_clk_khz * desc->gcnt_us) / 1000; 708 gcnt = gcnt & RBCPR_GCNT_TARGET_GCNT_MASK; 709 gcnt <<= RBCPR_GCNT_TARGET_GCNT_SHIFT; 710 drv->gcnt = gcnt; 711 712 /* Program the delay count for the timer */ 713 val = (drv->ref_clk_khz * desc->timer_delay_us) / 1000; 714 cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val); 715 dev_dbg(drv->dev, "Timer count: %#0x (for %d us)\n", val, 716 desc->timer_delay_us); 717 718 /* Program Consecutive Up & Down */ 719 val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT; 720 val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT; 721 val |= desc->clamp_timer_interval << RBIF_TIMER_ADJ_CLAMP_INT_SHIFT; 722 cpr_write(drv, REG_RBIF_TIMER_ADJUST, val); 723 724 /* Program the control register */ 725 val = desc->up_threshold << RBCPR_CTL_UP_THRESHOLD_SHIFT; 726 val |= desc->down_threshold << RBCPR_CTL_DN_THRESHOLD_SHIFT; 727 val |= RBCPR_CTL_TIMER_EN | RBCPR_CTL_COUNT_MODE; 728 val |= RBCPR_CTL_SW_AUTO_CONT_ACK_EN; 729 cpr_write(drv, REG_RBCPR_CTL, val); 730 731 for (i = 0; i < drv->num_corners; i++) { 732 corner = &drv->corners[i]; 733 corner->save_ctl = val; 734 corner->save_irq = CPR_INT_DEFAULT; 735 } 736 737 cpr_irq_set(drv, CPR_INT_DEFAULT); 738 739 val = cpr_read(drv, REG_RBCPR_VERSION); 740 if (val <= RBCPR_VER_2) 741 drv->flags |= FLAGS_IGNORE_1ST_IRQ_STATUS; 742 743 return 0; 744 } 745 746 static int cpr_set_performance_state(struct generic_pm_domain *domain, 747 unsigned int state) 748 { 749 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); 750 struct corner *corner, *end; 751 enum voltage_change_dir dir; 752 int ret, new_uV; 753 754 guard(mutex)(&drv->lock); 755 756 dev_dbg(drv->dev, "%s: setting perf state: %u (prev state: %u)\n", 757 __func__, state, cpr_get_cur_perf_state(drv)); 758 759 /* 760 * Determine new corner we're going to. 761 * Remove one since lowest performance state is 1. 762 */ 763 corner = drv->corners + state - 1; 764 end = &drv->corners[drv->num_corners - 1]; 765 if (corner > end || corner < drv->corners) 766 return -EINVAL; 767 768 /* Determine direction */ 769 if (drv->corner > corner) 770 dir = DOWN; 771 else if (drv->corner < corner) 772 dir = UP; 773 else 774 dir = NO_CHANGE; 775 776 if (cpr_is_allowed(drv)) 777 new_uV = corner->last_uV; 778 else 779 new_uV = corner->uV; 780 781 if (cpr_is_allowed(drv)) 782 cpr_ctl_disable(drv); 783 784 ret = cpr_scale_voltage(drv, corner, new_uV, dir); 785 if (ret) 786 return ret; 787 788 if (cpr_is_allowed(drv)) { 789 cpr_irq_clr(drv); 790 if (drv->corner != corner) 791 cpr_corner_restore(drv, corner); 792 cpr_ctl_enable(drv, corner); 793 } 794 795 drv->corner = corner; 796 797 return 0; 798 } 799 800 static int 801 cpr_populate_ring_osc_idx(struct cpr_drv *drv) 802 { 803 struct fuse_corner *fuse = drv->fuse_corners; 804 struct fuse_corner *end = fuse + drv->desc->num_fuse_corners; 805 const struct cpr_fuse *fuses = drv->cpr_fuses; 806 u32 data; 807 int ret; 808 809 for (; fuse < end; fuse++, fuses++) { 810 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->ring_osc, &data); 811 if (ret) 812 return ret; 813 fuse->ring_osc_idx = data; 814 } 815 816 return 0; 817 } 818 819 static int cpr_read_fuse_uV(const struct cpr_desc *desc, 820 const struct fuse_corner_data *fdata, 821 const char *init_v_efuse, 822 int step_volt, 823 struct cpr_drv *drv) 824 { 825 int step_size_uV, steps, uV; 826 u32 bits = 0; 827 int ret; 828 829 ret = nvmem_cell_read_variable_le_u32(drv->dev, init_v_efuse, &bits); 830 if (ret) 831 return ret; 832 833 steps = bits & ~BIT(desc->cpr_fuses.init_voltage_width - 1); 834 /* Not two's complement.. instead highest bit is sign bit */ 835 if (bits & BIT(desc->cpr_fuses.init_voltage_width - 1)) 836 steps = -steps; 837 838 step_size_uV = desc->cpr_fuses.init_voltage_step; 839 840 uV = fdata->ref_uV + steps * step_size_uV; 841 return DIV_ROUND_UP(uV, step_volt) * step_volt; 842 } 843 844 static int cpr_fuse_corner_init(struct cpr_drv *drv) 845 { 846 const struct cpr_desc *desc = drv->desc; 847 const struct cpr_fuse *fuses = drv->cpr_fuses; 848 const struct acc_desc *acc_desc = drv->acc_desc; 849 int i; 850 unsigned int step_volt; 851 struct fuse_corner_data *fdata; 852 struct fuse_corner *fuse, *end; 853 int uV; 854 const struct reg_sequence *accs; 855 int ret; 856 857 accs = acc_desc->settings; 858 859 step_volt = regulator_get_linear_step(drv->vdd_apc); 860 if (!step_volt) 861 return -EINVAL; 862 863 /* Populate fuse_corner members */ 864 fuse = drv->fuse_corners; 865 end = &fuse[desc->num_fuse_corners - 1]; 866 fdata = desc->cpr_fuses.fuse_corner_data; 867 868 for (i = 0; fuse <= end; fuse++, fuses++, i++, fdata++) { 869 /* 870 * Update SoC voltages: platforms might choose a different 871 * regulators than the one used to characterize the algorithms 872 * (ie, init_voltage_step). 873 */ 874 fdata->min_uV = roundup(fdata->min_uV, step_volt); 875 fdata->max_uV = roundup(fdata->max_uV, step_volt); 876 877 /* Populate uV */ 878 uV = cpr_read_fuse_uV(desc, fdata, fuses->init_voltage, 879 step_volt, drv); 880 if (uV < 0) 881 return uV; 882 883 fuse->min_uV = fdata->min_uV; 884 fuse->max_uV = fdata->max_uV; 885 fuse->uV = clamp(uV, fuse->min_uV, fuse->max_uV); 886 887 if (fuse == end) { 888 /* 889 * Allow the highest fuse corner's PVS voltage to 890 * define the ceiling voltage for that corner in order 891 * to support SoC's in which variable ceiling values 892 * are required. 893 */ 894 end->max_uV = max(end->max_uV, end->uV); 895 } 896 897 /* Populate target quotient by scaling */ 898 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->quotient, &fuse->quot); 899 if (ret) 900 return ret; 901 902 fuse->quot *= fdata->quot_scale; 903 fuse->quot += fdata->quot_offset; 904 fuse->quot += fdata->quot_adjust; 905 fuse->step_quot = desc->step_quot[fuse->ring_osc_idx]; 906 907 /* Populate acc settings */ 908 fuse->accs = accs; 909 fuse->num_accs = acc_desc->num_regs_per_fuse; 910 accs += acc_desc->num_regs_per_fuse; 911 } 912 913 /* 914 * Restrict all fuse corner PVS voltages based upon per corner 915 * ceiling and floor voltages. 916 */ 917 for (fuse = drv->fuse_corners, i = 0; fuse <= end; fuse++, i++) { 918 if (fuse->uV > fuse->max_uV) 919 fuse->uV = fuse->max_uV; 920 else if (fuse->uV < fuse->min_uV) 921 fuse->uV = fuse->min_uV; 922 923 ret = regulator_is_supported_voltage(drv->vdd_apc, 924 fuse->min_uV, 925 fuse->min_uV); 926 if (!ret) { 927 dev_err(drv->dev, 928 "min uV: %d (fuse corner: %d) not supported by regulator\n", 929 fuse->min_uV, i); 930 return -EINVAL; 931 } 932 933 ret = regulator_is_supported_voltage(drv->vdd_apc, 934 fuse->max_uV, 935 fuse->max_uV); 936 if (!ret) { 937 dev_err(drv->dev, 938 "max uV: %d (fuse corner: %d) not supported by regulator\n", 939 fuse->max_uV, i); 940 return -EINVAL; 941 } 942 943 dev_dbg(drv->dev, 944 "fuse corner %d: [%d %d %d] RO%hhu quot %d squot %d\n", 945 i, fuse->min_uV, fuse->uV, fuse->max_uV, 946 fuse->ring_osc_idx, fuse->quot, fuse->step_quot); 947 } 948 949 return 0; 950 } 951 952 static int cpr_calculate_scaling(const char *quot_offset, 953 struct cpr_drv *drv, 954 const struct fuse_corner_data *fdata, 955 const struct corner *corner) 956 { 957 u32 quot_diff = 0; 958 unsigned long freq_diff; 959 int scaling; 960 const struct fuse_corner *fuse, *prev_fuse; 961 int ret; 962 963 fuse = corner->fuse_corner; 964 prev_fuse = fuse - 1; 965 966 if (quot_offset) { 967 ret = nvmem_cell_read_variable_le_u32(drv->dev, quot_offset, "_diff); 968 if (ret) 969 return ret; 970 971 quot_diff *= fdata->quot_offset_scale; 972 quot_diff += fdata->quot_offset_adjust; 973 } else { 974 quot_diff = fuse->quot - prev_fuse->quot; 975 } 976 977 freq_diff = fuse->max_freq - prev_fuse->max_freq; 978 freq_diff /= 1000000; /* Convert to MHz */ 979 scaling = 1000 * quot_diff / freq_diff; 980 return min(scaling, fdata->max_quot_scale); 981 } 982 983 static int cpr_interpolate(const struct corner *corner, int step_volt, 984 const struct fuse_corner_data *fdata) 985 { 986 unsigned long f_high, f_low, f_diff; 987 int uV_high, uV_low, uV; 988 u64 temp, temp_limit; 989 const struct fuse_corner *fuse, *prev_fuse; 990 991 fuse = corner->fuse_corner; 992 prev_fuse = fuse - 1; 993 994 f_high = fuse->max_freq; 995 f_low = prev_fuse->max_freq; 996 uV_high = fuse->uV; 997 uV_low = prev_fuse->uV; 998 f_diff = fuse->max_freq - corner->freq; 999 1000 /* 1001 * Don't interpolate in the wrong direction. This could happen 1002 * if the adjusted fuse voltage overlaps with the previous fuse's 1003 * adjusted voltage. 1004 */ 1005 if (f_high <= f_low || uV_high <= uV_low || f_high <= corner->freq) 1006 return corner->uV; 1007 1008 temp = f_diff * (uV_high - uV_low); 1009 temp = div64_ul(temp, f_high - f_low); 1010 1011 /* 1012 * max_volt_scale has units of uV/MHz while freq values 1013 * have units of Hz. Divide by 1000000 to convert to. 1014 */ 1015 temp_limit = f_diff * fdata->max_volt_scale; 1016 do_div(temp_limit, 1000000); 1017 1018 uV = uV_high - min(temp, temp_limit); 1019 return roundup(uV, step_volt); 1020 } 1021 1022 static unsigned int cpr_get_fuse_corner(struct dev_pm_opp *opp) 1023 { 1024 struct device_node *np; 1025 unsigned int fuse_corner = 0; 1026 1027 np = dev_pm_opp_get_of_node(opp); 1028 if (of_property_read_u32(np, "qcom,opp-fuse-level", &fuse_corner)) 1029 pr_err("%s: missing 'qcom,opp-fuse-level' property\n", 1030 __func__); 1031 1032 of_node_put(np); 1033 1034 return fuse_corner; 1035 } 1036 1037 static unsigned long cpr_get_opp_hz_for_req(struct dev_pm_opp *ref, 1038 struct device *cpu_dev) 1039 { 1040 struct device_node *ref_np __free(device_node) = NULL; 1041 struct device_node *desc_np __free(device_node) = 1042 dev_pm_opp_of_get_opp_desc_node(cpu_dev); 1043 1044 if (!desc_np) 1045 return 0; 1046 1047 ref_np = dev_pm_opp_get_of_node(ref); 1048 if (!ref_np) 1049 return 0; 1050 1051 for_each_available_child_of_node_scoped(desc_np, child_np) { 1052 struct device_node *child_req_np __free(device_node) = 1053 of_parse_phandle(child_np, "required-opps", 0); 1054 1055 if (child_req_np == ref_np) { 1056 u64 rate = 0; 1057 1058 of_property_read_u64(child_np, "opp-hz", &rate); 1059 return (unsigned long) rate; 1060 } 1061 } 1062 1063 return 0; 1064 } 1065 1066 static int cpr_corner_init(struct cpr_drv *drv) 1067 { 1068 const struct cpr_desc *desc = drv->desc; 1069 const struct cpr_fuse *fuses = drv->cpr_fuses; 1070 int i, level, scaling = 0; 1071 unsigned int fnum, fc; 1072 const char *quot_offset; 1073 struct fuse_corner *fuse, *prev_fuse; 1074 struct corner *corner, *end; 1075 struct corner_data *cdata; 1076 const struct fuse_corner_data *fdata; 1077 bool apply_scaling; 1078 unsigned long freq_diff, freq_diff_mhz; 1079 unsigned long freq; 1080 int step_volt = regulator_get_linear_step(drv->vdd_apc); 1081 struct dev_pm_opp *opp; 1082 1083 if (!step_volt) 1084 return -EINVAL; 1085 1086 corner = drv->corners; 1087 end = &corner[drv->num_corners - 1]; 1088 1089 cdata = devm_kcalloc(drv->dev, drv->num_corners, 1090 sizeof(struct corner_data), 1091 GFP_KERNEL); 1092 if (!cdata) 1093 return -ENOMEM; 1094 1095 /* 1096 * Store maximum frequency for each fuse corner based on the frequency 1097 * plan 1098 */ 1099 for (level = 1; level <= drv->num_corners; level++) { 1100 opp = dev_pm_opp_find_level_exact(&drv->pd.dev, level); 1101 if (IS_ERR(opp)) 1102 return -EINVAL; 1103 fc = cpr_get_fuse_corner(opp); 1104 if (!fc) { 1105 dev_pm_opp_put(opp); 1106 return -EINVAL; 1107 } 1108 fnum = fc - 1; 1109 freq = cpr_get_opp_hz_for_req(opp, drv->attached_cpu_dev); 1110 if (!freq) { 1111 dev_pm_opp_put(opp); 1112 return -EINVAL; 1113 } 1114 cdata[level - 1].fuse_corner = fnum; 1115 cdata[level - 1].freq = freq; 1116 1117 fuse = &drv->fuse_corners[fnum]; 1118 dev_dbg(drv->dev, "freq: %lu level: %u fuse level: %u\n", 1119 freq, dev_pm_opp_get_level(opp) - 1, fnum); 1120 if (freq > fuse->max_freq) 1121 fuse->max_freq = freq; 1122 dev_pm_opp_put(opp); 1123 } 1124 1125 /* 1126 * Get the quotient adjustment scaling factor, according to: 1127 * 1128 * scaling = min(1000 * (QUOT(corner_N) - QUOT(corner_N-1)) 1129 * / (freq(corner_N) - freq(corner_N-1)), max_factor) 1130 * 1131 * QUOT(corner_N): quotient read from fuse for fuse corner N 1132 * QUOT(corner_N-1): quotient read from fuse for fuse corner (N - 1) 1133 * freq(corner_N): max frequency in MHz supported by fuse corner N 1134 * freq(corner_N-1): max frequency in MHz supported by fuse corner 1135 * (N - 1) 1136 * 1137 * Then walk through the corners mapped to each fuse corner 1138 * and calculate the quotient adjustment for each one using the 1139 * following formula: 1140 * 1141 * quot_adjust = (freq_max - freq_corner) * scaling / 1000 1142 * 1143 * freq_max: max frequency in MHz supported by the fuse corner 1144 * freq_corner: frequency in MHz corresponding to the corner 1145 * scaling: calculated from above equation 1146 * 1147 * 1148 * + + 1149 * | v | 1150 * q | f c o | f c 1151 * u | c l | c 1152 * o | f t | f 1153 * t | c a | c 1154 * | c f g | c f 1155 * | e | 1156 * +--------------- +---------------- 1157 * 0 1 2 3 4 5 6 0 1 2 3 4 5 6 1158 * corner corner 1159 * 1160 * c = corner 1161 * f = fuse corner 1162 * 1163 */ 1164 for (apply_scaling = false, i = 0; corner <= end; corner++, i++) { 1165 fnum = cdata[i].fuse_corner; 1166 fdata = &desc->cpr_fuses.fuse_corner_data[fnum]; 1167 quot_offset = fuses[fnum].quotient_offset; 1168 fuse = &drv->fuse_corners[fnum]; 1169 if (fnum) 1170 prev_fuse = &drv->fuse_corners[fnum - 1]; 1171 else 1172 prev_fuse = NULL; 1173 1174 corner->fuse_corner = fuse; 1175 corner->freq = cdata[i].freq; 1176 corner->uV = fuse->uV; 1177 1178 if (prev_fuse && cdata[i - 1].freq == prev_fuse->max_freq) { 1179 scaling = cpr_calculate_scaling(quot_offset, drv, 1180 fdata, corner); 1181 if (scaling < 0) 1182 return scaling; 1183 1184 apply_scaling = true; 1185 } else if (corner->freq == fuse->max_freq) { 1186 /* This is a fuse corner; don't scale anything */ 1187 apply_scaling = false; 1188 } 1189 1190 if (apply_scaling) { 1191 freq_diff = fuse->max_freq - corner->freq; 1192 freq_diff_mhz = freq_diff / 1000000; 1193 corner->quot_adjust = scaling * freq_diff_mhz / 1000; 1194 1195 corner->uV = cpr_interpolate(corner, step_volt, fdata); 1196 } 1197 1198 corner->max_uV = fuse->max_uV; 1199 corner->min_uV = fuse->min_uV; 1200 corner->uV = clamp(corner->uV, corner->min_uV, corner->max_uV); 1201 corner->last_uV = corner->uV; 1202 1203 /* Reduce the ceiling voltage if needed */ 1204 if (desc->reduce_to_corner_uV && corner->uV < corner->max_uV) 1205 corner->max_uV = corner->uV; 1206 else if (desc->reduce_to_fuse_uV && fuse->uV < corner->max_uV) 1207 corner->max_uV = max(corner->min_uV, fuse->uV); 1208 1209 dev_dbg(drv->dev, "corner %d: [%d %d %d] quot %d\n", i, 1210 corner->min_uV, corner->uV, corner->max_uV, 1211 fuse->quot - corner->quot_adjust); 1212 } 1213 1214 return 0; 1215 } 1216 1217 static const struct cpr_fuse *cpr_get_fuses(struct cpr_drv *drv) 1218 { 1219 const struct cpr_desc *desc = drv->desc; 1220 struct cpr_fuse *fuses; 1221 int i; 1222 1223 fuses = devm_kcalloc(drv->dev, desc->num_fuse_corners, 1224 sizeof(struct cpr_fuse), 1225 GFP_KERNEL); 1226 if (!fuses) 1227 return ERR_PTR(-ENOMEM); 1228 1229 for (i = 0; i < desc->num_fuse_corners; i++) { 1230 char tbuf[32]; 1231 1232 snprintf(tbuf, 32, "cpr_ring_osc%d", i + 1); 1233 fuses[i].ring_osc = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL); 1234 if (!fuses[i].ring_osc) 1235 return ERR_PTR(-ENOMEM); 1236 1237 snprintf(tbuf, 32, "cpr_init_voltage%d", i + 1); 1238 fuses[i].init_voltage = devm_kstrdup(drv->dev, tbuf, 1239 GFP_KERNEL); 1240 if (!fuses[i].init_voltage) 1241 return ERR_PTR(-ENOMEM); 1242 1243 snprintf(tbuf, 32, "cpr_quotient%d", i + 1); 1244 fuses[i].quotient = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL); 1245 if (!fuses[i].quotient) 1246 return ERR_PTR(-ENOMEM); 1247 1248 snprintf(tbuf, 32, "cpr_quotient_offset%d", i + 1); 1249 fuses[i].quotient_offset = devm_kstrdup(drv->dev, tbuf, 1250 GFP_KERNEL); 1251 if (!fuses[i].quotient_offset) 1252 return ERR_PTR(-ENOMEM); 1253 } 1254 1255 return fuses; 1256 } 1257 1258 static void cpr_set_loop_allowed(struct cpr_drv *drv) 1259 { 1260 drv->loop_disabled = false; 1261 } 1262 1263 static int cpr_init_parameters(struct cpr_drv *drv) 1264 { 1265 const struct cpr_desc *desc = drv->desc; 1266 struct clk *clk; 1267 1268 clk = clk_get(drv->dev, "ref"); 1269 if (IS_ERR(clk)) 1270 return PTR_ERR(clk); 1271 1272 drv->ref_clk_khz = clk_get_rate(clk) / 1000; 1273 clk_put(clk); 1274 1275 if (desc->timer_cons_up > RBIF_TIMER_ADJ_CONS_UP_MASK || 1276 desc->timer_cons_down > RBIF_TIMER_ADJ_CONS_DOWN_MASK || 1277 desc->up_threshold > RBCPR_CTL_UP_THRESHOLD_MASK || 1278 desc->down_threshold > RBCPR_CTL_DN_THRESHOLD_MASK || 1279 desc->idle_clocks > RBCPR_STEP_QUOT_IDLE_CLK_MASK || 1280 desc->clamp_timer_interval > RBIF_TIMER_ADJ_CLAMP_INT_MASK) 1281 return -EINVAL; 1282 1283 dev_dbg(drv->dev, "up threshold = %u, down threshold = %u\n", 1284 desc->up_threshold, desc->down_threshold); 1285 1286 return 0; 1287 } 1288 1289 static int cpr_find_initial_corner(struct cpr_drv *drv) 1290 { 1291 unsigned long rate; 1292 const struct corner *end; 1293 struct corner *iter; 1294 unsigned int i = 0; 1295 1296 if (!drv->cpu_clk) { 1297 dev_err(drv->dev, "cannot get rate from NULL clk\n"); 1298 return -EINVAL; 1299 } 1300 1301 end = &drv->corners[drv->num_corners - 1]; 1302 rate = clk_get_rate(drv->cpu_clk); 1303 1304 /* 1305 * Some bootloaders set a CPU clock frequency that is not defined 1306 * in the OPP table. When running at an unlisted frequency, 1307 * cpufreq_online() will change to the OPP which has the lowest 1308 * frequency, at or above the unlisted frequency. 1309 * Since cpufreq_online() always "rounds up" in the case of an 1310 * unlisted frequency, this function always "rounds down" in case 1311 * of an unlisted frequency. That way, when cpufreq_online() 1312 * triggers the first ever call to cpr_set_performance_state(), 1313 * it will correctly determine the direction as UP. 1314 */ 1315 for (iter = drv->corners; iter <= end; iter++) { 1316 if (iter->freq > rate) 1317 break; 1318 i++; 1319 if (iter->freq == rate) { 1320 drv->corner = iter; 1321 break; 1322 } 1323 if (iter->freq < rate) 1324 drv->corner = iter; 1325 } 1326 1327 if (!drv->corner) { 1328 dev_err(drv->dev, "boot up corner not found\n"); 1329 return -EINVAL; 1330 } 1331 1332 dev_dbg(drv->dev, "boot up perf state: %u\n", i); 1333 1334 return 0; 1335 } 1336 1337 static const struct cpr_desc qcs404_cpr_desc = { 1338 .num_fuse_corners = 3, 1339 .min_diff_quot = CPR_FUSE_MIN_QUOT_DIFF, 1340 .step_quot = (int []){ 25, 25, 25, }, 1341 .timer_delay_us = 5000, 1342 .timer_cons_up = 0, 1343 .timer_cons_down = 2, 1344 .up_threshold = 1, 1345 .down_threshold = 3, 1346 .idle_clocks = 15, 1347 .gcnt_us = 1, 1348 .vdd_apc_step_up_limit = 1, 1349 .vdd_apc_step_down_limit = 1, 1350 .cpr_fuses = { 1351 .init_voltage_step = 8000, 1352 .init_voltage_width = 6, 1353 .fuse_corner_data = (struct fuse_corner_data[]){ 1354 /* fuse corner 0 */ 1355 { 1356 .ref_uV = 1224000, 1357 .max_uV = 1224000, 1358 .min_uV = 1048000, 1359 .max_volt_scale = 0, 1360 .max_quot_scale = 0, 1361 .quot_offset = 0, 1362 .quot_scale = 1, 1363 .quot_adjust = 0, 1364 .quot_offset_scale = 5, 1365 .quot_offset_adjust = 0, 1366 }, 1367 /* fuse corner 1 */ 1368 { 1369 .ref_uV = 1288000, 1370 .max_uV = 1288000, 1371 .min_uV = 1048000, 1372 .max_volt_scale = 2000, 1373 .max_quot_scale = 1400, 1374 .quot_offset = 0, 1375 .quot_scale = 1, 1376 .quot_adjust = -20, 1377 .quot_offset_scale = 5, 1378 .quot_offset_adjust = 0, 1379 }, 1380 /* fuse corner 2 */ 1381 { 1382 .ref_uV = 1352000, 1383 .max_uV = 1384000, 1384 .min_uV = 1088000, 1385 .max_volt_scale = 2000, 1386 .max_quot_scale = 1400, 1387 .quot_offset = 0, 1388 .quot_scale = 1, 1389 .quot_adjust = 0, 1390 .quot_offset_scale = 5, 1391 .quot_offset_adjust = 0, 1392 }, 1393 }, 1394 }, 1395 }; 1396 1397 static const struct acc_desc qcs404_acc_desc = { 1398 .settings = (struct reg_sequence[]){ 1399 { 0xb120, 0x1041040 }, 1400 { 0xb124, 0x41 }, 1401 { 0xb120, 0x0 }, 1402 { 0xb124, 0x0 }, 1403 { 0xb120, 0x0 }, 1404 { 0xb124, 0x0 }, 1405 }, 1406 .config = (struct reg_sequence[]){ 1407 { 0xb138, 0xff }, 1408 { 0xb130, 0x5555 }, 1409 }, 1410 .num_regs_per_fuse = 2, 1411 }; 1412 1413 static const struct cpr_acc_desc qcs404_cpr_acc_desc = { 1414 .cpr_desc = &qcs404_cpr_desc, 1415 .acc_desc = &qcs404_acc_desc, 1416 }; 1417 1418 static int cpr_power_off(struct generic_pm_domain *domain) 1419 { 1420 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); 1421 1422 return cpr_disable(drv); 1423 } 1424 1425 static int cpr_power_on(struct generic_pm_domain *domain) 1426 { 1427 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); 1428 1429 return cpr_enable(drv); 1430 } 1431 1432 static int cpr_pd_attach_dev(struct generic_pm_domain *domain, 1433 struct device *dev) 1434 { 1435 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); 1436 const struct acc_desc *acc_desc = drv->acc_desc; 1437 int ret; 1438 1439 guard(mutex)(&drv->lock); 1440 1441 dev_dbg(drv->dev, "attach callback for: %s\n", dev_name(dev)); 1442 1443 /* 1444 * This driver only supports scaling voltage for a CPU cluster 1445 * where all CPUs in the cluster share a single regulator. 1446 * Therefore, save the struct device pointer only for the first 1447 * CPU device that gets attached. There is no need to do any 1448 * additional initialization when further CPUs get attached. 1449 */ 1450 if (drv->attached_cpu_dev) 1451 return 0; 1452 1453 /* 1454 * cpr_scale_voltage() requires the direction (if we are changing 1455 * to a higher or lower OPP). The first time 1456 * cpr_set_performance_state() is called, there is no previous 1457 * performance state defined. Therefore, we call 1458 * cpr_find_initial_corner() that gets the CPU clock frequency 1459 * set by the bootloader, so that we can determine the direction 1460 * the first time cpr_set_performance_state() is called. 1461 */ 1462 drv->cpu_clk = devm_clk_get(dev, NULL); 1463 if (IS_ERR(drv->cpu_clk)) 1464 return dev_err_probe(drv->dev, PTR_ERR(drv->cpu_clk), 1465 "could not get cpu clk\n"); 1466 1467 drv->attached_cpu_dev = dev; 1468 1469 dev_dbg(drv->dev, "using cpu clk from: %s\n", 1470 dev_name(drv->attached_cpu_dev)); 1471 1472 /* 1473 * Everything related to (virtual) corners has to be initialized 1474 * here, when attaching to the power domain, since we need to know 1475 * the maximum frequency for each fuse corner, and this is only 1476 * available after the cpufreq driver has attached to us. 1477 * The reason for this is that we need to know the highest 1478 * frequency associated with each fuse corner. 1479 */ 1480 ret = dev_pm_opp_get_opp_count(&drv->pd.dev); 1481 if (ret < 0) { 1482 dev_err(drv->dev, "could not get OPP count\n"); 1483 return ret; 1484 } 1485 drv->num_corners = ret; 1486 1487 if (drv->num_corners < 2) { 1488 dev_err(drv->dev, "need at least 2 OPPs to use CPR\n"); 1489 return -EINVAL; 1490 } 1491 1492 drv->corners = devm_kcalloc(drv->dev, drv->num_corners, 1493 sizeof(*drv->corners), 1494 GFP_KERNEL); 1495 if (!drv->corners) 1496 return -ENOMEM; 1497 1498 ret = cpr_corner_init(drv); 1499 if (ret) 1500 return ret; 1501 1502 cpr_set_loop_allowed(drv); 1503 1504 ret = cpr_init_parameters(drv); 1505 if (ret) 1506 return ret; 1507 1508 /* Configure CPR HW but keep it disabled */ 1509 ret = cpr_config(drv); 1510 if (ret) 1511 return ret; 1512 1513 ret = cpr_find_initial_corner(drv); 1514 if (ret) 1515 return ret; 1516 1517 if (acc_desc->config) 1518 regmap_multi_reg_write(drv->tcsr, acc_desc->config, 1519 acc_desc->num_regs_per_fuse); 1520 1521 /* Enable ACC if required */ 1522 if (acc_desc->enable_mask) 1523 regmap_update_bits(drv->tcsr, acc_desc->enable_reg, 1524 acc_desc->enable_mask, 1525 acc_desc->enable_mask); 1526 1527 dev_info(drv->dev, "driver initialized with %u OPPs\n", 1528 drv->num_corners); 1529 1530 return 0; 1531 } 1532 1533 static int cpr_debug_info_show(struct seq_file *s, void *unused) 1534 { 1535 u32 gcnt, ro_sel, ctl, irq_status, reg, error_steps; 1536 u32 step_dn, step_up, error, error_lt0, busy; 1537 struct cpr_drv *drv = s->private; 1538 struct fuse_corner *fuse_corner; 1539 struct corner *corner; 1540 1541 corner = drv->corner; 1542 fuse_corner = corner->fuse_corner; 1543 1544 seq_printf(s, "corner, current_volt = %d uV\n", 1545 corner->last_uV); 1546 1547 ro_sel = fuse_corner->ring_osc_idx; 1548 gcnt = cpr_read(drv, REG_RBCPR_GCNT_TARGET(ro_sel)); 1549 seq_printf(s, "rbcpr_gcnt_target (%u) = %#02X\n", ro_sel, gcnt); 1550 1551 ctl = cpr_read(drv, REG_RBCPR_CTL); 1552 seq_printf(s, "rbcpr_ctl = %#02X\n", ctl); 1553 1554 irq_status = cpr_read(drv, REG_RBIF_IRQ_STATUS); 1555 seq_printf(s, "rbcpr_irq_status = %#02X\n", irq_status); 1556 1557 reg = cpr_read(drv, REG_RBCPR_RESULT_0); 1558 seq_printf(s, "rbcpr_result_0 = %#02X\n", reg); 1559 1560 step_dn = reg & 0x01; 1561 step_up = (reg >> RBCPR_RESULT0_STEP_UP_SHIFT) & 0x01; 1562 seq_printf(s, " [step_dn = %u", step_dn); 1563 1564 seq_printf(s, ", step_up = %u", step_up); 1565 1566 error_steps = (reg >> RBCPR_RESULT0_ERROR_STEPS_SHIFT) 1567 & RBCPR_RESULT0_ERROR_STEPS_MASK; 1568 seq_printf(s, ", error_steps = %u", error_steps); 1569 1570 error = (reg >> RBCPR_RESULT0_ERROR_SHIFT) & RBCPR_RESULT0_ERROR_MASK; 1571 seq_printf(s, ", error = %u", error); 1572 1573 error_lt0 = (reg >> RBCPR_RESULT0_ERROR_LT0_SHIFT) & 0x01; 1574 seq_printf(s, ", error_lt_0 = %u", error_lt0); 1575 1576 busy = (reg >> RBCPR_RESULT0_BUSY_SHIFT) & 0x01; 1577 seq_printf(s, ", busy = %u]\n", busy); 1578 1579 return 0; 1580 } 1581 DEFINE_SHOW_ATTRIBUTE(cpr_debug_info); 1582 1583 static void cpr_debugfs_init(struct cpr_drv *drv) 1584 { 1585 drv->debugfs = debugfs_create_dir("qcom_cpr", NULL); 1586 1587 debugfs_create_file("debug_info", 0444, drv->debugfs, 1588 drv, &cpr_debug_info_fops); 1589 } 1590 1591 static int cpr_probe(struct platform_device *pdev) 1592 { 1593 struct device *dev = &pdev->dev; 1594 struct cpr_drv *drv; 1595 int irq, ret; 1596 const struct cpr_acc_desc *data; 1597 struct device_node *np; 1598 u32 cpr_rev = FUSE_REVISION_UNKNOWN; 1599 1600 data = of_device_get_match_data(dev); 1601 if (!data || !data->cpr_desc || !data->acc_desc) 1602 return -EINVAL; 1603 1604 drv = devm_kzalloc(dev, 1605 struct_size(drv, fuse_corners, data->cpr_desc->num_fuse_corners), 1606 GFP_KERNEL); 1607 if (!drv) 1608 return -ENOMEM; 1609 drv->dev = dev; 1610 drv->desc = data->cpr_desc; 1611 drv->acc_desc = data->acc_desc; 1612 1613 np = of_parse_phandle(dev->of_node, "acc-syscon", 0); 1614 if (!np) 1615 return -ENODEV; 1616 1617 drv->tcsr = syscon_node_to_regmap(np); 1618 of_node_put(np); 1619 if (IS_ERR(drv->tcsr)) 1620 return PTR_ERR(drv->tcsr); 1621 1622 drv->base = devm_platform_ioremap_resource(pdev, 0); 1623 if (IS_ERR(drv->base)) 1624 return PTR_ERR(drv->base); 1625 1626 irq = platform_get_irq(pdev, 0); 1627 if (irq < 0) 1628 return -EINVAL; 1629 1630 drv->vdd_apc = devm_regulator_get(dev, "vdd-apc"); 1631 if (IS_ERR(drv->vdd_apc)) 1632 return PTR_ERR(drv->vdd_apc); 1633 1634 /* 1635 * Initialize fuse corners, since it simply depends 1636 * on data in efuses. 1637 * Everything related to (virtual) corners has to be 1638 * initialized after attaching to the power domain, 1639 * since it depends on the CPU's OPP table. 1640 */ 1641 ret = nvmem_cell_read_variable_le_u32(dev, "cpr_fuse_revision", &cpr_rev); 1642 if (ret) 1643 return ret; 1644 1645 drv->cpr_fuses = cpr_get_fuses(drv); 1646 if (IS_ERR(drv->cpr_fuses)) 1647 return PTR_ERR(drv->cpr_fuses); 1648 1649 ret = cpr_populate_ring_osc_idx(drv); 1650 if (ret) 1651 return ret; 1652 1653 ret = cpr_fuse_corner_init(drv); 1654 if (ret) 1655 return ret; 1656 1657 mutex_init(&drv->lock); 1658 1659 ret = devm_request_threaded_irq(dev, irq, NULL, 1660 cpr_irq_handler, 1661 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 1662 "cpr", drv); 1663 if (ret) 1664 return ret; 1665 1666 drv->pd.name = devm_kstrdup_const(dev, dev->of_node->full_name, 1667 GFP_KERNEL); 1668 if (!drv->pd.name) 1669 return -EINVAL; 1670 1671 drv->pd.power_off = cpr_power_off; 1672 drv->pd.power_on = cpr_power_on; 1673 drv->pd.set_performance_state = cpr_set_performance_state; 1674 drv->pd.attach_dev = cpr_pd_attach_dev; 1675 1676 ret = pm_genpd_init(&drv->pd, NULL, true); 1677 if (ret) 1678 return ret; 1679 1680 ret = of_genpd_add_provider_simple(dev->of_node, &drv->pd); 1681 if (ret) 1682 goto err_remove_genpd; 1683 1684 platform_set_drvdata(pdev, drv); 1685 cpr_debugfs_init(drv); 1686 1687 return 0; 1688 1689 err_remove_genpd: 1690 pm_genpd_remove(&drv->pd); 1691 return ret; 1692 } 1693 1694 static void cpr_remove(struct platform_device *pdev) 1695 { 1696 struct cpr_drv *drv = platform_get_drvdata(pdev); 1697 1698 if (cpr_is_allowed(drv)) { 1699 cpr_ctl_disable(drv); 1700 cpr_irq_set(drv, 0); 1701 } 1702 1703 of_genpd_del_provider(pdev->dev.of_node); 1704 pm_genpd_remove(&drv->pd); 1705 1706 debugfs_remove_recursive(drv->debugfs); 1707 } 1708 1709 static const struct of_device_id cpr_match_table[] = { 1710 { .compatible = "qcom,qcs404-cpr", .data = &qcs404_cpr_acc_desc }, 1711 { } 1712 }; 1713 MODULE_DEVICE_TABLE(of, cpr_match_table); 1714 1715 static struct platform_driver cpr_driver = { 1716 .probe = cpr_probe, 1717 .remove = cpr_remove, 1718 .driver = { 1719 .name = "qcom-cpr", 1720 .of_match_table = cpr_match_table, 1721 }, 1722 }; 1723 module_platform_driver(cpr_driver); 1724 1725 MODULE_DESCRIPTION("Core Power Reduction (CPR) driver"); 1726 MODULE_LICENSE("GPL v2"); 1727