1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * LoongArch KGDB support
4 *
5 * Copyright (C) 2023 Loongson Technology Corporation Limited
6 */
7
8 #include <linux/hw_breakpoint.h>
9 #include <linux/kdebug.h>
10 #include <linux/kgdb.h>
11 #include <linux/objtool.h>
12 #include <linux/processor.h>
13 #include <linux/ptrace.h>
14 #include <linux/sched.h>
15 #include <linux/smp.h>
16
17 #include <asm/cacheflush.h>
18 #include <asm/fpu.h>
19 #include <asm/hw_breakpoint.h>
20 #include <asm/inst.h>
21 #include <asm/irq_regs.h>
22 #include <asm/ptrace.h>
23 #include <asm/sigcontext.h>
24
25 int kgdb_watch_activated;
26 static unsigned int stepped_opcode;
27 static unsigned long stepped_address;
28
29 struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
30 { "r0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[0]) },
31 { "r1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[1]) },
32 { "r2", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[2]) },
33 { "r3", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[3]) },
34 { "r4", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[4]) },
35 { "r5", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[5]) },
36 { "r6", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[6]) },
37 { "r7", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[7]) },
38 { "r8", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[8]) },
39 { "r9", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[9]) },
40 { "r10", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[10]) },
41 { "r11", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[11]) },
42 { "r12", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[12]) },
43 { "r13", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[13]) },
44 { "r14", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[14]) },
45 { "r15", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[15]) },
46 { "r16", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[16]) },
47 { "r17", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[17]) },
48 { "r18", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[18]) },
49 { "r19", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[19]) },
50 { "r20", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[20]) },
51 { "r21", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[21]) },
52 { "r22", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[22]) },
53 { "r23", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[23]) },
54 { "r24", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[24]) },
55 { "r25", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[25]) },
56 { "r26", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[26]) },
57 { "r27", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[27]) },
58 { "r28", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[28]) },
59 { "r29", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[29]) },
60 { "r30", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[30]) },
61 { "r31", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[31]) },
62 { "orig_a0", GDB_SIZEOF_REG, offsetof(struct pt_regs, orig_a0) },
63 { "pc", GDB_SIZEOF_REG, offsetof(struct pt_regs, csr_era) },
64 { "badv", GDB_SIZEOF_REG, offsetof(struct pt_regs, csr_badvaddr) },
65 { "f0", GDB_SIZEOF_REG, 0 },
66 { "f1", GDB_SIZEOF_REG, 1 },
67 { "f2", GDB_SIZEOF_REG, 2 },
68 { "f3", GDB_SIZEOF_REG, 3 },
69 { "f4", GDB_SIZEOF_REG, 4 },
70 { "f5", GDB_SIZEOF_REG, 5 },
71 { "f6", GDB_SIZEOF_REG, 6 },
72 { "f7", GDB_SIZEOF_REG, 7 },
73 { "f8", GDB_SIZEOF_REG, 8 },
74 { "f9", GDB_SIZEOF_REG, 9 },
75 { "f10", GDB_SIZEOF_REG, 10 },
76 { "f11", GDB_SIZEOF_REG, 11 },
77 { "f12", GDB_SIZEOF_REG, 12 },
78 { "f13", GDB_SIZEOF_REG, 13 },
79 { "f14", GDB_SIZEOF_REG, 14 },
80 { "f15", GDB_SIZEOF_REG, 15 },
81 { "f16", GDB_SIZEOF_REG, 16 },
82 { "f17", GDB_SIZEOF_REG, 17 },
83 { "f18", GDB_SIZEOF_REG, 18 },
84 { "f19", GDB_SIZEOF_REG, 19 },
85 { "f20", GDB_SIZEOF_REG, 20 },
86 { "f21", GDB_SIZEOF_REG, 21 },
87 { "f22", GDB_SIZEOF_REG, 22 },
88 { "f23", GDB_SIZEOF_REG, 23 },
89 { "f24", GDB_SIZEOF_REG, 24 },
90 { "f25", GDB_SIZEOF_REG, 25 },
91 { "f26", GDB_SIZEOF_REG, 26 },
92 { "f27", GDB_SIZEOF_REG, 27 },
93 { "f28", GDB_SIZEOF_REG, 28 },
94 { "f29", GDB_SIZEOF_REG, 29 },
95 { "f30", GDB_SIZEOF_REG, 30 },
96 { "f31", GDB_SIZEOF_REG, 31 },
97 { "fcc0", 1, 0 },
98 { "fcc1", 1, 1 },
99 { "fcc2", 1, 2 },
100 { "fcc3", 1, 3 },
101 { "fcc4", 1, 4 },
102 { "fcc5", 1, 5 },
103 { "fcc6", 1, 6 },
104 { "fcc7", 1, 7 },
105 { "fcsr", 4, 0 },
106 };
107
dbg_get_reg(int regno,void * mem,struct pt_regs * regs)108 char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs)
109 {
110 int reg_offset, reg_size;
111
112 if (regno < 0 || regno >= DBG_MAX_REG_NUM)
113 return NULL;
114
115 reg_offset = dbg_reg_def[regno].offset;
116 reg_size = dbg_reg_def[regno].size;
117
118 if (reg_offset == -1)
119 goto out;
120
121 /* Handle general-purpose/orig_a0/pc/badv registers */
122 if (regno <= DBG_PT_REGS_END) {
123 memcpy(mem, (void *)regs + reg_offset, reg_size);
124 goto out;
125 }
126
127 if (!(regs->csr_euen & CSR_EUEN_FPEN))
128 goto out;
129
130 save_fp(current);
131
132 /* Handle FP registers */
133 switch (regno) {
134 case DBG_FCSR: /* Process the fcsr */
135 memcpy(mem, (void *)¤t->thread.fpu.fcsr, reg_size);
136 break;
137 case DBG_FCC_BASE ... DBG_FCC_END: /* Process the fcc */
138 memcpy(mem, (void *)¤t->thread.fpu.fcc + reg_offset, reg_size);
139 break;
140 case DBG_FPR_BASE ... DBG_FPR_END: /* Process the fpr */
141 memcpy(mem, (void *)¤t->thread.fpu.fpr[reg_offset], reg_size);
142 break;
143 default:
144 break;
145 }
146
147 out:
148 return dbg_reg_def[regno].name;
149 }
150
dbg_set_reg(int regno,void * mem,struct pt_regs * regs)151 int dbg_set_reg(int regno, void *mem, struct pt_regs *regs)
152 {
153 int reg_offset, reg_size;
154
155 if (regno < 0 || regno >= DBG_MAX_REG_NUM)
156 return -EINVAL;
157
158 reg_offset = dbg_reg_def[regno].offset;
159 reg_size = dbg_reg_def[regno].size;
160
161 if (reg_offset == -1)
162 return 0;
163
164 /* Handle general-purpose/orig_a0/pc/badv registers */
165 if (regno <= DBG_PT_REGS_END) {
166 memcpy((void *)regs + reg_offset, mem, reg_size);
167 return 0;
168 }
169
170 if (!(regs->csr_euen & CSR_EUEN_FPEN))
171 return 0;
172
173 /* Handle FP registers */
174 switch (regno) {
175 case DBG_FCSR: /* Process the fcsr */
176 memcpy((void *)¤t->thread.fpu.fcsr, mem, reg_size);
177 break;
178 case DBG_FCC_BASE ... DBG_FCC_END: /* Process the fcc */
179 memcpy((void *)¤t->thread.fpu.fcc + reg_offset, mem, reg_size);
180 break;
181 case DBG_FPR_BASE ... DBG_FPR_END: /* Process the fpr */
182 memcpy((void *)¤t->thread.fpu.fpr[reg_offset], mem, reg_size);
183 break;
184 default:
185 break;
186 }
187
188 restore_fp(current);
189
190 return 0;
191 }
192
193 /*
194 * Similar to regs_to_gdb_regs() except that process is sleeping and so
195 * we may not be able to get all the info.
196 */
sleeping_thread_to_gdb_regs(unsigned long * gdb_regs,struct task_struct * p)197 void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
198 {
199 /* Initialize to zero */
200 memset((char *)gdb_regs, 0, NUMREGBYTES);
201
202 gdb_regs[DBG_LOONGARCH_RA] = p->thread.reg01;
203 gdb_regs[DBG_LOONGARCH_TP] = (long)p;
204 gdb_regs[DBG_LOONGARCH_SP] = p->thread.reg03;
205
206 /* S0 - S8 */
207 gdb_regs[DBG_LOONGARCH_S0] = p->thread.reg23;
208 gdb_regs[DBG_LOONGARCH_S1] = p->thread.reg24;
209 gdb_regs[DBG_LOONGARCH_S2] = p->thread.reg25;
210 gdb_regs[DBG_LOONGARCH_S3] = p->thread.reg26;
211 gdb_regs[DBG_LOONGARCH_S4] = p->thread.reg27;
212 gdb_regs[DBG_LOONGARCH_S5] = p->thread.reg28;
213 gdb_regs[DBG_LOONGARCH_S6] = p->thread.reg29;
214 gdb_regs[DBG_LOONGARCH_S7] = p->thread.reg30;
215 gdb_regs[DBG_LOONGARCH_S8] = p->thread.reg31;
216
217 /*
218 * PC use return address (RA), i.e. the moment after return from __switch_to()
219 */
220 gdb_regs[DBG_LOONGARCH_PC] = p->thread.reg01;
221 }
222
kgdb_arch_set_pc(struct pt_regs * regs,unsigned long pc)223 void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc)
224 {
225 regs->csr_era = pc;
226 }
227
arch_kgdb_breakpoint(void)228 noinline void arch_kgdb_breakpoint(void)
229 {
230 __asm__ __volatile__ ( \
231 ".globl kgdb_breakinst\n\t" \
232 "kgdb_breakinst:\tbreak 2\n\t"); /* BRK_KDB = 2 */
233 }
234 STACK_FRAME_NON_STANDARD(arch_kgdb_breakpoint);
235
236 /*
237 * Calls linux_debug_hook before the kernel dies. If KGDB is enabled,
238 * then try to fall into the debugger
239 */
kgdb_loongarch_notify(struct notifier_block * self,unsigned long cmd,void * ptr)240 static int kgdb_loongarch_notify(struct notifier_block *self, unsigned long cmd, void *ptr)
241 {
242 struct die_args *args = (struct die_args *)ptr;
243 struct pt_regs *regs = args->regs;
244
245 /* Userspace events, ignore. */
246 if (user_mode(regs))
247 return NOTIFY_DONE;
248
249 if (!kgdb_io_module_registered)
250 return NOTIFY_DONE;
251
252 if (atomic_read(&kgdb_active) != -1)
253 kgdb_nmicallback(smp_processor_id(), regs);
254
255 if (kgdb_handle_exception(regs->csr_era == stepped_address ? 0 : args->trapnr,
256 args->signr, cmd, regs))
257 return NOTIFY_DONE;
258
259 if (atomic_read(&kgdb_setting_breakpoint))
260 if (regs->csr_era == (unsigned long)&kgdb_breakinst)
261 regs->csr_era += LOONGARCH_INSN_SIZE;
262
263 return NOTIFY_STOP;
264 }
265
kgdb_breakpoint_handler(struct pt_regs * regs)266 bool kgdb_breakpoint_handler(struct pt_regs *regs)
267 {
268 struct die_args args = {
269 .regs = regs,
270 .str = "Break",
271 .err = BRK_KDB,
272 .trapnr = read_csr_excode(),
273 .signr = SIGTRAP,
274
275 };
276
277 return (kgdb_loongarch_notify(NULL, DIE_TRAP, &args) == NOTIFY_STOP) ? true : false;
278 }
279
280 static struct notifier_block kgdb_notifier = {
281 .notifier_call = kgdb_loongarch_notify,
282 };
283
kgdb_arch_update_addr(struct pt_regs * regs,char * remcom_in_buffer)284 static inline void kgdb_arch_update_addr(struct pt_regs *regs,
285 char *remcom_in_buffer)
286 {
287 unsigned long addr;
288 char *ptr;
289
290 ptr = &remcom_in_buffer[1];
291 if (kgdb_hex2long(&ptr, &addr))
292 regs->csr_era = addr;
293 }
294
295 /* Calculate the new address for after a step */
get_step_address(struct pt_regs * regs,unsigned long * next_addr)296 static int get_step_address(struct pt_regs *regs, unsigned long *next_addr)
297 {
298 char cj_val;
299 unsigned int si, si_l, si_h, rd, rj, cj;
300 unsigned long pc = instruction_pointer(regs);
301 union loongarch_instruction *ip = (union loongarch_instruction *)pc;
302
303 if (pc & 3) {
304 pr_warn("%s: invalid pc 0x%lx\n", __func__, pc);
305 return -EINVAL;
306 }
307
308 *next_addr = pc + LOONGARCH_INSN_SIZE;
309
310 si_h = ip->reg0i26_format.immediate_h;
311 si_l = ip->reg0i26_format.immediate_l;
312 switch (ip->reg0i26_format.opcode) {
313 case b_op:
314 *next_addr = pc + sign_extend64((si_h << 16 | si_l) << 2, 27);
315 return 0;
316 case bl_op:
317 *next_addr = pc + sign_extend64((si_h << 16 | si_l) << 2, 27);
318 regs->regs[1] = pc + LOONGARCH_INSN_SIZE;
319 return 0;
320 }
321
322 rj = ip->reg1i21_format.rj;
323 cj = (rj & 0x07) + DBG_FCC_BASE;
324 si_l = ip->reg1i21_format.immediate_l;
325 si_h = ip->reg1i21_format.immediate_h;
326 dbg_get_reg(cj, &cj_val, regs);
327 switch (ip->reg1i21_format.opcode) {
328 case beqz_op:
329 if (regs->regs[rj] == 0)
330 *next_addr = pc + sign_extend64((si_h << 16 | si_l) << 2, 22);
331 return 0;
332 case bnez_op:
333 if (regs->regs[rj] != 0)
334 *next_addr = pc + sign_extend64((si_h << 16 | si_l) << 2, 22);
335 return 0;
336 case bceqz_op: /* bceqz_op = bcnez_op */
337 if (((rj & 0x18) == 0x00) && !cj_val) /* bceqz */
338 *next_addr = pc + sign_extend64((si_h << 16 | si_l) << 2, 22);
339 if (((rj & 0x18) == 0x08) && cj_val) /* bcnez */
340 *next_addr = pc + sign_extend64((si_h << 16 | si_l) << 2, 22);
341 return 0;
342 }
343
344 rj = ip->reg2i16_format.rj;
345 rd = ip->reg2i16_format.rd;
346 si = ip->reg2i16_format.immediate;
347 switch (ip->reg2i16_format.opcode) {
348 case beq_op:
349 if (regs->regs[rj] == regs->regs[rd])
350 *next_addr = pc + sign_extend64(si << 2, 17);
351 return 0;
352 case bne_op:
353 if (regs->regs[rj] != regs->regs[rd])
354 *next_addr = pc + sign_extend64(si << 2, 17);
355 return 0;
356 case blt_op:
357 if ((long)regs->regs[rj] < (long)regs->regs[rd])
358 *next_addr = pc + sign_extend64(si << 2, 17);
359 return 0;
360 case bge_op:
361 if ((long)regs->regs[rj] >= (long)regs->regs[rd])
362 *next_addr = pc + sign_extend64(si << 2, 17);
363 return 0;
364 case bltu_op:
365 if (regs->regs[rj] < regs->regs[rd])
366 *next_addr = pc + sign_extend64(si << 2, 17);
367 return 0;
368 case bgeu_op:
369 if (regs->regs[rj] >= regs->regs[rd])
370 *next_addr = pc + sign_extend64(si << 2, 17);
371 return 0;
372 case jirl_op:
373 regs->regs[rd] = pc + LOONGARCH_INSN_SIZE;
374 *next_addr = regs->regs[rj] + sign_extend64(si << 2, 17);
375 return 0;
376 }
377
378 return 0;
379 }
380
do_single_step(struct pt_regs * regs)381 static int do_single_step(struct pt_regs *regs)
382 {
383 int error = 0;
384 unsigned long addr = 0; /* Determine where the target instruction will send us to */
385
386 error = get_step_address(regs, &addr);
387 if (error)
388 return error;
389
390 /* Store the opcode in the stepped address */
391 error = get_kernel_nofault(stepped_opcode, (void *)addr);
392 if (error)
393 return error;
394
395 stepped_address = addr;
396
397 /* Replace the opcode with the break instruction */
398 error = copy_to_kernel_nofault((void *)stepped_address,
399 arch_kgdb_ops.gdb_bpt_instr, BREAK_INSTR_SIZE);
400 flush_icache_range(addr, addr + BREAK_INSTR_SIZE);
401
402 if (error) {
403 stepped_opcode = 0;
404 stepped_address = 0;
405 } else {
406 kgdb_single_step = 1;
407 atomic_set(&kgdb_cpu_doing_single_step, raw_smp_processor_id());
408 }
409
410 return error;
411 }
412
413 /* Undo a single step */
undo_single_step(struct pt_regs * regs)414 static void undo_single_step(struct pt_regs *regs)
415 {
416 if (stepped_opcode) {
417 copy_to_kernel_nofault((void *)stepped_address,
418 (void *)&stepped_opcode, BREAK_INSTR_SIZE);
419 flush_icache_range(stepped_address, stepped_address + BREAK_INSTR_SIZE);
420 }
421
422 stepped_opcode = 0;
423 stepped_address = 0;
424 kgdb_single_step = 0;
425 atomic_set(&kgdb_cpu_doing_single_step, -1);
426 }
427
kgdb_arch_handle_exception(int vector,int signo,int err_code,char * remcom_in_buffer,char * remcom_out_buffer,struct pt_regs * regs)428 int kgdb_arch_handle_exception(int vector, int signo, int err_code,
429 char *remcom_in_buffer, char *remcom_out_buffer,
430 struct pt_regs *regs)
431 {
432 int ret = 0;
433
434 undo_single_step(regs);
435 regs->csr_prmd |= CSR_PRMD_PWE;
436
437 switch (remcom_in_buffer[0]) {
438 case 'D':
439 case 'k':
440 regs->csr_prmd &= ~CSR_PRMD_PWE;
441 fallthrough;
442 case 'c':
443 kgdb_arch_update_addr(regs, remcom_in_buffer);
444 break;
445 case 's':
446 kgdb_arch_update_addr(regs, remcom_in_buffer);
447 ret = do_single_step(regs);
448 break;
449 default:
450 ret = -1;
451 }
452
453 return ret;
454 }
455
456 static struct hw_breakpoint {
457 unsigned int enabled;
458 unsigned long addr;
459 int len;
460 int type;
461 struct perf_event * __percpu *pev;
462 } breakinfo[LOONGARCH_MAX_BRP];
463
hw_break_reserve_slot(int breakno)464 static int hw_break_reserve_slot(int breakno)
465 {
466 int cpu, cnt = 0;
467 struct perf_event **pevent;
468
469 for_each_online_cpu(cpu) {
470 cnt++;
471 pevent = per_cpu_ptr(breakinfo[breakno].pev, cpu);
472 if (dbg_reserve_bp_slot(*pevent))
473 goto fail;
474 }
475
476 return 0;
477
478 fail:
479 for_each_online_cpu(cpu) {
480 cnt--;
481 if (!cnt)
482 break;
483 pevent = per_cpu_ptr(breakinfo[breakno].pev, cpu);
484 dbg_release_bp_slot(*pevent);
485 }
486
487 return -1;
488 }
489
hw_break_release_slot(int breakno)490 static int hw_break_release_slot(int breakno)
491 {
492 int cpu;
493 struct perf_event **pevent;
494
495 if (dbg_is_early)
496 return 0;
497
498 for_each_online_cpu(cpu) {
499 pevent = per_cpu_ptr(breakinfo[breakno].pev, cpu);
500 if (dbg_release_bp_slot(*pevent))
501 /*
502 * The debugger is responsible for handing the retry on
503 * remove failure.
504 */
505 return -1;
506 }
507
508 return 0;
509 }
510
kgdb_set_hw_break(unsigned long addr,int len,enum kgdb_bptype bptype)511 static int kgdb_set_hw_break(unsigned long addr, int len, enum kgdb_bptype bptype)
512 {
513 int i;
514
515 for (i = 0; i < LOONGARCH_MAX_BRP; i++)
516 if (!breakinfo[i].enabled)
517 break;
518
519 if (i == LOONGARCH_MAX_BRP)
520 return -1;
521
522 switch (bptype) {
523 case BP_HARDWARE_BREAKPOINT:
524 breakinfo[i].type = HW_BREAKPOINT_X;
525 break;
526 case BP_READ_WATCHPOINT:
527 breakinfo[i].type = HW_BREAKPOINT_R;
528 break;
529 case BP_WRITE_WATCHPOINT:
530 breakinfo[i].type = HW_BREAKPOINT_W;
531 break;
532 case BP_ACCESS_WATCHPOINT:
533 breakinfo[i].type = HW_BREAKPOINT_RW;
534 break;
535 default:
536 return -1;
537 }
538
539 switch (len) {
540 case 1:
541 breakinfo[i].len = HW_BREAKPOINT_LEN_1;
542 break;
543 case 2:
544 breakinfo[i].len = HW_BREAKPOINT_LEN_2;
545 break;
546 case 4:
547 breakinfo[i].len = HW_BREAKPOINT_LEN_4;
548 break;
549 case 8:
550 breakinfo[i].len = HW_BREAKPOINT_LEN_8;
551 break;
552 default:
553 return -1;
554 }
555
556 breakinfo[i].addr = addr;
557 if (hw_break_reserve_slot(i)) {
558 breakinfo[i].addr = 0;
559 return -1;
560 }
561 breakinfo[i].enabled = 1;
562
563 return 0;
564 }
565
kgdb_remove_hw_break(unsigned long addr,int len,enum kgdb_bptype bptype)566 static int kgdb_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype bptype)
567 {
568 int i;
569
570 for (i = 0; i < LOONGARCH_MAX_BRP; i++)
571 if (breakinfo[i].addr == addr && breakinfo[i].enabled)
572 break;
573
574 if (i == LOONGARCH_MAX_BRP)
575 return -1;
576
577 if (hw_break_release_slot(i)) {
578 pr_err("Cannot remove hw breakpoint at %lx\n", addr);
579 return -1;
580 }
581 breakinfo[i].enabled = 0;
582
583 return 0;
584 }
585
kgdb_disable_hw_break(struct pt_regs * regs)586 static void kgdb_disable_hw_break(struct pt_regs *regs)
587 {
588 int i;
589 int cpu = raw_smp_processor_id();
590 struct perf_event *bp;
591
592 for (i = 0; i < LOONGARCH_MAX_BRP; i++) {
593 if (!breakinfo[i].enabled)
594 continue;
595
596 bp = *per_cpu_ptr(breakinfo[i].pev, cpu);
597 if (bp->attr.disabled == 1)
598 continue;
599
600 arch_uninstall_hw_breakpoint(bp);
601 bp->attr.disabled = 1;
602 }
603
604 /* Disable hardware debugging while we are in kgdb */
605 csr_xchg32(0, CSR_CRMD_WE, LOONGARCH_CSR_CRMD);
606 }
607
kgdb_remove_all_hw_break(void)608 static void kgdb_remove_all_hw_break(void)
609 {
610 int i;
611 int cpu = raw_smp_processor_id();
612 struct perf_event *bp;
613
614 for (i = 0; i < LOONGARCH_MAX_BRP; i++) {
615 if (!breakinfo[i].enabled)
616 continue;
617
618 bp = *per_cpu_ptr(breakinfo[i].pev, cpu);
619 if (!bp->attr.disabled) {
620 arch_uninstall_hw_breakpoint(bp);
621 bp->attr.disabled = 1;
622 continue;
623 }
624
625 if (hw_break_release_slot(i))
626 pr_err("KGDB: hw bpt remove failed %lx\n", breakinfo[i].addr);
627 breakinfo[i].enabled = 0;
628 }
629
630 csr_xchg32(0, CSR_CRMD_WE, LOONGARCH_CSR_CRMD);
631 kgdb_watch_activated = 0;
632 }
633
kgdb_correct_hw_break(void)634 static void kgdb_correct_hw_break(void)
635 {
636 int i, activated = 0;
637
638 for (i = 0; i < LOONGARCH_MAX_BRP; i++) {
639 struct perf_event *bp;
640 int val;
641 int cpu = raw_smp_processor_id();
642
643 if (!breakinfo[i].enabled)
644 continue;
645
646 bp = *per_cpu_ptr(breakinfo[i].pev, cpu);
647 if (bp->attr.disabled != 1)
648 continue;
649
650 bp->attr.bp_addr = breakinfo[i].addr;
651 bp->attr.bp_len = breakinfo[i].len;
652 bp->attr.bp_type = breakinfo[i].type;
653
654 val = hw_breakpoint_arch_parse(bp, &bp->attr, counter_arch_bp(bp));
655 if (val)
656 return;
657
658 val = arch_install_hw_breakpoint(bp);
659 if (!val)
660 bp->attr.disabled = 0;
661 activated = 1;
662 }
663
664 csr_xchg32(activated ? CSR_CRMD_WE : 0, CSR_CRMD_WE, LOONGARCH_CSR_CRMD);
665 kgdb_watch_activated = activated;
666 }
667
668 const struct kgdb_arch arch_kgdb_ops = {
669 .gdb_bpt_instr = {0x02, 0x00, break_op >> 1, 0x00}, /* BRK_KDB = 2 */
670 .flags = KGDB_HW_BREAKPOINT,
671 .set_hw_breakpoint = kgdb_set_hw_break,
672 .remove_hw_breakpoint = kgdb_remove_hw_break,
673 .disable_hw_break = kgdb_disable_hw_break,
674 .remove_all_hw_break = kgdb_remove_all_hw_break,
675 .correct_hw_break = kgdb_correct_hw_break,
676 };
677
kgdb_arch_init(void)678 int kgdb_arch_init(void)
679 {
680 return register_die_notifier(&kgdb_notifier);
681 }
682
kgdb_arch_late(void)683 void kgdb_arch_late(void)
684 {
685 int i, cpu;
686 struct perf_event_attr attr;
687 struct perf_event **pevent;
688
689 hw_breakpoint_init(&attr);
690
691 attr.bp_addr = (unsigned long)kgdb_arch_init;
692 attr.bp_len = HW_BREAKPOINT_LEN_4;
693 attr.bp_type = HW_BREAKPOINT_W;
694 attr.disabled = 1;
695
696 for (i = 0; i < LOONGARCH_MAX_BRP; i++) {
697 if (breakinfo[i].pev)
698 continue;
699
700 breakinfo[i].pev = register_wide_hw_breakpoint(&attr, NULL, NULL);
701 if (IS_ERR_PCPU(breakinfo[i].pev)) {
702 pr_err("kgdb: Could not allocate hw breakpoints.\n");
703 breakinfo[i].pev = NULL;
704 return;
705 }
706
707 for_each_online_cpu(cpu) {
708 pevent = per_cpu_ptr(breakinfo[i].pev, cpu);
709 if (pevent[0]->destroy) {
710 pevent[0]->destroy = NULL;
711 release_bp_slot(*pevent);
712 }
713 }
714 }
715 }
716
kgdb_arch_exit(void)717 void kgdb_arch_exit(void)
718 {
719 int i;
720
721 for (i = 0; i < LOONGARCH_MAX_BRP; i++) {
722 if (breakinfo[i].pev) {
723 unregister_wide_hw_breakpoint(breakinfo[i].pev);
724 breakinfo[i].pev = NULL;
725 }
726 }
727
728 unregister_die_notifier(&kgdb_notifier);
729 }
730