1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 #include <linux/seq_file.h> 27 28 #include "atom.h" 29 #include "ci_dpm.h" 30 #include "cik.h" 31 #include "cikd.h" 32 #include "r600_dpm.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "radeon_ucode.h" 36 #include "si_dpm.h" 37 38 #define MC_CG_ARB_FREQ_F0 0x0a 39 #define MC_CG_ARB_FREQ_F1 0x0b 40 #define MC_CG_ARB_FREQ_F2 0x0c 41 #define MC_CG_ARB_FREQ_F3 0x0d 42 43 #define SMC_RAM_END 0x40000 44 45 #define VOLTAGE_SCALE 4 46 #define VOLTAGE_VID_OFFSET_SCALE1 625 47 #define VOLTAGE_VID_OFFSET_SCALE2 100 48 49 static const struct ci_pt_defaults defaults_hawaii_xt = { 50 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000, 51 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 }, 52 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 } 53 }; 54 55 static const struct ci_pt_defaults defaults_hawaii_pro = { 56 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062, 57 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 }, 58 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 } 59 }; 60 61 static const struct ci_pt_defaults defaults_bonaire_xt = { 62 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, 63 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 }, 64 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } 65 }; 66 67 static const struct ci_pt_defaults defaults_saturn_xt = { 68 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000, 69 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D }, 70 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 } 71 }; 72 73 static const struct ci_pt_config_reg didt_config_ci[] = { 74 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 75 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 76 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 77 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 78 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 79 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 80 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 81 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 82 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 83 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 84 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 85 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 86 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 87 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 88 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 89 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 90 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 91 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 92 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 93 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 94 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 95 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 96 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 97 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 98 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 99 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 100 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 101 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 102 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 103 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 104 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 105 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 106 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 107 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 108 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 109 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 110 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 111 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 112 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 113 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 114 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 115 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 116 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 117 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 118 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 119 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 120 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 121 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 122 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 123 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 124 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 125 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 126 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 127 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 128 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 129 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 130 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 131 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 132 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 133 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 134 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 135 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 136 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 137 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 138 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 139 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 140 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 141 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 142 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 143 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 144 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 145 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 146 { 0xFFFFFFFF } 147 }; 148 149 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev); 150 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, 151 u32 arb_freq_src, u32 arb_freq_dest); 152 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, 153 struct atom_voltage_table_entry *voltage_table, 154 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd); 155 static int ci_set_power_limit(struct radeon_device *rdev, u32 n); 156 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, 157 u32 target_tdp); 158 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate); 159 160 static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg); 161 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 162 PPSMC_Msg msg, u32 parameter); 163 164 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev); 165 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev); 166 167 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev) 168 { 169 struct ci_power_info *pi = rdev->pm.dpm.priv; 170 171 return pi; 172 } 173 174 static struct ci_ps *ci_get_ps(struct radeon_ps *rps) 175 { 176 struct ci_ps *ps = rps->ps_priv; 177 178 return ps; 179 } 180 181 static void ci_initialize_powertune_defaults(struct radeon_device *rdev) 182 { 183 struct ci_power_info *pi = ci_get_pi(rdev); 184 185 switch (rdev->pdev->device) { 186 case 0x6649: 187 case 0x6650: 188 case 0x6651: 189 case 0x6658: 190 case 0x665C: 191 case 0x665D: 192 default: 193 pi->powertune_defaults = &defaults_bonaire_xt; 194 break; 195 case 0x6640: 196 case 0x6641: 197 case 0x6646: 198 case 0x6647: 199 pi->powertune_defaults = &defaults_saturn_xt; 200 break; 201 case 0x67B8: 202 case 0x67B0: 203 pi->powertune_defaults = &defaults_hawaii_xt; 204 break; 205 case 0x67BA: 206 case 0x67B1: 207 pi->powertune_defaults = &defaults_hawaii_pro; 208 break; 209 case 0x67A0: 210 case 0x67A1: 211 case 0x67A2: 212 case 0x67A8: 213 case 0x67A9: 214 case 0x67AA: 215 case 0x67B9: 216 case 0x67BE: 217 pi->powertune_defaults = &defaults_bonaire_xt; 218 break; 219 } 220 221 pi->dte_tj_offset = 0; 222 223 pi->caps_power_containment = true; 224 pi->caps_cac = false; 225 pi->caps_sq_ramping = false; 226 pi->caps_db_ramping = false; 227 pi->caps_td_ramping = false; 228 pi->caps_tcp_ramping = false; 229 230 if (pi->caps_power_containment) { 231 pi->caps_cac = true; 232 if (rdev->family == CHIP_HAWAII) 233 pi->enable_bapm_feature = false; 234 else 235 pi->enable_bapm_feature = true; 236 pi->enable_tdc_limit_feature = true; 237 pi->enable_pkg_pwr_tracking_feature = true; 238 } 239 } 240 241 static u8 ci_convert_to_vid(u16 vddc) 242 { 243 return (6200 - (vddc * VOLTAGE_SCALE)) / 25; 244 } 245 246 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev) 247 { 248 struct ci_power_info *pi = ci_get_pi(rdev); 249 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; 250 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; 251 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; 252 u32 i; 253 254 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) 255 return -EINVAL; 256 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) 257 return -EINVAL; 258 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != 259 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) 260 return -EINVAL; 261 262 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { 263 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { 264 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); 265 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); 266 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); 267 } else { 268 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); 269 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); 270 } 271 } 272 return 0; 273 } 274 275 static int ci_populate_vddc_vid(struct radeon_device *rdev) 276 { 277 struct ci_power_info *pi = ci_get_pi(rdev); 278 u8 *vid = pi->smc_powertune_table.VddCVid; 279 u32 i; 280 281 if (pi->vddc_voltage_table.count > 8) 282 return -EINVAL; 283 284 for (i = 0; i < pi->vddc_voltage_table.count; i++) 285 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); 286 287 return 0; 288 } 289 290 static int ci_populate_svi_load_line(struct radeon_device *rdev) 291 { 292 struct ci_power_info *pi = ci_get_pi(rdev); 293 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 294 295 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; 296 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; 297 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; 298 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; 299 300 return 0; 301 } 302 303 static int ci_populate_tdc_limit(struct radeon_device *rdev) 304 { 305 struct ci_power_info *pi = ci_get_pi(rdev); 306 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 307 u16 tdc_limit; 308 309 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; 310 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); 311 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = 312 pt_defaults->tdc_vddc_throttle_release_limit_perc; 313 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; 314 315 return 0; 316 } 317 318 static int ci_populate_dw8(struct radeon_device *rdev) 319 { 320 struct ci_power_info *pi = ci_get_pi(rdev); 321 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 322 int ret; 323 324 ret = ci_read_smc_sram_dword(rdev, 325 SMU7_FIRMWARE_HEADER_LOCATION + 326 offsetof(SMU7_Firmware_Header, PmFuseTable) + 327 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl), 328 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, 329 pi->sram_end); 330 if (ret) 331 return -EINVAL; 332 else 333 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; 334 335 return 0; 336 } 337 338 static int ci_populate_fuzzy_fan(struct radeon_device *rdev) 339 { 340 struct ci_power_info *pi = ci_get_pi(rdev); 341 342 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) || 343 (rdev->pm.dpm.fan.fan_output_sensitivity == 0)) 344 rdev->pm.dpm.fan.fan_output_sensitivity = 345 rdev->pm.dpm.fan.default_fan_output_sensitivity; 346 347 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = 348 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity); 349 350 return 0; 351 } 352 353 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev) 354 { 355 struct ci_power_info *pi = ci_get_pi(rdev); 356 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; 357 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; 358 int i, min, max; 359 360 min = max = hi_vid[0]; 361 for (i = 0; i < 8; i++) { 362 if (0 != hi_vid[i]) { 363 if (min > hi_vid[i]) 364 min = hi_vid[i]; 365 if (max < hi_vid[i]) 366 max = hi_vid[i]; 367 } 368 369 if (0 != lo_vid[i]) { 370 if (min > lo_vid[i]) 371 min = lo_vid[i]; 372 if (max < lo_vid[i]) 373 max = lo_vid[i]; 374 } 375 } 376 377 if ((min == 0) || (max == 0)) 378 return -EINVAL; 379 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; 380 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; 381 382 return 0; 383 } 384 385 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev) 386 { 387 struct ci_power_info *pi = ci_get_pi(rdev); 388 u16 hi_sidd, lo_sidd; 389 struct radeon_cac_tdp_table *cac_tdp_table = 390 rdev->pm.dpm.dyn_state.cac_tdp_table; 391 392 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256; 393 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256; 394 395 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); 396 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); 397 398 return 0; 399 } 400 401 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev) 402 { 403 struct ci_power_info *pi = ci_get_pi(rdev); 404 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 405 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; 406 struct radeon_cac_tdp_table *cac_tdp_table = 407 rdev->pm.dpm.dyn_state.cac_tdp_table; 408 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 409 int i, j, k; 410 const u16 *def1; 411 const u16 *def2; 412 413 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; 414 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; 415 416 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; 417 dpm_table->GpuTjMax = 418 (u8)(pi->thermal_temp_setting.temperature_high / 1000); 419 dpm_table->GpuTjHyst = 8; 420 421 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; 422 423 if (ppm) { 424 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); 425 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); 426 } else { 427 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); 428 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0); 429 } 430 431 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient); 432 def1 = pt_defaults->bapmti_r; 433 def2 = pt_defaults->bapmti_rc; 434 435 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) { 436 for (j = 0; j < SMU7_DTE_SOURCES; j++) { 437 for (k = 0; k < SMU7_DTE_SINKS; k++) { 438 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1); 439 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2); 440 def1++; 441 def2++; 442 } 443 } 444 } 445 446 return 0; 447 } 448 449 static int ci_populate_pm_base(struct radeon_device *rdev) 450 { 451 struct ci_power_info *pi = ci_get_pi(rdev); 452 u32 pm_fuse_table_offset; 453 int ret; 454 455 if (pi->caps_power_containment) { 456 ret = ci_read_smc_sram_dword(rdev, 457 SMU7_FIRMWARE_HEADER_LOCATION + 458 offsetof(SMU7_Firmware_Header, PmFuseTable), 459 &pm_fuse_table_offset, pi->sram_end); 460 if (ret) 461 return ret; 462 ret = ci_populate_bapm_vddc_vid_sidd(rdev); 463 if (ret) 464 return ret; 465 ret = ci_populate_vddc_vid(rdev); 466 if (ret) 467 return ret; 468 ret = ci_populate_svi_load_line(rdev); 469 if (ret) 470 return ret; 471 ret = ci_populate_tdc_limit(rdev); 472 if (ret) 473 return ret; 474 ret = ci_populate_dw8(rdev); 475 if (ret) 476 return ret; 477 ret = ci_populate_fuzzy_fan(rdev); 478 if (ret) 479 return ret; 480 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev); 481 if (ret) 482 return ret; 483 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev); 484 if (ret) 485 return ret; 486 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset, 487 (u8 *)&pi->smc_powertune_table, 488 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); 489 if (ret) 490 return ret; 491 } 492 493 return 0; 494 } 495 496 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable) 497 { 498 struct ci_power_info *pi = ci_get_pi(rdev); 499 u32 data; 500 501 if (pi->caps_sq_ramping) { 502 data = RREG32_DIDT(DIDT_SQ_CTRL0); 503 if (enable) 504 data |= DIDT_CTRL_EN; 505 else 506 data &= ~DIDT_CTRL_EN; 507 WREG32_DIDT(DIDT_SQ_CTRL0, data); 508 } 509 510 if (pi->caps_db_ramping) { 511 data = RREG32_DIDT(DIDT_DB_CTRL0); 512 if (enable) 513 data |= DIDT_CTRL_EN; 514 else 515 data &= ~DIDT_CTRL_EN; 516 WREG32_DIDT(DIDT_DB_CTRL0, data); 517 } 518 519 if (pi->caps_td_ramping) { 520 data = RREG32_DIDT(DIDT_TD_CTRL0); 521 if (enable) 522 data |= DIDT_CTRL_EN; 523 else 524 data &= ~DIDT_CTRL_EN; 525 WREG32_DIDT(DIDT_TD_CTRL0, data); 526 } 527 528 if (pi->caps_tcp_ramping) { 529 data = RREG32_DIDT(DIDT_TCP_CTRL0); 530 if (enable) 531 data |= DIDT_CTRL_EN; 532 else 533 data &= ~DIDT_CTRL_EN; 534 WREG32_DIDT(DIDT_TCP_CTRL0, data); 535 } 536 } 537 538 static int ci_program_pt_config_registers(struct radeon_device *rdev, 539 const struct ci_pt_config_reg *cac_config_regs) 540 { 541 const struct ci_pt_config_reg *config_regs = cac_config_regs; 542 u32 data; 543 u32 cache = 0; 544 545 if (config_regs == NULL) 546 return -EINVAL; 547 548 while (config_regs->offset != 0xFFFFFFFF) { 549 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) { 550 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); 551 } else { 552 switch (config_regs->type) { 553 case CISLANDS_CONFIGREG_SMC_IND: 554 data = RREG32_SMC(config_regs->offset); 555 break; 556 case CISLANDS_CONFIGREG_DIDT_IND: 557 data = RREG32_DIDT(config_regs->offset); 558 break; 559 default: 560 data = RREG32(config_regs->offset << 2); 561 break; 562 } 563 564 data &= ~config_regs->mask; 565 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 566 data |= cache; 567 568 switch (config_regs->type) { 569 case CISLANDS_CONFIGREG_SMC_IND: 570 WREG32_SMC(config_regs->offset, data); 571 break; 572 case CISLANDS_CONFIGREG_DIDT_IND: 573 WREG32_DIDT(config_regs->offset, data); 574 break; 575 default: 576 WREG32(config_regs->offset << 2, data); 577 break; 578 } 579 cache = 0; 580 } 581 config_regs++; 582 } 583 return 0; 584 } 585 586 static int ci_enable_didt(struct radeon_device *rdev, bool enable) 587 { 588 struct ci_power_info *pi = ci_get_pi(rdev); 589 int ret; 590 591 if (pi->caps_sq_ramping || pi->caps_db_ramping || 592 pi->caps_td_ramping || pi->caps_tcp_ramping) { 593 cik_enter_rlc_safe_mode(rdev); 594 595 if (enable) { 596 ret = ci_program_pt_config_registers(rdev, didt_config_ci); 597 if (ret) { 598 cik_exit_rlc_safe_mode(rdev); 599 return ret; 600 } 601 } 602 603 ci_do_enable_didt(rdev, enable); 604 605 cik_exit_rlc_safe_mode(rdev); 606 } 607 608 return 0; 609 } 610 611 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable) 612 { 613 struct ci_power_info *pi = ci_get_pi(rdev); 614 PPSMC_Result smc_result; 615 int ret = 0; 616 617 if (enable) { 618 pi->power_containment_features = 0; 619 if (pi->caps_power_containment) { 620 if (pi->enable_bapm_feature) { 621 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 622 if (smc_result != PPSMC_Result_OK) 623 ret = -EINVAL; 624 else 625 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; 626 } 627 628 if (pi->enable_tdc_limit_feature) { 629 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable); 630 if (smc_result != PPSMC_Result_OK) 631 ret = -EINVAL; 632 else 633 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; 634 } 635 636 if (pi->enable_pkg_pwr_tracking_feature) { 637 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable); 638 if (smc_result != PPSMC_Result_OK) { 639 ret = -EINVAL; 640 } else { 641 struct radeon_cac_tdp_table *cac_tdp_table = 642 rdev->pm.dpm.dyn_state.cac_tdp_table; 643 u32 default_pwr_limit = 644 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); 645 646 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; 647 648 ci_set_power_limit(rdev, default_pwr_limit); 649 } 650 } 651 } 652 } else { 653 if (pi->caps_power_containment && pi->power_containment_features) { 654 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) 655 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable); 656 657 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) 658 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 659 660 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) 661 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable); 662 pi->power_containment_features = 0; 663 } 664 } 665 666 return ret; 667 } 668 669 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable) 670 { 671 struct ci_power_info *pi = ci_get_pi(rdev); 672 PPSMC_Result smc_result; 673 int ret = 0; 674 675 if (pi->caps_cac) { 676 if (enable) { 677 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 678 if (smc_result != PPSMC_Result_OK) { 679 ret = -EINVAL; 680 pi->cac_enabled = false; 681 } else { 682 pi->cac_enabled = true; 683 } 684 } else if (pi->cac_enabled) { 685 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 686 pi->cac_enabled = false; 687 } 688 } 689 690 return ret; 691 } 692 693 static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev, 694 bool enable) 695 { 696 struct ci_power_info *pi = ci_get_pi(rdev); 697 PPSMC_Result smc_result = PPSMC_Result_OK; 698 699 if (pi->thermal_sclk_dpm_enabled) { 700 if (enable) 701 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM); 702 else 703 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM); 704 } 705 706 if (smc_result == PPSMC_Result_OK) 707 return 0; 708 else 709 return -EINVAL; 710 } 711 712 static int ci_power_control_set_level(struct radeon_device *rdev) 713 { 714 struct ci_power_info *pi = ci_get_pi(rdev); 715 struct radeon_cac_tdp_table *cac_tdp_table = 716 rdev->pm.dpm.dyn_state.cac_tdp_table; 717 s32 adjust_percent; 718 s32 target_tdp; 719 int ret = 0; 720 bool adjust_polarity = false; /* ??? */ 721 722 if (pi->caps_power_containment) { 723 adjust_percent = adjust_polarity ? 724 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment); 725 target_tdp = ((100 + adjust_percent) * 726 (s32)cac_tdp_table->configurable_tdp) / 100; 727 728 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp); 729 } 730 731 return ret; 732 } 733 734 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) 735 { 736 struct ci_power_info *pi = ci_get_pi(rdev); 737 738 if (pi->uvd_power_gated == gate) 739 return; 740 741 pi->uvd_power_gated = gate; 742 743 ci_update_uvd_dpm(rdev, gate); 744 } 745 746 bool ci_dpm_vblank_too_short(struct radeon_device *rdev) 747 { 748 struct ci_power_info *pi = ci_get_pi(rdev); 749 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 750 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; 751 752 /* disable mclk switching if the refresh is >120Hz, even if the 753 * blanking period would allow it 754 */ 755 if (r600_dpm_get_vrefresh(rdev) > 120) 756 return true; 757 758 if (vblank_time < switch_limit) 759 return true; 760 else 761 return false; 762 763 } 764 765 static void ci_apply_state_adjust_rules(struct radeon_device *rdev, 766 struct radeon_ps *rps) 767 { 768 struct ci_ps *ps = ci_get_ps(rps); 769 struct ci_power_info *pi = ci_get_pi(rdev); 770 struct radeon_clock_and_voltage_limits *max_limits; 771 bool disable_mclk_switching; 772 u32 sclk, mclk; 773 int i; 774 775 if (rps->vce_active) { 776 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 777 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 778 } else { 779 rps->evclk = 0; 780 rps->ecclk = 0; 781 } 782 783 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 784 ci_dpm_vblank_too_short(rdev)) 785 disable_mclk_switching = true; 786 else 787 disable_mclk_switching = false; 788 789 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) 790 pi->battery_state = true; 791 else 792 pi->battery_state = false; 793 794 if (rdev->pm.dpm.ac_power) 795 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 796 else 797 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 798 799 if (rdev->pm.dpm.ac_power == false) { 800 for (i = 0; i < ps->performance_level_count; i++) { 801 if (ps->performance_levels[i].mclk > max_limits->mclk) 802 ps->performance_levels[i].mclk = max_limits->mclk; 803 if (ps->performance_levels[i].sclk > max_limits->sclk) 804 ps->performance_levels[i].sclk = max_limits->sclk; 805 } 806 } 807 808 /* XXX validate the min clocks required for display */ 809 810 if (disable_mclk_switching) { 811 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 812 sclk = ps->performance_levels[0].sclk; 813 } else { 814 mclk = ps->performance_levels[0].mclk; 815 sclk = ps->performance_levels[0].sclk; 816 } 817 818 if (rps->vce_active) { 819 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 820 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 821 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 822 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 823 } 824 825 ps->performance_levels[0].sclk = sclk; 826 ps->performance_levels[0].mclk = mclk; 827 828 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) 829 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; 830 831 if (disable_mclk_switching) { 832 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk) 833 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk; 834 } else { 835 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk) 836 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk; 837 } 838 } 839 840 static int ci_thermal_set_temperature_range(struct radeon_device *rdev, 841 int min_temp, int max_temp) 842 { 843 int low_temp = 0 * 1000; 844 int high_temp = 255 * 1000; 845 u32 tmp; 846 847 if (low_temp < min_temp) 848 low_temp = min_temp; 849 if (high_temp > max_temp) 850 high_temp = max_temp; 851 if (high_temp < low_temp) { 852 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 853 return -EINVAL; 854 } 855 856 tmp = RREG32_SMC(CG_THERMAL_INT); 857 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK); 858 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) | 859 CI_DIG_THERM_INTL(low_temp / 1000); 860 WREG32_SMC(CG_THERMAL_INT, tmp); 861 862 #if 0 863 /* XXX: need to figure out how to handle this properly */ 864 tmp = RREG32_SMC(CG_THERMAL_CTRL); 865 tmp &= DIG_THERM_DPM_MASK; 866 tmp |= DIG_THERM_DPM(high_temp / 1000); 867 WREG32_SMC(CG_THERMAL_CTRL, tmp); 868 #endif 869 870 rdev->pm.dpm.thermal.min_temp = low_temp; 871 rdev->pm.dpm.thermal.max_temp = high_temp; 872 873 return 0; 874 } 875 876 static int ci_thermal_enable_alert(struct radeon_device *rdev, 877 bool enable) 878 { 879 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT); 880 PPSMC_Result result; 881 882 if (enable) { 883 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 884 WREG32_SMC(CG_THERMAL_INT, thermal_int); 885 rdev->irq.dpm_thermal = false; 886 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable); 887 if (result != PPSMC_Result_OK) { 888 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 889 return -EINVAL; 890 } 891 } else { 892 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 893 WREG32_SMC(CG_THERMAL_INT, thermal_int); 894 rdev->irq.dpm_thermal = true; 895 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable); 896 if (result != PPSMC_Result_OK) { 897 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n"); 898 return -EINVAL; 899 } 900 } 901 902 return 0; 903 } 904 905 static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 906 { 907 struct ci_power_info *pi = ci_get_pi(rdev); 908 u32 tmp; 909 910 if (pi->fan_ctrl_is_in_default_mode) { 911 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 912 pi->fan_ctrl_default_mode = tmp; 913 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 914 pi->t_min = tmp; 915 pi->fan_ctrl_is_in_default_mode = false; 916 } 917 918 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; 919 tmp |= TMIN(0); 920 WREG32_SMC(CG_FDO_CTRL2, tmp); 921 922 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 923 tmp |= FDO_PWM_MODE(mode); 924 WREG32_SMC(CG_FDO_CTRL2, tmp); 925 } 926 927 static int ci_thermal_setup_fan_table(struct radeon_device *rdev) 928 { 929 struct ci_power_info *pi = ci_get_pi(rdev); 930 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; 931 u32 duty100; 932 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 933 u16 fdo_min, slope1, slope2; 934 u32 reference_clock, tmp; 935 int ret; 936 u64 tmp64; 937 938 if (!pi->fan_table_start) { 939 rdev->pm.dpm.fan.ucode_fan_control = false; 940 return 0; 941 } 942 943 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 944 945 if (duty100 == 0) { 946 rdev->pm.dpm.fan.ucode_fan_control = false; 947 return 0; 948 } 949 950 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 951 do_div(tmp64, 10000); 952 fdo_min = (u16)tmp64; 953 954 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 955 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 956 957 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 958 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 959 960 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 961 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 962 963 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 964 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 965 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 966 967 fan_table.Slope1 = cpu_to_be16(slope1); 968 fan_table.Slope2 = cpu_to_be16(slope2); 969 970 fan_table.FdoMin = cpu_to_be16(fdo_min); 971 972 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 973 974 fan_table.HystUp = cpu_to_be16(1); 975 976 fan_table.HystSlope = cpu_to_be16(1); 977 978 fan_table.TempRespLim = cpu_to_be16(5); 979 980 reference_clock = radeon_get_xclk(rdev); 981 982 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 983 reference_clock) / 1600); 984 985 fan_table.FdoMax = cpu_to_be16((u16)duty100); 986 987 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 988 fan_table.TempSrc = (uint8_t)tmp; 989 990 ret = ci_copy_bytes_to_smc(rdev, 991 pi->fan_table_start, 992 (u8 *)(&fan_table), 993 sizeof(fan_table), 994 pi->sram_end); 995 996 if (ret) { 997 DRM_ERROR("Failed to load fan table to the SMC."); 998 rdev->pm.dpm.fan.ucode_fan_control = false; 999 } 1000 1001 return 0; 1002 } 1003 1004 static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 1005 { 1006 struct ci_power_info *pi = ci_get_pi(rdev); 1007 PPSMC_Result ret; 1008 1009 if (pi->caps_od_fuzzy_fan_control_support) { 1010 ret = ci_send_msg_to_smc_with_parameter(rdev, 1011 PPSMC_StartFanControl, 1012 FAN_CONTROL_FUZZY); 1013 if (ret != PPSMC_Result_OK) 1014 return -EINVAL; 1015 ret = ci_send_msg_to_smc_with_parameter(rdev, 1016 PPSMC_MSG_SetFanPwmMax, 1017 rdev->pm.dpm.fan.default_max_fan_pwm); 1018 if (ret != PPSMC_Result_OK) 1019 return -EINVAL; 1020 } else { 1021 ret = ci_send_msg_to_smc_with_parameter(rdev, 1022 PPSMC_StartFanControl, 1023 FAN_CONTROL_TABLE); 1024 if (ret != PPSMC_Result_OK) 1025 return -EINVAL; 1026 } 1027 1028 pi->fan_is_controlled_by_smc = true; 1029 return 0; 1030 } 1031 1032 static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 1033 { 1034 PPSMC_Result ret; 1035 struct ci_power_info *pi = ci_get_pi(rdev); 1036 1037 ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl); 1038 if (ret == PPSMC_Result_OK) { 1039 pi->fan_is_controlled_by_smc = false; 1040 return 0; 1041 } else 1042 return -EINVAL; 1043 } 1044 1045 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 1046 u32 *speed) 1047 { 1048 u32 duty, duty100; 1049 u64 tmp64; 1050 1051 if (rdev->pm.no_fan) 1052 return -ENOENT; 1053 1054 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 1055 duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 1056 1057 if (duty100 == 0) 1058 return -EINVAL; 1059 1060 tmp64 = (u64)duty * 100; 1061 do_div(tmp64, duty100); 1062 *speed = (u32)tmp64; 1063 1064 if (*speed > 100) 1065 *speed = 100; 1066 1067 return 0; 1068 } 1069 1070 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 1071 u32 speed) 1072 { 1073 u32 tmp; 1074 u32 duty, duty100; 1075 u64 tmp64; 1076 struct ci_power_info *pi = ci_get_pi(rdev); 1077 1078 if (rdev->pm.no_fan) 1079 return -ENOENT; 1080 1081 if (pi->fan_is_controlled_by_smc) 1082 return -EINVAL; 1083 1084 if (speed > 100) 1085 return -EINVAL; 1086 1087 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 1088 1089 if (duty100 == 0) 1090 return -EINVAL; 1091 1092 tmp64 = (u64)speed * duty100; 1093 do_div(tmp64, 100); 1094 duty = (u32)tmp64; 1095 1096 tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 1097 tmp |= FDO_STATIC_DUTY(duty); 1098 WREG32_SMC(CG_FDO_CTRL0, tmp); 1099 1100 return 0; 1101 } 1102 1103 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 1104 { 1105 if (mode) { 1106 /* stop auto-manage */ 1107 if (rdev->pm.dpm.fan.ucode_fan_control) 1108 ci_fan_ctrl_stop_smc_fan_control(rdev); 1109 ci_fan_ctrl_set_static_mode(rdev, mode); 1110 } else { 1111 /* restart auto-manage */ 1112 if (rdev->pm.dpm.fan.ucode_fan_control) 1113 ci_thermal_start_smc_fan_control(rdev); 1114 else 1115 ci_fan_ctrl_set_default_mode(rdev); 1116 } 1117 } 1118 1119 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev) 1120 { 1121 struct ci_power_info *pi = ci_get_pi(rdev); 1122 u32 tmp; 1123 1124 if (pi->fan_is_controlled_by_smc) 1125 return 0; 1126 1127 tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 1128 return (tmp >> FDO_PWM_MODE_SHIFT); 1129 } 1130 1131 #if 0 1132 static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 1133 u32 *speed) 1134 { 1135 u32 tach_period; 1136 u32 xclk = radeon_get_xclk(rdev); 1137 1138 if (rdev->pm.no_fan) 1139 return -ENOENT; 1140 1141 if (rdev->pm.fan_pulses_per_revolution == 0) 1142 return -ENOENT; 1143 1144 tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 1145 if (tach_period == 0) 1146 return -ENOENT; 1147 1148 *speed = 60 * xclk * 10000 / tach_period; 1149 1150 return 0; 1151 } 1152 1153 static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 1154 u32 speed) 1155 { 1156 u32 tach_period, tmp; 1157 u32 xclk = radeon_get_xclk(rdev); 1158 1159 if (rdev->pm.no_fan) 1160 return -ENOENT; 1161 1162 if (rdev->pm.fan_pulses_per_revolution == 0) 1163 return -ENOENT; 1164 1165 if ((speed < rdev->pm.fan_min_rpm) || 1166 (speed > rdev->pm.fan_max_rpm)) 1167 return -EINVAL; 1168 1169 if (rdev->pm.dpm.fan.ucode_fan_control) 1170 ci_fan_ctrl_stop_smc_fan_control(rdev); 1171 1172 tach_period = 60 * xclk * 10000 / (8 * speed); 1173 tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 1174 tmp |= TARGET_PERIOD(tach_period); 1175 WREG32_SMC(CG_TACH_CTRL, tmp); 1176 1177 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 1178 1179 return 0; 1180 } 1181 #endif 1182 1183 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev) 1184 { 1185 struct ci_power_info *pi = ci_get_pi(rdev); 1186 u32 tmp; 1187 1188 if (!pi->fan_ctrl_is_in_default_mode) { 1189 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 1190 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); 1191 WREG32_SMC(CG_FDO_CTRL2, tmp); 1192 1193 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; 1194 tmp |= TMIN(pi->t_min); 1195 WREG32_SMC(CG_FDO_CTRL2, tmp); 1196 pi->fan_ctrl_is_in_default_mode = true; 1197 } 1198 } 1199 1200 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev) 1201 { 1202 if (rdev->pm.dpm.fan.ucode_fan_control) { 1203 ci_fan_ctrl_start_smc_fan_control(rdev); 1204 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 1205 } 1206 } 1207 1208 static void ci_thermal_initialize(struct radeon_device *rdev) 1209 { 1210 u32 tmp; 1211 1212 if (rdev->pm.fan_pulses_per_revolution) { 1213 tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 1214 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution - 1); 1215 WREG32_SMC(CG_TACH_CTRL, tmp); 1216 } 1217 1218 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 1219 tmp |= TACH_PWM_RESP_RATE(0x28); 1220 WREG32_SMC(CG_FDO_CTRL2, tmp); 1221 } 1222 1223 static int ci_thermal_start_thermal_controller(struct radeon_device *rdev) 1224 { 1225 int ret; 1226 1227 ci_thermal_initialize(rdev); 1228 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 1229 if (ret) 1230 return ret; 1231 ret = ci_thermal_enable_alert(rdev, true); 1232 if (ret) 1233 return ret; 1234 if (rdev->pm.dpm.fan.ucode_fan_control) { 1235 ret = ci_thermal_setup_fan_table(rdev); 1236 if (ret) 1237 return ret; 1238 ci_thermal_start_smc_fan_control(rdev); 1239 } 1240 1241 return 0; 1242 } 1243 1244 static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev) 1245 { 1246 if (!rdev->pm.no_fan) 1247 ci_fan_ctrl_set_default_mode(rdev); 1248 } 1249 1250 #if 0 1251 static int ci_read_smc_soft_register(struct radeon_device *rdev, 1252 u16 reg_offset, u32 *value) 1253 { 1254 struct ci_power_info *pi = ci_get_pi(rdev); 1255 1256 return ci_read_smc_sram_dword(rdev, 1257 pi->soft_regs_start + reg_offset, 1258 value, pi->sram_end); 1259 } 1260 #endif 1261 1262 static int ci_write_smc_soft_register(struct radeon_device *rdev, 1263 u16 reg_offset, u32 value) 1264 { 1265 struct ci_power_info *pi = ci_get_pi(rdev); 1266 1267 return ci_write_smc_sram_dword(rdev, 1268 pi->soft_regs_start + reg_offset, 1269 value, pi->sram_end); 1270 } 1271 1272 static void ci_init_fps_limits(struct radeon_device *rdev) 1273 { 1274 struct ci_power_info *pi = ci_get_pi(rdev); 1275 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; 1276 1277 if (pi->caps_fps) { 1278 u16 tmp; 1279 1280 tmp = 45; 1281 table->FpsHighT = cpu_to_be16(tmp); 1282 1283 tmp = 30; 1284 table->FpsLowT = cpu_to_be16(tmp); 1285 } 1286 } 1287 1288 static int ci_update_sclk_t(struct radeon_device *rdev) 1289 { 1290 struct ci_power_info *pi = ci_get_pi(rdev); 1291 int ret = 0; 1292 u32 low_sclk_interrupt_t = 0; 1293 1294 if (pi->caps_sclk_throttle_low_notification) { 1295 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); 1296 1297 ret = ci_copy_bytes_to_smc(rdev, 1298 pi->dpm_table_start + 1299 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT), 1300 (u8 *)&low_sclk_interrupt_t, 1301 sizeof(u32), pi->sram_end); 1302 1303 } 1304 1305 return ret; 1306 } 1307 1308 static void ci_get_leakage_voltages(struct radeon_device *rdev) 1309 { 1310 struct ci_power_info *pi = ci_get_pi(rdev); 1311 u16 leakage_id, virtual_voltage_id; 1312 u16 vddc, vddci; 1313 int i; 1314 1315 pi->vddc_leakage.count = 0; 1316 pi->vddci_leakage.count = 0; 1317 1318 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { 1319 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { 1320 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 1321 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0) 1322 continue; 1323 if (vddc != 0 && vddc != virtual_voltage_id) { 1324 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; 1325 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; 1326 pi->vddc_leakage.count++; 1327 } 1328 } 1329 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) { 1330 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { 1331 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 1332 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci, 1333 virtual_voltage_id, 1334 leakage_id) == 0) { 1335 if (vddc != 0 && vddc != virtual_voltage_id) { 1336 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; 1337 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; 1338 pi->vddc_leakage.count++; 1339 } 1340 if (vddci != 0 && vddci != virtual_voltage_id) { 1341 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; 1342 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; 1343 pi->vddci_leakage.count++; 1344 } 1345 } 1346 } 1347 } 1348 } 1349 1350 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 1351 { 1352 struct ci_power_info *pi = ci_get_pi(rdev); 1353 bool want_thermal_protection; 1354 u32 tmp; 1355 1356 switch (sources) { 1357 case 0: 1358 default: 1359 want_thermal_protection = false; 1360 break; 1361 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 1362 want_thermal_protection = true; 1363 break; 1364 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 1365 want_thermal_protection = true; 1366 break; 1367 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 1368 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 1369 want_thermal_protection = true; 1370 break; 1371 } 1372 1373 if (want_thermal_protection) { 1374 tmp = RREG32_SMC(GENERAL_PWRMGT); 1375 if (pi->thermal_protection) 1376 tmp &= ~THERMAL_PROTECTION_DIS; 1377 else 1378 tmp |= THERMAL_PROTECTION_DIS; 1379 WREG32_SMC(GENERAL_PWRMGT, tmp); 1380 } else { 1381 tmp = RREG32_SMC(GENERAL_PWRMGT); 1382 tmp |= THERMAL_PROTECTION_DIS; 1383 WREG32_SMC(GENERAL_PWRMGT, tmp); 1384 } 1385 } 1386 1387 static void ci_enable_auto_throttle_source(struct radeon_device *rdev, 1388 enum radeon_dpm_auto_throttle_src source, 1389 bool enable) 1390 { 1391 struct ci_power_info *pi = ci_get_pi(rdev); 1392 1393 if (enable) { 1394 if (!(pi->active_auto_throttle_sources & (1 << source))) { 1395 pi->active_auto_throttle_sources |= 1 << source; 1396 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 1397 } 1398 } else { 1399 if (pi->active_auto_throttle_sources & (1 << source)) { 1400 pi->active_auto_throttle_sources &= ~(1 << source); 1401 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 1402 } 1403 } 1404 } 1405 1406 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev) 1407 { 1408 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) 1409 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt); 1410 } 1411 1412 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev) 1413 { 1414 struct ci_power_info *pi = ci_get_pi(rdev); 1415 PPSMC_Result smc_result; 1416 1417 if (!pi->need_update_smu7_dpm_table) 1418 return 0; 1419 1420 if ((!pi->sclk_dpm_key_disabled) && 1421 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 1422 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel); 1423 if (smc_result != PPSMC_Result_OK) 1424 return -EINVAL; 1425 } 1426 1427 if ((!pi->mclk_dpm_key_disabled) && 1428 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 1429 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel); 1430 if (smc_result != PPSMC_Result_OK) 1431 return -EINVAL; 1432 } 1433 1434 pi->need_update_smu7_dpm_table = 0; 1435 return 0; 1436 } 1437 1438 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable) 1439 { 1440 struct ci_power_info *pi = ci_get_pi(rdev); 1441 PPSMC_Result smc_result; 1442 1443 if (enable) { 1444 if (!pi->sclk_dpm_key_disabled) { 1445 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable); 1446 if (smc_result != PPSMC_Result_OK) 1447 return -EINVAL; 1448 } 1449 1450 if (!pi->mclk_dpm_key_disabled) { 1451 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable); 1452 if (smc_result != PPSMC_Result_OK) 1453 return -EINVAL; 1454 1455 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN); 1456 1457 WREG32_SMC(LCAC_MC0_CNTL, 0x05); 1458 WREG32_SMC(LCAC_MC1_CNTL, 0x05); 1459 WREG32_SMC(LCAC_CPL_CNTL, 0x100005); 1460 1461 udelay(10); 1462 1463 WREG32_SMC(LCAC_MC0_CNTL, 0x400005); 1464 WREG32_SMC(LCAC_MC1_CNTL, 0x400005); 1465 WREG32_SMC(LCAC_CPL_CNTL, 0x500005); 1466 } 1467 } else { 1468 if (!pi->sclk_dpm_key_disabled) { 1469 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable); 1470 if (smc_result != PPSMC_Result_OK) 1471 return -EINVAL; 1472 } 1473 1474 if (!pi->mclk_dpm_key_disabled) { 1475 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable); 1476 if (smc_result != PPSMC_Result_OK) 1477 return -EINVAL; 1478 } 1479 } 1480 1481 return 0; 1482 } 1483 1484 static int ci_start_dpm(struct radeon_device *rdev) 1485 { 1486 struct ci_power_info *pi = ci_get_pi(rdev); 1487 PPSMC_Result smc_result; 1488 int ret; 1489 u32 tmp; 1490 1491 tmp = RREG32_SMC(GENERAL_PWRMGT); 1492 tmp |= GLOBAL_PWRMGT_EN; 1493 WREG32_SMC(GENERAL_PWRMGT, tmp); 1494 1495 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1496 tmp |= DYNAMIC_PM_EN; 1497 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1498 1499 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000); 1500 1501 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN); 1502 1503 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable); 1504 if (smc_result != PPSMC_Result_OK) 1505 return -EINVAL; 1506 1507 ret = ci_enable_sclk_mclk_dpm(rdev, true); 1508 if (ret) 1509 return ret; 1510 1511 if (!pi->pcie_dpm_key_disabled) { 1512 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable); 1513 if (smc_result != PPSMC_Result_OK) 1514 return -EINVAL; 1515 } 1516 1517 return 0; 1518 } 1519 1520 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev) 1521 { 1522 struct ci_power_info *pi = ci_get_pi(rdev); 1523 PPSMC_Result smc_result; 1524 1525 if (!pi->need_update_smu7_dpm_table) 1526 return 0; 1527 1528 if ((!pi->sclk_dpm_key_disabled) && 1529 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 1530 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel); 1531 if (smc_result != PPSMC_Result_OK) 1532 return -EINVAL; 1533 } 1534 1535 if ((!pi->mclk_dpm_key_disabled) && 1536 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 1537 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel); 1538 if (smc_result != PPSMC_Result_OK) 1539 return -EINVAL; 1540 } 1541 1542 return 0; 1543 } 1544 1545 static int ci_stop_dpm(struct radeon_device *rdev) 1546 { 1547 struct ci_power_info *pi = ci_get_pi(rdev); 1548 PPSMC_Result smc_result; 1549 int ret; 1550 u32 tmp; 1551 1552 tmp = RREG32_SMC(GENERAL_PWRMGT); 1553 tmp &= ~GLOBAL_PWRMGT_EN; 1554 WREG32_SMC(GENERAL_PWRMGT, tmp); 1555 1556 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1557 tmp &= ~DYNAMIC_PM_EN; 1558 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1559 1560 if (!pi->pcie_dpm_key_disabled) { 1561 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable); 1562 if (smc_result != PPSMC_Result_OK) 1563 return -EINVAL; 1564 } 1565 1566 ret = ci_enable_sclk_mclk_dpm(rdev, false); 1567 if (ret) 1568 return ret; 1569 1570 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable); 1571 if (smc_result != PPSMC_Result_OK) 1572 return -EINVAL; 1573 1574 return 0; 1575 } 1576 1577 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable) 1578 { 1579 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1580 1581 if (enable) 1582 tmp &= ~SCLK_PWRMGT_OFF; 1583 else 1584 tmp |= SCLK_PWRMGT_OFF; 1585 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1586 } 1587 1588 #if 0 1589 static int ci_notify_hw_of_power_source(struct radeon_device *rdev, 1590 bool ac_power) 1591 { 1592 struct ci_power_info *pi = ci_get_pi(rdev); 1593 struct radeon_cac_tdp_table *cac_tdp_table = 1594 rdev->pm.dpm.dyn_state.cac_tdp_table; 1595 u32 power_limit; 1596 1597 if (ac_power) 1598 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); 1599 else 1600 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256); 1601 1602 ci_set_power_limit(rdev, power_limit); 1603 1604 if (pi->caps_automatic_dc_transition) { 1605 if (ac_power) 1606 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC); 1607 else 1608 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp); 1609 } 1610 1611 return 0; 1612 } 1613 #endif 1614 1615 static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg) 1616 { 1617 u32 tmp; 1618 int i; 1619 1620 if (!ci_is_smc_running(rdev)) 1621 return PPSMC_Result_Failed; 1622 1623 WREG32(SMC_MESSAGE_0, msg); 1624 1625 for (i = 0; i < rdev->usec_timeout; i++) { 1626 tmp = RREG32(SMC_RESP_0); 1627 if (tmp != 0) 1628 break; 1629 udelay(1); 1630 } 1631 tmp = RREG32(SMC_RESP_0); 1632 1633 return (PPSMC_Result)tmp; 1634 } 1635 1636 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 1637 PPSMC_Msg msg, u32 parameter) 1638 { 1639 WREG32(SMC_MSG_ARG_0, parameter); 1640 return ci_send_msg_to_smc(rdev, msg); 1641 } 1642 1643 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev, 1644 PPSMC_Msg msg, u32 *parameter) 1645 { 1646 PPSMC_Result smc_result; 1647 1648 smc_result = ci_send_msg_to_smc(rdev, msg); 1649 1650 if ((smc_result == PPSMC_Result_OK) && parameter) 1651 *parameter = RREG32(SMC_MSG_ARG_0); 1652 1653 return smc_result; 1654 } 1655 1656 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n) 1657 { 1658 struct ci_power_info *pi = ci_get_pi(rdev); 1659 1660 if (!pi->sclk_dpm_key_disabled) { 1661 PPSMC_Result smc_result = 1662 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n); 1663 if (smc_result != PPSMC_Result_OK) 1664 return -EINVAL; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n) 1671 { 1672 struct ci_power_info *pi = ci_get_pi(rdev); 1673 1674 if (!pi->mclk_dpm_key_disabled) { 1675 PPSMC_Result smc_result = 1676 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n); 1677 if (smc_result != PPSMC_Result_OK) 1678 return -EINVAL; 1679 } 1680 1681 return 0; 1682 } 1683 1684 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n) 1685 { 1686 struct ci_power_info *pi = ci_get_pi(rdev); 1687 1688 if (!pi->pcie_dpm_key_disabled) { 1689 PPSMC_Result smc_result = 1690 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n); 1691 if (smc_result != PPSMC_Result_OK) 1692 return -EINVAL; 1693 } 1694 1695 return 0; 1696 } 1697 1698 static int ci_set_power_limit(struct radeon_device *rdev, u32 n) 1699 { 1700 struct ci_power_info *pi = ci_get_pi(rdev); 1701 1702 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { 1703 PPSMC_Result smc_result = 1704 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n); 1705 if (smc_result != PPSMC_Result_OK) 1706 return -EINVAL; 1707 } 1708 1709 return 0; 1710 } 1711 1712 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, 1713 u32 target_tdp) 1714 { 1715 PPSMC_Result smc_result = 1716 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); 1717 if (smc_result != PPSMC_Result_OK) 1718 return -EINVAL; 1719 return 0; 1720 } 1721 1722 #if 0 1723 static int ci_set_boot_state(struct radeon_device *rdev) 1724 { 1725 return ci_enable_sclk_mclk_dpm(rdev, false); 1726 } 1727 #endif 1728 1729 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev) 1730 { 1731 u32 sclk_freq; 1732 PPSMC_Result smc_result = 1733 ci_send_msg_to_smc_return_parameter(rdev, 1734 PPSMC_MSG_API_GetSclkFrequency, 1735 &sclk_freq); 1736 if (smc_result != PPSMC_Result_OK) 1737 sclk_freq = 0; 1738 1739 return sclk_freq; 1740 } 1741 1742 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev) 1743 { 1744 u32 mclk_freq; 1745 PPSMC_Result smc_result = 1746 ci_send_msg_to_smc_return_parameter(rdev, 1747 PPSMC_MSG_API_GetMclkFrequency, 1748 &mclk_freq); 1749 if (smc_result != PPSMC_Result_OK) 1750 mclk_freq = 0; 1751 1752 return mclk_freq; 1753 } 1754 1755 static void ci_dpm_start_smc(struct radeon_device *rdev) 1756 { 1757 int i; 1758 1759 ci_program_jump_on_start(rdev); 1760 ci_start_smc_clock(rdev); 1761 ci_start_smc(rdev); 1762 for (i = 0; i < rdev->usec_timeout; i++) { 1763 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED) 1764 break; 1765 } 1766 } 1767 1768 static void ci_dpm_stop_smc(struct radeon_device *rdev) 1769 { 1770 ci_reset_smc(rdev); 1771 ci_stop_smc_clock(rdev); 1772 } 1773 1774 static int ci_process_firmware_header(struct radeon_device *rdev) 1775 { 1776 struct ci_power_info *pi = ci_get_pi(rdev); 1777 u32 tmp; 1778 int ret; 1779 1780 ret = ci_read_smc_sram_dword(rdev, 1781 SMU7_FIRMWARE_HEADER_LOCATION + 1782 offsetof(SMU7_Firmware_Header, DpmTable), 1783 &tmp, pi->sram_end); 1784 if (ret) 1785 return ret; 1786 1787 pi->dpm_table_start = tmp; 1788 1789 ret = ci_read_smc_sram_dword(rdev, 1790 SMU7_FIRMWARE_HEADER_LOCATION + 1791 offsetof(SMU7_Firmware_Header, SoftRegisters), 1792 &tmp, pi->sram_end); 1793 if (ret) 1794 return ret; 1795 1796 pi->soft_regs_start = tmp; 1797 1798 ret = ci_read_smc_sram_dword(rdev, 1799 SMU7_FIRMWARE_HEADER_LOCATION + 1800 offsetof(SMU7_Firmware_Header, mcRegisterTable), 1801 &tmp, pi->sram_end); 1802 if (ret) 1803 return ret; 1804 1805 pi->mc_reg_table_start = tmp; 1806 1807 ret = ci_read_smc_sram_dword(rdev, 1808 SMU7_FIRMWARE_HEADER_LOCATION + 1809 offsetof(SMU7_Firmware_Header, FanTable), 1810 &tmp, pi->sram_end); 1811 if (ret) 1812 return ret; 1813 1814 pi->fan_table_start = tmp; 1815 1816 ret = ci_read_smc_sram_dword(rdev, 1817 SMU7_FIRMWARE_HEADER_LOCATION + 1818 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable), 1819 &tmp, pi->sram_end); 1820 if (ret) 1821 return ret; 1822 1823 pi->arb_table_start = tmp; 1824 1825 return 0; 1826 } 1827 1828 static void ci_read_clock_registers(struct radeon_device *rdev) 1829 { 1830 struct ci_power_info *pi = ci_get_pi(rdev); 1831 1832 pi->clock_registers.cg_spll_func_cntl = 1833 RREG32_SMC(CG_SPLL_FUNC_CNTL); 1834 pi->clock_registers.cg_spll_func_cntl_2 = 1835 RREG32_SMC(CG_SPLL_FUNC_CNTL_2); 1836 pi->clock_registers.cg_spll_func_cntl_3 = 1837 RREG32_SMC(CG_SPLL_FUNC_CNTL_3); 1838 pi->clock_registers.cg_spll_func_cntl_4 = 1839 RREG32_SMC(CG_SPLL_FUNC_CNTL_4); 1840 pi->clock_registers.cg_spll_spread_spectrum = 1841 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); 1842 pi->clock_registers.cg_spll_spread_spectrum_2 = 1843 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2); 1844 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 1845 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 1846 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 1847 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 1848 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 1849 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 1850 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 1851 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 1852 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 1853 } 1854 1855 static void ci_init_sclk_t(struct radeon_device *rdev) 1856 { 1857 struct ci_power_info *pi = ci_get_pi(rdev); 1858 1859 pi->low_sclk_interrupt_t = 0; 1860 } 1861 1862 static void ci_enable_thermal_protection(struct radeon_device *rdev, 1863 bool enable) 1864 { 1865 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 1866 1867 if (enable) 1868 tmp &= ~THERMAL_PROTECTION_DIS; 1869 else 1870 tmp |= THERMAL_PROTECTION_DIS; 1871 WREG32_SMC(GENERAL_PWRMGT, tmp); 1872 } 1873 1874 static void ci_enable_acpi_power_management(struct radeon_device *rdev) 1875 { 1876 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 1877 1878 tmp |= STATIC_PM_EN; 1879 1880 WREG32_SMC(GENERAL_PWRMGT, tmp); 1881 } 1882 1883 #if 0 1884 static int ci_enter_ulp_state(struct radeon_device *rdev) 1885 { 1886 1887 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 1888 1889 udelay(25000); 1890 1891 return 0; 1892 } 1893 1894 static int ci_exit_ulp_state(struct radeon_device *rdev) 1895 { 1896 int i; 1897 1898 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 1899 1900 udelay(7000); 1901 1902 for (i = 0; i < rdev->usec_timeout; i++) { 1903 if (RREG32(SMC_RESP_0) == 1) 1904 break; 1905 udelay(1000); 1906 } 1907 1908 return 0; 1909 } 1910 #endif 1911 1912 static int ci_notify_smc_display_change(struct radeon_device *rdev, 1913 bool has_display) 1914 { 1915 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 1916 1917 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL; 1918 } 1919 1920 static int ci_enable_ds_master_switch(struct radeon_device *rdev, 1921 bool enable) 1922 { 1923 struct ci_power_info *pi = ci_get_pi(rdev); 1924 1925 if (enable) { 1926 if (pi->caps_sclk_ds) { 1927 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK) 1928 return -EINVAL; 1929 } else { 1930 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) 1931 return -EINVAL; 1932 } 1933 } else { 1934 if (pi->caps_sclk_ds) { 1935 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) 1936 return -EINVAL; 1937 } 1938 } 1939 1940 return 0; 1941 } 1942 1943 static void ci_program_display_gap(struct radeon_device *rdev) 1944 { 1945 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); 1946 u32 pre_vbi_time_in_us; 1947 u32 frame_time_in_us; 1948 u32 ref_clock = rdev->clock.spll.reference_freq; 1949 u32 refresh_rate = r600_dpm_get_vrefresh(rdev); 1950 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 1951 1952 tmp &= ~DISP_GAP_MASK; 1953 if (rdev->pm.dpm.new_active_crtc_count > 0) 1954 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 1955 else 1956 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE); 1957 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); 1958 1959 if (refresh_rate == 0) 1960 refresh_rate = 60; 1961 if (vblank_time == 0xffffffff) 1962 vblank_time = 500; 1963 frame_time_in_us = 1000000 / refresh_rate; 1964 pre_vbi_time_in_us = 1965 frame_time_in_us - 200 - vblank_time; 1966 tmp = pre_vbi_time_in_us * (ref_clock / 100); 1967 1968 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp); 1969 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64); 1970 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); 1971 1972 1973 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1)); 1974 1975 } 1976 1977 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 1978 { 1979 struct ci_power_info *pi = ci_get_pi(rdev); 1980 u32 tmp; 1981 1982 if (enable) { 1983 if (pi->caps_sclk_ss_support) { 1984 tmp = RREG32_SMC(GENERAL_PWRMGT); 1985 tmp |= DYN_SPREAD_SPECTRUM_EN; 1986 WREG32_SMC(GENERAL_PWRMGT, tmp); 1987 } 1988 } else { 1989 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); 1990 tmp &= ~SSEN; 1991 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp); 1992 1993 tmp = RREG32_SMC(GENERAL_PWRMGT); 1994 tmp &= ~DYN_SPREAD_SPECTRUM_EN; 1995 WREG32_SMC(GENERAL_PWRMGT, tmp); 1996 } 1997 } 1998 1999 static void ci_program_sstp(struct radeon_device *rdev) 2000 { 2001 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 2002 } 2003 2004 static void ci_enable_display_gap(struct radeon_device *rdev) 2005 { 2006 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); 2007 2008 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK); 2009 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 2010 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK)); 2011 2012 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); 2013 } 2014 2015 static void ci_program_vc(struct radeon_device *rdev) 2016 { 2017 u32 tmp; 2018 2019 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 2020 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT); 2021 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 2022 2023 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0); 2024 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1); 2025 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2); 2026 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3); 2027 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4); 2028 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5); 2029 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6); 2030 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7); 2031 } 2032 2033 static void ci_clear_vc(struct radeon_device *rdev) 2034 { 2035 u32 tmp; 2036 2037 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 2038 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT); 2039 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 2040 2041 WREG32_SMC(CG_FTV_0, 0); 2042 WREG32_SMC(CG_FTV_1, 0); 2043 WREG32_SMC(CG_FTV_2, 0); 2044 WREG32_SMC(CG_FTV_3, 0); 2045 WREG32_SMC(CG_FTV_4, 0); 2046 WREG32_SMC(CG_FTV_5, 0); 2047 WREG32_SMC(CG_FTV_6, 0); 2048 WREG32_SMC(CG_FTV_7, 0); 2049 } 2050 2051 static int ci_upload_firmware(struct radeon_device *rdev) 2052 { 2053 struct ci_power_info *pi = ci_get_pi(rdev); 2054 int i; 2055 2056 for (i = 0; i < rdev->usec_timeout; i++) { 2057 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE) 2058 break; 2059 } 2060 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1); 2061 2062 ci_stop_smc_clock(rdev); 2063 ci_reset_smc(rdev); 2064 2065 return ci_load_smc_ucode(rdev, pi->sram_end); 2066 2067 } 2068 2069 static int ci_get_svi2_voltage_table(struct radeon_device *rdev, 2070 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 2071 struct atom_voltage_table *voltage_table) 2072 { 2073 u32 i; 2074 2075 if (voltage_dependency_table == NULL) 2076 return -EINVAL; 2077 2078 voltage_table->mask_low = 0; 2079 voltage_table->phase_delay = 0; 2080 2081 voltage_table->count = voltage_dependency_table->count; 2082 for (i = 0; i < voltage_table->count; i++) { 2083 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 2084 voltage_table->entries[i].smio_low = 0; 2085 } 2086 2087 return 0; 2088 } 2089 2090 static int ci_construct_voltage_tables(struct radeon_device *rdev) 2091 { 2092 struct ci_power_info *pi = ci_get_pi(rdev); 2093 int ret; 2094 2095 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 2096 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 2097 VOLTAGE_OBJ_GPIO_LUT, 2098 &pi->vddc_voltage_table); 2099 if (ret) 2100 return ret; 2101 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 2102 ret = ci_get_svi2_voltage_table(rdev, 2103 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2104 &pi->vddc_voltage_table); 2105 if (ret) 2106 return ret; 2107 } 2108 2109 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) 2110 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC, 2111 &pi->vddc_voltage_table); 2112 2113 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 2114 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 2115 VOLTAGE_OBJ_GPIO_LUT, 2116 &pi->vddci_voltage_table); 2117 if (ret) 2118 return ret; 2119 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 2120 ret = ci_get_svi2_voltage_table(rdev, 2121 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2122 &pi->vddci_voltage_table); 2123 if (ret) 2124 return ret; 2125 } 2126 2127 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) 2128 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI, 2129 &pi->vddci_voltage_table); 2130 2131 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 2132 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 2133 VOLTAGE_OBJ_GPIO_LUT, 2134 &pi->mvdd_voltage_table); 2135 if (ret) 2136 return ret; 2137 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 2138 ret = ci_get_svi2_voltage_table(rdev, 2139 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, 2140 &pi->mvdd_voltage_table); 2141 if (ret) 2142 return ret; 2143 } 2144 2145 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) 2146 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD, 2147 &pi->mvdd_voltage_table); 2148 2149 return 0; 2150 } 2151 2152 static void ci_populate_smc_voltage_table(struct radeon_device *rdev, 2153 struct atom_voltage_table_entry *voltage_table, 2154 SMU7_Discrete_VoltageLevel *smc_voltage_table) 2155 { 2156 int ret; 2157 2158 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table, 2159 &smc_voltage_table->StdVoltageHiSidd, 2160 &smc_voltage_table->StdVoltageLoSidd); 2161 2162 if (ret) { 2163 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE; 2164 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE; 2165 } 2166 2167 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE); 2168 smc_voltage_table->StdVoltageHiSidd = 2169 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd); 2170 smc_voltage_table->StdVoltageLoSidd = 2171 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd); 2172 } 2173 2174 static int ci_populate_smc_vddc_table(struct radeon_device *rdev, 2175 SMU7_Discrete_DpmTable *table) 2176 { 2177 struct ci_power_info *pi = ci_get_pi(rdev); 2178 unsigned int count; 2179 2180 table->VddcLevelCount = pi->vddc_voltage_table.count; 2181 for (count = 0; count < table->VddcLevelCount; count++) { 2182 ci_populate_smc_voltage_table(rdev, 2183 &pi->vddc_voltage_table.entries[count], 2184 &table->VddcLevel[count]); 2185 2186 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 2187 table->VddcLevel[count].Smio |= 2188 pi->vddc_voltage_table.entries[count].smio_low; 2189 else 2190 table->VddcLevel[count].Smio = 0; 2191 } 2192 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); 2193 2194 return 0; 2195 } 2196 2197 static int ci_populate_smc_vddci_table(struct radeon_device *rdev, 2198 SMU7_Discrete_DpmTable *table) 2199 { 2200 unsigned int count; 2201 struct ci_power_info *pi = ci_get_pi(rdev); 2202 2203 table->VddciLevelCount = pi->vddci_voltage_table.count; 2204 for (count = 0; count < table->VddciLevelCount; count++) { 2205 ci_populate_smc_voltage_table(rdev, 2206 &pi->vddci_voltage_table.entries[count], 2207 &table->VddciLevel[count]); 2208 2209 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 2210 table->VddciLevel[count].Smio |= 2211 pi->vddci_voltage_table.entries[count].smio_low; 2212 else 2213 table->VddciLevel[count].Smio = 0; 2214 } 2215 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); 2216 2217 return 0; 2218 } 2219 2220 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev, 2221 SMU7_Discrete_DpmTable *table) 2222 { 2223 struct ci_power_info *pi = ci_get_pi(rdev); 2224 unsigned int count; 2225 2226 table->MvddLevelCount = pi->mvdd_voltage_table.count; 2227 for (count = 0; count < table->MvddLevelCount; count++) { 2228 ci_populate_smc_voltage_table(rdev, 2229 &pi->mvdd_voltage_table.entries[count], 2230 &table->MvddLevel[count]); 2231 2232 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 2233 table->MvddLevel[count].Smio |= 2234 pi->mvdd_voltage_table.entries[count].smio_low; 2235 else 2236 table->MvddLevel[count].Smio = 0; 2237 } 2238 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); 2239 2240 return 0; 2241 } 2242 2243 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev, 2244 SMU7_Discrete_DpmTable *table) 2245 { 2246 int ret; 2247 2248 ret = ci_populate_smc_vddc_table(rdev, table); 2249 if (ret) 2250 return ret; 2251 2252 ret = ci_populate_smc_vddci_table(rdev, table); 2253 if (ret) 2254 return ret; 2255 2256 ret = ci_populate_smc_mvdd_table(rdev, table); 2257 if (ret) 2258 return ret; 2259 2260 return 0; 2261 } 2262 2263 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 2264 SMU7_Discrete_VoltageLevel *voltage) 2265 { 2266 struct ci_power_info *pi = ci_get_pi(rdev); 2267 u32 i = 0; 2268 2269 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 2270 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { 2271 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { 2272 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; 2273 break; 2274 } 2275 } 2276 2277 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) 2278 return -EINVAL; 2279 } 2280 2281 return -EINVAL; 2282 } 2283 2284 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, 2285 struct atom_voltage_table_entry *voltage_table, 2286 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd) 2287 { 2288 u16 v_index, idx; 2289 bool voltage_found = false; 2290 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE; 2291 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE; 2292 2293 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 2294 return -EINVAL; 2295 2296 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 2297 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 2298 if (voltage_table->value == 2299 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 2300 voltage_found = true; 2301 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 2302 idx = v_index; 2303 else 2304 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; 2305 *std_voltage_lo_sidd = 2306 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; 2307 *std_voltage_hi_sidd = 2308 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; 2309 break; 2310 } 2311 } 2312 2313 if (!voltage_found) { 2314 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 2315 if (voltage_table->value <= 2316 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 2317 voltage_found = true; 2318 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 2319 idx = v_index; 2320 else 2321 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; 2322 *std_voltage_lo_sidd = 2323 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; 2324 *std_voltage_hi_sidd = 2325 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; 2326 break; 2327 } 2328 } 2329 } 2330 } 2331 2332 return 0; 2333 } 2334 2335 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev, 2336 const struct radeon_phase_shedding_limits_table *limits, 2337 u32 sclk, 2338 u32 *phase_shedding) 2339 { 2340 unsigned int i; 2341 2342 *phase_shedding = 1; 2343 2344 for (i = 0; i < limits->count; i++) { 2345 if (sclk < limits->entries[i].sclk) { 2346 *phase_shedding = i; 2347 break; 2348 } 2349 } 2350 } 2351 2352 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev, 2353 const struct radeon_phase_shedding_limits_table *limits, 2354 u32 mclk, 2355 u32 *phase_shedding) 2356 { 2357 unsigned int i; 2358 2359 *phase_shedding = 1; 2360 2361 for (i = 0; i < limits->count; i++) { 2362 if (mclk < limits->entries[i].mclk) { 2363 *phase_shedding = i; 2364 break; 2365 } 2366 } 2367 } 2368 2369 static int ci_init_arb_table_index(struct radeon_device *rdev) 2370 { 2371 struct ci_power_info *pi = ci_get_pi(rdev); 2372 u32 tmp; 2373 int ret; 2374 2375 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, 2376 &tmp, pi->sram_end); 2377 if (ret) 2378 return ret; 2379 2380 tmp &= 0x00FFFFFF; 2381 tmp |= MC_CG_ARB_FREQ_F1 << 24; 2382 2383 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, 2384 tmp, pi->sram_end); 2385 } 2386 2387 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev, 2388 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table, 2389 u32 clock, u32 *voltage) 2390 { 2391 u32 i = 0; 2392 2393 if (allowed_clock_voltage_table->count == 0) 2394 return -EINVAL; 2395 2396 for (i = 0; i < allowed_clock_voltage_table->count; i++) { 2397 if (allowed_clock_voltage_table->entries[i].clk >= clock) { 2398 *voltage = allowed_clock_voltage_table->entries[i].v; 2399 return 0; 2400 } 2401 } 2402 2403 *voltage = allowed_clock_voltage_table->entries[i-1].v; 2404 2405 return 0; 2406 } 2407 2408 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev, 2409 u32 sclk, u32 min_sclk_in_sr) 2410 { 2411 u32 i; 2412 u32 tmp; 2413 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ? 2414 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK; 2415 2416 if (sclk < min) 2417 return 0; 2418 2419 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { 2420 tmp = sclk / (1 << i); 2421 if (tmp >= min || i == 0) 2422 break; 2423 } 2424 2425 return (u8)i; 2426 } 2427 2428 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 2429 { 2430 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 2431 } 2432 2433 static int ci_reset_to_default(struct radeon_device *rdev) 2434 { 2435 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 2436 0 : -EINVAL; 2437 } 2438 2439 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev) 2440 { 2441 u32 tmp; 2442 2443 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8; 2444 2445 if (tmp == MC_CG_ARB_FREQ_F0) 2446 return 0; 2447 2448 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 2449 } 2450 2451 static void ci_register_patching_mc_arb(struct radeon_device *rdev, 2452 const u32 engine_clock, 2453 const u32 memory_clock, 2454 u32 *dram_timimg2) 2455 { 2456 bool patch; 2457 u32 tmp, tmp2; 2458 2459 tmp = RREG32(MC_SEQ_MISC0); 2460 patch = (tmp & 0x0000f00) == 0x300; 2461 2462 if (patch && 2463 ((rdev->pdev->device == 0x67B0) || 2464 (rdev->pdev->device == 0x67B1)) && 2465 (rdev->pdev->revision == 0)) { 2466 if ((memory_clock > 100000) && (memory_clock <= 125000)) { 2467 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; 2468 *dram_timimg2 &= ~0x00ff0000; 2469 *dram_timimg2 |= tmp2 << 16; 2470 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { 2471 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff; 2472 *dram_timimg2 &= ~0x00ff0000; 2473 *dram_timimg2 |= tmp2 << 16; 2474 } 2475 } 2476 } 2477 2478 2479 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev, 2480 u32 sclk, 2481 u32 mclk, 2482 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs) 2483 { 2484 u32 dram_timing; 2485 u32 dram_timing2; 2486 u32 burst_time; 2487 2488 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk); 2489 2490 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 2491 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 2492 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 2493 2494 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2); 2495 2496 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing); 2497 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2); 2498 arb_regs->McArbBurstTime = (u8)burst_time; 2499 2500 return 0; 2501 } 2502 2503 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev) 2504 { 2505 struct ci_power_info *pi = ci_get_pi(rdev); 2506 SMU7_Discrete_MCArbDramTimingTable arb_regs; 2507 u32 i, j; 2508 int ret = 0; 2509 2510 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable)); 2511 2512 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { 2513 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { 2514 ret = ci_populate_memory_timing_parameters(rdev, 2515 pi->dpm_table.sclk_table.dpm_levels[i].value, 2516 pi->dpm_table.mclk_table.dpm_levels[j].value, 2517 &arb_regs.entries[i][j]); 2518 if (ret) 2519 break; 2520 } 2521 } 2522 2523 if (ret == 0) 2524 ret = ci_copy_bytes_to_smc(rdev, 2525 pi->arb_table_start, 2526 (u8 *)&arb_regs, 2527 sizeof(SMU7_Discrete_MCArbDramTimingTable), 2528 pi->sram_end); 2529 2530 return ret; 2531 } 2532 2533 static int ci_program_memory_timing_parameters(struct radeon_device *rdev) 2534 { 2535 struct ci_power_info *pi = ci_get_pi(rdev); 2536 2537 if (pi->need_update_smu7_dpm_table == 0) 2538 return 0; 2539 2540 return ci_do_program_memory_timing_parameters(rdev); 2541 } 2542 2543 static void ci_populate_smc_initial_state(struct radeon_device *rdev, 2544 struct radeon_ps *radeon_boot_state) 2545 { 2546 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state); 2547 struct ci_power_info *pi = ci_get_pi(rdev); 2548 u32 level = 0; 2549 2550 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { 2551 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= 2552 boot_state->performance_levels[0].sclk) { 2553 pi->smc_state_table.GraphicsBootLevel = level; 2554 break; 2555 } 2556 } 2557 2558 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { 2559 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= 2560 boot_state->performance_levels[0].mclk) { 2561 pi->smc_state_table.MemoryBootLevel = level; 2562 break; 2563 } 2564 } 2565 } 2566 2567 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) 2568 { 2569 u32 i; 2570 u32 mask_value = 0; 2571 2572 for (i = dpm_table->count; i > 0; i--) { 2573 mask_value = mask_value << 1; 2574 if (dpm_table->dpm_levels[i-1].enabled) 2575 mask_value |= 0x1; 2576 else 2577 mask_value &= 0xFFFFFFFE; 2578 } 2579 2580 return mask_value; 2581 } 2582 2583 static void ci_populate_smc_link_level(struct radeon_device *rdev, 2584 SMU7_Discrete_DpmTable *table) 2585 { 2586 struct ci_power_info *pi = ci_get_pi(rdev); 2587 struct ci_dpm_table *dpm_table = &pi->dpm_table; 2588 u32 i; 2589 2590 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { 2591 table->LinkLevel[i].PcieGenSpeed = 2592 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; 2593 table->LinkLevel[i].PcieLaneCount = 2594 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); 2595 table->LinkLevel[i].EnabledForActivity = 1; 2596 table->LinkLevel[i].DownT = cpu_to_be32(5); 2597 table->LinkLevel[i].UpT = cpu_to_be32(30); 2598 } 2599 2600 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; 2601 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = 2602 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); 2603 } 2604 2605 static int ci_populate_smc_uvd_level(struct radeon_device *rdev, 2606 SMU7_Discrete_DpmTable *table) 2607 { 2608 u32 count; 2609 struct atom_clock_dividers dividers; 2610 int ret = -EINVAL; 2611 2612 table->UvdLevelCount = 2613 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; 2614 2615 for (count = 0; count < table->UvdLevelCount; count++) { 2616 table->UvdLevel[count].VclkFrequency = 2617 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; 2618 table->UvdLevel[count].DclkFrequency = 2619 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; 2620 table->UvdLevel[count].MinVddc = 2621 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2622 table->UvdLevel[count].MinVddcPhases = 1; 2623 2624 ret = radeon_atom_get_clock_dividers(rdev, 2625 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2626 table->UvdLevel[count].VclkFrequency, false, ÷rs); 2627 if (ret) 2628 return ret; 2629 2630 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; 2631 2632 ret = radeon_atom_get_clock_dividers(rdev, 2633 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2634 table->UvdLevel[count].DclkFrequency, false, ÷rs); 2635 if (ret) 2636 return ret; 2637 2638 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; 2639 2640 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); 2641 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); 2642 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); 2643 } 2644 2645 return ret; 2646 } 2647 2648 static int ci_populate_smc_vce_level(struct radeon_device *rdev, 2649 SMU7_Discrete_DpmTable *table) 2650 { 2651 u32 count; 2652 struct atom_clock_dividers dividers; 2653 int ret = -EINVAL; 2654 2655 table->VceLevelCount = 2656 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; 2657 2658 for (count = 0; count < table->VceLevelCount; count++) { 2659 table->VceLevel[count].Frequency = 2660 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; 2661 table->VceLevel[count].MinVoltage = 2662 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2663 table->VceLevel[count].MinPhases = 1; 2664 2665 ret = radeon_atom_get_clock_dividers(rdev, 2666 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2667 table->VceLevel[count].Frequency, false, ÷rs); 2668 if (ret) 2669 return ret; 2670 2671 table->VceLevel[count].Divider = (u8)dividers.post_divider; 2672 2673 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); 2674 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); 2675 } 2676 2677 return ret; 2678 2679 } 2680 2681 static int ci_populate_smc_acp_level(struct radeon_device *rdev, 2682 SMU7_Discrete_DpmTable *table) 2683 { 2684 u32 count; 2685 struct atom_clock_dividers dividers; 2686 int ret = -EINVAL; 2687 2688 table->AcpLevelCount = (u8) 2689 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); 2690 2691 for (count = 0; count < table->AcpLevelCount; count++) { 2692 table->AcpLevel[count].Frequency = 2693 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; 2694 table->AcpLevel[count].MinVoltage = 2695 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; 2696 table->AcpLevel[count].MinPhases = 1; 2697 2698 ret = radeon_atom_get_clock_dividers(rdev, 2699 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2700 table->AcpLevel[count].Frequency, false, ÷rs); 2701 if (ret) 2702 return ret; 2703 2704 table->AcpLevel[count].Divider = (u8)dividers.post_divider; 2705 2706 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); 2707 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); 2708 } 2709 2710 return ret; 2711 } 2712 2713 static int ci_populate_smc_samu_level(struct radeon_device *rdev, 2714 SMU7_Discrete_DpmTable *table) 2715 { 2716 u32 count; 2717 struct atom_clock_dividers dividers; 2718 int ret = -EINVAL; 2719 2720 table->SamuLevelCount = 2721 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; 2722 2723 for (count = 0; count < table->SamuLevelCount; count++) { 2724 table->SamuLevel[count].Frequency = 2725 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; 2726 table->SamuLevel[count].MinVoltage = 2727 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2728 table->SamuLevel[count].MinPhases = 1; 2729 2730 ret = radeon_atom_get_clock_dividers(rdev, 2731 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2732 table->SamuLevel[count].Frequency, false, ÷rs); 2733 if (ret) 2734 return ret; 2735 2736 table->SamuLevel[count].Divider = (u8)dividers.post_divider; 2737 2738 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); 2739 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); 2740 } 2741 2742 return ret; 2743 } 2744 2745 static int ci_calculate_mclk_params(struct radeon_device *rdev, 2746 u32 memory_clock, 2747 SMU7_Discrete_MemoryLevel *mclk, 2748 bool strobe_mode, 2749 bool dll_state_on) 2750 { 2751 struct ci_power_info *pi = ci_get_pi(rdev); 2752 u32 dll_cntl = pi->clock_registers.dll_cntl; 2753 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; 2754 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; 2755 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; 2756 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; 2757 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; 2758 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; 2759 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; 2760 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; 2761 struct atom_mpll_param mpll_param; 2762 int ret; 2763 2764 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 2765 if (ret) 2766 return ret; 2767 2768 mpll_func_cntl &= ~BWCTRL_MASK; 2769 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 2770 2771 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 2772 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 2773 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 2774 2775 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 2776 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 2777 2778 if (pi->mem_gddr5) { 2779 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 2780 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 2781 YCLK_POST_DIV(mpll_param.post_div); 2782 } 2783 2784 if (pi->caps_mclk_ss_support) { 2785 struct radeon_atom_ss ss; 2786 u32 freq_nom; 2787 u32 tmp; 2788 u32 reference_clock = rdev->clock.mpll.reference_freq; 2789 2790 if (mpll_param.qdr == 1) 2791 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div); 2792 else 2793 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div); 2794 2795 tmp = (freq_nom / reference_clock); 2796 tmp = tmp * tmp; 2797 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 2798 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 2799 u32 clks = reference_clock * 5 / ss.rate; 2800 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 2801 2802 mpll_ss1 &= ~CLKV_MASK; 2803 mpll_ss1 |= CLKV(clkv); 2804 2805 mpll_ss2 &= ~CLKS_MASK; 2806 mpll_ss2 |= CLKS(clks); 2807 } 2808 } 2809 2810 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 2811 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 2812 2813 if (dll_state_on) 2814 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 2815 else 2816 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 2817 2818 mclk->MclkFrequency = memory_clock; 2819 mclk->MpllFuncCntl = mpll_func_cntl; 2820 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; 2821 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; 2822 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; 2823 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; 2824 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; 2825 mclk->DllCntl = dll_cntl; 2826 mclk->MpllSs1 = mpll_ss1; 2827 mclk->MpllSs2 = mpll_ss2; 2828 2829 return 0; 2830 } 2831 2832 static int ci_populate_single_memory_level(struct radeon_device *rdev, 2833 u32 memory_clock, 2834 SMU7_Discrete_MemoryLevel *memory_level) 2835 { 2836 struct ci_power_info *pi = ci_get_pi(rdev); 2837 int ret; 2838 bool dll_state_on; 2839 2840 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { 2841 ret = ci_get_dependency_volt_by_clk(rdev, 2842 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2843 memory_clock, &memory_level->MinVddc); 2844 if (ret) 2845 return ret; 2846 } 2847 2848 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { 2849 ret = ci_get_dependency_volt_by_clk(rdev, 2850 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2851 memory_clock, &memory_level->MinVddci); 2852 if (ret) 2853 return ret; 2854 } 2855 2856 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { 2857 ret = ci_get_dependency_volt_by_clk(rdev, 2858 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, 2859 memory_clock, &memory_level->MinMvdd); 2860 if (ret) 2861 return ret; 2862 } 2863 2864 memory_level->MinVddcPhases = 1; 2865 2866 if (pi->vddc_phase_shed_control) 2867 ci_populate_phase_value_based_on_mclk(rdev, 2868 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 2869 memory_clock, 2870 &memory_level->MinVddcPhases); 2871 2872 memory_level->EnabledForThrottle = 1; 2873 memory_level->UpH = 0; 2874 memory_level->DownH = 100; 2875 memory_level->VoltageDownH = 0; 2876 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; 2877 2878 memory_level->StutterEnable = false; 2879 memory_level->StrobeEnable = false; 2880 memory_level->EdcReadEnable = false; 2881 memory_level->EdcWriteEnable = false; 2882 memory_level->RttEnable = false; 2883 2884 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2885 2886 if (pi->mclk_stutter_mode_threshold && 2887 (memory_clock <= pi->mclk_stutter_mode_threshold) && 2888 (pi->uvd_enabled == false) && 2889 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 2890 (rdev->pm.dpm.new_active_crtc_count <= 2)) 2891 memory_level->StutterEnable = true; 2892 2893 if (pi->mclk_strobe_mode_threshold && 2894 (memory_clock <= pi->mclk_strobe_mode_threshold)) 2895 memory_level->StrobeEnable = 1; 2896 2897 if (pi->mem_gddr5) { 2898 memory_level->StrobeRatio = 2899 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); 2900 if (pi->mclk_edc_enable_threshold && 2901 (memory_clock > pi->mclk_edc_enable_threshold)) 2902 memory_level->EdcReadEnable = true; 2903 2904 if (pi->mclk_edc_wr_enable_threshold && 2905 (memory_clock > pi->mclk_edc_wr_enable_threshold)) 2906 memory_level->EdcWriteEnable = true; 2907 2908 if (memory_level->StrobeEnable) { 2909 if (si_get_mclk_frequency_ratio(memory_clock, true) >= 2910 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 2911 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 2912 else 2913 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 2914 } else { 2915 dll_state_on = pi->dll_default_on; 2916 } 2917 } else { 2918 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock); 2919 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 2920 } 2921 2922 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); 2923 if (ret) 2924 return ret; 2925 2926 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE); 2927 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); 2928 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); 2929 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); 2930 2931 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency); 2932 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel); 2933 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl); 2934 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1); 2935 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2); 2936 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl); 2937 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl); 2938 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl); 2939 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl); 2940 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1); 2941 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2); 2942 2943 return 0; 2944 } 2945 2946 static int ci_populate_smc_acpi_level(struct radeon_device *rdev, 2947 SMU7_Discrete_DpmTable *table) 2948 { 2949 struct ci_power_info *pi = ci_get_pi(rdev); 2950 struct atom_clock_dividers dividers; 2951 SMU7_Discrete_VoltageLevel voltage_level; 2952 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; 2953 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; 2954 u32 dll_cntl = pi->clock_registers.dll_cntl; 2955 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; 2956 int ret; 2957 2958 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 2959 2960 if (pi->acpi_vddc) 2961 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); 2962 else 2963 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); 2964 2965 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; 2966 2967 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; 2968 2969 ret = radeon_atom_get_clock_dividers(rdev, 2970 COMPUTE_GPUCLK_INPUT_FLAG_SCLK, 2971 table->ACPILevel.SclkFrequency, false, ÷rs); 2972 if (ret) 2973 return ret; 2974 2975 table->ACPILevel.SclkDid = (u8)dividers.post_divider; 2976 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2977 table->ACPILevel.DeepSleepDivId = 0; 2978 2979 spll_func_cntl &= ~SPLL_PWRON; 2980 spll_func_cntl |= SPLL_RESET; 2981 2982 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 2983 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 2984 2985 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; 2986 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; 2987 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; 2988 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; 2989 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; 2990 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; 2991 table->ACPILevel.CcPwrDynRm = 0; 2992 table->ACPILevel.CcPwrDynRm1 = 0; 2993 2994 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); 2995 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); 2996 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); 2997 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); 2998 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); 2999 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); 3000 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); 3001 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); 3002 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); 3003 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); 3004 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); 3005 3006 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; 3007 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; 3008 3009 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 3010 if (pi->acpi_vddci) 3011 table->MemoryACPILevel.MinVddci = 3012 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); 3013 else 3014 table->MemoryACPILevel.MinVddci = 3015 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); 3016 } 3017 3018 if (ci_populate_mvdd_value(rdev, 0, &voltage_level)) 3019 table->MemoryACPILevel.MinMvdd = 0; 3020 else 3021 table->MemoryACPILevel.MinMvdd = 3022 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE); 3023 3024 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 3025 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 3026 3027 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 3028 3029 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); 3030 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); 3031 table->MemoryACPILevel.MpllAdFuncCntl = 3032 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); 3033 table->MemoryACPILevel.MpllDqFuncCntl = 3034 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); 3035 table->MemoryACPILevel.MpllFuncCntl = 3036 cpu_to_be32(pi->clock_registers.mpll_func_cntl); 3037 table->MemoryACPILevel.MpllFuncCntl_1 = 3038 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); 3039 table->MemoryACPILevel.MpllFuncCntl_2 = 3040 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); 3041 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); 3042 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); 3043 3044 table->MemoryACPILevel.EnabledForThrottle = 0; 3045 table->MemoryACPILevel.EnabledForActivity = 0; 3046 table->MemoryACPILevel.UpH = 0; 3047 table->MemoryACPILevel.DownH = 100; 3048 table->MemoryACPILevel.VoltageDownH = 0; 3049 table->MemoryACPILevel.ActivityLevel = 3050 cpu_to_be16((u16)pi->mclk_activity_target); 3051 3052 table->MemoryACPILevel.StutterEnable = false; 3053 table->MemoryACPILevel.StrobeEnable = false; 3054 table->MemoryACPILevel.EdcReadEnable = false; 3055 table->MemoryACPILevel.EdcWriteEnable = false; 3056 table->MemoryACPILevel.RttEnable = false; 3057 3058 return 0; 3059 } 3060 3061 3062 static int ci_enable_ulv(struct radeon_device *rdev, bool enable) 3063 { 3064 struct ci_power_info *pi = ci_get_pi(rdev); 3065 struct ci_ulv_parm *ulv = &pi->ulv; 3066 3067 if (ulv->supported) { 3068 if (enable) 3069 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 3070 0 : -EINVAL; 3071 else 3072 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 3073 0 : -EINVAL; 3074 } 3075 3076 return 0; 3077 } 3078 3079 static int ci_populate_ulv_level(struct radeon_device *rdev, 3080 SMU7_Discrete_Ulv *state) 3081 { 3082 struct ci_power_info *pi = ci_get_pi(rdev); 3083 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time; 3084 3085 state->CcPwrDynRm = 0; 3086 state->CcPwrDynRm1 = 0; 3087 3088 if (ulv_voltage == 0) { 3089 pi->ulv.supported = false; 3090 return 0; 3091 } 3092 3093 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 3094 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) 3095 state->VddcOffset = 0; 3096 else 3097 state->VddcOffset = 3098 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; 3099 } else { 3100 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) 3101 state->VddcOffsetVid = 0; 3102 else 3103 state->VddcOffsetVid = (u8) 3104 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * 3105 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 3106 } 3107 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; 3108 3109 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm); 3110 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1); 3111 state->VddcOffset = cpu_to_be16(state->VddcOffset); 3112 3113 return 0; 3114 } 3115 3116 static int ci_calculate_sclk_params(struct radeon_device *rdev, 3117 u32 engine_clock, 3118 SMU7_Discrete_GraphicsLevel *sclk) 3119 { 3120 struct ci_power_info *pi = ci_get_pi(rdev); 3121 struct atom_clock_dividers dividers; 3122 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; 3123 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; 3124 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; 3125 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; 3126 u32 reference_clock = rdev->clock.spll.reference_freq; 3127 u32 reference_divider; 3128 u32 fbdiv; 3129 int ret; 3130 3131 ret = radeon_atom_get_clock_dividers(rdev, 3132 COMPUTE_GPUCLK_INPUT_FLAG_SCLK, 3133 engine_clock, false, ÷rs); 3134 if (ret) 3135 return ret; 3136 3137 reference_divider = 1 + dividers.ref_div; 3138 fbdiv = dividers.fb_div & 0x3FFFFFF; 3139 3140 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 3141 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 3142 spll_func_cntl_3 |= SPLL_DITHEN; 3143 3144 if (pi->caps_sclk_ss_support) { 3145 struct radeon_atom_ss ss; 3146 u32 vco_freq = engine_clock * dividers.post_div; 3147 3148 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 3149 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 3150 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 3151 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 3152 3153 cg_spll_spread_spectrum &= ~CLK_S_MASK; 3154 cg_spll_spread_spectrum |= CLK_S(clk_s); 3155 cg_spll_spread_spectrum |= SSEN; 3156 3157 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 3158 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 3159 } 3160 } 3161 3162 sclk->SclkFrequency = engine_clock; 3163 sclk->CgSpllFuncCntl3 = spll_func_cntl_3; 3164 sclk->CgSpllFuncCntl4 = spll_func_cntl_4; 3165 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; 3166 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; 3167 sclk->SclkDid = (u8)dividers.post_divider; 3168 3169 return 0; 3170 } 3171 3172 static int ci_populate_single_graphic_level(struct radeon_device *rdev, 3173 u32 engine_clock, 3174 u16 sclk_activity_level_t, 3175 SMU7_Discrete_GraphicsLevel *graphic_level) 3176 { 3177 struct ci_power_info *pi = ci_get_pi(rdev); 3178 int ret; 3179 3180 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); 3181 if (ret) 3182 return ret; 3183 3184 ret = ci_get_dependency_volt_by_clk(rdev, 3185 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3186 engine_clock, &graphic_level->MinVddc); 3187 if (ret) 3188 return ret; 3189 3190 graphic_level->SclkFrequency = engine_clock; 3191 3192 graphic_level->Flags = 0; 3193 graphic_level->MinVddcPhases = 1; 3194 3195 if (pi->vddc_phase_shed_control) 3196 ci_populate_phase_value_based_on_sclk(rdev, 3197 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 3198 engine_clock, 3199 &graphic_level->MinVddcPhases); 3200 3201 graphic_level->ActivityLevel = sclk_activity_level_t; 3202 3203 graphic_level->CcPwrDynRm = 0; 3204 graphic_level->CcPwrDynRm1 = 0; 3205 graphic_level->EnabledForThrottle = 1; 3206 graphic_level->UpH = 0; 3207 graphic_level->DownH = 0; 3208 graphic_level->VoltageDownH = 0; 3209 graphic_level->PowerThrottle = 0; 3210 3211 if (pi->caps_sclk_ds) 3212 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev, 3213 engine_clock, 3214 CISLAND_MINIMUM_ENGINE_CLOCK); 3215 3216 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 3217 3218 graphic_level->Flags = cpu_to_be32(graphic_level->Flags); 3219 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); 3220 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); 3221 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency); 3222 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel); 3223 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3); 3224 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4); 3225 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum); 3226 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2); 3227 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm); 3228 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1); 3229 3230 return 0; 3231 } 3232 3233 static int ci_populate_all_graphic_levels(struct radeon_device *rdev) 3234 { 3235 struct ci_power_info *pi = ci_get_pi(rdev); 3236 struct ci_dpm_table *dpm_table = &pi->dpm_table; 3237 u32 level_array_address = pi->dpm_table_start + 3238 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); 3239 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) * 3240 SMU7_MAX_LEVELS_GRAPHICS; 3241 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; 3242 int ret; 3243 u32 i; 3244 3245 memset(levels, 0, level_array_size); 3246 3247 for (i = 0; i < dpm_table->sclk_table.count; i++) { 3248 ret = ci_populate_single_graphic_level(rdev, 3249 dpm_table->sclk_table.dpm_levels[i].value, 3250 (u16)pi->activity_target[i], 3251 &pi->smc_state_table.GraphicsLevel[i]); 3252 if (ret) 3253 return ret; 3254 if (i > 1) 3255 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; 3256 if (i == (dpm_table->sclk_table.count - 1)) 3257 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = 3258 PPSMC_DISPLAY_WATERMARK_HIGH; 3259 } 3260 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; 3261 3262 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; 3263 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = 3264 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); 3265 3266 ret = ci_copy_bytes_to_smc(rdev, level_array_address, 3267 (u8 *)levels, level_array_size, 3268 pi->sram_end); 3269 if (ret) 3270 return ret; 3271 3272 return 0; 3273 } 3274 3275 static int ci_populate_ulv_state(struct radeon_device *rdev, 3276 SMU7_Discrete_Ulv *ulv_level) 3277 { 3278 return ci_populate_ulv_level(rdev, ulv_level); 3279 } 3280 3281 static int ci_populate_all_memory_levels(struct radeon_device *rdev) 3282 { 3283 struct ci_power_info *pi = ci_get_pi(rdev); 3284 struct ci_dpm_table *dpm_table = &pi->dpm_table; 3285 u32 level_array_address = pi->dpm_table_start + 3286 offsetof(SMU7_Discrete_DpmTable, MemoryLevel); 3287 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * 3288 SMU7_MAX_LEVELS_MEMORY; 3289 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; 3290 int ret; 3291 u32 i; 3292 3293 memset(levels, 0, level_array_size); 3294 3295 for (i = 0; i < dpm_table->mclk_table.count; i++) { 3296 if (dpm_table->mclk_table.dpm_levels[i].value == 0) 3297 return -EINVAL; 3298 ret = ci_populate_single_memory_level(rdev, 3299 dpm_table->mclk_table.dpm_levels[i].value, 3300 &pi->smc_state_table.MemoryLevel[i]); 3301 if (ret) 3302 return ret; 3303 } 3304 3305 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; 3306 3307 if ((dpm_table->mclk_table.count >= 2) && 3308 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1)) && 3309 (rdev->pdev->revision == 0)) { 3310 pi->smc_state_table.MemoryLevel[1].MinVddc = 3311 pi->smc_state_table.MemoryLevel[0].MinVddc; 3312 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = 3313 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; 3314 } 3315 3316 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); 3317 3318 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; 3319 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = 3320 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 3321 3322 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = 3323 PPSMC_DISPLAY_WATERMARK_HIGH; 3324 3325 ret = ci_copy_bytes_to_smc(rdev, level_array_address, 3326 (u8 *)levels, level_array_size, 3327 pi->sram_end); 3328 if (ret) 3329 return ret; 3330 3331 return 0; 3332 } 3333 3334 static void ci_reset_single_dpm_table(struct radeon_device *rdev, 3335 struct ci_single_dpm_table *dpm_table, 3336 u32 count) 3337 { 3338 u32 i; 3339 3340 dpm_table->count = count; 3341 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) 3342 dpm_table->dpm_levels[i].enabled = false; 3343 } 3344 3345 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table *dpm_table, 3346 u32 index, u32 pcie_gen, u32 pcie_lanes) 3347 { 3348 dpm_table->dpm_levels[index].value = pcie_gen; 3349 dpm_table->dpm_levels[index].param1 = pcie_lanes; 3350 dpm_table->dpm_levels[index].enabled = true; 3351 } 3352 3353 static int ci_setup_default_pcie_tables(struct radeon_device *rdev) 3354 { 3355 struct ci_power_info *pi = ci_get_pi(rdev); 3356 3357 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) 3358 return -EINVAL; 3359 3360 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { 3361 pi->pcie_gen_powersaving = pi->pcie_gen_performance; 3362 pi->pcie_lane_powersaving = pi->pcie_lane_performance; 3363 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { 3364 pi->pcie_gen_performance = pi->pcie_gen_powersaving; 3365 pi->pcie_lane_performance = pi->pcie_lane_powersaving; 3366 } 3367 3368 ci_reset_single_dpm_table(rdev, 3369 &pi->dpm_table.pcie_speed_table, 3370 SMU7_MAX_LEVELS_LINK); 3371 3372 if (rdev->family == CHIP_BONAIRE) 3373 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, 3374 pi->pcie_gen_powersaving.min, 3375 pi->pcie_lane_powersaving.max); 3376 else 3377 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, 3378 pi->pcie_gen_powersaving.min, 3379 pi->pcie_lane_powersaving.min); 3380 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, 3381 pi->pcie_gen_performance.min, 3382 pi->pcie_lane_performance.min); 3383 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, 3384 pi->pcie_gen_powersaving.min, 3385 pi->pcie_lane_powersaving.max); 3386 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, 3387 pi->pcie_gen_performance.min, 3388 pi->pcie_lane_performance.max); 3389 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, 3390 pi->pcie_gen_powersaving.max, 3391 pi->pcie_lane_powersaving.max); 3392 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, 3393 pi->pcie_gen_performance.max, 3394 pi->pcie_lane_performance.max); 3395 3396 pi->dpm_table.pcie_speed_table.count = 6; 3397 3398 return 0; 3399 } 3400 3401 static int ci_setup_default_dpm_tables(struct radeon_device *rdev) 3402 { 3403 struct ci_power_info *pi = ci_get_pi(rdev); 3404 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = 3405 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 3406 struct radeon_clock_voltage_dependency_table *allowed_mclk_table = 3407 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; 3408 struct radeon_cac_leakage_table *std_voltage_table = 3409 &rdev->pm.dpm.dyn_state.cac_leakage_table; 3410 u32 i; 3411 3412 if (allowed_sclk_vddc_table->count < 1) 3413 return -EINVAL; 3414 if (allowed_mclk_table->count < 1) 3415 return -EINVAL; 3416 3417 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); 3418 3419 ci_reset_single_dpm_table(rdev, 3420 &pi->dpm_table.sclk_table, 3421 SMU7_MAX_LEVELS_GRAPHICS); 3422 ci_reset_single_dpm_table(rdev, 3423 &pi->dpm_table.mclk_table, 3424 SMU7_MAX_LEVELS_MEMORY); 3425 ci_reset_single_dpm_table(rdev, 3426 &pi->dpm_table.vddc_table, 3427 SMU7_MAX_LEVELS_VDDC); 3428 ci_reset_single_dpm_table(rdev, 3429 &pi->dpm_table.vddci_table, 3430 SMU7_MAX_LEVELS_VDDCI); 3431 ci_reset_single_dpm_table(rdev, 3432 &pi->dpm_table.mvdd_table, 3433 SMU7_MAX_LEVELS_MVDD); 3434 3435 pi->dpm_table.sclk_table.count = 0; 3436 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { 3437 if ((i == 0) || 3438 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != 3439 allowed_sclk_vddc_table->entries[i].clk)) { 3440 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = 3441 allowed_sclk_vddc_table->entries[i].clk; 3442 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = 3443 i == 0; 3444 pi->dpm_table.sclk_table.count++; 3445 } 3446 } 3447 3448 pi->dpm_table.mclk_table.count = 0; 3449 for (i = 0; i < allowed_mclk_table->count; i++) { 3450 if ((i == 0) || 3451 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != 3452 allowed_mclk_table->entries[i].clk)) { 3453 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = 3454 allowed_mclk_table->entries[i].clk; 3455 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = 3456 i == 0; 3457 pi->dpm_table.mclk_table.count++; 3458 } 3459 } 3460 3461 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { 3462 pi->dpm_table.vddc_table.dpm_levels[i].value = 3463 allowed_sclk_vddc_table->entries[i].v; 3464 pi->dpm_table.vddc_table.dpm_levels[i].param1 = 3465 std_voltage_table->entries[i].leakage; 3466 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; 3467 } 3468 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; 3469 3470 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; 3471 for (i = 0; i < allowed_mclk_table->count; i++) { 3472 pi->dpm_table.vddci_table.dpm_levels[i].value = 3473 allowed_mclk_table->entries[i].v; 3474 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; 3475 } 3476 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; 3477 3478 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; 3479 for (i = 0; i < allowed_mclk_table->count; i++) { 3480 pi->dpm_table.mvdd_table.dpm_levels[i].value = 3481 allowed_mclk_table->entries[i].v; 3482 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; 3483 } 3484 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; 3485 3486 ci_setup_default_pcie_tables(rdev); 3487 3488 return 0; 3489 } 3490 3491 static int ci_find_boot_level(struct ci_single_dpm_table *table, 3492 u32 value, u32 *boot_level) 3493 { 3494 u32 i; 3495 int ret = -EINVAL; 3496 3497 for (i = 0; i < table->count; i++) { 3498 if (value == table->dpm_levels[i].value) { 3499 *boot_level = i; 3500 ret = 0; 3501 } 3502 } 3503 3504 return ret; 3505 } 3506 3507 static int ci_init_smc_table(struct radeon_device *rdev) 3508 { 3509 struct ci_power_info *pi = ci_get_pi(rdev); 3510 struct ci_ulv_parm *ulv = &pi->ulv; 3511 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 3512 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; 3513 int ret; 3514 3515 ret = ci_setup_default_dpm_tables(rdev); 3516 if (ret) 3517 return ret; 3518 3519 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) 3520 ci_populate_smc_voltage_tables(rdev, table); 3521 3522 ci_init_fps_limits(rdev); 3523 3524 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 3525 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 3526 3527 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 3528 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 3529 3530 if (pi->mem_gddr5) 3531 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 3532 3533 if (ulv->supported) { 3534 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); 3535 if (ret) 3536 return ret; 3537 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 3538 } 3539 3540 ret = ci_populate_all_graphic_levels(rdev); 3541 if (ret) 3542 return ret; 3543 3544 ret = ci_populate_all_memory_levels(rdev); 3545 if (ret) 3546 return ret; 3547 3548 ci_populate_smc_link_level(rdev, table); 3549 3550 ret = ci_populate_smc_acpi_level(rdev, table); 3551 if (ret) 3552 return ret; 3553 3554 ret = ci_populate_smc_vce_level(rdev, table); 3555 if (ret) 3556 return ret; 3557 3558 ret = ci_populate_smc_acp_level(rdev, table); 3559 if (ret) 3560 return ret; 3561 3562 ret = ci_populate_smc_samu_level(rdev, table); 3563 if (ret) 3564 return ret; 3565 3566 ret = ci_do_program_memory_timing_parameters(rdev); 3567 if (ret) 3568 return ret; 3569 3570 ret = ci_populate_smc_uvd_level(rdev, table); 3571 if (ret) 3572 return ret; 3573 3574 table->UvdBootLevel = 0; 3575 table->VceBootLevel = 0; 3576 table->AcpBootLevel = 0; 3577 table->SamuBootLevel = 0; 3578 table->GraphicsBootLevel = 0; 3579 table->MemoryBootLevel = 0; 3580 3581 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, 3582 pi->vbios_boot_state.sclk_bootup_value, 3583 (u32 *)&pi->smc_state_table.GraphicsBootLevel); 3584 3585 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, 3586 pi->vbios_boot_state.mclk_bootup_value, 3587 (u32 *)&pi->smc_state_table.MemoryBootLevel); 3588 3589 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; 3590 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; 3591 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; 3592 3593 ci_populate_smc_initial_state(rdev, radeon_boot_state); 3594 3595 ret = ci_populate_bapm_parameters_in_dpm_table(rdev); 3596 if (ret) 3597 return ret; 3598 3599 table->UVDInterval = 1; 3600 table->VCEInterval = 1; 3601 table->ACPInterval = 1; 3602 table->SAMUInterval = 1; 3603 table->GraphicsVoltageChangeEnable = 1; 3604 table->GraphicsThermThrottleEnable = 1; 3605 table->GraphicsInterval = 1; 3606 table->VoltageInterval = 1; 3607 table->ThermalInterval = 1; 3608 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * 3609 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); 3610 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * 3611 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); 3612 table->MemoryVoltageChangeEnable = 1; 3613 table->MemoryInterval = 1; 3614 table->VoltageResponseTime = 0; 3615 table->VddcVddciDelta = 4000; 3616 table->PhaseResponseTime = 0; 3617 table->MemoryThermThrottleEnable = 1; 3618 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; 3619 table->PCIeGenInterval = 1; 3620 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) 3621 table->SVI2Enable = 1; 3622 else 3623 table->SVI2Enable = 0; 3624 3625 table->ThermGpio = 17; 3626 table->SclkStepSize = 0x4000; 3627 3628 table->SystemFlags = cpu_to_be32(table->SystemFlags); 3629 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); 3630 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); 3631 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); 3632 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); 3633 table->SclkStepSize = cpu_to_be32(table->SclkStepSize); 3634 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); 3635 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); 3636 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); 3637 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); 3638 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); 3639 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); 3640 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); 3641 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); 3642 3643 ret = ci_copy_bytes_to_smc(rdev, 3644 pi->dpm_table_start + 3645 offsetof(SMU7_Discrete_DpmTable, SystemFlags), 3646 (u8 *)&table->SystemFlags, 3647 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController), 3648 pi->sram_end); 3649 if (ret) 3650 return ret; 3651 3652 return 0; 3653 } 3654 3655 static void ci_trim_single_dpm_states(struct radeon_device *rdev, 3656 struct ci_single_dpm_table *dpm_table, 3657 u32 low_limit, u32 high_limit) 3658 { 3659 u32 i; 3660 3661 for (i = 0; i < dpm_table->count; i++) { 3662 if ((dpm_table->dpm_levels[i].value < low_limit) || 3663 (dpm_table->dpm_levels[i].value > high_limit)) 3664 dpm_table->dpm_levels[i].enabled = false; 3665 else 3666 dpm_table->dpm_levels[i].enabled = true; 3667 } 3668 } 3669 3670 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev, 3671 u32 speed_low, u32 lanes_low, 3672 u32 speed_high, u32 lanes_high) 3673 { 3674 struct ci_power_info *pi = ci_get_pi(rdev); 3675 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; 3676 u32 i, j; 3677 3678 for (i = 0; i < pcie_table->count; i++) { 3679 if ((pcie_table->dpm_levels[i].value < speed_low) || 3680 (pcie_table->dpm_levels[i].param1 < lanes_low) || 3681 (pcie_table->dpm_levels[i].value > speed_high) || 3682 (pcie_table->dpm_levels[i].param1 > lanes_high)) 3683 pcie_table->dpm_levels[i].enabled = false; 3684 else 3685 pcie_table->dpm_levels[i].enabled = true; 3686 } 3687 3688 for (i = 0; i < pcie_table->count; i++) { 3689 if (pcie_table->dpm_levels[i].enabled) { 3690 for (j = i + 1; j < pcie_table->count; j++) { 3691 if (pcie_table->dpm_levels[j].enabled) { 3692 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) && 3693 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1)) 3694 pcie_table->dpm_levels[j].enabled = false; 3695 } 3696 } 3697 } 3698 } 3699 } 3700 3701 static int ci_trim_dpm_states(struct radeon_device *rdev, 3702 struct radeon_ps *radeon_state) 3703 { 3704 struct ci_ps *state = ci_get_ps(radeon_state); 3705 struct ci_power_info *pi = ci_get_pi(rdev); 3706 u32 high_limit_count; 3707 3708 if (state->performance_level_count < 1) 3709 return -EINVAL; 3710 3711 if (state->performance_level_count == 1) 3712 high_limit_count = 0; 3713 else 3714 high_limit_count = 1; 3715 3716 ci_trim_single_dpm_states(rdev, 3717 &pi->dpm_table.sclk_table, 3718 state->performance_levels[0].sclk, 3719 state->performance_levels[high_limit_count].sclk); 3720 3721 ci_trim_single_dpm_states(rdev, 3722 &pi->dpm_table.mclk_table, 3723 state->performance_levels[0].mclk, 3724 state->performance_levels[high_limit_count].mclk); 3725 3726 ci_trim_pcie_dpm_states(rdev, 3727 state->performance_levels[0].pcie_gen, 3728 state->performance_levels[0].pcie_lane, 3729 state->performance_levels[high_limit_count].pcie_gen, 3730 state->performance_levels[high_limit_count].pcie_lane); 3731 3732 return 0; 3733 } 3734 3735 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev) 3736 { 3737 struct radeon_clock_voltage_dependency_table *disp_voltage_table = 3738 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; 3739 struct radeon_clock_voltage_dependency_table *vddc_table = 3740 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 3741 u32 requested_voltage = 0; 3742 u32 i; 3743 3744 if (disp_voltage_table == NULL) 3745 return -EINVAL; 3746 if (!disp_voltage_table->count) 3747 return -EINVAL; 3748 3749 for (i = 0; i < disp_voltage_table->count; i++) { 3750 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk) 3751 requested_voltage = disp_voltage_table->entries[i].v; 3752 } 3753 3754 for (i = 0; i < vddc_table->count; i++) { 3755 if (requested_voltage <= vddc_table->entries[i].v) { 3756 requested_voltage = vddc_table->entries[i].v; 3757 return (ci_send_msg_to_smc_with_parameter(rdev, 3758 PPSMC_MSG_VddC_Request, 3759 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ? 3760 0 : -EINVAL; 3761 } 3762 } 3763 3764 return -EINVAL; 3765 } 3766 3767 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev) 3768 { 3769 struct ci_power_info *pi = ci_get_pi(rdev); 3770 PPSMC_Result result; 3771 3772 ci_apply_disp_minimum_voltage_request(rdev); 3773 3774 if (!pi->sclk_dpm_key_disabled) { 3775 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3776 result = ci_send_msg_to_smc_with_parameter(rdev, 3777 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3778 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); 3779 if (result != PPSMC_Result_OK) 3780 return -EINVAL; 3781 } 3782 } 3783 3784 if (!pi->mclk_dpm_key_disabled) { 3785 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3786 result = ci_send_msg_to_smc_with_parameter(rdev, 3787 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3788 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3789 if (result != PPSMC_Result_OK) 3790 return -EINVAL; 3791 } 3792 } 3793 #if 0 3794 if (!pi->pcie_dpm_key_disabled) { 3795 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3796 result = ci_send_msg_to_smc_with_parameter(rdev, 3797 PPSMC_MSG_PCIeDPM_SetEnabledMask, 3798 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); 3799 if (result != PPSMC_Result_OK) 3800 return -EINVAL; 3801 } 3802 } 3803 #endif 3804 return 0; 3805 } 3806 3807 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev, 3808 struct radeon_ps *radeon_state) 3809 { 3810 struct ci_power_info *pi = ci_get_pi(rdev); 3811 struct ci_ps *state = ci_get_ps(radeon_state); 3812 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; 3813 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; 3814 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; 3815 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; 3816 u32 i; 3817 3818 pi->need_update_smu7_dpm_table = 0; 3819 3820 for (i = 0; i < sclk_table->count; i++) { 3821 if (sclk == sclk_table->dpm_levels[i].value) 3822 break; 3823 } 3824 3825 if (i >= sclk_table->count) { 3826 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 3827 } else { 3828 /* XXX The current code always reprogrammed the sclk levels, 3829 * but we don't currently handle disp sclk requirements 3830 * so just skip it. 3831 */ 3832 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK) 3833 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; 3834 } 3835 3836 for (i = 0; i < mclk_table->count; i++) { 3837 if (mclk == mclk_table->dpm_levels[i].value) 3838 break; 3839 } 3840 3841 if (i >= mclk_table->count) 3842 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 3843 3844 if (rdev->pm.dpm.current_active_crtc_count != 3845 rdev->pm.dpm.new_active_crtc_count) 3846 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; 3847 } 3848 3849 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev, 3850 struct radeon_ps *radeon_state) 3851 { 3852 struct ci_power_info *pi = ci_get_pi(rdev); 3853 struct ci_ps *state = ci_get_ps(radeon_state); 3854 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; 3855 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; 3856 struct ci_dpm_table *dpm_table = &pi->dpm_table; 3857 int ret; 3858 3859 if (!pi->need_update_smu7_dpm_table) 3860 return 0; 3861 3862 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) 3863 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; 3864 3865 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) 3866 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; 3867 3868 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { 3869 ret = ci_populate_all_graphic_levels(rdev); 3870 if (ret) 3871 return ret; 3872 } 3873 3874 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { 3875 ret = ci_populate_all_memory_levels(rdev); 3876 if (ret) 3877 return ret; 3878 } 3879 3880 return 0; 3881 } 3882 3883 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable) 3884 { 3885 struct ci_power_info *pi = ci_get_pi(rdev); 3886 const struct radeon_clock_and_voltage_limits *max_limits; 3887 int i; 3888 3889 if (rdev->pm.dpm.ac_power) 3890 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3891 else 3892 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3893 3894 if (enable) { 3895 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; 3896 3897 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3898 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3899 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; 3900 3901 if (!pi->caps_uvd_dpm) 3902 break; 3903 } 3904 } 3905 3906 ci_send_msg_to_smc_with_parameter(rdev, 3907 PPSMC_MSG_UVDDPM_SetEnabledMask, 3908 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); 3909 3910 if (pi->last_mclk_dpm_enable_mask & 0x1) { 3911 pi->uvd_enabled = true; 3912 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; 3913 ci_send_msg_to_smc_with_parameter(rdev, 3914 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3915 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3916 } 3917 } else { 3918 if (pi->last_mclk_dpm_enable_mask & 0x1) { 3919 pi->uvd_enabled = false; 3920 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; 3921 ci_send_msg_to_smc_with_parameter(rdev, 3922 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3923 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3924 } 3925 } 3926 3927 return (ci_send_msg_to_smc(rdev, enable ? 3928 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ? 3929 0 : -EINVAL; 3930 } 3931 3932 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable) 3933 { 3934 struct ci_power_info *pi = ci_get_pi(rdev); 3935 const struct radeon_clock_and_voltage_limits *max_limits; 3936 int i; 3937 3938 if (rdev->pm.dpm.ac_power) 3939 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3940 else 3941 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3942 3943 if (enable) { 3944 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; 3945 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3946 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3947 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; 3948 3949 if (!pi->caps_vce_dpm) 3950 break; 3951 } 3952 } 3953 3954 ci_send_msg_to_smc_with_parameter(rdev, 3955 PPSMC_MSG_VCEDPM_SetEnabledMask, 3956 pi->dpm_level_enable_mask.vce_dpm_enable_mask); 3957 } 3958 3959 return (ci_send_msg_to_smc(rdev, enable ? 3960 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ? 3961 0 : -EINVAL; 3962 } 3963 3964 #if 0 3965 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable) 3966 { 3967 struct ci_power_info *pi = ci_get_pi(rdev); 3968 const struct radeon_clock_and_voltage_limits *max_limits; 3969 int i; 3970 3971 if (rdev->pm.dpm.ac_power) 3972 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3973 else 3974 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3975 3976 if (enable) { 3977 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0; 3978 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3979 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3980 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i; 3981 3982 if (!pi->caps_samu_dpm) 3983 break; 3984 } 3985 } 3986 3987 ci_send_msg_to_smc_with_parameter(rdev, 3988 PPSMC_MSG_SAMUDPM_SetEnabledMask, 3989 pi->dpm_level_enable_mask.samu_dpm_enable_mask); 3990 } 3991 return (ci_send_msg_to_smc(rdev, enable ? 3992 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ? 3993 0 : -EINVAL; 3994 } 3995 3996 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable) 3997 { 3998 struct ci_power_info *pi = ci_get_pi(rdev); 3999 const struct radeon_clock_and_voltage_limits *max_limits; 4000 int i; 4001 4002 if (rdev->pm.dpm.ac_power) 4003 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 4004 else 4005 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 4006 4007 if (enable) { 4008 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0; 4009 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 4010 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 4011 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i; 4012 4013 if (!pi->caps_acp_dpm) 4014 break; 4015 } 4016 } 4017 4018 ci_send_msg_to_smc_with_parameter(rdev, 4019 PPSMC_MSG_ACPDPM_SetEnabledMask, 4020 pi->dpm_level_enable_mask.acp_dpm_enable_mask); 4021 } 4022 4023 return (ci_send_msg_to_smc(rdev, enable ? 4024 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ? 4025 0 : -EINVAL; 4026 } 4027 #endif 4028 4029 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate) 4030 { 4031 struct ci_power_info *pi = ci_get_pi(rdev); 4032 u32 tmp; 4033 4034 if (!gate) { 4035 if (pi->caps_uvd_dpm || 4036 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) 4037 pi->smc_state_table.UvdBootLevel = 0; 4038 else 4039 pi->smc_state_table.UvdBootLevel = 4040 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; 4041 4042 tmp = RREG32_SMC(DPM_TABLE_475); 4043 tmp &= ~UvdBootLevel_MASK; 4044 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); 4045 WREG32_SMC(DPM_TABLE_475, tmp); 4046 } 4047 4048 return ci_enable_uvd_dpm(rdev, !gate); 4049 } 4050 4051 static u8 ci_get_vce_boot_level(struct radeon_device *rdev) 4052 { 4053 u8 i; 4054 u32 min_evclk = 30000; /* ??? */ 4055 struct radeon_vce_clock_voltage_dependency_table *table = 4056 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 4057 4058 for (i = 0; i < table->count; i++) { 4059 if (table->entries[i].evclk >= min_evclk) 4060 return i; 4061 } 4062 4063 return table->count - 1; 4064 } 4065 4066 static int ci_update_vce_dpm(struct radeon_device *rdev, 4067 struct radeon_ps *radeon_new_state, 4068 struct radeon_ps *radeon_current_state) 4069 { 4070 struct ci_power_info *pi = ci_get_pi(rdev); 4071 int ret = 0; 4072 u32 tmp; 4073 4074 if (radeon_current_state->evclk != radeon_new_state->evclk) { 4075 if (radeon_new_state->evclk) { 4076 /* turn the clocks on when encoding */ 4077 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false); 4078 4079 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); 4080 tmp = RREG32_SMC(DPM_TABLE_475); 4081 tmp &= ~VceBootLevel_MASK; 4082 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); 4083 WREG32_SMC(DPM_TABLE_475, tmp); 4084 4085 ret = ci_enable_vce_dpm(rdev, true); 4086 } else { 4087 /* turn the clocks off when not encoding */ 4088 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true); 4089 4090 ret = ci_enable_vce_dpm(rdev, false); 4091 } 4092 } 4093 return ret; 4094 } 4095 4096 #if 0 4097 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate) 4098 { 4099 return ci_enable_samu_dpm(rdev, gate); 4100 } 4101 4102 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate) 4103 { 4104 struct ci_power_info *pi = ci_get_pi(rdev); 4105 u32 tmp; 4106 4107 if (!gate) { 4108 pi->smc_state_table.AcpBootLevel = 0; 4109 4110 tmp = RREG32_SMC(DPM_TABLE_475); 4111 tmp &= ~AcpBootLevel_MASK; 4112 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel); 4113 WREG32_SMC(DPM_TABLE_475, tmp); 4114 } 4115 4116 return ci_enable_acp_dpm(rdev, !gate); 4117 } 4118 #endif 4119 4120 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev, 4121 struct radeon_ps *radeon_state) 4122 { 4123 struct ci_power_info *pi = ci_get_pi(rdev); 4124 int ret; 4125 4126 ret = ci_trim_dpm_states(rdev, radeon_state); 4127 if (ret) 4128 return ret; 4129 4130 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = 4131 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); 4132 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = 4133 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); 4134 pi->last_mclk_dpm_enable_mask = 4135 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; 4136 if (pi->uvd_enabled) { 4137 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) 4138 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; 4139 } 4140 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = 4141 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); 4142 4143 return 0; 4144 } 4145 4146 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev, 4147 u32 level_mask) 4148 { 4149 u32 level = 0; 4150 4151 while ((level_mask & (1 << level)) == 0) 4152 level++; 4153 4154 return level; 4155 } 4156 4157 4158 int ci_dpm_force_performance_level(struct radeon_device *rdev, 4159 enum radeon_dpm_forced_level level) 4160 { 4161 struct ci_power_info *pi = ci_get_pi(rdev); 4162 u32 tmp, levels, i; 4163 int ret; 4164 4165 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 4166 if ((!pi->pcie_dpm_key_disabled) && 4167 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 4168 levels = 0; 4169 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; 4170 while (tmp >>= 1) 4171 levels++; 4172 if (levels) { 4173 ret = ci_dpm_force_state_pcie(rdev, level); 4174 if (ret) 4175 return ret; 4176 for (i = 0; i < rdev->usec_timeout; i++) { 4177 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & 4178 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; 4179 if (tmp == levels) 4180 break; 4181 udelay(1); 4182 } 4183 } 4184 } 4185 if ((!pi->sclk_dpm_key_disabled) && 4186 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 4187 levels = 0; 4188 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; 4189 while (tmp >>= 1) 4190 levels++; 4191 if (levels) { 4192 ret = ci_dpm_force_state_sclk(rdev, levels); 4193 if (ret) 4194 return ret; 4195 for (i = 0; i < rdev->usec_timeout; i++) { 4196 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 4197 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; 4198 if (tmp == levels) 4199 break; 4200 udelay(1); 4201 } 4202 } 4203 } 4204 if ((!pi->mclk_dpm_key_disabled) && 4205 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 4206 levels = 0; 4207 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; 4208 while (tmp >>= 1) 4209 levels++; 4210 if (levels) { 4211 ret = ci_dpm_force_state_mclk(rdev, levels); 4212 if (ret) 4213 return ret; 4214 for (i = 0; i < rdev->usec_timeout; i++) { 4215 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 4216 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; 4217 if (tmp == levels) 4218 break; 4219 udelay(1); 4220 } 4221 } 4222 } 4223 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 4224 if ((!pi->sclk_dpm_key_disabled) && 4225 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 4226 levels = ci_get_lowest_enabled_level(rdev, 4227 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); 4228 ret = ci_dpm_force_state_sclk(rdev, levels); 4229 if (ret) 4230 return ret; 4231 for (i = 0; i < rdev->usec_timeout; i++) { 4232 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 4233 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; 4234 if (tmp == levels) 4235 break; 4236 udelay(1); 4237 } 4238 } 4239 if ((!pi->mclk_dpm_key_disabled) && 4240 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 4241 levels = ci_get_lowest_enabled_level(rdev, 4242 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 4243 ret = ci_dpm_force_state_mclk(rdev, levels); 4244 if (ret) 4245 return ret; 4246 for (i = 0; i < rdev->usec_timeout; i++) { 4247 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 4248 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; 4249 if (tmp == levels) 4250 break; 4251 udelay(1); 4252 } 4253 } 4254 if ((!pi->pcie_dpm_key_disabled) && 4255 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 4256 levels = ci_get_lowest_enabled_level(rdev, 4257 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); 4258 ret = ci_dpm_force_state_pcie(rdev, levels); 4259 if (ret) 4260 return ret; 4261 for (i = 0; i < rdev->usec_timeout; i++) { 4262 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & 4263 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; 4264 if (tmp == levels) 4265 break; 4266 udelay(1); 4267 } 4268 } 4269 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 4270 if (!pi->pcie_dpm_key_disabled) { 4271 PPSMC_Result smc_result; 4272 4273 smc_result = ci_send_msg_to_smc(rdev, 4274 PPSMC_MSG_PCIeDPM_UnForceLevel); 4275 if (smc_result != PPSMC_Result_OK) 4276 return -EINVAL; 4277 } 4278 ret = ci_upload_dpm_level_enable_mask(rdev); 4279 if (ret) 4280 return ret; 4281 } 4282 4283 rdev->pm.dpm.forced_level = level; 4284 4285 return 0; 4286 } 4287 4288 static int ci_set_mc_special_registers(struct radeon_device *rdev, 4289 struct ci_mc_reg_table *table) 4290 { 4291 struct ci_power_info *pi = ci_get_pi(rdev); 4292 u8 i, j, k; 4293 u32 temp_reg; 4294 4295 for (i = 0, j = table->last; i < table->last; i++) { 4296 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4297 return -EINVAL; 4298 switch (table->mc_reg_address[i].s1 << 2) { 4299 case MC_SEQ_MISC1: 4300 temp_reg = RREG32(MC_PMG_CMD_EMRS); 4301 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 4302 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 4303 for (k = 0; k < table->num_entries; k++) { 4304 table->mc_reg_table_entry[k].mc_data[j] = 4305 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 4306 } 4307 j++; 4308 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4309 return -EINVAL; 4310 4311 temp_reg = RREG32(MC_PMG_CMD_MRS); 4312 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 4313 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 4314 for (k = 0; k < table->num_entries; k++) { 4315 table->mc_reg_table_entry[k].mc_data[j] = 4316 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 4317 if (!pi->mem_gddr5) 4318 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 4319 } 4320 j++; 4321 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4322 return -EINVAL; 4323 4324 if (!pi->mem_gddr5) { 4325 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 4326 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 4327 for (k = 0; k < table->num_entries; k++) { 4328 table->mc_reg_table_entry[k].mc_data[j] = 4329 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 4330 } 4331 j++; 4332 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4333 return -EINVAL; 4334 } 4335 break; 4336 case MC_SEQ_RESERVE_M: 4337 temp_reg = RREG32(MC_PMG_CMD_MRS1); 4338 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 4339 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 4340 for (k = 0; k < table->num_entries; k++) { 4341 table->mc_reg_table_entry[k].mc_data[j] = 4342 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 4343 } 4344 j++; 4345 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4346 return -EINVAL; 4347 break; 4348 default: 4349 break; 4350 } 4351 4352 } 4353 4354 table->last = j; 4355 4356 return 0; 4357 } 4358 4359 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 4360 { 4361 bool result = true; 4362 4363 switch (in_reg) { 4364 case MC_SEQ_RAS_TIMING >> 2: 4365 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 4366 break; 4367 case MC_SEQ_DLL_STBY >> 2: 4368 *out_reg = MC_SEQ_DLL_STBY_LP >> 2; 4369 break; 4370 case MC_SEQ_G5PDX_CMD0 >> 2: 4371 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2; 4372 break; 4373 case MC_SEQ_G5PDX_CMD1 >> 2: 4374 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2; 4375 break; 4376 case MC_SEQ_G5PDX_CTRL >> 2: 4377 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2; 4378 break; 4379 case MC_SEQ_CAS_TIMING >> 2: 4380 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 4381 break; 4382 case MC_SEQ_MISC_TIMING >> 2: 4383 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 4384 break; 4385 case MC_SEQ_MISC_TIMING2 >> 2: 4386 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 4387 break; 4388 case MC_SEQ_PMG_DVS_CMD >> 2: 4389 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2; 4390 break; 4391 case MC_SEQ_PMG_DVS_CTL >> 2: 4392 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2; 4393 break; 4394 case MC_SEQ_RD_CTL_D0 >> 2: 4395 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 4396 break; 4397 case MC_SEQ_RD_CTL_D1 >> 2: 4398 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 4399 break; 4400 case MC_SEQ_WR_CTL_D0 >> 2: 4401 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 4402 break; 4403 case MC_SEQ_WR_CTL_D1 >> 2: 4404 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 4405 break; 4406 case MC_PMG_CMD_EMRS >> 2: 4407 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 4408 break; 4409 case MC_PMG_CMD_MRS >> 2: 4410 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 4411 break; 4412 case MC_PMG_CMD_MRS1 >> 2: 4413 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 4414 break; 4415 case MC_SEQ_PMG_TIMING >> 2: 4416 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 4417 break; 4418 case MC_PMG_CMD_MRS2 >> 2: 4419 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 4420 break; 4421 case MC_SEQ_WR_CTL_2 >> 2: 4422 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 4423 break; 4424 default: 4425 result = false; 4426 break; 4427 } 4428 4429 return result; 4430 } 4431 4432 static void ci_set_valid_flag(struct ci_mc_reg_table *table) 4433 { 4434 u8 i, j; 4435 4436 for (i = 0; i < table->last; i++) { 4437 for (j = 1; j < table->num_entries; j++) { 4438 if (table->mc_reg_table_entry[j-1].mc_data[i] != 4439 table->mc_reg_table_entry[j].mc_data[i]) { 4440 table->valid_flag |= 1 << i; 4441 break; 4442 } 4443 } 4444 } 4445 } 4446 4447 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) 4448 { 4449 u32 i; 4450 u16 address; 4451 4452 for (i = 0; i < table->last; i++) { 4453 table->mc_reg_address[i].s0 = 4454 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 4455 address : table->mc_reg_address[i].s1; 4456 } 4457 } 4458 4459 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, 4460 struct ci_mc_reg_table *ci_table) 4461 { 4462 u8 i, j; 4463 4464 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4465 return -EINVAL; 4466 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 4467 return -EINVAL; 4468 4469 for (i = 0; i < table->last; i++) 4470 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 4471 4472 ci_table->last = table->last; 4473 4474 for (i = 0; i < table->num_entries; i++) { 4475 ci_table->mc_reg_table_entry[i].mclk_max = 4476 table->mc_reg_table_entry[i].mclk_max; 4477 for (j = 0; j < table->last; j++) 4478 ci_table->mc_reg_table_entry[i].mc_data[j] = 4479 table->mc_reg_table_entry[i].mc_data[j]; 4480 } 4481 ci_table->num_entries = table->num_entries; 4482 4483 return 0; 4484 } 4485 4486 static int ci_register_patching_mc_seq(struct radeon_device *rdev, 4487 struct ci_mc_reg_table *table) 4488 { 4489 u8 i, k; 4490 u32 tmp; 4491 bool patch; 4492 4493 tmp = RREG32(MC_SEQ_MISC0); 4494 patch = (tmp & 0x0000f00) == 0x300; 4495 4496 if (patch && 4497 ((rdev->pdev->device == 0x67B0) || 4498 (rdev->pdev->device == 0x67B1)) && 4499 (rdev->pdev->revision == 0)) { 4500 for (i = 0; i < table->last; i++) { 4501 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4502 return -EINVAL; 4503 switch (table->mc_reg_address[i].s1 >> 2) { 4504 case MC_SEQ_MISC1: 4505 for (k = 0; k < table->num_entries; k++) { 4506 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || 4507 (table->mc_reg_table_entry[k].mclk_max == 137500)) 4508 table->mc_reg_table_entry[k].mc_data[i] = 4509 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) | 4510 0x00000007; 4511 } 4512 break; 4513 case MC_SEQ_WR_CTL_D0: 4514 for (k = 0; k < table->num_entries; k++) { 4515 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || 4516 (table->mc_reg_table_entry[k].mclk_max == 137500)) 4517 table->mc_reg_table_entry[k].mc_data[i] = 4518 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | 4519 0x0000D0DD; 4520 } 4521 break; 4522 case MC_SEQ_WR_CTL_D1: 4523 for (k = 0; k < table->num_entries; k++) { 4524 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || 4525 (table->mc_reg_table_entry[k].mclk_max == 137500)) 4526 table->mc_reg_table_entry[k].mc_data[i] = 4527 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | 4528 0x0000D0DD; 4529 } 4530 break; 4531 case MC_SEQ_WR_CTL_2: 4532 for (k = 0; k < table->num_entries; k++) { 4533 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || 4534 (table->mc_reg_table_entry[k].mclk_max == 137500)) 4535 table->mc_reg_table_entry[k].mc_data[i] = 0; 4536 } 4537 break; 4538 case MC_SEQ_CAS_TIMING: 4539 for (k = 0; k < table->num_entries; k++) { 4540 if (table->mc_reg_table_entry[k].mclk_max == 125000) 4541 table->mc_reg_table_entry[k].mc_data[i] = 4542 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | 4543 0x000C0140; 4544 else if (table->mc_reg_table_entry[k].mclk_max == 137500) 4545 table->mc_reg_table_entry[k].mc_data[i] = 4546 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | 4547 0x000C0150; 4548 } 4549 break; 4550 case MC_SEQ_MISC_TIMING: 4551 for (k = 0; k < table->num_entries; k++) { 4552 if (table->mc_reg_table_entry[k].mclk_max == 125000) 4553 table->mc_reg_table_entry[k].mc_data[i] = 4554 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | 4555 0x00000030; 4556 else if (table->mc_reg_table_entry[k].mclk_max == 137500) 4557 table->mc_reg_table_entry[k].mc_data[i] = 4558 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | 4559 0x00000035; 4560 } 4561 break; 4562 default: 4563 break; 4564 } 4565 } 4566 4567 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3); 4568 tmp = RREG32(MC_SEQ_IO_DEBUG_DATA); 4569 tmp = (tmp & 0xFFF8FFFF) | (1 << 16); 4570 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3); 4571 WREG32(MC_SEQ_IO_DEBUG_DATA, tmp); 4572 } 4573 4574 return 0; 4575 } 4576 4577 static int ci_initialize_mc_reg_table(struct radeon_device *rdev) 4578 { 4579 struct ci_power_info *pi = ci_get_pi(rdev); 4580 struct atom_mc_reg_table *table; 4581 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; 4582 u8 module_index = rv770_get_memory_module_index(rdev); 4583 int ret; 4584 4585 table = kzalloc_obj(struct atom_mc_reg_table); 4586 if (!table) 4587 return -ENOMEM; 4588 4589 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 4590 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 4591 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY)); 4592 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0)); 4593 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1)); 4594 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL)); 4595 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD)); 4596 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL)); 4597 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 4598 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 4599 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 4600 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 4601 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 4602 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 4603 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 4604 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 4605 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 4606 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 4607 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 4608 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 4609 4610 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 4611 if (ret) 4612 goto init_mc_done; 4613 4614 ret = ci_copy_vbios_mc_reg_table(table, ci_table); 4615 if (ret) 4616 goto init_mc_done; 4617 4618 ci_set_s0_mc_reg_index(ci_table); 4619 4620 ret = ci_register_patching_mc_seq(rdev, ci_table); 4621 if (ret) 4622 goto init_mc_done; 4623 4624 ret = ci_set_mc_special_registers(rdev, ci_table); 4625 if (ret) 4626 goto init_mc_done; 4627 4628 ci_set_valid_flag(ci_table); 4629 4630 init_mc_done: 4631 kfree(table); 4632 4633 return ret; 4634 } 4635 4636 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev, 4637 SMU7_Discrete_MCRegisters *mc_reg_table) 4638 { 4639 struct ci_power_info *pi = ci_get_pi(rdev); 4640 u32 i, j; 4641 4642 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { 4643 if (pi->mc_reg_table.valid_flag & (1 << j)) { 4644 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4645 return -EINVAL; 4646 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); 4647 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); 4648 i++; 4649 } 4650 } 4651 4652 mc_reg_table->last = (u8)i; 4653 4654 return 0; 4655 } 4656 4657 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry, 4658 SMU7_Discrete_MCRegisterSet *data, 4659 u32 num_entries, u32 valid_flag) 4660 { 4661 u32 i, j; 4662 4663 for (i = 0, j = 0; j < num_entries; j++) { 4664 if (valid_flag & (1 << j)) { 4665 data->value[i] = cpu_to_be32(entry->mc_data[j]); 4666 i++; 4667 } 4668 } 4669 } 4670 4671 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 4672 const u32 memory_clock, 4673 SMU7_Discrete_MCRegisterSet *mc_reg_table_data) 4674 { 4675 struct ci_power_info *pi = ci_get_pi(rdev); 4676 u32 i = 0; 4677 4678 for (i = 0; i < pi->mc_reg_table.num_entries; i++) { 4679 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 4680 break; 4681 } 4682 4683 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) 4684 --i; 4685 4686 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], 4687 mc_reg_table_data, pi->mc_reg_table.last, 4688 pi->mc_reg_table.valid_flag); 4689 } 4690 4691 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 4692 SMU7_Discrete_MCRegisters *mc_reg_table) 4693 { 4694 struct ci_power_info *pi = ci_get_pi(rdev); 4695 u32 i; 4696 4697 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) 4698 ci_convert_mc_reg_table_entry_to_smc(rdev, 4699 pi->dpm_table.mclk_table.dpm_levels[i].value, 4700 &mc_reg_table->data[i]); 4701 } 4702 4703 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev) 4704 { 4705 struct ci_power_info *pi = ci_get_pi(rdev); 4706 int ret; 4707 4708 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); 4709 4710 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); 4711 if (ret) 4712 return ret; 4713 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); 4714 4715 return ci_copy_bytes_to_smc(rdev, 4716 pi->mc_reg_table_start, 4717 (u8 *)&pi->smc_mc_reg_table, 4718 sizeof(SMU7_Discrete_MCRegisters), 4719 pi->sram_end); 4720 } 4721 4722 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev) 4723 { 4724 struct ci_power_info *pi = ci_get_pi(rdev); 4725 4726 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) 4727 return 0; 4728 4729 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); 4730 4731 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); 4732 4733 return ci_copy_bytes_to_smc(rdev, 4734 pi->mc_reg_table_start + 4735 offsetof(SMU7_Discrete_MCRegisters, data[0]), 4736 (u8 *)&pi->smc_mc_reg_table.data[0], 4737 sizeof(SMU7_Discrete_MCRegisterSet) * 4738 pi->dpm_table.mclk_table.count, 4739 pi->sram_end); 4740 } 4741 4742 static void ci_enable_voltage_control(struct radeon_device *rdev) 4743 { 4744 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 4745 4746 tmp |= VOLT_PWRMGT_EN; 4747 WREG32_SMC(GENERAL_PWRMGT, tmp); 4748 } 4749 4750 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev, 4751 struct radeon_ps *radeon_state) 4752 { 4753 struct ci_ps *state = ci_get_ps(radeon_state); 4754 int i; 4755 u16 pcie_speed, max_speed = 0; 4756 4757 for (i = 0; i < state->performance_level_count; i++) { 4758 pcie_speed = state->performance_levels[i].pcie_gen; 4759 if (max_speed < pcie_speed) 4760 max_speed = pcie_speed; 4761 } 4762 4763 return max_speed; 4764 } 4765 4766 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev) 4767 { 4768 u32 speed_cntl = 0; 4769 4770 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 4771 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 4772 4773 return (u16)speed_cntl; 4774 } 4775 4776 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev) 4777 { 4778 u32 link_width = 0; 4779 4780 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; 4781 link_width >>= LC_LINK_WIDTH_RD_SHIFT; 4782 4783 switch (link_width) { 4784 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4785 return 1; 4786 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4787 return 2; 4788 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4789 return 4; 4790 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4791 return 8; 4792 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4793 /* not actually supported */ 4794 return 12; 4795 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4796 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4797 default: 4798 return 16; 4799 } 4800 } 4801 4802 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev, 4803 struct radeon_ps *radeon_new_state, 4804 struct radeon_ps *radeon_current_state) 4805 { 4806 struct ci_power_info *pi = ci_get_pi(rdev); 4807 enum radeon_pcie_gen target_link_speed = 4808 ci_get_maximum_link_speed(rdev, radeon_new_state); 4809 enum radeon_pcie_gen current_link_speed; 4810 4811 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 4812 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state); 4813 else 4814 current_link_speed = pi->force_pcie_gen; 4815 4816 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 4817 pi->pspp_notify_required = false; 4818 if (target_link_speed > current_link_speed) { 4819 switch (target_link_speed) { 4820 #ifdef CONFIG_ACPI 4821 case RADEON_PCIE_GEN3: 4822 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 4823 break; 4824 pi->force_pcie_gen = RADEON_PCIE_GEN2; 4825 if (current_link_speed == RADEON_PCIE_GEN2) 4826 break; 4827 fallthrough; 4828 case RADEON_PCIE_GEN2: 4829 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 4830 break; 4831 fallthrough; 4832 #endif 4833 default: 4834 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); 4835 break; 4836 } 4837 } else { 4838 if (target_link_speed < current_link_speed) 4839 pi->pspp_notify_required = true; 4840 } 4841 } 4842 4843 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 4844 struct radeon_ps *radeon_new_state, 4845 struct radeon_ps *radeon_current_state) 4846 { 4847 struct ci_power_info *pi = ci_get_pi(rdev); 4848 enum radeon_pcie_gen target_link_speed = 4849 ci_get_maximum_link_speed(rdev, radeon_new_state); 4850 u8 request; 4851 4852 if (pi->pspp_notify_required) { 4853 if (target_link_speed == RADEON_PCIE_GEN3) 4854 request = PCIE_PERF_REQ_PECI_GEN3; 4855 else if (target_link_speed == RADEON_PCIE_GEN2) 4856 request = PCIE_PERF_REQ_PECI_GEN2; 4857 else 4858 request = PCIE_PERF_REQ_PECI_GEN1; 4859 4860 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 4861 (ci_get_current_pcie_speed(rdev) > 0)) 4862 return; 4863 4864 #ifdef CONFIG_ACPI 4865 radeon_acpi_pcie_performance_request(rdev, request, false); 4866 #endif 4867 } 4868 } 4869 4870 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev) 4871 { 4872 struct ci_power_info *pi = ci_get_pi(rdev); 4873 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = 4874 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 4875 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table = 4876 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; 4877 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table = 4878 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; 4879 4880 if (allowed_sclk_vddc_table->count < 1) 4881 return -EINVAL; 4882 if (allowed_mclk_vddc_table->count < 1) 4883 return -EINVAL; 4884 if (allowed_mclk_vddci_table->count < 1) 4885 return -EINVAL; 4886 4887 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; 4888 pi->max_vddc_in_pp_table = 4889 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 4890 4891 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; 4892 pi->max_vddci_in_pp_table = 4893 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 4894 4895 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = 4896 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 4897 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = 4898 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 4899 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = 4900 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 4901 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = 4902 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 4903 4904 return 0; 4905 } 4906 4907 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc) 4908 { 4909 struct ci_power_info *pi = ci_get_pi(rdev); 4910 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; 4911 u32 leakage_index; 4912 4913 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { 4914 if (leakage_table->leakage_id[leakage_index] == *vddc) { 4915 *vddc = leakage_table->actual_voltage[leakage_index]; 4916 break; 4917 } 4918 } 4919 } 4920 4921 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci) 4922 { 4923 struct ci_power_info *pi = ci_get_pi(rdev); 4924 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; 4925 u32 leakage_index; 4926 4927 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { 4928 if (leakage_table->leakage_id[leakage_index] == *vddci) { 4929 *vddci = leakage_table->actual_voltage[leakage_index]; 4930 break; 4931 } 4932 } 4933 } 4934 4935 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4936 struct radeon_clock_voltage_dependency_table *table) 4937 { 4938 u32 i; 4939 4940 if (table) { 4941 for (i = 0; i < table->count; i++) 4942 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4943 } 4944 } 4945 4946 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev, 4947 struct radeon_clock_voltage_dependency_table *table) 4948 { 4949 u32 i; 4950 4951 if (table) { 4952 for (i = 0; i < table->count; i++) 4953 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v); 4954 } 4955 } 4956 4957 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4958 struct radeon_vce_clock_voltage_dependency_table *table) 4959 { 4960 u32 i; 4961 4962 if (table) { 4963 for (i = 0; i < table->count; i++) 4964 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4965 } 4966 } 4967 4968 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4969 struct radeon_uvd_clock_voltage_dependency_table *table) 4970 { 4971 u32 i; 4972 4973 if (table) { 4974 for (i = 0; i < table->count; i++) 4975 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4976 } 4977 } 4978 4979 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev, 4980 struct radeon_phase_shedding_limits_table *table) 4981 { 4982 u32 i; 4983 4984 if (table) { 4985 for (i = 0; i < table->count; i++) 4986 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage); 4987 } 4988 } 4989 4990 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev, 4991 struct radeon_clock_and_voltage_limits *table) 4992 { 4993 if (table) { 4994 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); 4995 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); 4996 } 4997 } 4998 4999 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev, 5000 struct radeon_cac_leakage_table *table) 5001 { 5002 u32 i; 5003 5004 if (table) { 5005 for (i = 0; i < table->count; i++) 5006 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc); 5007 } 5008 } 5009 5010 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev) 5011 { 5012 5013 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5014 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5015 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5016 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5017 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5018 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); 5019 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev, 5020 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5021 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5022 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); 5023 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5024 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); 5025 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5026 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); 5027 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5028 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); 5029 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev, 5030 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); 5031 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, 5032 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); 5033 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, 5034 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); 5035 ci_patch_cac_leakage_table_with_vddc_leakage(rdev, 5036 &rdev->pm.dpm.dyn_state.cac_leakage_table); 5037 5038 } 5039 5040 static void ci_get_memory_type(struct radeon_device *rdev) 5041 { 5042 struct ci_power_info *pi = ci_get_pi(rdev); 5043 u32 tmp; 5044 5045 tmp = RREG32(MC_SEQ_MISC0); 5046 5047 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) == 5048 MC_SEQ_MISC0_GDDR5_VALUE) 5049 pi->mem_gddr5 = true; 5050 else 5051 pi->mem_gddr5 = false; 5052 5053 } 5054 5055 static void ci_update_current_ps(struct radeon_device *rdev, 5056 struct radeon_ps *rps) 5057 { 5058 struct ci_ps *new_ps = ci_get_ps(rps); 5059 struct ci_power_info *pi = ci_get_pi(rdev); 5060 5061 pi->current_rps = *rps; 5062 pi->current_ps = *new_ps; 5063 pi->current_rps.ps_priv = &pi->current_ps; 5064 } 5065 5066 static void ci_update_requested_ps(struct radeon_device *rdev, 5067 struct radeon_ps *rps) 5068 { 5069 struct ci_ps *new_ps = ci_get_ps(rps); 5070 struct ci_power_info *pi = ci_get_pi(rdev); 5071 5072 pi->requested_rps = *rps; 5073 pi->requested_ps = *new_ps; 5074 pi->requested_rps.ps_priv = &pi->requested_ps; 5075 } 5076 5077 int ci_dpm_pre_set_power_state(struct radeon_device *rdev) 5078 { 5079 struct ci_power_info *pi = ci_get_pi(rdev); 5080 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 5081 struct radeon_ps *new_ps = &requested_ps; 5082 5083 ci_update_requested_ps(rdev, new_ps); 5084 5085 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); 5086 5087 return 0; 5088 } 5089 5090 void ci_dpm_post_set_power_state(struct radeon_device *rdev) 5091 { 5092 struct ci_power_info *pi = ci_get_pi(rdev); 5093 struct radeon_ps *new_ps = &pi->requested_rps; 5094 5095 ci_update_current_ps(rdev, new_ps); 5096 } 5097 5098 5099 void ci_dpm_setup_asic(struct radeon_device *rdev) 5100 { 5101 int r; 5102 5103 r = ci_mc_load_microcode(rdev); 5104 if (r) 5105 DRM_ERROR("Failed to load MC firmware!\n"); 5106 ci_read_clock_registers(rdev); 5107 ci_get_memory_type(rdev); 5108 ci_enable_acpi_power_management(rdev); 5109 ci_init_sclk_t(rdev); 5110 } 5111 5112 int ci_dpm_enable(struct radeon_device *rdev) 5113 { 5114 struct ci_power_info *pi = ci_get_pi(rdev); 5115 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5116 int ret; 5117 5118 if (ci_is_smc_running(rdev)) 5119 return -EINVAL; 5120 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 5121 ci_enable_voltage_control(rdev); 5122 ret = ci_construct_voltage_tables(rdev); 5123 if (ret) { 5124 DRM_ERROR("ci_construct_voltage_tables failed\n"); 5125 return ret; 5126 } 5127 } 5128 if (pi->caps_dynamic_ac_timing) { 5129 ret = ci_initialize_mc_reg_table(rdev); 5130 if (ret) 5131 pi->caps_dynamic_ac_timing = false; 5132 } 5133 if (pi->dynamic_ss) 5134 ci_enable_spread_spectrum(rdev, true); 5135 if (pi->thermal_protection) 5136 ci_enable_thermal_protection(rdev, true); 5137 ci_program_sstp(rdev); 5138 ci_enable_display_gap(rdev); 5139 ci_program_vc(rdev); 5140 ret = ci_upload_firmware(rdev); 5141 if (ret) { 5142 DRM_ERROR("ci_upload_firmware failed\n"); 5143 return ret; 5144 } 5145 ret = ci_process_firmware_header(rdev); 5146 if (ret) { 5147 DRM_ERROR("ci_process_firmware_header failed\n"); 5148 return ret; 5149 } 5150 ret = ci_initial_switch_from_arb_f0_to_f1(rdev); 5151 if (ret) { 5152 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n"); 5153 return ret; 5154 } 5155 ret = ci_init_smc_table(rdev); 5156 if (ret) { 5157 DRM_ERROR("ci_init_smc_table failed\n"); 5158 return ret; 5159 } 5160 ret = ci_init_arb_table_index(rdev); 5161 if (ret) { 5162 DRM_ERROR("ci_init_arb_table_index failed\n"); 5163 return ret; 5164 } 5165 if (pi->caps_dynamic_ac_timing) { 5166 ret = ci_populate_initial_mc_reg_table(rdev); 5167 if (ret) { 5168 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n"); 5169 return ret; 5170 } 5171 } 5172 ret = ci_populate_pm_base(rdev); 5173 if (ret) { 5174 DRM_ERROR("ci_populate_pm_base failed\n"); 5175 return ret; 5176 } 5177 ci_dpm_start_smc(rdev); 5178 ci_enable_vr_hot_gpio_interrupt(rdev); 5179 ret = ci_notify_smc_display_change(rdev, false); 5180 if (ret) { 5181 DRM_ERROR("ci_notify_smc_display_change failed\n"); 5182 return ret; 5183 } 5184 ci_enable_sclk_control(rdev, true); 5185 ret = ci_enable_ulv(rdev, true); 5186 if (ret) { 5187 DRM_ERROR("ci_enable_ulv failed\n"); 5188 return ret; 5189 } 5190 ret = ci_enable_ds_master_switch(rdev, true); 5191 if (ret) { 5192 DRM_ERROR("ci_enable_ds_master_switch failed\n"); 5193 return ret; 5194 } 5195 ret = ci_start_dpm(rdev); 5196 if (ret) { 5197 DRM_ERROR("ci_start_dpm failed\n"); 5198 return ret; 5199 } 5200 ret = ci_enable_didt(rdev, true); 5201 if (ret) { 5202 DRM_ERROR("ci_enable_didt failed\n"); 5203 return ret; 5204 } 5205 ret = ci_enable_smc_cac(rdev, true); 5206 if (ret) { 5207 DRM_ERROR("ci_enable_smc_cac failed\n"); 5208 return ret; 5209 } 5210 ret = ci_enable_power_containment(rdev, true); 5211 if (ret) { 5212 DRM_ERROR("ci_enable_power_containment failed\n"); 5213 return ret; 5214 } 5215 5216 ret = ci_power_control_set_level(rdev); 5217 if (ret) { 5218 DRM_ERROR("ci_power_control_set_level failed\n"); 5219 return ret; 5220 } 5221 5222 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5223 5224 ret = ci_enable_thermal_based_sclk_dpm(rdev, true); 5225 if (ret) { 5226 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n"); 5227 return ret; 5228 } 5229 5230 ci_thermal_start_thermal_controller(rdev); 5231 5232 ci_update_current_ps(rdev, boot_ps); 5233 5234 return 0; 5235 } 5236 5237 static int ci_set_temperature_range(struct radeon_device *rdev) 5238 { 5239 int ret; 5240 5241 ret = ci_thermal_enable_alert(rdev, false); 5242 if (ret) 5243 return ret; 5244 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5245 if (ret) 5246 return ret; 5247 ret = ci_thermal_enable_alert(rdev, true); 5248 if (ret) 5249 return ret; 5250 5251 return ret; 5252 } 5253 5254 int ci_dpm_late_enable(struct radeon_device *rdev) 5255 { 5256 int ret; 5257 5258 ret = ci_set_temperature_range(rdev); 5259 if (ret) 5260 return ret; 5261 5262 ci_dpm_powergate_uvd(rdev, true); 5263 5264 return 0; 5265 } 5266 5267 void ci_dpm_disable(struct radeon_device *rdev) 5268 { 5269 struct ci_power_info *pi = ci_get_pi(rdev); 5270 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5271 5272 ci_dpm_powergate_uvd(rdev, false); 5273 5274 if (!ci_is_smc_running(rdev)) 5275 return; 5276 5277 ci_thermal_stop_thermal_controller(rdev); 5278 5279 if (pi->thermal_protection) 5280 ci_enable_thermal_protection(rdev, false); 5281 ci_enable_power_containment(rdev, false); 5282 ci_enable_smc_cac(rdev, false); 5283 ci_enable_didt(rdev, false); 5284 ci_enable_spread_spectrum(rdev, false); 5285 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 5286 ci_stop_dpm(rdev); 5287 ci_enable_ds_master_switch(rdev, false); 5288 ci_enable_ulv(rdev, false); 5289 ci_clear_vc(rdev); 5290 ci_reset_to_default(rdev); 5291 ci_dpm_stop_smc(rdev); 5292 ci_force_switch_to_arb_f0(rdev); 5293 ci_enable_thermal_based_sclk_dpm(rdev, false); 5294 5295 ci_update_current_ps(rdev, boot_ps); 5296 } 5297 5298 int ci_dpm_set_power_state(struct radeon_device *rdev) 5299 { 5300 struct ci_power_info *pi = ci_get_pi(rdev); 5301 struct radeon_ps *new_ps = &pi->requested_rps; 5302 struct radeon_ps *old_ps = &pi->current_rps; 5303 int ret; 5304 5305 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps); 5306 if (pi->pcie_performance_request) 5307 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 5308 ret = ci_freeze_sclk_mclk_dpm(rdev); 5309 if (ret) { 5310 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n"); 5311 return ret; 5312 } 5313 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps); 5314 if (ret) { 5315 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n"); 5316 return ret; 5317 } 5318 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps); 5319 if (ret) { 5320 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n"); 5321 return ret; 5322 } 5323 5324 ret = ci_update_vce_dpm(rdev, new_ps, old_ps); 5325 if (ret) { 5326 DRM_ERROR("ci_update_vce_dpm failed\n"); 5327 return ret; 5328 } 5329 5330 ret = ci_update_sclk_t(rdev); 5331 if (ret) { 5332 DRM_ERROR("ci_update_sclk_t failed\n"); 5333 return ret; 5334 } 5335 if (pi->caps_dynamic_ac_timing) { 5336 ret = ci_update_and_upload_mc_reg_table(rdev); 5337 if (ret) { 5338 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n"); 5339 return ret; 5340 } 5341 } 5342 ret = ci_program_memory_timing_parameters(rdev); 5343 if (ret) { 5344 DRM_ERROR("ci_program_memory_timing_parameters failed\n"); 5345 return ret; 5346 } 5347 ret = ci_unfreeze_sclk_mclk_dpm(rdev); 5348 if (ret) { 5349 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n"); 5350 return ret; 5351 } 5352 ret = ci_upload_dpm_level_enable_mask(rdev); 5353 if (ret) { 5354 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n"); 5355 return ret; 5356 } 5357 if (pi->pcie_performance_request) 5358 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 5359 5360 return 0; 5361 } 5362 5363 #if 0 5364 void ci_dpm_reset_asic(struct radeon_device *rdev) 5365 { 5366 ci_set_boot_state(rdev); 5367 } 5368 #endif 5369 5370 void ci_dpm_display_configuration_changed(struct radeon_device *rdev) 5371 { 5372 ci_program_display_gap(rdev); 5373 } 5374 5375 union power_info { 5376 struct _ATOM_POWERPLAY_INFO info; 5377 struct _ATOM_POWERPLAY_INFO_V2 info_2; 5378 struct _ATOM_POWERPLAY_INFO_V3 info_3; 5379 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 5380 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 5381 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 5382 }; 5383 5384 union pplib_clock_info { 5385 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 5386 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 5387 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 5388 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 5389 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 5390 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 5391 }; 5392 5393 union pplib_power_state { 5394 struct _ATOM_PPLIB_STATE v1; 5395 struct _ATOM_PPLIB_STATE_V2 v2; 5396 }; 5397 5398 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev, 5399 struct radeon_ps *rps, 5400 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 5401 u8 table_rev) 5402 { 5403 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 5404 rps->class = le16_to_cpu(non_clock_info->usClassification); 5405 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 5406 5407 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 5408 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 5409 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 5410 } else { 5411 rps->vclk = 0; 5412 rps->dclk = 0; 5413 } 5414 5415 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 5416 rdev->pm.dpm.boot_ps = rps; 5417 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 5418 rdev->pm.dpm.uvd_ps = rps; 5419 } 5420 5421 static void ci_parse_pplib_clock_info(struct radeon_device *rdev, 5422 struct radeon_ps *rps, int index, 5423 union pplib_clock_info *clock_info) 5424 { 5425 struct ci_power_info *pi = ci_get_pi(rdev); 5426 struct ci_ps *ps = ci_get_ps(rps); 5427 struct ci_pl *pl = &ps->performance_levels[index]; 5428 5429 ps->performance_level_count = index + 1; 5430 5431 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 5432 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16; 5433 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 5434 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16; 5435 5436 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 5437 pi->sys_pcie_mask, 5438 pi->vbios_boot_state.pcie_gen_bootup_value, 5439 clock_info->ci.ucPCIEGen); 5440 pl->pcie_lane = r600_get_pcie_lane_support(rdev, 5441 pi->vbios_boot_state.pcie_lane_bootup_value, 5442 le16_to_cpu(clock_info->ci.usPCIELane)); 5443 5444 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 5445 pi->acpi_pcie_gen = pl->pcie_gen; 5446 } 5447 5448 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { 5449 pi->ulv.supported = true; 5450 pi->ulv.pl = *pl; 5451 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; 5452 } 5453 5454 /* patch up boot state */ 5455 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 5456 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; 5457 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; 5458 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; 5459 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; 5460 } 5461 5462 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 5463 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 5464 pi->use_pcie_powersaving_levels = true; 5465 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) 5466 pi->pcie_gen_powersaving.max = pl->pcie_gen; 5467 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) 5468 pi->pcie_gen_powersaving.min = pl->pcie_gen; 5469 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) 5470 pi->pcie_lane_powersaving.max = pl->pcie_lane; 5471 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) 5472 pi->pcie_lane_powersaving.min = pl->pcie_lane; 5473 break; 5474 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 5475 pi->use_pcie_performance_levels = true; 5476 if (pi->pcie_gen_performance.max < pl->pcie_gen) 5477 pi->pcie_gen_performance.max = pl->pcie_gen; 5478 if (pi->pcie_gen_performance.min > pl->pcie_gen) 5479 pi->pcie_gen_performance.min = pl->pcie_gen; 5480 if (pi->pcie_lane_performance.max < pl->pcie_lane) 5481 pi->pcie_lane_performance.max = pl->pcie_lane; 5482 if (pi->pcie_lane_performance.min > pl->pcie_lane) 5483 pi->pcie_lane_performance.min = pl->pcie_lane; 5484 break; 5485 default: 5486 break; 5487 } 5488 } 5489 5490 static int ci_parse_power_table(struct radeon_device *rdev) 5491 { 5492 struct radeon_mode_info *mode_info = &rdev->mode_info; 5493 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 5494 union pplib_power_state *power_state; 5495 int i, j, k, non_clock_array_index, clock_array_index; 5496 union pplib_clock_info *clock_info; 5497 struct _StateArray *state_array; 5498 struct _ClockInfoArray *clock_info_array; 5499 struct _NonClockInfoArray *non_clock_info_array; 5500 union power_info *power_info; 5501 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 5502 u16 data_offset; 5503 u8 frev, crev; 5504 u8 *power_state_offset; 5505 struct ci_ps *ps; 5506 int ret; 5507 5508 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 5509 &frev, &crev, &data_offset)) 5510 return -EINVAL; 5511 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 5512 5513 state_array = (struct _StateArray *) 5514 (mode_info->atom_context->bios + data_offset + 5515 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 5516 clock_info_array = (struct _ClockInfoArray *) 5517 (mode_info->atom_context->bios + data_offset + 5518 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 5519 non_clock_info_array = (struct _NonClockInfoArray *) 5520 (mode_info->atom_context->bios + data_offset + 5521 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 5522 5523 rdev->pm.dpm.ps = kzalloc_objs(struct radeon_ps, 5524 state_array->ucNumEntries); 5525 if (!rdev->pm.dpm.ps) 5526 return -ENOMEM; 5527 power_state_offset = (u8 *)state_array->states; 5528 rdev->pm.dpm.num_ps = 0; 5529 for (i = 0; i < state_array->ucNumEntries; i++) { 5530 u8 *idx; 5531 power_state = (union pplib_power_state *)power_state_offset; 5532 non_clock_array_index = power_state->v2.nonClockInfoIndex; 5533 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 5534 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 5535 if (!rdev->pm.power_state[i].clock_info) { 5536 ret = -EINVAL; 5537 goto err_free_ps; 5538 } 5539 ps = kzalloc_obj(struct ci_ps); 5540 if (ps == NULL) { 5541 ret = -ENOMEM; 5542 goto err_free_ps; 5543 } 5544 rdev->pm.dpm.ps[i].ps_priv = ps; 5545 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 5546 non_clock_info, 5547 non_clock_info_array->ucEntrySize); 5548 k = 0; 5549 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 5550 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 5551 clock_array_index = idx[j]; 5552 if (clock_array_index >= clock_info_array->ucNumEntries) 5553 continue; 5554 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS) 5555 break; 5556 clock_info = (union pplib_clock_info *) 5557 ((u8 *)&clock_info_array->clockInfo[0] + 5558 (clock_array_index * clock_info_array->ucEntrySize)); 5559 ci_parse_pplib_clock_info(rdev, 5560 &rdev->pm.dpm.ps[i], k, 5561 clock_info); 5562 k++; 5563 } 5564 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 5565 rdev->pm.dpm.num_ps = i + 1; 5566 } 5567 5568 /* fill in the vce power states */ 5569 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 5570 u32 sclk, mclk; 5571 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 5572 clock_info = (union pplib_clock_info *) 5573 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 5574 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 5575 sclk |= clock_info->ci.ucEngineClockHigh << 16; 5576 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 5577 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 5578 rdev->pm.dpm.vce_states[i].sclk = sclk; 5579 rdev->pm.dpm.vce_states[i].mclk = mclk; 5580 } 5581 5582 return 0; 5583 5584 err_free_ps: 5585 for (i = 0; i < rdev->pm.dpm.num_ps; i++) 5586 kfree(rdev->pm.dpm.ps[i].ps_priv); 5587 kfree(rdev->pm.dpm.ps); 5588 return ret; 5589 } 5590 5591 static int ci_get_vbios_boot_values(struct radeon_device *rdev, 5592 struct ci_vbios_boot_state *boot_state) 5593 { 5594 struct radeon_mode_info *mode_info = &rdev->mode_info; 5595 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 5596 ATOM_FIRMWARE_INFO_V2_2 *firmware_info; 5597 u8 frev, crev; 5598 u16 data_offset; 5599 5600 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 5601 &frev, &crev, &data_offset)) { 5602 firmware_info = 5603 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios + 5604 data_offset); 5605 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage); 5606 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage); 5607 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage); 5608 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev); 5609 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev); 5610 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock); 5611 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock); 5612 5613 return 0; 5614 } 5615 return -EINVAL; 5616 } 5617 5618 void ci_dpm_fini(struct radeon_device *rdev) 5619 { 5620 int i; 5621 5622 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 5623 kfree(rdev->pm.dpm.ps[i].ps_priv); 5624 } 5625 kfree(rdev->pm.dpm.ps); 5626 kfree(rdev->pm.dpm.priv); 5627 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 5628 r600_free_extended_power_table(rdev); 5629 } 5630 5631 int ci_dpm_init(struct radeon_device *rdev) 5632 { 5633 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 5634 SMU7_Discrete_DpmTable *dpm_table; 5635 struct radeon_gpio_rec gpio; 5636 u16 data_offset, size; 5637 u8 frev, crev; 5638 struct ci_power_info *pi; 5639 enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN; 5640 struct pci_dev *root = rdev->pdev->bus->self; 5641 int ret; 5642 5643 pi = kzalloc_obj(struct ci_power_info); 5644 if (pi == NULL) 5645 return -ENOMEM; 5646 rdev->pm.dpm.priv = pi; 5647 5648 if (!pci_is_root_bus(rdev->pdev->bus)) 5649 speed_cap = pcie_get_speed_cap(root); 5650 if (speed_cap == PCI_SPEED_UNKNOWN) { 5651 pi->sys_pcie_mask = 0; 5652 } else { 5653 if (speed_cap == PCIE_SPEED_8_0GT) 5654 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 5655 RADEON_PCIE_SPEED_50 | 5656 RADEON_PCIE_SPEED_80; 5657 else if (speed_cap == PCIE_SPEED_5_0GT) 5658 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 5659 RADEON_PCIE_SPEED_50; 5660 else 5661 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; 5662 } 5663 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5664 5665 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; 5666 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; 5667 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; 5668 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; 5669 5670 pi->pcie_lane_performance.max = 0; 5671 pi->pcie_lane_performance.min = 16; 5672 pi->pcie_lane_powersaving.max = 0; 5673 pi->pcie_lane_powersaving.min = 16; 5674 5675 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); 5676 if (ret) { 5677 kfree(rdev->pm.dpm.priv); 5678 return ret; 5679 } 5680 5681 ret = r600_get_platform_caps(rdev); 5682 if (ret) { 5683 kfree(rdev->pm.dpm.priv); 5684 return ret; 5685 } 5686 5687 ret = r600_parse_extended_power_table(rdev); 5688 if (ret) { 5689 kfree(rdev->pm.dpm.priv); 5690 return ret; 5691 } 5692 5693 ret = ci_parse_power_table(rdev); 5694 if (ret) { 5695 kfree(rdev->pm.dpm.priv); 5696 r600_free_extended_power_table(rdev); 5697 return ret; 5698 } 5699 5700 pi->dll_default_on = false; 5701 pi->sram_end = SMC_RAM_END; 5702 5703 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; 5704 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; 5705 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; 5706 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; 5707 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; 5708 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; 5709 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; 5710 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; 5711 5712 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; 5713 5714 pi->sclk_dpm_key_disabled = 0; 5715 pi->mclk_dpm_key_disabled = 0; 5716 pi->pcie_dpm_key_disabled = 0; 5717 pi->thermal_sclk_dpm_enabled = 0; 5718 5719 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */ 5720 if ((rdev->pdev->device == 0x6658) && 5721 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) { 5722 pi->mclk_dpm_key_disabled = 1; 5723 } 5724 5725 pi->caps_sclk_ds = true; 5726 5727 pi->mclk_strobe_mode_threshold = 40000; 5728 pi->mclk_stutter_mode_threshold = 40000; 5729 pi->mclk_edc_enable_threshold = 40000; 5730 pi->mclk_edc_wr_enable_threshold = 40000; 5731 5732 ci_initialize_powertune_defaults(rdev); 5733 5734 pi->caps_fps = false; 5735 5736 pi->caps_sclk_throttle_low_notification = false; 5737 5738 pi->caps_uvd_dpm = true; 5739 pi->caps_vce_dpm = true; 5740 5741 ci_get_leakage_voltages(rdev); 5742 ci_patch_dependency_tables_with_leakage(rdev); 5743 ci_set_private_data_variables_based_on_pptable(rdev); 5744 5745 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 5746 kzalloc_objs(struct radeon_clock_voltage_dependency_entry, 4); 5747 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 5748 ci_dpm_fini(rdev); 5749 return -ENOMEM; 5750 } 5751 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 5752 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 5753 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 5754 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 5755 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 5756 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 5757 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 5758 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 5759 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 5760 5761 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 5762 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 5763 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 5764 5765 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 5766 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 5767 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 5768 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 5769 5770 if (rdev->family == CHIP_HAWAII) { 5771 pi->thermal_temp_setting.temperature_low = 94500; 5772 pi->thermal_temp_setting.temperature_high = 95000; 5773 pi->thermal_temp_setting.temperature_shutdown = 104000; 5774 } else { 5775 pi->thermal_temp_setting.temperature_low = 99500; 5776 pi->thermal_temp_setting.temperature_high = 100000; 5777 pi->thermal_temp_setting.temperature_shutdown = 104000; 5778 } 5779 5780 pi->uvd_enabled = false; 5781 5782 dpm_table = &pi->smc_state_table; 5783 5784 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID); 5785 if (gpio.valid) { 5786 dpm_table->VRHotGpio = gpio.shift; 5787 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; 5788 } else { 5789 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN; 5790 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; 5791 } 5792 5793 gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID); 5794 if (gpio.valid) { 5795 dpm_table->AcDcGpio = gpio.shift; 5796 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC; 5797 } else { 5798 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN; 5799 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC; 5800 } 5801 5802 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID); 5803 if (gpio.valid) { 5804 u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL); 5805 5806 switch (gpio.shift) { 5807 case 0: 5808 tmp &= ~GNB_SLOW_MODE_MASK; 5809 tmp |= GNB_SLOW_MODE(1); 5810 break; 5811 case 1: 5812 tmp &= ~GNB_SLOW_MODE_MASK; 5813 tmp |= GNB_SLOW_MODE(2); 5814 break; 5815 case 2: 5816 tmp |= GNB_SLOW; 5817 break; 5818 case 3: 5819 tmp |= FORCE_NB_PS1; 5820 break; 5821 case 4: 5822 tmp |= DPM_ENABLED; 5823 break; 5824 default: 5825 DRM_DEBUG("Invalid PCC GPIO: %u!\n", gpio.shift); 5826 break; 5827 } 5828 WREG32_SMC(CNB_PWRMGT_CNTL, tmp); 5829 } 5830 5831 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5832 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5833 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5834 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) 5835 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5836 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) 5837 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5838 5839 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { 5840 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 5841 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5842 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) 5843 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5844 else 5845 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; 5846 } 5847 5848 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { 5849 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) 5850 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5851 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) 5852 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5853 else 5854 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; 5855 } 5856 5857 pi->vddc_phase_shed_control = true; 5858 5859 #if defined(CONFIG_ACPI) 5860 pi->pcie_performance_request = 5861 radeon_acpi_is_pcie_performance_request_supported(rdev); 5862 #else 5863 pi->pcie_performance_request = false; 5864 #endif 5865 5866 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 5867 &frev, &crev, &data_offset)) { 5868 pi->caps_sclk_ss_support = true; 5869 pi->caps_mclk_ss_support = true; 5870 pi->dynamic_ss = true; 5871 } else { 5872 pi->caps_sclk_ss_support = false; 5873 pi->caps_mclk_ss_support = false; 5874 pi->dynamic_ss = true; 5875 } 5876 5877 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 5878 pi->thermal_protection = true; 5879 else 5880 pi->thermal_protection = false; 5881 5882 pi->caps_dynamic_ac_timing = true; 5883 5884 pi->uvd_power_gated = false; 5885 5886 /* make sure dc limits are valid */ 5887 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 5888 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 5889 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 5890 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 5891 5892 pi->fan_ctrl_is_in_default_mode = true; 5893 5894 return 0; 5895 } 5896 5897 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 5898 struct seq_file *m) 5899 { 5900 struct ci_power_info *pi = ci_get_pi(rdev); 5901 struct radeon_ps *rps = &pi->current_rps; 5902 u32 sclk = ci_get_average_sclk_freq(rdev); 5903 u32 mclk = ci_get_average_mclk_freq(rdev); 5904 5905 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); 5906 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis"); 5907 seq_printf(m, "power level avg sclk: %u mclk: %u\n", 5908 sclk, mclk); 5909 } 5910 5911 void ci_dpm_print_power_state(struct radeon_device *rdev, 5912 struct radeon_ps *rps) 5913 { 5914 struct ci_ps *ps = ci_get_ps(rps); 5915 struct ci_pl *pl; 5916 int i; 5917 5918 r600_dpm_print_class_info(rps->class, rps->class2); 5919 r600_dpm_print_cap_info(rps->caps); 5920 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 5921 for (i = 0; i < ps->performance_level_count; i++) { 5922 pl = &ps->performance_levels[i]; 5923 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n", 5924 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane); 5925 } 5926 r600_dpm_print_ps_status(rdev, rps); 5927 } 5928 5929 u32 ci_dpm_get_current_sclk(struct radeon_device *rdev) 5930 { 5931 u32 sclk = ci_get_average_sclk_freq(rdev); 5932 5933 return sclk; 5934 } 5935 5936 u32 ci_dpm_get_current_mclk(struct radeon_device *rdev) 5937 { 5938 u32 mclk = ci_get_average_mclk_freq(rdev); 5939 5940 return mclk; 5941 } 5942 5943 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low) 5944 { 5945 struct ci_power_info *pi = ci_get_pi(rdev); 5946 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 5947 5948 if (low) 5949 return requested_state->performance_levels[0].sclk; 5950 else 5951 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 5952 } 5953 5954 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low) 5955 { 5956 struct ci_power_info *pi = ci_get_pi(rdev); 5957 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 5958 5959 if (low) 5960 return requested_state->performance_levels[0].mclk; 5961 else 5962 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 5963 } 5964