1 /*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27
28 #include <linux/file.h>
29 #include <linux/pagemap.h>
30 #include <linux/sync_file.h>
31 #include <linux/dma-buf.h>
32
33 #include <drm/amdgpu_drm.h>
34 #include <drm/drm_syncobj.h>
35 #include <drm/ttm/ttm_tt.h>
36
37 #include "amdgpu_cs.h"
38 #include "amdgpu.h"
39 #include "amdgpu_trace.h"
40 #include "amdgpu_gmc.h"
41 #include "amdgpu_gem.h"
42 #include "amdgpu_ras.h"
43 #include "amdgpu_hmm.h"
44
45 /*
46 * Maximum IB length (dwords) for rings whose emit_ib packet format
47 * documents a 20-bit size field.
48 */
49 #define AMDGPU_GFX_SDMA_IB_PACKET_SIZE_MAX_DW 0xFFFFF
50 #define AMDGPU_MM_IB_PACKET_SIZE_MAX_DW 0x7FFFF0
51
amdgpu_cs_ib_packet_size_max_dw(enum amdgpu_ring_type type)52 static u32 amdgpu_cs_ib_packet_size_max_dw(enum amdgpu_ring_type type)
53 {
54 switch (type) {
55 case AMDGPU_RING_TYPE_GFX:
56 case AMDGPU_RING_TYPE_COMPUTE:
57 case AMDGPU_RING_TYPE_SDMA:
58 case AMDGPU_RING_TYPE_VPE:
59 return AMDGPU_GFX_SDMA_IB_PACKET_SIZE_MAX_DW;
60 default:
61 return AMDGPU_MM_IB_PACKET_SIZE_MAX_DW;
62 }
63 }
64
amdgpu_cs_parser_init(struct amdgpu_cs_parser * p,struct amdgpu_device * adev,struct drm_file * filp,union drm_amdgpu_cs * cs)65 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p,
66 struct amdgpu_device *adev,
67 struct drm_file *filp,
68 union drm_amdgpu_cs *cs)
69 {
70 struct amdgpu_fpriv *fpriv = filp->driver_priv;
71
72 if (cs->in.num_chunks == 0)
73 return -EINVAL;
74
75 memset(p, 0, sizeof(*p));
76 p->adev = adev;
77 p->filp = filp;
78
79 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
80 if (!p->ctx)
81 return -EINVAL;
82
83 amdgpu_sync_create(&p->sync);
84 drm_exec_init(&p->exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
85 DRM_EXEC_IGNORE_DUPLICATES, 0);
86 return 0;
87 }
88
amdgpu_cs_job_idx(struct amdgpu_cs_parser * p,struct drm_amdgpu_cs_chunk_ib * chunk_ib)89 static int amdgpu_cs_job_idx(struct amdgpu_cs_parser *p,
90 struct drm_amdgpu_cs_chunk_ib *chunk_ib)
91 {
92 struct drm_sched_entity *entity;
93 unsigned int i;
94 int r;
95
96 r = amdgpu_ctx_get_entity(p->ctx, chunk_ib->ip_type,
97 chunk_ib->ip_instance,
98 chunk_ib->ring, &entity);
99 if (r)
100 return r;
101
102 /* Check if we can add this IB to some existing job */
103 for (i = 0; i < p->gang_size; ++i)
104 if (p->entities[i] == entity)
105 return i;
106
107 /* If not increase the gang size if possible */
108 if (i == AMDGPU_CS_GANG_SIZE)
109 return -EINVAL;
110
111 p->entities[i] = entity;
112 p->gang_size = i + 1;
113 return i;
114 }
115
amdgpu_cs_p1_ib(struct amdgpu_cs_parser * p,struct drm_amdgpu_cs_chunk_ib * chunk_ib,unsigned int * num_ibs)116 static int amdgpu_cs_p1_ib(struct amdgpu_cs_parser *p,
117 struct drm_amdgpu_cs_chunk_ib *chunk_ib,
118 unsigned int *num_ibs)
119 {
120 int r;
121
122 r = amdgpu_cs_job_idx(p, chunk_ib);
123 if (r < 0)
124 return r;
125
126 if (num_ibs[r] >= amdgpu_ring_max_ibs(chunk_ib->ip_type))
127 return -EINVAL;
128
129 ++(num_ibs[r]);
130 p->gang_leader_idx = r;
131 return 0;
132 }
133
amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser * p,struct drm_amdgpu_cs_chunk_fence * data,uint32_t * offset)134 static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p,
135 struct drm_amdgpu_cs_chunk_fence *data,
136 uint32_t *offset)
137 {
138 struct drm_gem_object *gobj;
139 unsigned long size;
140
141 gobj = drm_gem_object_lookup(p->filp, data->handle);
142 if (gobj == NULL)
143 return -EINVAL;
144
145 p->uf_bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
146 drm_gem_object_put(gobj);
147
148 size = amdgpu_bo_size(p->uf_bo);
149 if (size != PAGE_SIZE || data->offset > (size - 8))
150 return -EINVAL;
151
152 if (amdgpu_ttm_tt_get_usermm(p->uf_bo->tbo.ttm))
153 return -EINVAL;
154
155 *offset = data->offset;
156 return 0;
157 }
158
amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser * p,struct drm_amdgpu_bo_list_in * data)159 static int amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser *p,
160 struct drm_amdgpu_bo_list_in *data)
161 {
162 struct drm_amdgpu_bo_list_entry *info;
163 int r;
164
165 r = amdgpu_bo_create_list_entry_array(data, &info);
166 if (r)
167 return r;
168
169 r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
170 &p->bo_list);
171 if (r)
172 goto error_free;
173
174 kvfree(info);
175 return 0;
176
177 error_free:
178 kvfree(info);
179
180 return r;
181 }
182
183 /* Copy the data from userspace and go over it the first time */
amdgpu_cs_pass1(struct amdgpu_cs_parser * p,union drm_amdgpu_cs * cs)184 static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
185 union drm_amdgpu_cs *cs)
186 {
187 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
188 unsigned int num_ibs[AMDGPU_CS_GANG_SIZE] = { };
189 struct amdgpu_vm *vm = &fpriv->vm;
190 uint64_t *chunk_array;
191 uint32_t uf_offset = 0;
192 size_t size;
193 int ret;
194 int i;
195
196 chunk_array = memdup_array_user(u64_to_user_ptr(cs->in.chunks),
197 cs->in.num_chunks,
198 sizeof(uint64_t));
199 if (IS_ERR(chunk_array))
200 return PTR_ERR(chunk_array);
201
202 p->nchunks = cs->in.num_chunks;
203 p->chunks = kvmalloc_objs(struct amdgpu_cs_chunk, p->nchunks);
204 if (!p->chunks) {
205 ret = -ENOMEM;
206 goto free_chunk;
207 }
208
209 for (i = 0; i < p->nchunks; i++) {
210 struct drm_amdgpu_cs_chunk __user *chunk_ptr = NULL;
211 struct drm_amdgpu_cs_chunk user_chunk;
212
213 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
214 if (copy_from_user(&user_chunk, chunk_ptr,
215 sizeof(struct drm_amdgpu_cs_chunk))) {
216 ret = -EFAULT;
217 i--;
218 goto free_partial_kdata;
219 }
220 p->chunks[i].chunk_id = user_chunk.chunk_id;
221 p->chunks[i].length_dw = user_chunk.length_dw;
222
223 size = p->chunks[i].length_dw;
224
225 p->chunks[i].kdata = vmemdup_array_user(u64_to_user_ptr(user_chunk.chunk_data),
226 size,
227 sizeof(uint32_t));
228 if (IS_ERR(p->chunks[i].kdata)) {
229 ret = PTR_ERR(p->chunks[i].kdata);
230 i--;
231 goto free_partial_kdata;
232 }
233 size *= sizeof(uint32_t);
234
235 /* Assume the worst on the following checks */
236 ret = -EINVAL;
237 switch (p->chunks[i].chunk_id) {
238 case AMDGPU_CHUNK_ID_IB:
239 if (size < sizeof(struct drm_amdgpu_cs_chunk_ib))
240 goto free_partial_kdata;
241
242 ret = amdgpu_cs_p1_ib(p, p->chunks[i].kdata, num_ibs);
243 if (ret)
244 goto free_partial_kdata;
245 break;
246
247 case AMDGPU_CHUNK_ID_FENCE:
248 if (size < sizeof(struct drm_amdgpu_cs_chunk_fence))
249 goto free_partial_kdata;
250
251 /* Only a single user fence is allowed to simplify handling. */
252 if (p->uf_bo)
253 goto free_partial_kdata;
254
255 ret = amdgpu_cs_p1_user_fence(p, p->chunks[i].kdata,
256 &uf_offset);
257 if (ret)
258 goto free_partial_kdata;
259 break;
260
261 case AMDGPU_CHUNK_ID_BO_HANDLES:
262 if (size < sizeof(struct drm_amdgpu_bo_list_in))
263 goto free_partial_kdata;
264
265 /* Only a single BO list is allowed to simplify handling. */
266 if (p->bo_list)
267 goto free_partial_kdata;
268
269 ret = amdgpu_cs_p1_bo_handles(p, p->chunks[i].kdata);
270 if (ret)
271 goto free_partial_kdata;
272 break;
273
274 case AMDGPU_CHUNK_ID_CP_GFX_SHADOW:
275 if (size < sizeof(struct drm_amdgpu_cs_chunk_cp_gfx_shadow))
276 goto free_partial_kdata;
277 break;
278
279 case AMDGPU_CHUNK_ID_DEPENDENCIES:
280 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
281 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
282 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
283 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
284 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
285 break;
286
287 default:
288 goto free_partial_kdata;
289 }
290 }
291
292 if (!p->gang_size || (amdgpu_sriov_vf(p->adev) && p->gang_size > 1)) {
293 ret = -EINVAL;
294 goto free_all_kdata;
295 }
296
297 for (i = 0; i < p->gang_size; ++i) {
298 ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm,
299 num_ibs[i], &p->jobs[i],
300 p->filp->client_id);
301 if (ret)
302 goto free_all_kdata;
303 switch (p->adev->enforce_isolation[fpriv->xcp_id]) {
304 case AMDGPU_ENFORCE_ISOLATION_DISABLE:
305 default:
306 p->jobs[i]->enforce_isolation = false;
307 p->jobs[i]->run_cleaner_shader = false;
308 break;
309 case AMDGPU_ENFORCE_ISOLATION_ENABLE:
310 p->jobs[i]->enforce_isolation = true;
311 p->jobs[i]->run_cleaner_shader = true;
312 break;
313 case AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY:
314 p->jobs[i]->enforce_isolation = true;
315 p->jobs[i]->run_cleaner_shader = false;
316 break;
317 case AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER:
318 p->jobs[i]->enforce_isolation = true;
319 p->jobs[i]->run_cleaner_shader = false;
320 break;
321 }
322 }
323 p->gang_leader = p->jobs[p->gang_leader_idx];
324
325 if (p->ctx->generation != p->gang_leader->generation) {
326 ret = -ECANCELED;
327 goto free_all_kdata;
328 }
329
330 if (p->uf_bo)
331 p->gang_leader->uf_addr = uf_offset;
332 kvfree(chunk_array);
333
334 /* Use this opportunity to fill in task info for the vm */
335 amdgpu_vm_set_task_info(vm);
336
337 return 0;
338
339 free_all_kdata:
340 i = p->nchunks - 1;
341 free_partial_kdata:
342 for (; i >= 0; i--)
343 kvfree(p->chunks[i].kdata);
344 kvfree(p->chunks);
345 p->chunks = NULL;
346 p->nchunks = 0;
347 free_chunk:
348 kvfree(chunk_array);
349
350 return ret;
351 }
352
amdgpu_cs_p2_ib(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk,unsigned int * ce_preempt,unsigned int * de_preempt)353 static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p,
354 struct amdgpu_cs_chunk *chunk,
355 unsigned int *ce_preempt,
356 unsigned int *de_preempt)
357 {
358 struct drm_amdgpu_cs_chunk_ib *chunk_ib = chunk->kdata;
359 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
360 struct amdgpu_vm *vm = &fpriv->vm;
361 struct amdgpu_ring *ring;
362 struct amdgpu_job *job;
363 struct amdgpu_ib *ib;
364 int r;
365
366 r = amdgpu_cs_job_idx(p, chunk_ib);
367 if (r < 0)
368 return r;
369
370 job = p->jobs[r];
371 ring = amdgpu_job_ring(job);
372
373 /* submissions to kernel queues are disabled */
374 if (ring->no_user_submission)
375 return -EINVAL;
376
377 /* MM engine doesn't support user fences */
378 if (p->uf_bo && ring->funcs->no_user_fence)
379 return -EINVAL;
380
381 if (!p->adev->debug_enable_ce_cs &&
382 chunk_ib->flags & AMDGPU_IB_FLAG_CE) {
383 dev_err_ratelimited(p->adev->dev, "CE CS is blocked, use debug=0x400 to override\n");
384 return -EINVAL;
385 }
386
387 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
388 chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
389 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
390 (*ce_preempt)++;
391 else
392 (*de_preempt)++;
393
394 /* Each GFX command submit allows only 1 IB max
395 * preemptible for CE & DE */
396 if (*ce_preempt > 1 || *de_preempt > 1)
397 return -EINVAL;
398 }
399
400 if (chunk_ib->ib_bytes / 4 >
401 amdgpu_cs_ib_packet_size_max_dw(ring->funcs->type))
402 return -EINVAL;
403
404 ib = &job->ibs[job->num_ibs++];
405
406 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
407 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
408
409 r = amdgpu_ib_get(p->adev, vm, ring->funcs->parse_cs ?
410 chunk_ib->ib_bytes : 0,
411 AMDGPU_IB_POOL_DELAYED, ib);
412 if (r) {
413 drm_err(adev_to_drm(p->adev), "Failed to get ib !\n");
414 return r;
415 }
416
417 ib->gpu_addr = chunk_ib->va_start;
418 ib->length_dw = chunk_ib->ib_bytes / 4;
419 ib->flags = chunk_ib->flags;
420 return 0;
421 }
422
amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)423 static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p,
424 struct amdgpu_cs_chunk *chunk)
425 {
426 struct drm_amdgpu_cs_chunk_dep *deps = chunk->kdata;
427 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
428 unsigned int num_deps;
429 int i, r;
430
431 num_deps = chunk->length_dw * 4 /
432 sizeof(struct drm_amdgpu_cs_chunk_dep);
433
434 for (i = 0; i < num_deps; ++i) {
435 struct amdgpu_ctx *ctx;
436 struct drm_sched_entity *entity;
437 struct dma_fence *fence;
438
439 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
440 if (ctx == NULL)
441 return -EINVAL;
442
443 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
444 deps[i].ip_instance,
445 deps[i].ring, &entity);
446 if (r) {
447 amdgpu_ctx_put(ctx);
448 return r;
449 }
450
451 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
452 amdgpu_ctx_put(ctx);
453
454 if (IS_ERR(fence))
455 return PTR_ERR(fence);
456 else if (!fence)
457 continue;
458
459 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
460 struct drm_sched_fence *s_fence;
461 struct dma_fence *old = fence;
462
463 s_fence = to_drm_sched_fence(fence);
464 fence = dma_fence_get(&s_fence->scheduled);
465 dma_fence_put(old);
466 }
467
468 r = amdgpu_sync_fence(&p->sync, fence, GFP_KERNEL);
469 dma_fence_put(fence);
470 if (r)
471 return r;
472 }
473 return 0;
474 }
475
amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser * p,uint32_t handle,u64 point,u64 flags)476 static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p,
477 uint32_t handle, u64 point,
478 u64 flags)
479 {
480 struct dma_fence *fence;
481 int r;
482
483 r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
484 if (r) {
485 drm_err(adev_to_drm(p->adev), "syncobj %u failed to find fence @ %llu (%d)!\n",
486 handle, point, r);
487 return r;
488 }
489
490 r = amdgpu_sync_fence(&p->sync, fence, GFP_KERNEL);
491 dma_fence_put(fence);
492 return r;
493 }
494
amdgpu_cs_p2_syncobj_in(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)495 static int amdgpu_cs_p2_syncobj_in(struct amdgpu_cs_parser *p,
496 struct amdgpu_cs_chunk *chunk)
497 {
498 struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
499 unsigned int num_deps;
500 int i, r;
501
502 num_deps = chunk->length_dw * 4 /
503 sizeof(struct drm_amdgpu_cs_chunk_sem);
504 for (i = 0; i < num_deps; ++i) {
505 r = amdgpu_syncobj_lookup_and_add(p, deps[i].handle, 0, 0);
506 if (r)
507 return r;
508 }
509
510 return 0;
511 }
512
amdgpu_cs_p2_syncobj_timeline_wait(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)513 static int amdgpu_cs_p2_syncobj_timeline_wait(struct amdgpu_cs_parser *p,
514 struct amdgpu_cs_chunk *chunk)
515 {
516 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
517 unsigned int num_deps;
518 int i, r;
519
520 num_deps = chunk->length_dw * 4 /
521 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
522 for (i = 0; i < num_deps; ++i) {
523 r = amdgpu_syncobj_lookup_and_add(p, syncobj_deps[i].handle,
524 syncobj_deps[i].point,
525 syncobj_deps[i].flags);
526 if (r)
527 return r;
528 }
529
530 return 0;
531 }
532
amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)533 static int amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser *p,
534 struct amdgpu_cs_chunk *chunk)
535 {
536 struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
537 unsigned int num_deps;
538 int i;
539
540 num_deps = chunk->length_dw * 4 /
541 sizeof(struct drm_amdgpu_cs_chunk_sem);
542
543 if (p->post_deps)
544 return -EINVAL;
545
546 p->post_deps = kmalloc_objs(*p->post_deps, num_deps);
547 p->num_post_deps = 0;
548
549 if (!p->post_deps)
550 return -ENOMEM;
551
552
553 for (i = 0; i < num_deps; ++i) {
554 p->post_deps[i].syncobj =
555 drm_syncobj_find(p->filp, deps[i].handle);
556 if (!p->post_deps[i].syncobj)
557 return -EINVAL;
558 p->post_deps[i].chain = NULL;
559 p->post_deps[i].point = 0;
560 p->num_post_deps++;
561 }
562
563 return 0;
564 }
565
amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)566 static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p,
567 struct amdgpu_cs_chunk *chunk)
568 {
569 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
570 unsigned int num_deps;
571 int i;
572
573 num_deps = chunk->length_dw * 4 /
574 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
575
576 if (p->post_deps)
577 return -EINVAL;
578
579 p->post_deps = kmalloc_objs(*p->post_deps, num_deps);
580 p->num_post_deps = 0;
581
582 if (!p->post_deps)
583 return -ENOMEM;
584
585 for (i = 0; i < num_deps; ++i) {
586 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
587
588 dep->chain = NULL;
589 if (syncobj_deps[i].point) {
590 dep->chain = dma_fence_chain_alloc();
591 if (!dep->chain)
592 return -ENOMEM;
593 }
594
595 dep->syncobj = drm_syncobj_find(p->filp,
596 syncobj_deps[i].handle);
597 if (!dep->syncobj) {
598 dma_fence_chain_free(dep->chain);
599 return -EINVAL;
600 }
601 dep->point = syncobj_deps[i].point;
602 p->num_post_deps++;
603 }
604
605 return 0;
606 }
607
amdgpu_cs_p2_shadow(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)608 static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p,
609 struct amdgpu_cs_chunk *chunk)
610 {
611 struct drm_amdgpu_cs_chunk_cp_gfx_shadow *shadow = chunk->kdata;
612 int i;
613
614 if (shadow->flags & ~AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW)
615 return -EINVAL;
616
617 for (i = 0; i < p->gang_size; ++i) {
618 p->jobs[i]->shadow_va = shadow->shadow_va;
619 p->jobs[i]->csa_va = shadow->csa_va;
620 p->jobs[i]->gds_va = shadow->gds_va;
621 p->jobs[i]->init_shadow =
622 shadow->flags & AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW;
623 }
624
625 return 0;
626 }
627
amdgpu_cs_pass2(struct amdgpu_cs_parser * p)628 static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p)
629 {
630 unsigned int ce_preempt = 0, de_preempt = 0;
631 int i, r;
632
633 for (i = 0; i < p->nchunks; ++i) {
634 struct amdgpu_cs_chunk *chunk;
635
636 chunk = &p->chunks[i];
637
638 switch (chunk->chunk_id) {
639 case AMDGPU_CHUNK_ID_IB:
640 r = amdgpu_cs_p2_ib(p, chunk, &ce_preempt, &de_preempt);
641 if (r)
642 return r;
643 break;
644 case AMDGPU_CHUNK_ID_DEPENDENCIES:
645 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
646 r = amdgpu_cs_p2_dependencies(p, chunk);
647 if (r)
648 return r;
649 break;
650 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
651 r = amdgpu_cs_p2_syncobj_in(p, chunk);
652 if (r)
653 return r;
654 break;
655 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
656 r = amdgpu_cs_p2_syncobj_out(p, chunk);
657 if (r)
658 return r;
659 break;
660 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
661 r = amdgpu_cs_p2_syncobj_timeline_wait(p, chunk);
662 if (r)
663 return r;
664 break;
665 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
666 r = amdgpu_cs_p2_syncobj_timeline_signal(p, chunk);
667 if (r)
668 return r;
669 break;
670 case AMDGPU_CHUNK_ID_CP_GFX_SHADOW:
671 r = amdgpu_cs_p2_shadow(p, chunk);
672 if (r)
673 return r;
674 break;
675 }
676 }
677
678 return 0;
679 }
680
681 /* Convert microseconds to bytes. */
us_to_bytes(struct amdgpu_device * adev,s64 us)682 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
683 {
684 if (us <= 0 || !adev->mm_stats.log2_max_MBps)
685 return 0;
686
687 /* Since accum_us is incremented by a million per second, just
688 * multiply it by the number of MB/s to get the number of bytes.
689 */
690 return us << adev->mm_stats.log2_max_MBps;
691 }
692
bytes_to_us(struct amdgpu_device * adev,u64 bytes)693 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
694 {
695 if (!adev->mm_stats.log2_max_MBps)
696 return 0;
697
698 return bytes >> adev->mm_stats.log2_max_MBps;
699 }
700
701 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
702 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
703 * which means it can go over the threshold once. If that happens, the driver
704 * will be in debt and no other buffer migrations can be done until that debt
705 * is repaid.
706 *
707 * This approach allows moving a buffer of any size (it's important to allow
708 * that).
709 *
710 * The currency is simply time in microseconds and it increases as the clock
711 * ticks. The accumulated microseconds (us) are converted to bytes and
712 * returned.
713 */
amdgpu_cs_get_threshold_for_moves(struct amdgpu_device * adev,u64 * max_bytes,u64 * max_vis_bytes)714 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
715 u64 *max_bytes,
716 u64 *max_vis_bytes)
717 {
718 s64 time_us, increment_us;
719 u64 free_vram, total_vram, used_vram;
720 /* Allow a maximum of 200 accumulated ms. This is basically per-IB
721 * throttling.
722 *
723 * It means that in order to get full max MBps, at least 5 IBs per
724 * second must be submitted and not more than 200ms apart from each
725 * other.
726 */
727 const s64 us_upper_bound = 200000;
728
729 if ((!adev->mm_stats.log2_max_MBps) || !ttm_resource_manager_used(&adev->mman.vram_mgr.manager)) {
730 *max_bytes = 0;
731 *max_vis_bytes = 0;
732 return;
733 }
734
735 total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
736 used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
737 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
738
739 spin_lock(&adev->mm_stats.lock);
740
741 /* Increase the amount of accumulated us. */
742 time_us = ktime_to_us(ktime_get());
743 increment_us = time_us - adev->mm_stats.last_update_us;
744 adev->mm_stats.last_update_us = time_us;
745 adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
746 us_upper_bound);
747
748 /* This prevents the short period of low performance when the VRAM
749 * usage is low and the driver is in debt or doesn't have enough
750 * accumulated us to fill VRAM quickly.
751 *
752 * The situation can occur in these cases:
753 * - a lot of VRAM is freed by userspace
754 * - the presence of a big buffer causes a lot of evictions
755 * (solution: split buffers into smaller ones)
756 *
757 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
758 * accum_us to a positive number.
759 */
760 if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
761 s64 min_us;
762
763 /* Be more aggressive on dGPUs. Try to fill a portion of free
764 * VRAM now.
765 */
766 if (!(adev->flags & AMD_IS_APU))
767 min_us = bytes_to_us(adev, free_vram / 4);
768 else
769 min_us = 0; /* Reset accum_us on APUs. */
770
771 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
772 }
773
774 /* This is set to 0 if the driver is in debt to disallow (optional)
775 * buffer moves.
776 */
777 *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
778
779 /* Do the same for visible VRAM if half of it is free */
780 if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
781 u64 total_vis_vram = adev->gmc.visible_vram_size;
782 u64 used_vis_vram =
783 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
784
785 if (used_vis_vram < total_vis_vram) {
786 u64 free_vis_vram = total_vis_vram - used_vis_vram;
787
788 adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
789 increment_us, us_upper_bound);
790
791 if (free_vis_vram >= total_vis_vram / 2)
792 adev->mm_stats.accum_us_vis =
793 max(bytes_to_us(adev, free_vis_vram / 2),
794 adev->mm_stats.accum_us_vis);
795 }
796
797 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
798 } else {
799 *max_vis_bytes = 0;
800 }
801
802 spin_unlock(&adev->mm_stats.lock);
803 }
804
805 /* Report how many bytes have really been moved for the last command
806 * submission. This can result in a debt that can stop buffer migrations
807 * temporarily.
808 */
amdgpu_cs_report_moved_bytes(struct amdgpu_device * adev,u64 num_bytes,u64 num_vis_bytes)809 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
810 u64 num_vis_bytes)
811 {
812 spin_lock(&adev->mm_stats.lock);
813 adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
814 adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
815 spin_unlock(&adev->mm_stats.lock);
816 }
817
amdgpu_cs_bo_validate(void * param,struct amdgpu_bo * bo)818 static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
819 {
820 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
821 struct amdgpu_cs_parser *p = param;
822 struct ttm_operation_ctx ctx = {
823 .interruptible = true,
824 .no_wait_gpu = false,
825 .resv = bo->tbo.base.resv
826 };
827 uint32_t domain;
828 int r;
829
830 if (bo->tbo.pin_count)
831 return 0;
832
833 /* Don't move this buffer if we have depleted our allowance
834 * to move it. Don't move anything if the threshold is zero.
835 */
836 if (p->bytes_moved < p->bytes_moved_threshold &&
837 (!bo->tbo.base.dma_buf ||
838 list_empty(&bo->tbo.base.dma_buf->attachments))) {
839 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
840 (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
841 /* And don't move a CPU_ACCESS_REQUIRED BO to limited
842 * visible VRAM if we've depleted our allowance to do
843 * that.
844 */
845 if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
846 domain = bo->preferred_domains;
847 else
848 domain = bo->allowed_domains;
849 } else {
850 domain = bo->preferred_domains;
851 }
852 } else {
853 domain = bo->allowed_domains;
854 }
855
856 retry:
857 amdgpu_bo_placement_from_domain(bo, domain);
858 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
859
860 p->bytes_moved += ctx.bytes_moved;
861 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
862 amdgpu_res_cpu_visible(adev, bo->tbo.resource))
863 p->bytes_moved_vis += ctx.bytes_moved;
864
865 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
866 domain = bo->allowed_domains;
867 goto retry;
868 }
869
870 return r;
871 }
872
amdgpu_cs_parser_bos(struct amdgpu_cs_parser * p,union drm_amdgpu_cs * cs)873 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
874 union drm_amdgpu_cs *cs)
875 {
876 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
877 struct ttm_operation_ctx ctx = { true, false };
878 struct amdgpu_vm *vm = &fpriv->vm;
879 struct amdgpu_bo_list_entry *e;
880 struct drm_gem_object *obj;
881 unsigned int i;
882 int r;
883
884 /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
885 if (cs->in.bo_list_handle) {
886 if (p->bo_list)
887 return -EINVAL;
888
889 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
890 &p->bo_list);
891 if (r)
892 return r;
893 } else if (!p->bo_list) {
894 /* Create a empty bo_list when no handle is provided */
895 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
896 &p->bo_list);
897 if (r)
898 return r;
899 }
900
901 mutex_lock(&p->bo_list->bo_list_mutex);
902
903 /* Get userptr backing pages. If pages are updated after registered
904 * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
905 * amdgpu_ttm_backend_bind() to flush and invalidate new pages
906 */
907 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
908 bool userpage_invalidated = false;
909 struct amdgpu_bo *bo = e->bo;
910
911 e->range = amdgpu_hmm_range_alloc(NULL);
912 if (unlikely(!e->range)) {
913 r = -ENOMEM;
914 goto out_free_user_pages;
915 }
916
917 r = amdgpu_ttm_tt_get_user_pages(bo, e->range);
918 if (r)
919 goto out_free_user_pages;
920
921 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
922 if (bo->tbo.ttm->pages[i] !=
923 hmm_pfn_to_page(e->range->hmm_range.hmm_pfns[i])) {
924 userpage_invalidated = true;
925 break;
926 }
927 }
928 e->user_invalidated = userpage_invalidated;
929 }
930
931 drm_exec_until_all_locked(&p->exec) {
932 r = amdgpu_vm_lock_pd(&fpriv->vm, &p->exec, 1 + p->gang_size);
933 drm_exec_retry_on_contention(&p->exec);
934 if (unlikely(r))
935 goto out_free_user_pages;
936
937 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
938 r = drm_exec_prepare_obj(&p->exec, &e->bo->tbo.base,
939 TTM_NUM_MOVE_FENCES + p->gang_size);
940 drm_exec_retry_on_contention(&p->exec);
941 if (unlikely(r))
942 goto out_free_user_pages;
943
944 e->bo_va = amdgpu_vm_bo_find(vm, e->bo);
945 }
946
947 if (p->uf_bo) {
948 r = drm_exec_prepare_obj(&p->exec, &p->uf_bo->tbo.base,
949 TTM_NUM_MOVE_FENCES + p->gang_size);
950 drm_exec_retry_on_contention(&p->exec);
951 if (unlikely(r))
952 goto out_free_user_pages;
953 }
954 }
955
956 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
957 struct mm_struct *usermm;
958
959 usermm = amdgpu_ttm_tt_get_usermm(e->bo->tbo.ttm);
960 if (usermm && usermm != current->mm) {
961 r = -EPERM;
962 goto out_free_user_pages;
963 }
964
965 if (amdgpu_ttm_tt_is_userptr(e->bo->tbo.ttm) &&
966 e->user_invalidated) {
967 amdgpu_bo_placement_from_domain(e->bo,
968 AMDGPU_GEM_DOMAIN_CPU);
969 r = ttm_bo_validate(&e->bo->tbo, &e->bo->placement,
970 &ctx);
971 if (r)
972 goto out_free_user_pages;
973
974 amdgpu_ttm_tt_set_user_pages(e->bo->tbo.ttm,
975 e->range);
976 }
977 }
978
979 amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
980 &p->bytes_moved_vis_threshold);
981 p->bytes_moved = 0;
982 p->bytes_moved_vis = 0;
983
984 r = amdgpu_vm_validate(p->adev, &fpriv->vm, NULL,
985 amdgpu_cs_bo_validate, p);
986 if (r) {
987 drm_err(adev_to_drm(p->adev), "amdgpu_vm_validate() failed.\n");
988 goto out_free_user_pages;
989 }
990
991 drm_exec_for_each_locked_object(&p->exec, obj) {
992 r = amdgpu_cs_bo_validate(p, gem_to_amdgpu_bo(obj));
993 if (unlikely(r))
994 goto out_free_user_pages;
995 }
996
997 if (p->uf_bo) {
998 r = amdgpu_ttm_alloc_gart(&p->uf_bo->tbo);
999 if (unlikely(r))
1000 goto out_free_user_pages;
1001
1002 p->gang_leader->uf_addr += amdgpu_bo_gpu_offset(p->uf_bo);
1003 }
1004
1005 amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
1006 p->bytes_moved_vis);
1007
1008 for (i = 0; i < p->gang_size; ++i)
1009 amdgpu_job_set_resources(p->jobs[i], p->bo_list->gds_obj,
1010 p->bo_list->gws_obj,
1011 p->bo_list->oa_obj);
1012 return 0;
1013
1014 out_free_user_pages:
1015 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1016 amdgpu_hmm_range_free(e->range);
1017 e->range = NULL;
1018 }
1019 mutex_unlock(&p->bo_list->bo_list_mutex);
1020 return r;
1021 }
1022
trace_amdgpu_cs_ibs(struct amdgpu_cs_parser * p)1023 static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *p)
1024 {
1025 int i, j;
1026
1027 if (!trace_amdgpu_cs_enabled())
1028 return;
1029
1030 for (i = 0; i < p->gang_size; ++i) {
1031 struct amdgpu_job *job = p->jobs[i];
1032
1033 for (j = 0; j < job->num_ibs; ++j)
1034 trace_amdgpu_cs(p, job, &job->ibs[j]);
1035 }
1036 }
1037
amdgpu_cs_patch_ibs(struct amdgpu_cs_parser * p,struct amdgpu_job * job)1038 static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p,
1039 struct amdgpu_job *job)
1040 {
1041 struct amdgpu_ring *ring = amdgpu_job_ring(job);
1042 struct amdgpu_device *adev = ring->adev;
1043 unsigned int i;
1044 int r;
1045
1046 /* Only for UVD/VCE VM emulation */
1047 if (!ring->funcs->parse_cs && !ring->funcs->patch_cs_in_place)
1048 return 0;
1049
1050 for (i = 0; i < job->num_ibs; ++i) {
1051 struct amdgpu_ib *ib = &job->ibs[i];
1052 struct amdgpu_bo_va_mapping *m;
1053 struct amdgpu_bo *aobj;
1054 uint64_t va_start;
1055 uint8_t *kptr;
1056
1057 va_start = ib->gpu_addr & AMDGPU_GMC_HOLE_MASK;
1058 r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
1059 if (r) {
1060 drm_err(adev_to_drm(p->adev), "IB va_start is invalid\n");
1061 return r;
1062 }
1063
1064 if ((va_start + ib->length_dw * 4) >
1065 (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
1066 drm_err(adev_to_drm(p->adev), "IB va_start+ib_bytes is invalid\n");
1067 return -EINVAL;
1068 }
1069
1070 /* the IB should be reserved at this point */
1071 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
1072 if (r)
1073 return r;
1074
1075 kptr += va_start - (m->start * AMDGPU_GPU_PAGE_SIZE);
1076
1077 if (ring->funcs->parse_cs) {
1078 memcpy(ib->ptr, kptr, ib->length_dw * 4);
1079 amdgpu_bo_kunmap(aobj);
1080
1081 r = amdgpu_ring_parse_cs(ring, p, job, ib);
1082 if (r)
1083 return r;
1084
1085 if (ib->sa_bo)
1086 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
1087 } else {
1088 ib->ptr = (uint32_t *)kptr;
1089 r = amdgpu_ring_patch_cs_in_place(ring, p, job, ib);
1090 amdgpu_bo_kunmap(aobj);
1091 if (r)
1092 return r;
1093 }
1094 }
1095
1096 return 0;
1097 }
1098
amdgpu_cs_patch_jobs(struct amdgpu_cs_parser * p)1099 static int amdgpu_cs_patch_jobs(struct amdgpu_cs_parser *p)
1100 {
1101 unsigned int i;
1102 int r;
1103
1104 for (i = 0; i < p->gang_size; ++i) {
1105 r = amdgpu_cs_patch_ibs(p, p->jobs[i]);
1106 if (r)
1107 return r;
1108 }
1109 return 0;
1110 }
1111
amdgpu_cs_vm_handling(struct amdgpu_cs_parser * p)1112 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
1113 {
1114 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1115 struct amdgpu_job *job = p->gang_leader;
1116 struct amdgpu_device *adev = p->adev;
1117 struct amdgpu_vm *vm = &fpriv->vm;
1118 struct amdgpu_bo_list_entry *e;
1119 struct amdgpu_bo_va *bo_va;
1120 unsigned int i;
1121 int r;
1122
1123 /*
1124 * We can't use gang submit on with reserved VMIDs when the VM changes
1125 * can't be invalidated by more than one engine at the same time.
1126 */
1127 if (p->gang_size > 1 && !adev->vm_manager.concurrent_flush) {
1128 for (i = 0; i < p->gang_size; ++i) {
1129 struct drm_sched_entity *entity = p->entities[i];
1130 struct drm_gpu_scheduler *sched = entity->rq->sched;
1131 struct amdgpu_ring *ring = to_amdgpu_ring(sched);
1132
1133 if (amdgpu_vmid_uses_reserved(vm, ring->vm_hub))
1134 return -EINVAL;
1135 }
1136 }
1137
1138 if (!amdgpu_vm_ready(vm))
1139 return -EINVAL;
1140
1141 r = amdgpu_vm_clear_freed(adev, vm, NULL);
1142 if (r)
1143 return r;
1144
1145 r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
1146 if (r)
1147 return r;
1148
1149 r = amdgpu_sync_fence(&p->sync, fpriv->prt_va->last_pt_update,
1150 GFP_KERNEL);
1151 if (r)
1152 return r;
1153
1154 if (fpriv->csa_va) {
1155 bo_va = fpriv->csa_va;
1156 BUG_ON(!bo_va);
1157 r = amdgpu_vm_bo_update(adev, bo_va, false);
1158 if (r)
1159 return r;
1160
1161 r = amdgpu_sync_fence(&p->sync, bo_va->last_pt_update,
1162 GFP_KERNEL);
1163 if (r)
1164 return r;
1165 }
1166
1167 /* FIXME: In theory this loop shouldn't be needed any more when
1168 * amdgpu_vm_handle_moved handles all moved BOs that are reserved
1169 * with p->ticket. But removing it caused test regressions, so I'm
1170 * leaving it here for now.
1171 */
1172 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1173 bo_va = e->bo_va;
1174 if (bo_va == NULL)
1175 continue;
1176
1177 r = amdgpu_vm_bo_update(adev, bo_va, false);
1178 if (r)
1179 return r;
1180
1181 r = amdgpu_sync_fence(&p->sync, bo_va->last_pt_update,
1182 GFP_KERNEL);
1183 if (r)
1184 return r;
1185 }
1186
1187 r = amdgpu_vm_handle_moved(adev, vm, drm_exec_ticket(&p->exec));
1188 if (r)
1189 return r;
1190
1191 r = amdgpu_vm_update_pdes(adev, vm, false);
1192 if (r)
1193 return r;
1194
1195 r = amdgpu_sync_fence(&p->sync, vm->last_update, GFP_KERNEL);
1196 if (r)
1197 return r;
1198
1199 for (i = 0; i < p->gang_size; ++i) {
1200 job = p->jobs[i];
1201
1202 if (!job->vm)
1203 continue;
1204
1205 job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
1206 }
1207
1208 return 0;
1209 }
1210
amdgpu_cs_sync_rings(struct amdgpu_cs_parser * p)1211 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
1212 {
1213 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1214 struct drm_gpu_scheduler *sched;
1215 struct drm_gem_object *obj;
1216 struct dma_fence *fence;
1217 unsigned int i;
1218 int r;
1219
1220 r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entities[p->gang_leader_idx]);
1221 if (r) {
1222 if (r != -ERESTARTSYS)
1223 drm_err(adev_to_drm(p->adev), "amdgpu_ctx_wait_prev_fence failed.\n");
1224 return r;
1225 }
1226
1227 drm_exec_for_each_locked_object(&p->exec, obj) {
1228 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
1229
1230 struct dma_resv *resv = bo->tbo.base.resv;
1231 enum amdgpu_sync_mode sync_mode;
1232
1233 sync_mode = amdgpu_bo_explicit_sync(bo) ?
1234 AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
1235 r = amdgpu_sync_resv(p->adev, &p->sync, resv, sync_mode,
1236 &fpriv->vm);
1237 if (r)
1238 return r;
1239 }
1240
1241 for (i = 0; i < p->gang_size; ++i) {
1242 r = amdgpu_sync_push_to_job(&p->sync, p->jobs[i]);
1243 if (r)
1244 return r;
1245 }
1246
1247 sched = p->gang_leader->base.entity->rq->sched;
1248 while ((fence = amdgpu_sync_get_fence(&p->sync))) {
1249 struct drm_sched_fence *s_fence = to_drm_sched_fence(fence);
1250
1251 /*
1252 * When we have an dependency it might be necessary to insert a
1253 * pipeline sync to make sure that all caches etc are flushed and the
1254 * next job actually sees the results from the previous one
1255 * before we start executing on the same scheduler ring.
1256 */
1257 if (!s_fence || s_fence->sched != sched) {
1258 dma_fence_put(fence);
1259 continue;
1260 }
1261
1262 r = amdgpu_sync_fence(&p->gang_leader->explicit_sync, fence,
1263 GFP_KERNEL);
1264 dma_fence_put(fence);
1265 if (r)
1266 return r;
1267 }
1268 return 0;
1269 }
1270
amdgpu_cs_post_dependencies(struct amdgpu_cs_parser * p)1271 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1272 {
1273 int i;
1274
1275 for (i = 0; i < p->num_post_deps; ++i) {
1276 if (p->post_deps[i].chain && p->post_deps[i].point) {
1277 drm_syncobj_add_point(p->post_deps[i].syncobj,
1278 p->post_deps[i].chain,
1279 p->fence, p->post_deps[i].point);
1280 p->post_deps[i].chain = NULL;
1281 } else {
1282 drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1283 p->fence);
1284 }
1285 }
1286 }
1287
amdgpu_cs_submit(struct amdgpu_cs_parser * p,union drm_amdgpu_cs * cs)1288 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1289 union drm_amdgpu_cs *cs)
1290 {
1291 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1292 struct amdgpu_job *leader = p->gang_leader;
1293 struct amdgpu_vm *vm = &fpriv->vm;
1294 struct amdgpu_bo_list_entry *e;
1295 struct drm_gem_object *gobj;
1296 unsigned int i;
1297 uint64_t seq;
1298 int r;
1299
1300 for (i = 0; i < p->gang_size; ++i)
1301 drm_sched_job_arm(&p->jobs[i]->base);
1302
1303 for (i = 0; i < p->gang_size; ++i) {
1304 struct dma_fence *fence;
1305
1306 if (p->jobs[i] == leader)
1307 continue;
1308
1309 fence = &p->jobs[i]->base.s_fence->scheduled;
1310 dma_fence_get(fence);
1311 r = drm_sched_job_add_dependency(&leader->base, fence);
1312 if (r) {
1313 dma_fence_put(fence);
1314 return r;
1315 }
1316 }
1317
1318 if (p->gang_size > 1) {
1319 for (i = 0; i < p->gang_size; ++i)
1320 amdgpu_job_set_gang_leader(p->jobs[i], leader);
1321 }
1322
1323 /* No memory allocation is allowed while holding the notifier lock.
1324 * The lock is held until amdgpu_cs_submit is finished and fence is
1325 * added to BOs.
1326 */
1327 mutex_lock(&p->adev->notifier_lock);
1328
1329 /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1330 * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1331 */
1332 r = 0;
1333 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1334 r |= !amdgpu_hmm_range_valid(e->range);
1335 amdgpu_hmm_range_free(e->range);
1336 e->range = NULL;
1337 }
1338
1339 if (r || !list_empty(&vm->individual.needs_update)) {
1340 r = -EAGAIN;
1341 mutex_unlock(&p->adev->notifier_lock);
1342 return r;
1343 }
1344
1345 p->fence = dma_fence_get(&leader->base.s_fence->finished);
1346 drm_exec_for_each_locked_object(&p->exec, gobj) {
1347
1348 ttm_bo_move_to_lru_tail_unlocked(&gem_to_amdgpu_bo(gobj)->tbo);
1349
1350 /* Everybody except for the gang leader uses READ */
1351 for (i = 0; i < p->gang_size; ++i) {
1352 if (p->jobs[i] == leader)
1353 continue;
1354
1355 dma_resv_add_fence(gobj->resv,
1356 &p->jobs[i]->base.s_fence->finished,
1357 DMA_RESV_USAGE_READ);
1358 }
1359
1360 /* The gang leader as remembered as writer */
1361 dma_resv_add_fence(gobj->resv, p->fence, DMA_RESV_USAGE_WRITE);
1362 }
1363
1364 seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_leader_idx],
1365 p->fence);
1366 amdgpu_cs_post_dependencies(p);
1367
1368 if ((leader->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1369 !p->ctx->preamble_presented) {
1370 leader->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1371 p->ctx->preamble_presented = true;
1372 }
1373
1374 cs->out.handle = seq;
1375 leader->uf_sequence = seq;
1376
1377 amdgpu_vm_bo_trace_cs(&fpriv->vm, drm_exec_ticket(&p->exec));
1378 for (i = 0; i < p->gang_size; ++i) {
1379 amdgpu_job_free_resources(p->jobs[i]);
1380 trace_amdgpu_cs_ioctl(p->jobs[i]);
1381 drm_sched_entity_push_job(&p->jobs[i]->base);
1382 p->jobs[i] = NULL;
1383 }
1384
1385 amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1386
1387 mutex_unlock(&p->adev->notifier_lock);
1388 mutex_unlock(&p->bo_list->bo_list_mutex);
1389 return 0;
1390 }
1391
1392 /* Cleanup the parser structure */
amdgpu_cs_parser_fini(struct amdgpu_cs_parser * parser)1393 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser)
1394 {
1395 struct amdgpu_device *adev = parser->adev;
1396 struct amdgpu_bo_list_entry *e;
1397 unsigned int i;
1398
1399 amdgpu_sync_free(&parser->sync);
1400 drm_exec_fini(&parser->exec);
1401
1402 for (i = 0; i < parser->num_post_deps; i++) {
1403 drm_syncobj_put(parser->post_deps[i].syncobj);
1404 kfree(parser->post_deps[i].chain);
1405 }
1406 kfree(parser->post_deps);
1407
1408 dma_fence_put(parser->fence);
1409
1410 if (parser->ctx)
1411 amdgpu_ctx_put(parser->ctx);
1412 if (parser->bo_list) {
1413 if (adev->debug_vm) {
1414 /* Invalidate all BOs to test for userspace bugs */
1415 amdgpu_bo_list_for_each_entry(e, parser->bo_list) {
1416 struct amdgpu_bo *bo = e->bo;
1417
1418 /* ignore duplicates */
1419 if (!bo)
1420 continue;
1421
1422 amdgpu_vm_bo_invalidate(bo, false);
1423 }
1424 }
1425 amdgpu_bo_list_put(parser->bo_list);
1426 }
1427
1428 for (i = 0; i < parser->nchunks; i++)
1429 kvfree(parser->chunks[i].kdata);
1430 kvfree(parser->chunks);
1431 for (i = 0; i < parser->gang_size; ++i) {
1432 if (parser->jobs[i])
1433 amdgpu_job_free(parser->jobs[i]);
1434 }
1435 amdgpu_bo_unref(&parser->uf_bo);
1436 }
1437
amdgpu_cs_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1438 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1439 {
1440 struct amdgpu_device *adev = drm_to_adev(dev);
1441 struct amdgpu_cs_parser parser;
1442 int r;
1443
1444 if (amdgpu_ras_intr_triggered())
1445 return -EHWPOISON;
1446
1447 if (!adev->accel_working)
1448 return -EBUSY;
1449
1450 r = amdgpu_cs_parser_init(&parser, adev, filp, data);
1451 if (r) {
1452 drm_err_ratelimited(dev, "Failed to initialize parser %d!\n", r);
1453 return r;
1454 }
1455
1456 r = amdgpu_cs_pass1(&parser, data);
1457 if (r)
1458 goto error_fini;
1459
1460 r = amdgpu_cs_pass2(&parser);
1461 if (r)
1462 goto error_fini;
1463
1464 r = amdgpu_cs_parser_bos(&parser, data);
1465 if (r) {
1466 if (r == -ENOMEM)
1467 drm_err(dev, "Not enough memory for command submission!\n");
1468 else if (r != -ERESTARTSYS && r != -EAGAIN)
1469 drm_dbg(dev, "Failed to process the buffer list %d!\n", r);
1470 goto error_fini;
1471 }
1472
1473 r = amdgpu_cs_patch_jobs(&parser);
1474 if (r)
1475 goto error_backoff;
1476
1477 r = amdgpu_cs_vm_handling(&parser);
1478 if (r)
1479 goto error_backoff;
1480
1481 r = amdgpu_cs_sync_rings(&parser);
1482 if (r)
1483 goto error_backoff;
1484
1485 trace_amdgpu_cs_ibs(&parser);
1486
1487 r = amdgpu_cs_submit(&parser, data);
1488 if (r)
1489 goto error_backoff;
1490
1491 amdgpu_cs_parser_fini(&parser);
1492 return 0;
1493
1494 error_backoff:
1495 mutex_unlock(&parser.bo_list->bo_list_mutex);
1496
1497 error_fini:
1498 amdgpu_cs_parser_fini(&parser);
1499 return r;
1500 }
1501
1502 /**
1503 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1504 *
1505 * @dev: drm device
1506 * @data: data from userspace
1507 * @filp: file private
1508 *
1509 * Wait for the command submission identified by handle to finish.
1510 */
amdgpu_cs_wait_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1511 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1512 struct drm_file *filp)
1513 {
1514 union drm_amdgpu_wait_cs *wait = data;
1515 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1516 struct drm_sched_entity *entity;
1517 struct amdgpu_ctx *ctx;
1518 struct dma_fence *fence;
1519 long r;
1520
1521 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1522 if (ctx == NULL)
1523 return -EINVAL;
1524
1525 r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1526 wait->in.ring, &entity);
1527 if (r) {
1528 amdgpu_ctx_put(ctx);
1529 return r;
1530 }
1531
1532 fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1533 if (IS_ERR(fence))
1534 r = PTR_ERR(fence);
1535 else if (fence) {
1536 r = dma_fence_wait_timeout(fence, true, timeout);
1537 if (r > 0 && fence->error)
1538 r = fence->error;
1539 dma_fence_put(fence);
1540 } else
1541 r = 1;
1542
1543 amdgpu_ctx_put(ctx);
1544 if (r < 0)
1545 return r;
1546
1547 memset(wait, 0, sizeof(*wait));
1548 wait->out.status = (r == 0);
1549
1550 return 0;
1551 }
1552
1553 /**
1554 * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1555 *
1556 * @adev: amdgpu device
1557 * @filp: file private
1558 * @user: drm_amdgpu_fence copied from user space
1559 */
amdgpu_cs_get_fence(struct amdgpu_device * adev,struct drm_file * filp,struct drm_amdgpu_fence * user)1560 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1561 struct drm_file *filp,
1562 struct drm_amdgpu_fence *user)
1563 {
1564 struct drm_sched_entity *entity;
1565 struct amdgpu_ctx *ctx;
1566 struct dma_fence *fence;
1567 int r;
1568
1569 ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1570 if (ctx == NULL)
1571 return ERR_PTR(-EINVAL);
1572
1573 r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1574 user->ring, &entity);
1575 if (r) {
1576 amdgpu_ctx_put(ctx);
1577 return ERR_PTR(r);
1578 }
1579
1580 fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1581 amdgpu_ctx_put(ctx);
1582
1583 return fence;
1584 }
1585
amdgpu_cs_fence_to_handle_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1586 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1587 struct drm_file *filp)
1588 {
1589 struct amdgpu_device *adev = drm_to_adev(dev);
1590 union drm_amdgpu_fence_to_handle *info = data;
1591 struct dma_fence *fence;
1592 struct drm_syncobj *syncobj;
1593 struct sync_file *sync_file;
1594 int fd, r;
1595
1596 fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1597 if (IS_ERR(fence))
1598 return PTR_ERR(fence);
1599
1600 if (!fence)
1601 fence = dma_fence_get_stub();
1602
1603 switch (info->in.what) {
1604 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1605 r = drm_syncobj_create(&syncobj, 0, fence);
1606 dma_fence_put(fence);
1607 if (r)
1608 return r;
1609 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1610 drm_syncobj_put(syncobj);
1611 return r;
1612
1613 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1614 r = drm_syncobj_create(&syncobj, 0, fence);
1615 dma_fence_put(fence);
1616 if (r)
1617 return r;
1618 r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
1619 drm_syncobj_put(syncobj);
1620 return r;
1621
1622 case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1623 fd = get_unused_fd_flags(O_CLOEXEC);
1624 if (fd < 0) {
1625 dma_fence_put(fence);
1626 return fd;
1627 }
1628
1629 sync_file = sync_file_create(fence);
1630 dma_fence_put(fence);
1631 if (!sync_file) {
1632 put_unused_fd(fd);
1633 return -ENOMEM;
1634 }
1635
1636 fd_install(fd, sync_file->file);
1637 info->out.handle = fd;
1638 return 0;
1639
1640 default:
1641 dma_fence_put(fence);
1642 return -EINVAL;
1643 }
1644 }
1645
1646 /**
1647 * amdgpu_cs_wait_all_fences - wait on all fences to signal
1648 *
1649 * @adev: amdgpu device
1650 * @filp: file private
1651 * @wait: wait parameters
1652 * @fences: array of drm_amdgpu_fence
1653 */
amdgpu_cs_wait_all_fences(struct amdgpu_device * adev,struct drm_file * filp,union drm_amdgpu_wait_fences * wait,struct drm_amdgpu_fence * fences)1654 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1655 struct drm_file *filp,
1656 union drm_amdgpu_wait_fences *wait,
1657 struct drm_amdgpu_fence *fences)
1658 {
1659 uint32_t fence_count = wait->in.fence_count;
1660 unsigned int i;
1661 long r = 1;
1662
1663 for (i = 0; i < fence_count; i++) {
1664 struct dma_fence *fence;
1665 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1666
1667 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1668 if (IS_ERR(fence))
1669 return PTR_ERR(fence);
1670 else if (!fence)
1671 continue;
1672
1673 r = dma_fence_wait_timeout(fence, true, timeout);
1674 if (r > 0 && fence->error)
1675 r = fence->error;
1676
1677 dma_fence_put(fence);
1678 if (r < 0)
1679 return r;
1680
1681 if (r == 0)
1682 break;
1683 }
1684
1685 memset(wait, 0, sizeof(*wait));
1686 wait->out.status = (r > 0);
1687
1688 return 0;
1689 }
1690
1691 /**
1692 * amdgpu_cs_wait_any_fence - wait on any fence to signal
1693 *
1694 * @adev: amdgpu device
1695 * @filp: file private
1696 * @wait: wait parameters
1697 * @fences: array of drm_amdgpu_fence
1698 */
amdgpu_cs_wait_any_fence(struct amdgpu_device * adev,struct drm_file * filp,union drm_amdgpu_wait_fences * wait,struct drm_amdgpu_fence * fences)1699 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1700 struct drm_file *filp,
1701 union drm_amdgpu_wait_fences *wait,
1702 struct drm_amdgpu_fence *fences)
1703 {
1704 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1705 uint32_t fence_count = wait->in.fence_count;
1706 uint32_t first = ~0;
1707 struct dma_fence **array;
1708 unsigned int i;
1709 long r;
1710
1711 /* Prepare the fence array */
1712 array = kzalloc_objs(struct dma_fence *, fence_count);
1713
1714 if (array == NULL)
1715 return -ENOMEM;
1716
1717 for (i = 0; i < fence_count; i++) {
1718 struct dma_fence *fence;
1719
1720 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1721 if (IS_ERR(fence)) {
1722 r = PTR_ERR(fence);
1723 goto err_free_fence_array;
1724 } else if (fence) {
1725 array[i] = fence;
1726 } else { /* NULL, the fence has been already signaled */
1727 r = 1;
1728 first = i;
1729 goto out;
1730 }
1731 }
1732
1733 r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1734 &first);
1735 if (r < 0)
1736 goto err_free_fence_array;
1737
1738 out:
1739 memset(wait, 0, sizeof(*wait));
1740 wait->out.status = (r > 0);
1741 wait->out.first_signaled = first;
1742
1743 if (first < fence_count && array[first])
1744 r = array[first]->error;
1745 else
1746 r = 0;
1747
1748 err_free_fence_array:
1749 for (i = 0; i < fence_count; i++)
1750 dma_fence_put(array[i]);
1751 kfree(array);
1752
1753 return r;
1754 }
1755
1756 /**
1757 * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1758 *
1759 * @dev: drm device
1760 * @data: data from userspace
1761 * @filp: file private
1762 */
amdgpu_cs_wait_fences_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1763 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1764 struct drm_file *filp)
1765 {
1766 struct amdgpu_device *adev = drm_to_adev(dev);
1767 union drm_amdgpu_wait_fences *wait = data;
1768 struct drm_amdgpu_fence *fences;
1769 int r;
1770
1771 /*
1772 * fence_count must be non-zero; dma_fence_wait_any_timeout()
1773 * does not accept an empty fence array.
1774 */
1775 if (!wait->in.fence_count)
1776 return -EINVAL;
1777
1778 /* Get the fences from userspace */
1779 fences = memdup_array_user(u64_to_user_ptr(wait->in.fences),
1780 wait->in.fence_count,
1781 sizeof(struct drm_amdgpu_fence));
1782 if (IS_ERR(fences))
1783 return PTR_ERR(fences);
1784
1785 if (wait->in.wait_all)
1786 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1787 else
1788 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1789
1790 kfree(fences);
1791
1792 return r;
1793 }
1794
1795 /**
1796 * amdgpu_cs_find_mapping - find bo_va for VM address
1797 *
1798 * @parser: command submission parser context
1799 * @addr: VM address
1800 * @bo: resulting BO of the mapping found
1801 * @map: Placeholder to return found BO mapping
1802 *
1803 * Search the buffer objects in the command submission context for a certain
1804 * virtual memory address. Returns allocation structure when found, NULL
1805 * otherwise.
1806 */
amdgpu_cs_find_mapping(struct amdgpu_cs_parser * parser,uint64_t addr,struct amdgpu_bo ** bo,struct amdgpu_bo_va_mapping ** map)1807 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1808 uint64_t addr, struct amdgpu_bo **bo,
1809 struct amdgpu_bo_va_mapping **map)
1810 {
1811 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1812 struct ttm_operation_ctx ctx = { false, false };
1813 struct amdgpu_vm *vm = &fpriv->vm;
1814 struct amdgpu_bo_va_mapping *mapping;
1815 int i, r;
1816
1817 addr /= AMDGPU_GPU_PAGE_SIZE;
1818
1819 mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1820 if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1821 return -EINVAL;
1822
1823 *bo = mapping->bo_va->base.bo;
1824 *map = mapping;
1825
1826 /* Double check that the BO is reserved by this CS */
1827 if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != drm_exec_ticket(&parser->exec))
1828 return -EINVAL;
1829
1830 /* Make sure VRAM is allocated contigiously */
1831 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1832 if ((*bo)->tbo.resource->mem_type == TTM_PL_VRAM &&
1833 !((*bo)->tbo.resource->placement & TTM_PL_FLAG_CONTIGUOUS)) {
1834
1835 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1836 for (i = 0; i < (*bo)->placement.num_placement; i++)
1837 (*bo)->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;
1838 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1839 if (r)
1840 return r;
1841 }
1842
1843 return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1844 }
1845