1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2017-2026 Morse Micro
4 */
5
6 #ifndef _MM81X_CORE_H_
7 #define _MM81X_CORE_H_
8
9 #include <net/mac80211.h>
10 #include <linux/workqueue.h>
11 #include <linux/interrupt.h>
12 #include <linux/kfifo.h>
13 #include <linux/types.h>
14 #include <linux/version.h>
15 #include <linux/crc32.h>
16 #include <linux/notifier.h>
17 #include <linux/nospec.h>
18 #include <linux/wait.h>
19 #include "yaps.h"
20 #include "yaps_hw.h"
21 #include "hw.h"
22 #include "fw.h"
23 #include "rc.h"
24
25 #define MM81X_DRIVER_SEMVER_MAJOR 56
26 #define MM81X_DRIVER_SEMVER_MINOR 3
27 #define MM81X_DRIVER_SEMVER_PATCH 0
28
29 #define MM81X_SEMVER_GET_MAJOR(x) (((x) >> 22) & 0x3FF)
30 #define MM81X_SEMVER_GET_MINOR(x) (((x) >> 10) & 0xFFF)
31 #define MM81X_SEMVER_GET_PATCH(x) ((x) & 0x3FF)
32
33 #define DRV_VERSION __stringify(MM81X_VERSION)
34
35 #define MM8108_FW_BASE "mm8108"
36
37 #define BCF_SIZE_MAX 48
38
39 #define KHZ100_TO_MHZ(x) ((x) / 10)
40 #define KHZ100_TO_KHZ(freq) ((freq) * 100)
41 #define KHZ100_TO_HZ(freq) ((freq) * 100000)
42
43 #define QDBM_TO_MBM(gain) (((gain) * 100) >> 2)
44 #define MBM_TO_QDBM(gain) (((gain) << 2) / 100)
45 #define QDBM_TO_DBM(gain) ((gain) / 4)
46
47 #define BPS_TO_KBPS(x) ((x) / 1000)
48
49 #define NSS_IDX_TO_NSS(x) ((x) + 1)
50 #define NSS_TO_NSS_IDX(x) ((x) - 1)
51
52 #define ROUND_BYTES_TO_WORD(_nbytes) \
53 (((_nbytes) + 3) & ~((typeof(_nbytes))0x03))
54
55 struct mm81x_bus_ops;
56 struct mm81x_hif_ops;
57
58 #define MM81X_CAPS_MAX_FW_VAL (128)
59
60 /* Max number of interfaces */
61 #define MM81X_MAX_IF (2)
62
63 enum mm81x_caps_flags {
64 MM81X_CAPS_FW_START = 0,
65 MM81X_CAPS_2MHZ = MM81X_CAPS_FW_START,
66 MM81X_CAPS_4MHZ,
67 MM81X_CAPS_8MHZ,
68 MM81X_CAPS_16MHZ,
69 MM81X_CAPS_SGI,
70 MM81X_CAPS_S1G_LONG,
71 MM81X_CAPS_TRAVELING_PILOT_ONE_STREAM,
72 MM81X_CAPS_TRAVELING_PILOT_TWO_STREAM,
73 MM81X_CAPS_MU_BEAMFORMEE,
74 MM81X_CAPS_MU_BEAMFORMER,
75 MM81X_CAPS_RD_RESPONDER,
76 MM81X_CAPS_STA_TYPE_SENSOR,
77 MM81X_CAPS_STA_TYPE_NON_SENSOR,
78 MM81X_CAPS_GROUP_AID,
79 MM81X_CAPS_NON_TIM,
80 MM81X_CAPS_TIM_ADE,
81 MM81X_CAPS_BAT,
82 MM81X_CAPS_DYNAMIC_AID,
83 MM81X_CAPS_UPLINK_SYNC,
84 MM81X_CAPS_FLOW_CONTROL,
85 MM81X_CAPS_AMPDU,
86 MM81X_CAPS_AMSDU,
87 MM81X_CAPS_1MHZ_CONTROL_RESPONSE_PREAMBLE,
88 MM81X_CAPS_PAGE_SLICING,
89 MM81X_CAPS_RAW,
90 MM81X_CAPS_MCS8,
91 MM81X_CAPS_MCS9,
92 MM81X_CAPS_ASYMMETRIC_BA_SUPPORT,
93 MM81X_CAPS_DAC,
94 MM81X_CAPS_CAC,
95 MM81X_CAPS_TXOP_SHARING_IMPLICIT_ACK,
96 MM81X_CAPS_NDP_PSPOLL,
97 MM81X_CAPS_FRAGMENT_BA,
98 MM81X_CAPS_OBSS_MITIGATION,
99 MM81X_CAPS_TMP_PS_MODE_SWITCH,
100 MM81X_CAPS_SECTOR_TRAINING,
101 MM81X_CAPS_UNSOLICIT_DYNAMIC_AID,
102 MM81X_CAPS_NDP_BEAMFORMING_REPORT,
103 MM81X_CAPS_MCS_NEGOTIATION,
104 MM81X_CAPS_DUPLICATE_1MHZ,
105 MM81X_CAPS_TACK_AS_PSPOLL,
106 MM81X_CAPS_PV1,
107 MM81X_CAPS_TWT_RESPONDER,
108 MM81X_CAPS_TWT_REQUESTER,
109 MM81X_CAPS_BDT,
110 MM81X_CAPS_TWT_GROUPING,
111 MM81X_CAPS_LINK_ADAPTATION_WO_NDP_CMAC,
112 MM81X_CAPS_LONG_MPDU,
113 MM81X_CAPS_TXOP_SECTORIZATION,
114 MM81X_CAPS_GROUP_SECTORIZATION,
115 MM81X_CAPS_HTC_VHT,
116 MM81X_CAPS_HTC_VHT_MFB,
117 MM81X_CAPS_HTC_VHT_MRQ,
118 MM81X_CAPS_2SS,
119 MM81X_CAPS_3SS,
120 MM81X_CAPS_4SS,
121 MM81X_CAPS_SU_BEAMFORMEE,
122 MM81X_CAPS_SU_BEAMFORMER,
123 MM81X_CAPS_RX_STBC,
124 MM81X_CAPS_TX_STBC,
125 MM81X_CAPS_RX_LDPC,
126 MM81X_CAPS_HW_FRAGMENT,
127
128 MM81X_CAPS_FW_END = MM81X_CAPS_MAX_FW_VAL,
129 MM81X_CAPS_LAST = MM81X_CAPS_FW_END,
130 };
131
132 struct mm81x_fw_caps {
133 u32 flags[FW_CAPABILITIES_FLAGS_WIDTH];
134 u8 ampdu_mss;
135 u8 beamformee_sts_capability;
136 u8 number_sounding_dimensions;
137 u8 maximum_ampdu_length_exponent;
138 u8 mm81x_mmss_offset;
139 };
140
141 #define MM81X_FW_SUPP(MM81X_CAPS, CAPABILITY) \
142 mm81x_caps_supported(MM81X_CAPS, MM81X_CAPS_##CAPABILITY)
143
mm81x_caps_supported(struct mm81x_fw_caps * caps,enum mm81x_caps_flags flag)144 static inline bool mm81x_caps_supported(struct mm81x_fw_caps *caps,
145 enum mm81x_caps_flags flag)
146 {
147 const unsigned long *flags_ptr = (unsigned long *)caps->flags;
148
149 return test_bit(flag, flags_ptr);
150 }
151
152 struct mm81x_ps {
153 u32 wakers;
154 bool enable;
155 bool suspended;
156 /* PS state lock */
157 struct mutex lock;
158 struct delayed_work delayed_eval_work;
159 };
160
161 enum mm81x_page_aci {
162 MM81X_ACI_BE = 0,
163 MM81X_ACI_BK = 1,
164 MM81X_ACI_VI = 2,
165 MM81X_ACI_VO = 3,
166 };
167
168 enum mm81x_qos_tid_up_index {
169 MM81X_QOS_TID_UP_BK = 1,
170 MM81X_QOS_TID_UP_XX = 2,
171 MM81X_QOS_TID_UP_BE = 0,
172 MM81X_QOS_TID_UP_EE = 3,
173 MM81X_QOS_TID_UP_CL = 4,
174 MM81X_QOS_TID_UP_VI = 5,
175 MM81X_QOS_TID_UP_VO = 6,
176 MM81X_QOS_TID_UP_NC = 7,
177
178 MM81X_QOS_TID_UP_LOWEST = MM81X_QOS_TID_UP_BK,
179 MM81X_QOS_TID_UP_HIGHEST = MM81X_QOS_TID_UP_NC
180 };
181
182 struct mm81x_sw_version {
183 u8 major;
184 u8 minor;
185 u8 patch;
186 };
187
188 struct mm81x_sta {
189 const struct ieee80211_vif *vif;
190 u8 addr[ETH_ALEN];
191 enum ieee80211_sta_state state;
192 bool tid_tx[IEEE80211_NUM_TIDS];
193 bool tid_start_tx[IEEE80211_NUM_TIDS];
194 u8 tid_params[IEEE80211_NUM_TIDS];
195 int max_bw_mhz;
196 struct mm81x_rc_sta rc;
197 struct mmrc_rate last_sta_tx_rate;
198 s16 avg_rssi;
199 bool tx_ps_filter_en;
200 };
201
202 struct mm81x_vif {
203 struct mm81x *mors;
204 u16 id;
205
206 union {
207 struct {
208 bool is_assoc;
209 } sta;
210 struct {
211 u32 num_stas;
212 struct work_struct beacon_work;
213 } ap;
214 } u;
215 };
216
217 struct mm81x_stale_tx_status {
218 /* Stale Tx lock */
219 spinlock_t lock;
220 struct timer_list timer;
221 };
222
223 struct mcast_filter {
224 u8 count;
225 /*
226 * Integer representation of the last four bytes of a multicast MAC
227 * address. The first two bytes are always 0x0100 (IPv4) or 0x3333
228 * (IPv6).
229 */
230 __le32 addr_list[];
231 };
232
233 enum mm81x_hw_scan_op {
234 MM81X_HW_SCAN_OP_START,
235 MM81X_HW_SCAN_OP_STOP,
236 };
237
238 struct mm81x_hw_scan_params {
239 struct ieee80211_hw *hw;
240
241 /* vif which initiated the scan */
242 struct ieee80211_vif *vif;
243 bool has_directed_ssid;
244 u32 dwell_time_ms;
245 u32 dwell_on_home_ms;
246 enum mm81x_hw_scan_op operation;
247 bool store;
248 struct sk_buff *probe_req;
249 u16 num_chans;
250 u16 allocated_chans;
251
252 struct {
253 struct ieee80211_channel *channel;
254 /* Index into @ref powers_qdbm for the power of this channel */
255 u8 power_idx;
256 } *channels;
257
258 s32 *powers_qdbm;
259 u8 n_powers;
260 };
261
262 enum mm81x_hw_scan_state {
263 HW_SCAN_STATE_IDLE,
264 HW_SCAN_STATE_RUNNING,
265 HW_SCAN_STATE_ABORTING,
266 };
267
268 struct mm81x_hw_scan {
269 enum mm81x_hw_scan_state state;
270 struct completion scan_done;
271 struct mm81x_hw_scan_params *params;
272 struct delayed_work timeout;
273 u32 home_dwell_ms;
274 };
275
276 enum mm81x_hif_event_flags {
277 MM81X_HIF_EVT_RX_PEND,
278 MM81X_HIF_EVT_PAGE_RETURN_PEND,
279 MM81X_HIF_EVT_TX_COMMAND_PEND,
280 MM81X_HIF_EVT_TX_BEACON_PEND,
281 MM81X_HIF_EVT_TX_MGMT_PEND,
282 MM81X_HIF_EVT_TX_DATA_PEND,
283 MM81X_HIF_EVT_TX_PACKET_FREED_UP_PEND,
284 MM81X_HIF_EVT_DATA_TRAFFIC_PAUSE_PEND,
285 MM81X_HIF_EVT_DATA_TRAFFIC_RESUME_PEND,
286 MM81X_HIF_EVT_UPDATE_HW_CLOCK_REFERENCE,
287 };
288
289 enum mm81x_state_flags {
290 MM81X_STATE_CHIP_UNRESPONSIVE,
291 MM81X_STATE_DATA_QS_STOPPED,
292 MM81X_STATE_DATA_TX_STOPPED,
293 MM81X_STATE_REGDOM_SET_BY_USER,
294 MM81X_STATE_REGDOM_SET_BY_OTP,
295 MM81X_STATE_RELOAD_FW_AFTER_START,
296 MM81X_STATE_HOST_TO_CHIP_TX_BLOCKED,
297 MM81X_STATE_HOST_TO_CHIP_CMD_BLOCKED,
298 };
299
300 #define MM81X_COUNTRY_LEN (3)
301 #define INVALID_VIF_INDEX 0xFF
302
303 struct mm81x {
304 u32 chip_id;
305 u32 host_table_ptr;
306
307 /* Refer to @enum mm81x_bus_type */
308 u32 bus_type;
309 u32 bcf_address;
310
311 /*
312 * Parsed from the release tag, which should be in the format
313 * 'rel_<major>_<minor>_<patch>'. If the tag is not in this format
314 * then corresponding version field will be 0.
315 */
316 struct mm81x_sw_version sw_ver;
317 u8 macaddr[ETH_ALEN];
318 u8 country[MM81X_COUNTRY_LEN];
319
320 /* Mask of type @enum host_table_firmware_flags */
321 u32 fw_flags;
322 u32 fw_major;
323 struct mm81x_fw_caps fw_caps;
324 bool started;
325 bool chip_was_reset;
326 struct wiphy *wiphy;
327 struct mm81x_hw_scan hw_scan;
328 struct ieee80211_hw *hw;
329 struct device *dev;
330
331 struct ieee80211_vif __rcu *vifs[MM81X_MAX_IF];
332
333 /* @mm81x_state_flags */
334 unsigned long state_flags;
335
336 u16 cmd_seq;
337 struct completion *cmd_comp;
338 /* Serialises commands */
339 struct mutex cmd_lock;
340
341 /* Serialises command completion */
342 struct mutex cmd_wait;
343
344 const struct mm81x_regs *regs;
345
346 struct {
347 union {
348 struct mm81x_yaps yaps;
349 } u;
350 const struct mm81x_hif_ops *ops;
351 /* See @enum mm81x_hif_event_flags for values */
352 unsigned long event_flags;
353 bool validate_skb_checksum;
354 } hif;
355
356 struct workqueue_struct *chip_wq;
357 struct work_struct hif_work;
358 struct work_struct usb_irq_work;
359 struct mm81x_stale_tx_status stale_status;
360 bool config_ps;
361 struct mm81x_ps ps;
362
363 /* Tx power in mBm received from the FW before association */
364 s32 tx_power_mbm;
365 s32 tx_max_power_mbm;
366
367 const struct mm81x_bus_ops *bus_ops;
368 struct mm81x_rc mrc;
369 int rts_threshold;
370 struct workqueue_struct *net_wq;
371 struct work_struct tx_stale_work;
372 wait_queue_head_t tx_empty_waitq;
373
374 struct cfg80211_chan_def chandef;
375 struct mcast_filter *mcast_filter;
376 atomic_t num_bcn_vifs;
377 unsigned long beacon_irqs_enabled;
378 u8 drv_priv[] __aligned(sizeof(void *));
379 };
380
381 /* Map from mac80211 queue to Morse ACI value for page metadata */
map_mac80211q_2_mm81x_aci(u16 mac80211queue)382 static inline u8 map_mac80211q_2_mm81x_aci(u16 mac80211queue)
383 {
384 switch (mac80211queue) {
385 case IEEE80211_AC_VO:
386 return MM81X_ACI_VO;
387 case IEEE80211_AC_VI:
388 return MM81X_ACI_VI;
389 case IEEE80211_AC_BK:
390 return MM81X_ACI_BK;
391 default:
392 return MM81X_ACI_BE;
393 }
394 }
395
396 static inline enum mm81x_page_aci
dot11_tid_to_ac(enum mm81x_qos_tid_up_index tid)397 dot11_tid_to_ac(enum mm81x_qos_tid_up_index tid)
398 {
399 switch (tid) {
400 case MM81X_QOS_TID_UP_BK:
401 case MM81X_QOS_TID_UP_XX:
402 return MM81X_ACI_BK;
403 case MM81X_QOS_TID_UP_CL:
404 case MM81X_QOS_TID_UP_VI:
405 return MM81X_ACI_VI;
406 case MM81X_QOS_TID_UP_VO:
407 case MM81X_QOS_TID_UP_NC:
408 return MM81X_ACI_VO;
409 case MM81X_QOS_TID_UP_BE:
410 case MM81X_QOS_TID_UP_EE:
411 default:
412 return MM81X_ACI_BE;
413 }
414 }
415
mm81x_is_data_tx_allowed(struct mm81x * mors)416 static inline bool mm81x_is_data_tx_allowed(struct mm81x *mors)
417 {
418 return !test_bit(MM81X_STATE_DATA_TX_STOPPED, &mors->state_flags) &&
419 !test_bit(MM81X_HIF_EVT_DATA_TRAFFIC_PAUSE_PEND,
420 &mors->hif.event_flags);
421 }
422
423 static inline struct ieee80211_vif *
mm81x_vif_to_ieee80211_vif(struct mm81x_vif * mors_vif)424 mm81x_vif_to_ieee80211_vif(struct mm81x_vif *mors_vif)
425 {
426 return container_of((void *)mors_vif, struct ieee80211_vif, drv_priv);
427 }
428
429 static inline struct mm81x_vif *
ieee80211_vif_to_mors_vif(struct ieee80211_vif * vif)430 ieee80211_vif_to_mors_vif(struct ieee80211_vif *vif)
431 {
432 return (struct mm81x_vif *)vif->drv_priv;
433 }
434
mm81x_vif_to_mors(struct mm81x_vif * mors_vif)435 static inline struct mm81x *mm81x_vif_to_mors(struct mm81x_vif *mors_vif)
436 {
437 return mors_vif->mors;
438 }
439
mm81x_generate_cssid(const u8 * ssid,u8 len)440 static inline u32 mm81x_generate_cssid(const u8 *ssid, u8 len)
441 {
442 return ~crc32(~0, ssid, len);
443 }
444
445 int mm81x_beacon_init(struct mm81x_vif *mors_vif);
446 void mm81x_beacon_finish(struct mm81x_vif *mors_vif);
447 void mm81x_beacon_irq_handle(struct mm81x *mors, u32 status);
448 char *mm81x_core_get_fw_path(u32 chip_id, u32 fw_ver);
449 struct mm81x *mm81x_core_alloc(size_t priv_size, struct device *dev);
450 int mm81x_core_init(struct mm81x *mors);
451 int mm81x_core_register(struct mm81x *mors);
452 void mm81x_core_unregister(struct mm81x *mors);
453 void mm81x_core_deinit(struct mm81x *mors);
454 void mm81x_core_free(struct mm81x *mors);
455
456 #endif /* !_MM81X_MM81X_H_ */
457