1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA PCIe driver
5 *
6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/device.h>
13 #include <linux/dma/edma.h>
14 #include <linux/pci-epf.h>
15 #include <linux/msi.h>
16 #include <linux/bitfield.h>
17 #include <linux/sizes.h>
18
19 #include "dw-edma-core.h"
20
21 /* Synopsys */
22 #define DW_PCIE_SYNOPSYS_VSEC_DMA_ID 0x6
23 #define DW_PCIE_SYNOPSYS_VSEC_DMA_BAR GENMASK(10, 8)
24 #define DW_PCIE_SYNOPSYS_VSEC_DMA_MAP GENMASK(2, 0)
25 #define DW_PCIE_SYNOPSYS_VSEC_DMA_WR_CH GENMASK(9, 0)
26 #define DW_PCIE_SYNOPSYS_VSEC_DMA_RD_CH GENMASK(25, 16)
27
28 /* AMD MDB (Xilinx) specific defines */
29 #define PCI_DEVICE_ID_XILINX_B054 0xb054
30 #define PCI_DEVICE_ID_XILINX_B00F 0xb00f
31
32 #define DW_PCIE_XILINX_MDB_VSEC_DMA_ID 0x6
33 #define DW_PCIE_XILINX_MDB_VSEC_ID 0x20
34 #define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR GENMASK(10, 8)
35 #define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP GENMASK(2, 0)
36 #define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH GENMASK(9, 0)
37 #define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH GENMASK(25, 16)
38
39 #define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH 0xc
40 #define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW 0x8
41 #define DW_PCIE_XILINX_MDB_INVALID_ADDR (~0ULL)
42
43 #define DW_PCIE_XILINX_MDB_LL_OFF_GAP 0x200000
44 #define DW_PCIE_XILINX_MDB_LL_SIZE 0x800
45 #define DW_PCIE_XILINX_MDB_DT_OFF_GAP 0x100000
46 #define DW_PCIE_XILINX_MDB_DT_SIZE 0x800
47
48 #define DW_BLOCK(a, b, c) \
49 { \
50 .bar = a, \
51 .off = b, \
52 .sz = c, \
53 },
54
55 struct dw_edma_block {
56 enum pci_barno bar;
57 off_t off;
58 u64 paddr;
59 bool paddr_valid;
60 size_t sz;
61 };
62
63 struct dw_edma_pcie_data {
64 /* eDMA registers location */
65 struct dw_edma_block rg;
66 /* eDMA memory linked list location */
67 struct dw_edma_block ll_wr[HDMA_MAX_WR_CH];
68 struct dw_edma_block ll_rd[HDMA_MAX_RD_CH];
69 /* eDMA memory data location */
70 struct dw_edma_block dt_wr[HDMA_MAX_WR_CH];
71 struct dw_edma_block dt_rd[HDMA_MAX_RD_CH];
72 /* Other */
73 enum dw_edma_map_format mf;
74 u8 irqs;
75 u16 wr_ch_cnt;
76 u16 rd_ch_cnt;
77 u64 devmem_phys_off;
78 bool cfg_non_ll;
79 };
80
81 struct dw_edma_pcie_match_data {
82 const struct dw_edma_pcie_data *data;
83 const struct dw_edma_plat_ops *plat_ops;
84 /*
85 * Mandatory callback. It may leave @pdata unchanged when the static
86 * template already describes the device.
87 */
88 int (*parse_caps)(struct pci_dev *pdev,
89 struct dw_edma_pcie_data *pdata);
90 unsigned long flags;
91 u32 chip_flags;
92 };
93
94 #define DW_EDMA_PCIE_F_DEVMEM_PHYS_OFF BIT(0)
95 #define DW_EDMA_PCIE_F_REG_OFFSET BIT(1)
96
97 static const struct dw_edma_pcie_data snps_edda_data = {
98 /* eDMA registers location */
99 .rg.bar = BAR_0,
100 .rg.off = 0x00001000, /* 4 Kbytes */
101 .rg.sz = 0x00002000, /* 8 Kbytes */
102 /* eDMA memory linked list location */
103 .ll_wr = {
104 /* Channel 0 - BAR 2, offset 0 Mbytes, size 2 Kbytes */
105 DW_BLOCK(BAR_2, 0x00000000, 0x00000800)
106 /* Channel 1 - BAR 2, offset 2 Mbytes, size 2 Kbytes */
107 DW_BLOCK(BAR_2, 0x00200000, 0x00000800)
108 },
109 .ll_rd = {
110 /* Channel 0 - BAR 2, offset 4 Mbytes, size 2 Kbytes */
111 DW_BLOCK(BAR_2, 0x00400000, 0x00000800)
112 /* Channel 1 - BAR 2, offset 6 Mbytes, size 2 Kbytes */
113 DW_BLOCK(BAR_2, 0x00600000, 0x00000800)
114 },
115 /* eDMA memory data location */
116 .dt_wr = {
117 /* Channel 0 - BAR 2, offset 8 Mbytes, size 2 Kbytes */
118 DW_BLOCK(BAR_2, 0x00800000, 0x00000800)
119 /* Channel 1 - BAR 2, offset 9 Mbytes, size 2 Kbytes */
120 DW_BLOCK(BAR_2, 0x00900000, 0x00000800)
121 },
122 .dt_rd = {
123 /* Channel 0 - BAR 2, offset 10 Mbytes, size 2 Kbytes */
124 DW_BLOCK(BAR_2, 0x00a00000, 0x00000800)
125 /* Channel 1 - BAR 2, offset 11 Mbytes, size 2 Kbytes */
126 DW_BLOCK(BAR_2, 0x00b00000, 0x00000800)
127 },
128 /* Other */
129 .mf = EDMA_MF_EDMA_UNROLL,
130 .irqs = 1,
131 .wr_ch_cnt = 2,
132 .rd_ch_cnt = 2,
133 };
134
135 static const struct dw_edma_pcie_data xilinx_mdb_data = {
136 /* MDB registers location */
137 .rg.bar = BAR_0,
138 .rg.off = SZ_4K, /* 4 Kbytes */
139 .rg.sz = SZ_8K, /* 8 Kbytes */
140
141 /* Other */
142 .mf = EDMA_MF_HDMA_NATIVE,
143 .irqs = 1,
144 .wr_ch_cnt = 8,
145 .rd_ch_cnt = 8,
146 };
147
148 static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = {
149 /* MDB registers location */
150 .rg.bar = BAR_0,
151 .rg.off = SZ_4K, /* 4 Kbytes */
152 .rg.sz = SZ_8K, /* 8 Kbytes */
153
154 /* Other */
155 .mf = EDMA_MF_HDMA_NATIVE,
156 .irqs = 1,
157 .wr_ch_cnt = 8,
158 .rd_ch_cnt = 8,
159 };
160
dw_edma_set_chan_region_offset(struct dw_edma_pcie_data * pdata,enum pci_barno bar,off_t start_off,off_t ll_off_gap,size_t ll_size,off_t dt_off_gap,size_t dt_size)161 static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata,
162 enum pci_barno bar, off_t start_off,
163 off_t ll_off_gap, size_t ll_size,
164 off_t dt_off_gap, size_t dt_size)
165 {
166 u16 wr_ch = pdata->wr_ch_cnt;
167 u16 rd_ch = pdata->rd_ch_cnt;
168 off_t off;
169 u16 i;
170
171 off = start_off;
172
173 /* Write channel LL region */
174 for (i = 0; i < wr_ch; i++) {
175 pdata->ll_wr[i].bar = bar;
176 pdata->ll_wr[i].off = off;
177 pdata->ll_wr[i].sz = ll_size;
178 off += ll_off_gap;
179 }
180
181 /* Read channel LL region */
182 for (i = 0; i < rd_ch; i++) {
183 pdata->ll_rd[i].bar = bar;
184 pdata->ll_rd[i].off = off;
185 pdata->ll_rd[i].sz = ll_size;
186 off += ll_off_gap;
187 }
188
189 /* Write channel data region */
190 for (i = 0; i < wr_ch; i++) {
191 pdata->dt_wr[i].bar = bar;
192 pdata->dt_wr[i].off = off;
193 pdata->dt_wr[i].sz = dt_size;
194 off += dt_off_gap;
195 }
196
197 /* Read channel data region */
198 for (i = 0; i < rd_ch; i++) {
199 pdata->dt_rd[i].bar = bar;
200 pdata->dt_rd[i].off = off;
201 pdata->dt_rd[i].sz = dt_size;
202 off += dt_off_gap;
203 }
204 }
205
dw_edma_pcie_irq_vector(struct device * dev,unsigned int nr)206 static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr)
207 {
208 return pci_irq_vector(to_pci_dev(dev), nr);
209 }
210
dw_edma_pcie_address(struct device * dev,phys_addr_t cpu_addr)211 static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr)
212 {
213 struct pci_dev *pdev = to_pci_dev(dev);
214 struct pci_bus_region region;
215 struct resource res = {
216 .flags = IORESOURCE_MEM,
217 .start = cpu_addr,
218 .end = cpu_addr,
219 };
220
221 pcibios_resource_to_bus(pdev->bus, ®ion, &res);
222 return region.start;
223 }
224
225 static const struct dw_edma_plat_ops dw_edma_pcie_plat_ops = {
226 .irq_vector = dw_edma_pcie_irq_vector,
227 .pci_address = dw_edma_pcie_address,
228 };
229
dw_edma_pcie_get_synopsys_dma_data(struct pci_dev * pdev,struct dw_edma_pcie_data * pdata)230 static void dw_edma_pcie_get_synopsys_dma_data(struct pci_dev *pdev,
231 struct dw_edma_pcie_data *pdata)
232 {
233 u32 val, map;
234 u16 vsec;
235 u64 off;
236
237 vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_SYNOPSYS,
238 DW_PCIE_SYNOPSYS_VSEC_DMA_ID);
239 if (!vsec)
240 return;
241
242 pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val);
243 if (PCI_VNDR_HEADER_REV(val) != 0x00 ||
244 PCI_VNDR_HEADER_LEN(val) != 0x18)
245 return;
246
247 pci_dbg(pdev, "Detected Synopsys PCIe Vendor-Specific Extended Capability DMA\n");
248 pci_read_config_dword(pdev, vsec + 0x8, &val);
249 map = FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_MAP, val);
250 if (map != EDMA_MF_EDMA_LEGACY &&
251 map != EDMA_MF_EDMA_UNROLL &&
252 map != EDMA_MF_HDMA_COMPAT &&
253 map != EDMA_MF_HDMA_NATIVE)
254 return;
255
256 pdata->mf = map;
257 pdata->rg.bar = FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_BAR, val);
258
259 pci_read_config_dword(pdev, vsec + 0xc, &val);
260 pdata->wr_ch_cnt = min_t(u16, pdata->wr_ch_cnt,
261 FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_WR_CH, val));
262 pdata->rd_ch_cnt = min_t(u16, pdata->rd_ch_cnt,
263 FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_RD_CH, val));
264
265 pci_read_config_dword(pdev, vsec + 0x14, &val);
266 off = val;
267 pci_read_config_dword(pdev, vsec + 0x10, &val);
268 off <<= 32;
269 off |= val;
270 pdata->rg.off = off;
271 }
272
dw_edma_pcie_get_xilinx_dma_data(struct pci_dev * pdev,struct dw_edma_pcie_data * pdata)273 static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev,
274 struct dw_edma_pcie_data *pdata)
275 {
276 u32 val, map;
277 u16 vsec;
278 u64 off;
279
280 pdata->devmem_phys_off = DW_PCIE_XILINX_MDB_INVALID_ADDR;
281
282 vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX,
283 DW_PCIE_XILINX_MDB_VSEC_DMA_ID);
284 if (!vsec)
285 return;
286
287 pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val);
288 if (PCI_VNDR_HEADER_REV(val) != 0x00 ||
289 PCI_VNDR_HEADER_LEN(val) != 0x18)
290 return;
291
292 pci_dbg(pdev, "Detected Xilinx PCIe Vendor-Specific Extended Capability DMA\n");
293 pci_read_config_dword(pdev, vsec + 0x8, &val);
294 map = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_MAP, val);
295 if (map != EDMA_MF_HDMA_NATIVE)
296 return;
297
298 pdata->mf = map;
299 pdata->rg.bar = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_BAR, val);
300
301 pci_read_config_dword(pdev, vsec + 0xc, &val);
302 pdata->wr_ch_cnt = min(pdata->wr_ch_cnt,
303 FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH, val));
304 pdata->rd_ch_cnt = min(pdata->rd_ch_cnt,
305 FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH, val));
306
307 pci_read_config_dword(pdev, vsec + 0x14, &val);
308 off = val;
309 pci_read_config_dword(pdev, vsec + 0x10, &val);
310 off <<= 32;
311 off |= val;
312 pdata->rg.off = off;
313
314 vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX,
315 DW_PCIE_XILINX_MDB_VSEC_ID);
316 if (!vsec)
317 return;
318
319 pci_read_config_dword(pdev,
320 vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH,
321 &val);
322 off = val;
323 pci_read_config_dword(pdev,
324 vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW,
325 &val);
326 off <<= 32;
327 off |= val;
328 pdata->devmem_phys_off = off;
329 }
330
331 static int
dw_edma_pcie_parse_synopsys_caps(struct pci_dev * pdev,struct dw_edma_pcie_data * pdata)332 dw_edma_pcie_parse_synopsys_caps(struct pci_dev *pdev,
333 struct dw_edma_pcie_data *pdata)
334 {
335 dw_edma_pcie_get_synopsys_dma_data(pdev, pdata);
336
337 return 0;
338 }
339
340 static int
dw_edma_pcie_parse_xilinx_caps(struct pci_dev * pdev,struct dw_edma_pcie_data * pdata)341 dw_edma_pcie_parse_xilinx_caps(struct pci_dev *pdev,
342 struct dw_edma_pcie_data *pdata)
343 {
344 dw_edma_pcie_get_xilinx_dma_data(pdev, pdata);
345
346 /*
347 * There is no valid address found for the LL memory space on the
348 * device side. In the absence of LL base address use the non-LL mode or
349 * simple mode supported by the HDMA IP.
350 */
351 if (pdata->devmem_phys_off == DW_PCIE_XILINX_MDB_INVALID_ADDR) {
352 pdata->cfg_non_ll = true;
353 return 0;
354 }
355
356 /*
357 * Configure the channel LL and data blocks if number of channels
358 * enabled in VSEC capability are more than the channels configured in
359 * xilinx_mdb_data.
360 */
361 dw_edma_set_chan_region_offset(pdata, BAR_2, 0,
362 DW_PCIE_XILINX_MDB_LL_OFF_GAP,
363 DW_PCIE_XILINX_MDB_LL_SIZE,
364 DW_PCIE_XILINX_MDB_DT_OFF_GAP,
365 DW_PCIE_XILINX_MDB_DT_SIZE);
366
367 return 0;
368 }
369
dw_edma_get_phys_addr(struct pci_dev * pdev,const struct dw_edma_pcie_match_data * match,struct dw_edma_pcie_data * pdata,enum pci_barno bar)370 static u64 dw_edma_get_phys_addr(struct pci_dev *pdev,
371 const struct dw_edma_pcie_match_data *match,
372 struct dw_edma_pcie_data *pdata,
373 enum pci_barno bar)
374 {
375 if (match->flags & DW_EDMA_PCIE_F_DEVMEM_PHYS_OFF)
376 return pdata->devmem_phys_off;
377
378 return pci_bus_address(pdev, bar);
379 }
380
dw_edma_get_block_addr(struct pci_dev * pdev,const struct dw_edma_pcie_match_data * match,struct dw_edma_pcie_data * pdata,const struct dw_edma_block * block)381 static u64 dw_edma_get_block_addr(struct pci_dev *pdev,
382 const struct dw_edma_pcie_match_data *match,
383 struct dw_edma_pcie_data *pdata,
384 const struct dw_edma_block *block)
385 {
386 if (block->paddr_valid)
387 return block->paddr;
388
389 return dw_edma_get_phys_addr(pdev, match, pdata, block->bar) +
390 block->off;
391 }
392
dw_edma_pcie_probe(struct pci_dev * pdev,const struct pci_device_id * pid)393 static int dw_edma_pcie_probe(struct pci_dev *pdev,
394 const struct pci_device_id *pid)
395 {
396 const struct dw_edma_pcie_match_data *match = (void *)pid->driver_data;
397 const struct dw_edma_pcie_data *pdata;
398 struct device *dev = &pdev->dev;
399 struct dw_edma_chip *chip;
400 int err, nr_irqs;
401 int i, mask;
402
403 if (!match)
404 return -ENODEV;
405 pdata = match->data;
406
407 if (!pdata)
408 return -ENODEV;
409
410 struct dw_edma_pcie_data *dma_data __free(kfree) =
411 kmemdup(pdata, sizeof(*dma_data), GFP_KERNEL);
412 if (!dma_data)
413 return -ENOMEM;
414
415 /* Enable PCI device */
416 err = pcim_enable_device(pdev);
417 if (err) {
418 pci_err(pdev, "enabling device failed\n");
419 return err;
420 }
421
422 /* Let device-specific discovery override the static template data. */
423 if (!match->parse_caps || !match->plat_ops)
424 return -EINVAL;
425
426 err = match->parse_caps(pdev, dma_data);
427 if (err)
428 return err;
429
430 /* Mapping PCI BAR regions */
431 mask = BIT(dma_data->rg.bar);
432 for (i = 0; i < dma_data->wr_ch_cnt; i++) {
433 mask |= BIT(dma_data->ll_wr[i].bar);
434 if (dma_data->dt_wr[i].sz)
435 mask |= BIT(dma_data->dt_wr[i].bar);
436 }
437 for (i = 0; i < dma_data->rd_ch_cnt; i++) {
438 mask |= BIT(dma_data->ll_rd[i].bar);
439 if (dma_data->dt_rd[i].sz)
440 mask |= BIT(dma_data->dt_rd[i].bar);
441 }
442 err = pcim_iomap_regions(pdev, mask, pci_name(pdev));
443 if (err) {
444 pci_err(pdev, "eDMA BAR I/O remapping failed\n");
445 return err;
446 }
447
448 pci_set_master(pdev);
449
450 /* DMA configuration */
451 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
452 if (err) {
453 pci_err(pdev, "DMA mask 64 set failed\n");
454 return err;
455 }
456
457 /* Data structure allocation */
458 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
459 if (!chip)
460 return -ENOMEM;
461
462 /* IRQs allocation */
463 nr_irqs = pci_alloc_irq_vectors(pdev, 1, dma_data->irqs,
464 PCI_IRQ_MSI | PCI_IRQ_MSIX);
465 if (nr_irqs < 1) {
466 pci_err(pdev, "fail to alloc IRQ vector (number of IRQs=%u)\n",
467 nr_irqs);
468 return -EPERM;
469 }
470
471 /* Data structure initialization */
472 chip->dev = dev;
473
474 chip->mf = dma_data->mf;
475 chip->flags = match->chip_flags;
476 chip->func_no = PCI_FUNC(pdev->devfn);
477 chip->nr_irqs = nr_irqs;
478 chip->ops = match->plat_ops;
479 chip->cfg_non_ll = dma_data->cfg_non_ll;
480
481 chip->ll_wr_cnt = dma_data->wr_ch_cnt;
482 chip->ll_rd_cnt = dma_data->rd_ch_cnt;
483
484 chip->reg_base = pcim_iomap_table(pdev)[dma_data->rg.bar];
485 if (!chip->reg_base)
486 return -ENOMEM;
487 if (match->flags & DW_EDMA_PCIE_F_REG_OFFSET)
488 chip->reg_base += dma_data->rg.off;
489
490 for (i = 0; i < chip->ll_wr_cnt && !dma_data->cfg_non_ll; i++) {
491 struct dw_edma_region *ll_region = &chip->ll_region_wr[i];
492 struct dw_edma_region *dt_region = &chip->dt_region_wr[i];
493 struct dw_edma_block *ll_block = &dma_data->ll_wr[i];
494 struct dw_edma_block *dt_block = &dma_data->dt_wr[i];
495
496 ll_region->vaddr.io = pcim_iomap_table(pdev)[ll_block->bar];
497 if (!ll_region->vaddr.io)
498 return -ENOMEM;
499
500 ll_region->vaddr.io += ll_block->off;
501 ll_region->paddr = dw_edma_get_block_addr(pdev, match, dma_data,
502 ll_block);
503 ll_region->sz = ll_block->sz;
504
505 if (!dt_block->sz)
506 continue;
507
508 dt_region->vaddr.io = pcim_iomap_table(pdev)[dt_block->bar];
509 if (!dt_region->vaddr.io)
510 return -ENOMEM;
511
512 dt_region->vaddr.io += dt_block->off;
513 dt_region->paddr = dw_edma_get_block_addr(pdev, match, dma_data,
514 dt_block);
515 dt_region->sz = dt_block->sz;
516 }
517
518 for (i = 0; i < chip->ll_rd_cnt && !dma_data->cfg_non_ll; i++) {
519 struct dw_edma_region *ll_region = &chip->ll_region_rd[i];
520 struct dw_edma_region *dt_region = &chip->dt_region_rd[i];
521 struct dw_edma_block *ll_block = &dma_data->ll_rd[i];
522 struct dw_edma_block *dt_block = &dma_data->dt_rd[i];
523
524 ll_region->vaddr.io = pcim_iomap_table(pdev)[ll_block->bar];
525 if (!ll_region->vaddr.io)
526 return -ENOMEM;
527
528 ll_region->vaddr.io += ll_block->off;
529 ll_region->paddr = dw_edma_get_block_addr(pdev, match, dma_data,
530 ll_block);
531 ll_region->sz = ll_block->sz;
532
533 if (!dt_block->sz)
534 continue;
535
536 dt_region->vaddr.io = pcim_iomap_table(pdev)[dt_block->bar];
537 if (!dt_region->vaddr.io)
538 return -ENOMEM;
539
540 dt_region->vaddr.io += dt_block->off;
541 dt_region->paddr = dw_edma_get_block_addr(pdev, match, dma_data,
542 dt_block);
543 dt_region->sz = dt_block->sz;
544 }
545
546 /* Debug info */
547 if (chip->mf == EDMA_MF_EDMA_LEGACY)
548 pci_dbg(pdev, "Version:\teDMA Port Logic (0x%x)\n", chip->mf);
549 else if (chip->mf == EDMA_MF_EDMA_UNROLL)
550 pci_dbg(pdev, "Version:\teDMA Unroll (0x%x)\n", chip->mf);
551 else if (chip->mf == EDMA_MF_HDMA_COMPAT)
552 pci_dbg(pdev, "Version:\tHDMA Compatible (0x%x)\n", chip->mf);
553 else if (chip->mf == EDMA_MF_HDMA_NATIVE)
554 pci_dbg(pdev, "Version:\tHDMA Native (0x%x)\n", chip->mf);
555 else
556 pci_dbg(pdev, "Version:\tUnknown (0x%x)\n", chip->mf);
557
558 pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p)\n",
559 dma_data->rg.bar, dma_data->rg.off, dma_data->rg.sz,
560 chip->reg_base);
561
562
563 for (i = 0; i < chip->ll_wr_cnt; i++) {
564 pci_dbg(pdev, "L. List:\tWRITE CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
565 i, dma_data->ll_wr[i].bar,
566 dma_data->ll_wr[i].off, chip->ll_region_wr[i].sz,
567 chip->ll_region_wr[i].vaddr.io, &chip->ll_region_wr[i].paddr);
568
569 if (!dma_data->dt_wr[i].sz)
570 continue;
571
572 pci_dbg(pdev, "Data:\tWRITE CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
573 i, dma_data->dt_wr[i].bar,
574 dma_data->dt_wr[i].off, chip->dt_region_wr[i].sz,
575 chip->dt_region_wr[i].vaddr.io,
576 &chip->dt_region_wr[i].paddr);
577 }
578
579 for (i = 0; i < chip->ll_rd_cnt; i++) {
580 pci_dbg(pdev, "L. List:\tREAD CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
581 i, dma_data->ll_rd[i].bar,
582 dma_data->ll_rd[i].off, chip->ll_region_rd[i].sz,
583 chip->ll_region_rd[i].vaddr.io, &chip->ll_region_rd[i].paddr);
584
585 if (!dma_data->dt_rd[i].sz)
586 continue;
587
588 pci_dbg(pdev, "Data:\tREAD CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
589 i, dma_data->dt_rd[i].bar,
590 dma_data->dt_rd[i].off, chip->dt_region_rd[i].sz,
591 chip->dt_region_rd[i].vaddr.io,
592 &chip->dt_region_rd[i].paddr);
593 }
594
595 pci_dbg(pdev, "Nr. IRQs:\t%u\n", chip->nr_irqs);
596
597 /* Validating if PCI interrupts were enabled */
598 if (!pci_dev_msi_enabled(pdev)) {
599 pci_err(pdev, "enable interrupt failed\n");
600 return -EPERM;
601 }
602
603 /* Starting eDMA driver */
604 err = dw_edma_probe(chip);
605 if (err) {
606 pci_err(pdev, "eDMA probe failed\n");
607 return err;
608 }
609
610 /* Saving data structure reference */
611 pci_set_drvdata(pdev, chip);
612
613 return 0;
614 }
615
dw_edma_pcie_remove(struct pci_dev * pdev)616 static void dw_edma_pcie_remove(struct pci_dev *pdev)
617 {
618 struct dw_edma_chip *chip = pci_get_drvdata(pdev);
619 int err;
620
621 /* Stopping eDMA driver */
622 err = dw_edma_remove(chip);
623 if (err)
624 pci_warn(pdev, "can't remove device properly: %d\n", err);
625 }
626
627 static const struct dw_edma_pcie_match_data snps_edda_match_data = {
628 .data = &snps_edda_data,
629 .plat_ops = &dw_edma_pcie_plat_ops,
630 .parse_caps = dw_edma_pcie_parse_synopsys_caps,
631 };
632
633 static const struct dw_edma_pcie_match_data xilinx_mdb_match_data = {
634 .data = &xilinx_mdb_data,
635 .plat_ops = &dw_edma_pcie_plat_ops,
636 .parse_caps = dw_edma_pcie_parse_xilinx_caps,
637 .flags = DW_EDMA_PCIE_F_DEVMEM_PHYS_OFF,
638 };
639
640 static const struct dw_edma_pcie_match_data xilinx_cpm6_dma_match_data = {
641 .data = &xilinx_cpm6_dma_data,
642 .plat_ops = &dw_edma_pcie_plat_ops,
643 .parse_caps = dw_edma_pcie_parse_xilinx_caps,
644 .flags = DW_EDMA_PCIE_F_DEVMEM_PHYS_OFF,
645 };
646
647 static const struct pci_device_id dw_edma_pcie_id_table[] = {
648 { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_match_data) },
649 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B054),
650 .driver_data = (kernel_ulong_t)&xilinx_mdb_match_data },
651 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B00F),
652 .driver_data = (kernel_ulong_t)&xilinx_cpm6_dma_match_data },
653 { }
654 };
655 MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);
656
657 static struct pci_driver dw_edma_pcie_driver = {
658 .name = "dw-edma-pcie",
659 .id_table = dw_edma_pcie_id_table,
660 .probe = dw_edma_pcie_probe,
661 .remove = dw_edma_pcie_remove,
662 };
663
664 module_pci_driver(dw_edma_pcie_driver);
665
666 MODULE_LICENSE("GPL v2");
667 MODULE_DESCRIPTION("Synopsys DesignWare eDMA PCIe driver");
668 MODULE_AUTHOR("Gustavo Pimentel <gustavo.pimentel@synopsys.com>");
669