1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * it87.c - Part of lm_sensors, Linux kernel modules for hardware 4 * monitoring. 5 * 6 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a 7 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in 8 * addition to an Environment Controller (Enhanced Hardware Monitor and 9 * Fan Controller) 10 * 11 * This driver supports only the Environment Controller in the IT8705F and 12 * similar parts. The other devices are supported by different drivers. 13 * 14 * Supports: IT8603E Super I/O chip w/LPC interface 15 * IT8620E Super I/O chip w/LPC interface 16 * IT8622E Super I/O chip w/LPC interface 17 * IT8623E Super I/O chip w/LPC interface 18 * IT8628E Super I/O chip w/LPC interface 19 * IT8689E Super I/O chip w/LPC interface 20 * IT8705F Super I/O chip w/LPC interface 21 * IT8712F Super I/O chip w/LPC interface 22 * IT8716F Super I/O chip w/LPC interface 23 * IT8718F Super I/O chip w/LPC interface 24 * IT8720F Super I/O chip w/LPC interface 25 * IT8721F Super I/O chip w/LPC interface 26 * IT8726F Super I/O chip w/LPC interface 27 * IT8728F Super I/O chip w/LPC interface 28 * IT8732F Super I/O chip w/LPC interface 29 * IT8758E Super I/O chip w/LPC interface 30 * IT8771E Super I/O chip w/LPC interface 31 * IT8772E Super I/O chip w/LPC interface 32 * IT8781F Super I/O chip w/LPC interface 33 * IT8782F Super I/O chip w/LPC interface 34 * IT8783E/F Super I/O chip w/LPC interface 35 * IT8786E Super I/O chip w/LPC interface 36 * IT8790E Super I/O chip w/LPC interface 37 * IT8792E Super I/O chip w/LPC interface 38 * IT87952E Super I/O chip w/LPC interface 39 * Sis950 A clone of the IT8705F 40 * 41 * Copyright (C) 2001 Chris Gauthron 42 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de> 43 */ 44 45 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 46 47 #include <linux/bitops.h> 48 #include <linux/module.h> 49 #include <linux/init.h> 50 #include <linux/slab.h> 51 #include <linux/jiffies.h> 52 #include <linux/platform_device.h> 53 #include <linux/hwmon.h> 54 #include <linux/hwmon-sysfs.h> 55 #include <linux/hwmon-vid.h> 56 #include <linux/err.h> 57 #include <linux/mutex.h> 58 #include <linux/sysfs.h> 59 #include <linux/string.h> 60 #include <linux/dmi.h> 61 #include <linux/acpi.h> 62 #include <linux/io.h> 63 64 #define DRVNAME "it87" 65 66 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732, 67 it8771, it8772, it8781, it8782, it8783, it8786, it8790, 68 it8792, it8603, it8620, it8622, it8628, it8689, it87952 }; 69 70 static struct platform_device *it87_pdev[2]; 71 72 #define REG_2E 0x2e /* The register to read/write */ 73 #define REG_4E 0x4e /* Secondary register to read/write */ 74 75 #define DEV 0x07 /* Register: Logical device select */ 76 #define PME 0x04 /* The device with the fan registers in it */ 77 78 /* The device with the IT8718F/IT8720F VID value in it */ 79 #define GPIO 0x07 80 81 #define DEVID 0x20 /* Register: Device ID */ 82 #define DEVREV 0x22 /* Register: Device Revision */ 83 84 static inline void __superio_enter(int ioreg) 85 { 86 outb(0x87, ioreg); 87 outb(0x01, ioreg); 88 outb(0x55, ioreg); 89 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg); 90 } 91 92 static inline int superio_inb(int ioreg, int reg) 93 { 94 outb(reg, ioreg); 95 return inb(ioreg + 1); 96 } 97 98 static inline void superio_outb(int ioreg, int reg, int val) 99 { 100 outb(reg, ioreg); 101 outb(val, ioreg + 1); 102 } 103 104 static int superio_inw(int ioreg, int reg) 105 { 106 int val; 107 108 outb(reg++, ioreg); 109 val = inb(ioreg + 1) << 8; 110 outb(reg, ioreg); 111 val |= inb(ioreg + 1); 112 return val; 113 } 114 115 static inline void superio_select(int ioreg, int ldn) 116 { 117 outb(DEV, ioreg); 118 outb(ldn, ioreg + 1); 119 } 120 121 static inline int superio_enter(int ioreg, bool noentry) 122 { 123 /* 124 * Try to reserve ioreg and ioreg + 1 for exclusive access. 125 */ 126 if (!request_muxed_region(ioreg, 2, DRVNAME)) 127 return -EBUSY; 128 129 if (!noentry) 130 __superio_enter(ioreg); 131 return 0; 132 } 133 134 static inline void superio_exit(int ioreg, bool noexit) 135 { 136 if (!noexit) { 137 outb(0x02, ioreg); 138 outb(0x02, ioreg + 1); 139 } 140 release_region(ioreg, 2); 141 } 142 143 /* Logical device 4 registers */ 144 #define IT8712F_DEVID 0x8712 145 #define IT8705F_DEVID 0x8705 146 #define IT8716F_DEVID 0x8716 147 #define IT8718F_DEVID 0x8718 148 #define IT8720F_DEVID 0x8720 149 #define IT8721F_DEVID 0x8721 150 #define IT8726F_DEVID 0x8726 151 #define IT8728F_DEVID 0x8728 152 #define IT8732F_DEVID 0x8732 153 #define IT8792E_DEVID 0x8733 154 #define IT8771E_DEVID 0x8771 155 #define IT8772E_DEVID 0x8772 156 #define IT8781F_DEVID 0x8781 157 #define IT8782F_DEVID 0x8782 158 #define IT8783E_DEVID 0x8783 159 #define IT8786E_DEVID 0x8786 160 #define IT8790E_DEVID 0x8790 161 #define IT8603E_DEVID 0x8603 162 #define IT8620E_DEVID 0x8620 163 #define IT8622E_DEVID 0x8622 164 #define IT8623E_DEVID 0x8623 165 #define IT8628E_DEVID 0x8628 166 #define IT8689E_DEVID 0x8689 167 #define IT87952E_DEVID 0x8695 168 169 /* Logical device 4 (Environmental Monitor) registers */ 170 #define IT87_ACT_REG 0x30 171 #define IT87_BASE_REG 0x60 172 #define IT87_SPECIAL_CFG_REG 0xf3 /* special configuration register */ 173 174 /* Logical device 7 registers (IT8712F and later) */ 175 #define IT87_SIO_GPIO1_REG 0x25 176 #define IT87_SIO_GPIO2_REG 0x26 177 #define IT87_SIO_GPIO3_REG 0x27 178 #define IT87_SIO_GPIO4_REG 0x28 179 #define IT87_SIO_GPIO5_REG 0x29 180 #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */ 181 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */ 182 #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */ 183 #define IT87_SIO_VID_REG 0xfc /* VID value */ 184 #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */ 185 186 /* Force chip IDs to specified values. Should only be used for testing */ 187 static unsigned short force_id[2]; 188 static unsigned int force_id_cnt; 189 190 /* ACPI resource conflicts are ignored if this parameter is set to 1 */ 191 static bool ignore_resource_conflict; 192 193 /* Update battery voltage after every reading if true */ 194 static bool update_vbat; 195 196 /* Not all BIOSes properly configure the PWM registers */ 197 static bool fix_pwm_polarity; 198 199 /* Many IT87 constants specified below */ 200 201 /* Length of ISA address segment */ 202 #define IT87_EXTENT 8 203 204 /* Length of ISA address segment for Environmental Controller */ 205 #define IT87_EC_EXTENT 2 206 207 /* Offset of EC registers from ISA base address */ 208 #define IT87_EC_OFFSET 5 209 210 /* Where are the ISA address/data registers relative to the EC base address */ 211 #define IT87_ADDR_REG_OFFSET 0 212 #define IT87_DATA_REG_OFFSET 1 213 214 /*----- The IT87 registers -----*/ 215 216 #define IT87_REG_CONFIG 0x00 217 218 #define IT87_REG_ALARM1 0x01 219 #define IT87_REG_ALARM2 0x02 220 #define IT87_REG_ALARM3 0x03 221 222 /* 223 * The IT8718F and IT8720F have the VID value in a different register, in 224 * Super-I/O configuration space. 225 */ 226 #define IT87_REG_VID 0x0a 227 228 /* Interface Selection register on other chips */ 229 #define IT87_REG_IFSEL 0x0a 230 231 /* 232 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b 233 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer 234 * mode. 235 */ 236 #define IT87_REG_FAN_DIV 0x0b 237 #define IT87_REG_FAN_16BIT 0x0c 238 239 /* 240 * Monitors: 241 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12) 242 * - up to 6 temp (1 to 6) 243 * - up to 6 fan (1 to 6) 244 */ 245 246 static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c }; 247 static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e }; 248 static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d }; 249 static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f }; 250 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 }; 251 252 #define IT87_REG_FAN_MAIN_CTRL 0x13 253 #define IT87_REG_FAN_CTL 0x14 254 static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf }; 255 static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab }; 256 257 static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 258 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e }; 259 260 #define IT87_REG_TEMP(nr) (0x29 + (nr)) 261 262 #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2) 263 #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2) 264 #define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2) 265 #define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2) 266 267 #define IT87_REG_VIN_ENABLE 0x50 268 #define IT87_REG_TEMP_ENABLE 0x51 269 #define IT87_REG_TEMP_EXTRA 0x55 270 #define IT87_REG_BEEP_ENABLE 0x5c 271 272 #define IT87_REG_CHIPID 0x58 273 274 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 }; 275 276 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i)) 277 #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i)) 278 279 #define IT87_REG_TEMP456_ENABLE 0x77 280 281 #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN) 282 #define NUM_VIN_LIMIT 8 283 #define NUM_TEMP 6 284 #define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET) 285 #define NUM_TEMP_LIMIT 3 286 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN) 287 #define NUM_FAN_DIV 3 288 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM) 289 #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM) 290 291 struct it87_devices { 292 const char *name; 293 const char * const model; 294 u32 features; 295 u8 peci_mask; 296 u8 old_peci_mask; 297 u8 smbus_bitmap; /* SMBus enable bits in extra config register */ 298 u8 ec_special_config; 299 }; 300 301 #define FEAT_12MV_ADC BIT(0) 302 #define FEAT_NEWER_AUTOPWM BIT(1) 303 #define FEAT_OLD_AUTOPWM BIT(2) 304 #define FEAT_16BIT_FANS BIT(3) 305 #define FEAT_TEMP_OFFSET BIT(4) 306 #define FEAT_TEMP_PECI BIT(5) 307 #define FEAT_TEMP_OLD_PECI BIT(6) 308 #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */ 309 #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */ 310 #define FEAT_VID BIT(9) /* Set if chip supports VID */ 311 #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */ 312 #define FEAT_SIX_FANS BIT(11) /* Supports six fans */ 313 #define FEAT_10_9MV_ADC BIT(12) 314 #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */ 315 #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */ 316 #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */ 317 #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */ 318 #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */ 319 #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */ 320 /* 321 * Disabling configuration mode on some chips can result in system 322 * hang-ups and access failures to the Super-IO chip at the 323 * second SIO address. Never exit configuration mode on these 324 * chips to avoid the problem. 325 */ 326 #define FEAT_NOCONF BIT(19) /* Chip conf mode enabled on startup */ 327 #define FEAT_FOUR_FANS BIT(20) /* Supports four fans */ 328 #define FEAT_FOUR_PWM BIT(21) /* Supports four fan controls */ 329 #define FEAT_FOUR_TEMP BIT(22) 330 #define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */ 331 332 static const struct it87_devices it87_devices[] = { 333 [it87] = { 334 .name = "it87", 335 .model = "IT87F", 336 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF, 337 /* may need to overwrite */ 338 }, 339 [it8712] = { 340 .name = "it8712", 341 .model = "IT8712F", 342 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF, 343 /* may need to overwrite */ 344 }, 345 [it8716] = { 346 .name = "it8716", 347 .model = "IT8716F", 348 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 349 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2 350 | FEAT_FANCTL_ONOFF, 351 }, 352 [it8718] = { 353 .name = "it8718", 354 .model = "IT8718F", 355 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 356 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS 357 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 358 .old_peci_mask = 0x4, 359 }, 360 [it8720] = { 361 .name = "it8720", 362 .model = "IT8720F", 363 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 364 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS 365 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 366 .old_peci_mask = 0x4, 367 }, 368 [it8721] = { 369 .name = "it8721", 370 .model = "IT8721F", 371 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 372 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 373 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL 374 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 375 .peci_mask = 0x05, 376 .old_peci_mask = 0x02, /* Actually reports PCH */ 377 }, 378 [it8728] = { 379 .name = "it8728", 380 .model = "IT8728F", 381 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 382 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS 383 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 384 | FEAT_FANCTL_ONOFF, 385 .peci_mask = 0x07, 386 }, 387 [it8732] = { 388 .name = "it8732", 389 .model = "IT8732F", 390 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS 391 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 392 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS 393 | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF, 394 .peci_mask = 0x07, 395 .old_peci_mask = 0x02, /* Actually reports PCH */ 396 }, 397 [it8771] = { 398 .name = "it8771", 399 .model = "IT8771E", 400 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 401 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 402 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 403 /* PECI: guesswork */ 404 /* 12mV ADC (OHM) */ 405 /* 16 bit fans (OHM) */ 406 /* three fans, always 16 bit (guesswork) */ 407 .peci_mask = 0x07, 408 }, 409 [it8772] = { 410 .name = "it8772", 411 .model = "IT8772E", 412 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 413 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 414 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 415 /* PECI (coreboot) */ 416 /* 12mV ADC (HWSensors4, OHM) */ 417 /* 16 bit fans (HWSensors4, OHM) */ 418 /* three fans, always 16 bit (datasheet) */ 419 .peci_mask = 0x07, 420 }, 421 [it8781] = { 422 .name = "it8781", 423 .model = "IT8781F", 424 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 425 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 426 | FEAT_FANCTL_ONOFF, 427 .old_peci_mask = 0x4, 428 }, 429 [it8782] = { 430 .name = "it8782", 431 .model = "IT8782F", 432 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 433 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 434 | FEAT_FANCTL_ONOFF, 435 .old_peci_mask = 0x4, 436 }, 437 [it8783] = { 438 .name = "it8783", 439 .model = "IT8783E/F", 440 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 441 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 442 | FEAT_FANCTL_ONOFF, 443 .old_peci_mask = 0x4, 444 }, 445 [it8786] = { 446 .name = "it8786", 447 .model = "IT8786E", 448 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 449 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 450 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 451 .peci_mask = 0x07, 452 }, 453 [it8790] = { 454 .name = "it8790", 455 .model = "IT8790E", 456 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 457 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 458 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF | FEAT_NOCONF, 459 .peci_mask = 0x07, 460 }, 461 [it8792] = { 462 .name = "it8792", 463 .model = "IT8792E/IT8795E", 464 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS 465 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 466 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FANCTL_ONOFF 467 | FEAT_NOCONF, 468 .peci_mask = 0x07, 469 .old_peci_mask = 0x02, /* Actually reports PCH */ 470 }, 471 [it8603] = { 472 .name = "it8603", 473 .model = "IT8603E", 474 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 475 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 476 | FEAT_AVCC3 | FEAT_PWM_FREQ2, 477 .peci_mask = 0x07, 478 }, 479 [it8620] = { 480 .name = "it8620", 481 .model = "IT8620E", 482 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 483 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS 484 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 485 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_FANCTL_ONOFF, 486 .peci_mask = 0x07, 487 }, 488 [it8622] = { 489 .name = "it8622", 490 .model = "IT8622E", 491 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 492 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS 493 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 494 | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_FOUR_TEMP, 495 .peci_mask = 0x07, 496 .smbus_bitmap = BIT(1) | BIT(2), 497 }, 498 [it8628] = { 499 .name = "it8628", 500 .model = "IT8628E", 501 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 502 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS 503 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 504 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_FANCTL_ONOFF, 505 .peci_mask = 0x07, 506 }, 507 [it8689] = { 508 .name = "it8689", 509 .model = "IT8689E", 510 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 511 | FEAT_TEMP_OFFSET | FEAT_SIX_FANS | FEAT_IN7_INTERNAL 512 | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | FEAT_SIX_TEMP | FEAT_AVCC3 513 | FEAT_FANCTL_ONOFF, 514 .smbus_bitmap = BIT(1) | BIT(2), 515 }, 516 [it87952] = { 517 .name = "it87952", 518 .model = "IT87952E", 519 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS 520 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 521 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FANCTL_ONOFF 522 | FEAT_NOCONF, 523 .peci_mask = 0x07, 524 .old_peci_mask = 0x02, /* Actually reports PCH */ 525 }, 526 }; 527 528 #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS) 529 #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC) 530 #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC) 531 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM) 532 #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM) 533 #define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET) 534 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \ 535 ((data)->peci_mask & BIT(nr))) 536 #define has_temp_old_peci(data, nr) \ 537 (((data)->features & FEAT_TEMP_OLD_PECI) && \ 538 ((data)->old_peci_mask & BIT(nr))) 539 #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG) 540 #define has_four_fans(data) ((data)->features & (FEAT_FOUR_FANS | \ 541 FEAT_FIVE_FANS | \ 542 FEAT_SIX_FANS)) 543 #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \ 544 FEAT_SIX_FANS)) 545 #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS) 546 #define has_vid(data) ((data)->features & FEAT_VID) 547 #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL) 548 #define has_avcc3(data) ((data)->features & FEAT_AVCC3) 549 #define has_four_pwm(data) ((data)->features & (FEAT_FOUR_PWM | \ 550 FEAT_FIVE_PWM | \ 551 FEAT_SIX_PWM)) 552 #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM | \ 553 FEAT_SIX_PWM)) 554 #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM) 555 #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2) 556 #define has_four_temp(data) ((data)->features & FEAT_FOUR_TEMP) 557 #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP) 558 #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V) 559 #define has_noconf(data) ((data)->features & FEAT_NOCONF) 560 #define has_scaling(data) ((data)->features & (FEAT_12MV_ADC | \ 561 FEAT_10_9MV_ADC)) 562 #define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF) 563 564 struct it87_sio_data { 565 int sioaddr; 566 enum chips type; 567 /* Values read from Super-I/O config space */ 568 u8 revision; 569 u8 vid_value; 570 u8 beep_pin; 571 u8 internal; /* Internal sensors can be labeled */ 572 bool need_in7_reroute; 573 /* Features skipped based on config or DMI */ 574 u16 skip_in; 575 u8 skip_vid; 576 u8 skip_fan; 577 u8 skip_pwm; 578 u8 skip_temp; 579 u8 smbus_bitmap; 580 u8 ec_special_config; 581 }; 582 583 /* 584 * For each registered chip, we need to keep some data in memory. 585 * The structure is dynamically allocated. 586 */ 587 struct it87_data { 588 const struct attribute_group *groups[7]; 589 int sioaddr; 590 enum chips type; 591 u32 features; 592 u8 peci_mask; 593 u8 old_peci_mask; 594 595 u8 smbus_bitmap; /* !=0 if SMBus needs to be disabled */ 596 u8 ec_special_config; /* EC special config register restore value */ 597 598 unsigned short addr; 599 const char *name; 600 struct mutex update_lock; 601 bool valid; /* true if following fields are valid */ 602 unsigned long last_updated; /* In jiffies */ 603 604 u16 in_scaled; /* Internal voltage sensors are scaled */ 605 u16 in_internal; /* Bitfield, internal sensors (for labels) */ 606 u16 has_in; /* Bitfield, voltage sensors enabled */ 607 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */ 608 bool need_in7_reroute; 609 u8 has_fan; /* Bitfield, fans enabled */ 610 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */ 611 u8 has_temp; /* Bitfield, temp sensors enabled */ 612 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */ 613 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */ 614 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */ 615 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */ 616 bool has_vid; /* True if VID supported */ 617 u8 vid; /* Register encoding, combined */ 618 u8 vrm; 619 u32 alarms; /* Register encoding, combined */ 620 bool has_beep; /* true if beep supported */ 621 u8 beeps; /* Register encoding */ 622 u8 fan_main_ctrl; /* Register value */ 623 u8 fan_ctl; /* Register value */ 624 625 /* 626 * The following 3 arrays correspond to the same registers up to 627 * the IT8720F. The meaning of bits 6-0 depends on the value of bit 628 * 7, and we want to preserve settings on mode changes, so we have 629 * to track all values separately. 630 * Starting with the IT8721F, the manual PWM duty cycles are stored 631 * in separate registers (8-bit values), so the separate tracking 632 * is no longer needed, but it is still done to keep the driver 633 * simple. 634 */ 635 u8 has_pwm; /* Bitfield, pwm control enabled */ 636 u8 pwm_ctrl[NUM_PWM]; /* Register value */ 637 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */ 638 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */ 639 640 /* Automatic fan speed control registers */ 641 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */ 642 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */ 643 }; 644 645 /* Board specific settings from DMI matching */ 646 struct it87_dmi_data { 647 u8 skip_pwm; /* pwm channels to skip for this board */ 648 }; 649 650 /* Global for results from DMI matching, if needed */ 651 static struct it87_dmi_data *dmi_data; 652 653 static int adc_lsb(const struct it87_data *data, int nr) 654 { 655 int lsb; 656 657 if (has_12mv_adc(data)) 658 lsb = 120; 659 else if (has_10_9mv_adc(data)) 660 lsb = 109; 661 else 662 lsb = 160; 663 if (data->in_scaled & BIT(nr)) 664 lsb <<= 1; 665 return lsb; 666 } 667 668 static u8 in_to_reg(const struct it87_data *data, int nr, long val) 669 { 670 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr)); 671 return clamp_val(val, 0, 255); 672 } 673 674 static int in_from_reg(const struct it87_data *data, int nr, int val) 675 { 676 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10); 677 } 678 679 static inline u8 FAN_TO_REG(long rpm, int div) 680 { 681 if (rpm == 0) 682 return 255; 683 rpm = clamp_val(rpm, 1, 1000000); 684 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254); 685 } 686 687 static inline u16 FAN16_TO_REG(long rpm) 688 { 689 if (rpm == 0) 690 return 0xffff; 691 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe); 692 } 693 694 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \ 695 1350000 / ((val) * (div))) 696 /* The divider is fixed to 2 in 16-bit mode */ 697 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \ 698 1350000 / ((val) * 2)) 699 700 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \ 701 ((val) + 500) / 1000), -128, 127)) 702 #define TEMP_FROM_REG(val) ((val) * 1000) 703 704 static u8 pwm_to_reg(const struct it87_data *data, long val) 705 { 706 if (has_newer_autopwm(data)) 707 return val; 708 else 709 return val >> 1; 710 } 711 712 static int pwm_from_reg(const struct it87_data *data, u8 reg) 713 { 714 if (has_newer_autopwm(data)) 715 return reg; 716 else 717 return (reg & 0x7f) << 1; 718 } 719 720 static int DIV_TO_REG(int val) 721 { 722 int answer = 0; 723 724 while (answer < 7 && (val >>= 1)) 725 answer++; 726 return answer; 727 } 728 729 #define DIV_FROM_REG(val) BIT(val) 730 731 /* 732 * PWM base frequencies. The frequency has to be divided by either 128 or 256, 733 * depending on the chip type, to calculate the actual PWM frequency. 734 * 735 * Some of the chip datasheets suggest a base frequency of 51 kHz instead 736 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency 737 * of 200 Hz. Sometimes both PWM frequency select registers are affected, 738 * sometimes just one. It is unknown if this is a datasheet error or real, 739 * so this is ignored for now. 740 */ 741 static const unsigned int pwm_freq[8] = { 742 48000000, 743 24000000, 744 12000000, 745 8000000, 746 6000000, 747 3000000, 748 1500000, 749 750000, 750 }; 751 752 static int smbus_disable(struct it87_data *data) 753 { 754 int err; 755 756 if (data->smbus_bitmap) { 757 err = superio_enter(data->sioaddr, has_noconf(data)); 758 if (err) 759 return err; 760 superio_select(data->sioaddr, PME); 761 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG, 762 data->ec_special_config & ~data->smbus_bitmap); 763 superio_exit(data->sioaddr, has_noconf(data)); 764 } 765 return 0; 766 } 767 768 static int smbus_enable(struct it87_data *data) 769 { 770 int err; 771 772 if (data->smbus_bitmap) { 773 err = superio_enter(data->sioaddr, has_noconf(data)); 774 if (err) 775 return err; 776 777 superio_select(data->sioaddr, PME); 778 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG, 779 data->ec_special_config); 780 superio_exit(data->sioaddr, has_noconf(data)); 781 } 782 return 0; 783 } 784 785 /* 786 * Must be called with data->update_lock held, except during initialization. 787 * Must be called with SMBus accesses disabled. 788 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, 789 * would slow down the IT87 access and should not be necessary. 790 */ 791 static int it87_read_value(struct it87_data *data, u8 reg) 792 { 793 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); 794 return inb_p(data->addr + IT87_DATA_REG_OFFSET); 795 } 796 797 /* 798 * Must be called with data->update_lock held, except during initialization. 799 * Must be called with SMBus accesses disabled. 800 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, 801 * would slow down the IT87 access and should not be necessary. 802 */ 803 static void it87_write_value(struct it87_data *data, u8 reg, u8 value) 804 { 805 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); 806 outb_p(value, data->addr + IT87_DATA_REG_OFFSET); 807 } 808 809 static void it87_update_pwm_ctrl(struct it87_data *data, int nr) 810 { 811 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]); 812 if (has_newer_autopwm(data)) { 813 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; 814 data->pwm_duty[nr] = it87_read_value(data, 815 IT87_REG_PWM_DUTY[nr]); 816 } else { 817 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */ 818 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; 819 else /* Manual mode */ 820 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f; 821 } 822 823 if (has_old_autopwm(data)) { 824 int i; 825 826 for (i = 0; i < 5 ; i++) 827 data->auto_temp[nr][i] = it87_read_value(data, 828 IT87_REG_AUTO_TEMP(nr, i)); 829 for (i = 0; i < 3 ; i++) 830 data->auto_pwm[nr][i] = it87_read_value(data, 831 IT87_REG_AUTO_PWM(nr, i)); 832 } else if (has_newer_autopwm(data)) { 833 int i; 834 835 /* 836 * 0: temperature hysteresis (base + 5) 837 * 1: fan off temperature (base + 0) 838 * 2: fan start temperature (base + 1) 839 * 3: fan max temperature (base + 2) 840 */ 841 data->auto_temp[nr][0] = 842 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5)); 843 844 for (i = 0; i < 3 ; i++) 845 data->auto_temp[nr][i + 1] = 846 it87_read_value(data, 847 IT87_REG_AUTO_TEMP(nr, i)); 848 /* 849 * 0: start pwm value (base + 3) 850 * 1: pwm slope (base + 4, 1/8th pwm) 851 */ 852 data->auto_pwm[nr][0] = 853 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3)); 854 data->auto_pwm[nr][1] = 855 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4)); 856 } 857 } 858 859 static int it87_lock(struct it87_data *data) 860 { 861 int err; 862 863 mutex_lock(&data->update_lock); 864 err = smbus_disable(data); 865 if (err) 866 mutex_unlock(&data->update_lock); 867 return err; 868 } 869 870 static void it87_unlock(struct it87_data *data) 871 { 872 smbus_enable(data); 873 mutex_unlock(&data->update_lock); 874 } 875 876 static struct it87_data *it87_update_device(struct device *dev) 877 { 878 struct it87_data *data = dev_get_drvdata(dev); 879 struct it87_data *ret = data; 880 int err; 881 int i; 882 883 mutex_lock(&data->update_lock); 884 885 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) || 886 !data->valid) { 887 err = smbus_disable(data); 888 if (err) { 889 ret = ERR_PTR(err); 890 goto unlock; 891 } 892 if (update_vbat) { 893 /* 894 * Cleared after each update, so reenable. Value 895 * returned by this read will be previous value 896 */ 897 it87_write_value(data, IT87_REG_CONFIG, 898 it87_read_value(data, IT87_REG_CONFIG) | 0x40); 899 } 900 for (i = 0; i < NUM_VIN; i++) { 901 if (!(data->has_in & BIT(i))) 902 continue; 903 904 data->in[i][0] = 905 it87_read_value(data, IT87_REG_VIN[i]); 906 907 /* VBAT and AVCC don't have limit registers */ 908 if (i >= NUM_VIN_LIMIT) 909 continue; 910 911 data->in[i][1] = 912 it87_read_value(data, IT87_REG_VIN_MIN(i)); 913 data->in[i][2] = 914 it87_read_value(data, IT87_REG_VIN_MAX(i)); 915 } 916 917 for (i = 0; i < NUM_FAN; i++) { 918 /* Skip disabled fans */ 919 if (!(data->has_fan & BIT(i))) 920 continue; 921 922 data->fan[i][1] = 923 it87_read_value(data, IT87_REG_FAN_MIN[i]); 924 data->fan[i][0] = it87_read_value(data, 925 IT87_REG_FAN[i]); 926 /* Add high byte if in 16-bit mode */ 927 if (has_16bit_fans(data)) { 928 data->fan[i][0] |= it87_read_value(data, 929 IT87_REG_FANX[i]) << 8; 930 data->fan[i][1] |= it87_read_value(data, 931 IT87_REG_FANX_MIN[i]) << 8; 932 } 933 } 934 for (i = 0; i < NUM_TEMP; i++) { 935 if (!(data->has_temp & BIT(i))) 936 continue; 937 data->temp[i][0] = 938 it87_read_value(data, IT87_REG_TEMP(i)); 939 940 if (has_temp_offset(data) && i < NUM_TEMP_OFFSET) 941 data->temp[i][3] = 942 it87_read_value(data, 943 IT87_REG_TEMP_OFFSET[i]); 944 945 if (i >= NUM_TEMP_LIMIT) 946 continue; 947 948 data->temp[i][1] = 949 it87_read_value(data, IT87_REG_TEMP_LOW(i)); 950 data->temp[i][2] = 951 it87_read_value(data, IT87_REG_TEMP_HIGH(i)); 952 } 953 954 /* Newer chips don't have clock dividers */ 955 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) { 956 i = it87_read_value(data, IT87_REG_FAN_DIV); 957 data->fan_div[0] = i & 0x07; 958 data->fan_div[1] = (i >> 3) & 0x07; 959 data->fan_div[2] = (i & 0x40) ? 3 : 1; 960 } 961 962 data->alarms = 963 it87_read_value(data, IT87_REG_ALARM1) | 964 (it87_read_value(data, IT87_REG_ALARM2) << 8) | 965 (it87_read_value(data, IT87_REG_ALARM3) << 16); 966 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); 967 968 data->fan_main_ctrl = it87_read_value(data, 969 IT87_REG_FAN_MAIN_CTRL); 970 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL); 971 for (i = 0; i < NUM_PWM; i++) { 972 if (!(data->has_pwm & BIT(i))) 973 continue; 974 it87_update_pwm_ctrl(data, i); 975 } 976 977 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE); 978 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); 979 /* 980 * The IT8705F does not have VID capability. 981 * The IT8718F and later don't use IT87_REG_VID for the 982 * same purpose. 983 */ 984 if (data->type == it8712 || data->type == it8716) { 985 data->vid = it87_read_value(data, IT87_REG_VID); 986 /* 987 * The older IT8712F revisions had only 5 VID pins, 988 * but we assume it is always safe to read 6 bits. 989 */ 990 data->vid &= 0x3f; 991 } 992 data->last_updated = jiffies; 993 data->valid = true; 994 smbus_enable(data); 995 } 996 unlock: 997 mutex_unlock(&data->update_lock); 998 return ret; 999 } 1000 1001 static ssize_t show_in(struct device *dev, struct device_attribute *attr, 1002 char *buf) 1003 { 1004 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1005 struct it87_data *data = it87_update_device(dev); 1006 int index = sattr->index; 1007 int nr = sattr->nr; 1008 1009 if (IS_ERR(data)) 1010 return PTR_ERR(data); 1011 1012 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index])); 1013 } 1014 1015 static ssize_t set_in(struct device *dev, struct device_attribute *attr, 1016 const char *buf, size_t count) 1017 { 1018 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1019 struct it87_data *data = dev_get_drvdata(dev); 1020 int index = sattr->index; 1021 int nr = sattr->nr; 1022 unsigned long val; 1023 int err; 1024 1025 if (kstrtoul(buf, 10, &val) < 0) 1026 return -EINVAL; 1027 1028 err = it87_lock(data); 1029 if (err) 1030 return err; 1031 1032 data->in[nr][index] = in_to_reg(data, nr, val); 1033 it87_write_value(data, 1034 index == 1 ? IT87_REG_VIN_MIN(nr) 1035 : IT87_REG_VIN_MAX(nr), 1036 data->in[nr][index]); 1037 it87_unlock(data); 1038 return count; 1039 } 1040 1041 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0); 1042 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in, 1043 0, 1); 1044 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in, 1045 0, 2); 1046 1047 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0); 1048 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in, 1049 1, 1); 1050 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in, 1051 1, 2); 1052 1053 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0); 1054 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in, 1055 2, 1); 1056 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in, 1057 2, 2); 1058 1059 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0); 1060 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in, 1061 3, 1); 1062 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in, 1063 3, 2); 1064 1065 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0); 1066 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in, 1067 4, 1); 1068 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in, 1069 4, 2); 1070 1071 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0); 1072 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in, 1073 5, 1); 1074 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in, 1075 5, 2); 1076 1077 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0); 1078 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in, 1079 6, 1); 1080 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in, 1081 6, 2); 1082 1083 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0); 1084 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in, 1085 7, 1); 1086 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in, 1087 7, 2); 1088 1089 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0); 1090 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0); 1091 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0); 1092 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0); 1093 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0); 1094 1095 /* Up to 6 temperatures */ 1096 static ssize_t show_temp(struct device *dev, struct device_attribute *attr, 1097 char *buf) 1098 { 1099 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1100 int nr = sattr->nr; 1101 int index = sattr->index; 1102 struct it87_data *data = it87_update_device(dev); 1103 1104 if (IS_ERR(data)) 1105 return PTR_ERR(data); 1106 1107 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index])); 1108 } 1109 1110 static ssize_t set_temp(struct device *dev, struct device_attribute *attr, 1111 const char *buf, size_t count) 1112 { 1113 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1114 int nr = sattr->nr; 1115 int index = sattr->index; 1116 struct it87_data *data = dev_get_drvdata(dev); 1117 long val; 1118 u8 reg, regval; 1119 int err; 1120 1121 if (kstrtol(buf, 10, &val) < 0) 1122 return -EINVAL; 1123 1124 err = it87_lock(data); 1125 if (err) 1126 return err; 1127 1128 switch (index) { 1129 default: 1130 case 1: 1131 reg = IT87_REG_TEMP_LOW(nr); 1132 break; 1133 case 2: 1134 reg = IT87_REG_TEMP_HIGH(nr); 1135 break; 1136 case 3: 1137 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE); 1138 if (!(regval & 0x80)) { 1139 regval |= 0x80; 1140 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval); 1141 } 1142 data->valid = false; 1143 reg = IT87_REG_TEMP_OFFSET[nr]; 1144 break; 1145 } 1146 1147 data->temp[nr][index] = TEMP_TO_REG(val); 1148 it87_write_value(data, reg, data->temp[nr][index]); 1149 it87_unlock(data); 1150 return count; 1151 } 1152 1153 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0); 1154 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 1155 0, 1); 1156 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 1157 0, 2); 1158 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp, 1159 set_temp, 0, 3); 1160 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0); 1161 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 1162 1, 1); 1163 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 1164 1, 2); 1165 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp, 1166 set_temp, 1, 3); 1167 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0); 1168 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 1169 2, 1); 1170 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 1171 2, 2); 1172 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp, 1173 set_temp, 2, 3); 1174 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0); 1175 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0); 1176 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0); 1177 1178 static int get_temp_type(struct it87_data *data, int index) 1179 { 1180 /* 1181 * 2 is deprecated; 1182 * 3 = thermal diode; 1183 * 4 = thermistor; 1184 * 5 = AMDTSI; 1185 * 6 = Intel PECI; 1186 * 0 = disabled 1187 */ 1188 u8 reg, extra; 1189 int ttype, type = 0; 1190 1191 /* Detect PECI vs. AMDTSI */ 1192 ttype = 6; 1193 if ((has_temp_peci(data, index)) || data->type == it8721 || 1194 data->type == it8720) { 1195 extra = it87_read_value(data, IT87_REG_IFSEL); 1196 if ((extra & 0x70) == 0x40) 1197 ttype = 5; 1198 } 1199 1200 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE); 1201 1202 /* Per chip special detection */ 1203 switch (data->type) { 1204 case it8622: 1205 if (!(reg & 0xc0) && index == 3) 1206 type = ttype; 1207 break; 1208 default: 1209 break; 1210 } 1211 1212 if (type || index >= 3) 1213 return type; 1214 1215 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); 1216 1217 if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) || 1218 (has_temp_old_peci(data, index) && (extra & 0x80))) 1219 type = ttype; /* Intel PECI or AMDTSI */ 1220 else if (reg & BIT(index)) 1221 type = 3; /* thermal diode */ 1222 else if (reg & BIT(index + 3)) 1223 type = 4; /* thermistor */ 1224 1225 return type; 1226 } 1227 1228 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr, 1229 char *buf) 1230 { 1231 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1232 struct it87_data *data = it87_update_device(dev); 1233 1234 if (IS_ERR(data)) 1235 return PTR_ERR(data); 1236 1237 return sprintf(buf, "%d\n", get_temp_type(data, sensor_attr->index)); 1238 } 1239 1240 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr, 1241 const char *buf, size_t count) 1242 { 1243 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1244 int nr = sensor_attr->index; 1245 1246 struct it87_data *data = dev_get_drvdata(dev); 1247 long val; 1248 u8 reg, extra; 1249 int err; 1250 1251 if (kstrtol(buf, 10, &val) < 0) 1252 return -EINVAL; 1253 1254 err = it87_lock(data); 1255 if (err) 1256 return err; 1257 1258 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE); 1259 reg &= ~(1 << nr); 1260 reg &= ~(8 << nr); 1261 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6)) 1262 reg &= 0x3f; 1263 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); 1264 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6)) 1265 extra &= 0x7f; 1266 if (val == 2) { /* backwards compatibility */ 1267 dev_warn(dev, 1268 "Sensor type 2 is deprecated, please use 4 instead\n"); 1269 val = 4; 1270 } 1271 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */ 1272 if (val == 3) 1273 reg |= 1 << nr; 1274 else if (val == 4) 1275 reg |= 8 << nr; 1276 else if (has_temp_peci(data, nr) && val == 6) 1277 reg |= (nr + 1) << 6; 1278 else if (has_temp_old_peci(data, nr) && val == 6) 1279 extra |= 0x80; 1280 else if (val != 0) { 1281 count = -EINVAL; 1282 goto unlock; 1283 } 1284 1285 data->sensor = reg; 1286 data->extra = extra; 1287 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor); 1288 if (has_temp_old_peci(data, nr)) 1289 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); 1290 data->valid = false; /* Force cache refresh */ 1291 unlock: 1292 it87_unlock(data); 1293 return count; 1294 } 1295 1296 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type, 1297 set_temp_type, 0); 1298 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type, 1299 set_temp_type, 1); 1300 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type, 1301 set_temp_type, 2); 1302 1303 /* 6 Fans */ 1304 1305 static int pwm_mode(const struct it87_data *data, int nr) 1306 { 1307 if (has_fanctl_onoff(data) && nr < 3 && 1308 !(data->fan_main_ctrl & BIT(nr))) 1309 return 0; /* Full speed */ 1310 if (data->pwm_ctrl[nr] & 0x80) 1311 return 2; /* Automatic mode */ 1312 if ((!has_fanctl_onoff(data) || nr >= 3) && 1313 data->pwm_duty[nr] == pwm_to_reg(data, 0xff)) 1314 return 0; /* Full speed */ 1315 1316 return 1; /* Manual mode */ 1317 } 1318 1319 static ssize_t show_fan(struct device *dev, struct device_attribute *attr, 1320 char *buf) 1321 { 1322 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1323 int nr = sattr->nr; 1324 int index = sattr->index; 1325 int speed; 1326 struct it87_data *data = it87_update_device(dev); 1327 1328 if (IS_ERR(data)) 1329 return PTR_ERR(data); 1330 1331 speed = has_16bit_fans(data) ? 1332 FAN16_FROM_REG(data->fan[nr][index]) : 1333 FAN_FROM_REG(data->fan[nr][index], 1334 DIV_FROM_REG(data->fan_div[nr])); 1335 return sprintf(buf, "%d\n", speed); 1336 } 1337 1338 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr, 1339 char *buf) 1340 { 1341 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1342 struct it87_data *data = it87_update_device(dev); 1343 int nr = sensor_attr->index; 1344 1345 if (IS_ERR(data)) 1346 return PTR_ERR(data); 1347 1348 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr])); 1349 } 1350 1351 static ssize_t show_pwm_enable(struct device *dev, 1352 struct device_attribute *attr, char *buf) 1353 { 1354 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1355 struct it87_data *data = it87_update_device(dev); 1356 int nr = sensor_attr->index; 1357 1358 if (IS_ERR(data)) 1359 return PTR_ERR(data); 1360 1361 return sprintf(buf, "%d\n", pwm_mode(data, nr)); 1362 } 1363 1364 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, 1365 char *buf) 1366 { 1367 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1368 struct it87_data *data = it87_update_device(dev); 1369 int nr = sensor_attr->index; 1370 1371 if (IS_ERR(data)) 1372 return PTR_ERR(data); 1373 1374 return sprintf(buf, "%d\n", 1375 pwm_from_reg(data, data->pwm_duty[nr])); 1376 } 1377 1378 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr, 1379 char *buf) 1380 { 1381 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1382 struct it87_data *data = it87_update_device(dev); 1383 int nr = sensor_attr->index; 1384 unsigned int freq; 1385 int index; 1386 1387 if (IS_ERR(data)) 1388 return PTR_ERR(data); 1389 1390 if (has_pwm_freq2(data) && nr == 1) 1391 index = (data->extra >> 4) & 0x07; 1392 else 1393 index = (data->fan_ctl >> 4) & 0x07; 1394 1395 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128); 1396 1397 return sprintf(buf, "%u\n", freq); 1398 } 1399 1400 static ssize_t set_fan(struct device *dev, struct device_attribute *attr, 1401 const char *buf, size_t count) 1402 { 1403 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1404 int nr = sattr->nr; 1405 int index = sattr->index; 1406 1407 struct it87_data *data = dev_get_drvdata(dev); 1408 long val; 1409 int err; 1410 u8 reg; 1411 1412 if (kstrtol(buf, 10, &val) < 0) 1413 return -EINVAL; 1414 1415 if (val < 0) 1416 val = 0; 1417 1418 err = it87_lock(data); 1419 if (err) 1420 return err; 1421 1422 if (has_16bit_fans(data)) { 1423 data->fan[nr][index] = FAN16_TO_REG(val); 1424 it87_write_value(data, IT87_REG_FAN_MIN[nr], 1425 data->fan[nr][index] & 0xff); 1426 it87_write_value(data, IT87_REG_FANX_MIN[nr], 1427 data->fan[nr][index] >> 8); 1428 } else { 1429 reg = it87_read_value(data, IT87_REG_FAN_DIV); 1430 switch (nr) { 1431 case 0: 1432 data->fan_div[nr] = reg & 0x07; 1433 break; 1434 case 1: 1435 data->fan_div[nr] = (reg >> 3) & 0x07; 1436 break; 1437 case 2: 1438 data->fan_div[nr] = (reg & 0x40) ? 3 : 1; 1439 break; 1440 } 1441 data->fan[nr][index] = 1442 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); 1443 it87_write_value(data, IT87_REG_FAN_MIN[nr], 1444 data->fan[nr][index]); 1445 } 1446 1447 it87_unlock(data); 1448 return count; 1449 } 1450 1451 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr, 1452 const char *buf, size_t count) 1453 { 1454 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1455 struct it87_data *data = dev_get_drvdata(dev); 1456 int nr = sensor_attr->index; 1457 unsigned long val; 1458 int min, err; 1459 u8 old; 1460 1461 if (kstrtoul(buf, 10, &val) < 0) 1462 return -EINVAL; 1463 1464 err = it87_lock(data); 1465 if (err) 1466 return err; 1467 1468 old = it87_read_value(data, IT87_REG_FAN_DIV); 1469 1470 /* Save fan min limit */ 1471 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr])); 1472 1473 switch (nr) { 1474 case 0: 1475 case 1: 1476 data->fan_div[nr] = DIV_TO_REG(val); 1477 break; 1478 case 2: 1479 if (val < 8) 1480 data->fan_div[nr] = 1; 1481 else 1482 data->fan_div[nr] = 3; 1483 } 1484 val = old & 0x80; 1485 val |= (data->fan_div[0] & 0x07); 1486 val |= (data->fan_div[1] & 0x07) << 3; 1487 if (data->fan_div[2] == 3) 1488 val |= 0x1 << 6; 1489 it87_write_value(data, IT87_REG_FAN_DIV, val); 1490 1491 /* Restore fan min limit */ 1492 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr])); 1493 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]); 1494 1495 it87_unlock(data); 1496 return count; 1497 } 1498 1499 /* Returns 0 if OK, -EINVAL otherwise */ 1500 static int check_trip_points(struct device *dev, int nr) 1501 { 1502 const struct it87_data *data = dev_get_drvdata(dev); 1503 int i, err = 0; 1504 1505 if (has_old_autopwm(data)) { 1506 for (i = 0; i < 3; i++) { 1507 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) 1508 err = -EINVAL; 1509 } 1510 for (i = 0; i < 2; i++) { 1511 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1]) 1512 err = -EINVAL; 1513 } 1514 } else if (has_newer_autopwm(data)) { 1515 for (i = 1; i < 3; i++) { 1516 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) 1517 err = -EINVAL; 1518 } 1519 } 1520 1521 if (err) { 1522 dev_err(dev, 1523 "Inconsistent trip points, not switching to automatic mode\n"); 1524 dev_err(dev, "Adjust the trip points and try again\n"); 1525 } 1526 return err; 1527 } 1528 1529 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr, 1530 const char *buf, size_t count) 1531 { 1532 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1533 struct it87_data *data = dev_get_drvdata(dev); 1534 int nr = sensor_attr->index; 1535 long val; 1536 int err; 1537 1538 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2) 1539 return -EINVAL; 1540 1541 /* Check trip points before switching to automatic mode */ 1542 if (val == 2) { 1543 if (check_trip_points(dev, nr) < 0) 1544 return -EINVAL; 1545 } 1546 1547 err = it87_lock(data); 1548 if (err) 1549 return err; 1550 1551 if (val == 0) { 1552 if (nr < 3 && has_fanctl_onoff(data)) { 1553 int tmp; 1554 /* make sure the fan is on when in on/off mode */ 1555 tmp = it87_read_value(data, IT87_REG_FAN_CTL); 1556 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr)); 1557 /* set on/off mode */ 1558 data->fan_main_ctrl &= ~BIT(nr); 1559 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 1560 data->fan_main_ctrl); 1561 } else { 1562 u8 ctrl; 1563 1564 /* No on/off mode, set maximum pwm value */ 1565 data->pwm_duty[nr] = pwm_to_reg(data, 0xff); 1566 it87_write_value(data, IT87_REG_PWM_DUTY[nr], 1567 data->pwm_duty[nr]); 1568 /* and set manual mode */ 1569 if (has_newer_autopwm(data)) { 1570 ctrl = (data->pwm_ctrl[nr] & 0x7c) | 1571 data->pwm_temp_map[nr]; 1572 } else { 1573 ctrl = data->pwm_duty[nr]; 1574 } 1575 data->pwm_ctrl[nr] = ctrl; 1576 it87_write_value(data, IT87_REG_PWM[nr], ctrl); 1577 } 1578 } else { 1579 u8 ctrl; 1580 1581 if (has_newer_autopwm(data)) { 1582 ctrl = (data->pwm_ctrl[nr] & 0x7c) | 1583 data->pwm_temp_map[nr]; 1584 if (val != 1) 1585 ctrl |= 0x80; 1586 } else { 1587 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80); 1588 } 1589 data->pwm_ctrl[nr] = ctrl; 1590 it87_write_value(data, IT87_REG_PWM[nr], ctrl); 1591 1592 if (has_fanctl_onoff(data) && nr < 3) { 1593 /* set SmartGuardian mode */ 1594 data->fan_main_ctrl |= BIT(nr); 1595 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 1596 data->fan_main_ctrl); 1597 } 1598 } 1599 1600 it87_unlock(data); 1601 return count; 1602 } 1603 1604 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, 1605 const char *buf, size_t count) 1606 { 1607 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1608 struct it87_data *data = dev_get_drvdata(dev); 1609 int nr = sensor_attr->index; 1610 long val; 1611 int err; 1612 1613 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) 1614 return -EINVAL; 1615 1616 err = it87_lock(data); 1617 if (err) 1618 return err; 1619 1620 it87_update_pwm_ctrl(data, nr); 1621 if (has_newer_autopwm(data)) { 1622 /* 1623 * If we are in automatic mode, the PWM duty cycle register 1624 * is read-only so we can't write the value. 1625 */ 1626 if (data->pwm_ctrl[nr] & 0x80) { 1627 count = -EBUSY; 1628 goto unlock; 1629 } 1630 data->pwm_duty[nr] = pwm_to_reg(data, val); 1631 it87_write_value(data, IT87_REG_PWM_DUTY[nr], 1632 data->pwm_duty[nr]); 1633 } else { 1634 data->pwm_duty[nr] = pwm_to_reg(data, val); 1635 /* 1636 * If we are in manual mode, write the duty cycle immediately; 1637 * otherwise, just store it for later use. 1638 */ 1639 if (!(data->pwm_ctrl[nr] & 0x80)) { 1640 data->pwm_ctrl[nr] = data->pwm_duty[nr]; 1641 it87_write_value(data, IT87_REG_PWM[nr], 1642 data->pwm_ctrl[nr]); 1643 } 1644 } 1645 unlock: 1646 it87_unlock(data); 1647 return count; 1648 } 1649 1650 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr, 1651 const char *buf, size_t count) 1652 { 1653 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1654 struct it87_data *data = dev_get_drvdata(dev); 1655 int nr = sensor_attr->index; 1656 unsigned long val; 1657 int err; 1658 int i; 1659 1660 if (kstrtoul(buf, 10, &val) < 0) 1661 return -EINVAL; 1662 1663 val = clamp_val(val, 0, 1000000); 1664 val *= has_newer_autopwm(data) ? 256 : 128; 1665 1666 /* Search for the nearest available frequency */ 1667 for (i = 0; i < 7; i++) { 1668 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2) 1669 break; 1670 } 1671 1672 err = it87_lock(data); 1673 if (err) 1674 return err; 1675 1676 if (nr == 0) { 1677 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f; 1678 data->fan_ctl |= i << 4; 1679 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl); 1680 } else { 1681 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f; 1682 data->extra |= i << 4; 1683 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); 1684 } 1685 it87_unlock(data); 1686 1687 return count; 1688 } 1689 1690 static ssize_t show_pwm_temp_map(struct device *dev, 1691 struct device_attribute *attr, char *buf) 1692 { 1693 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1694 struct it87_data *data = it87_update_device(dev); 1695 int nr = sensor_attr->index; 1696 int map; 1697 1698 if (IS_ERR(data)) 1699 return PTR_ERR(data); 1700 1701 map = data->pwm_temp_map[nr]; 1702 if (map >= 3) 1703 map = 0; /* Should never happen */ 1704 if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */ 1705 map += 3; 1706 1707 return sprintf(buf, "%d\n", (int)BIT(map)); 1708 } 1709 1710 static ssize_t set_pwm_temp_map(struct device *dev, 1711 struct device_attribute *attr, const char *buf, 1712 size_t count) 1713 { 1714 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1715 struct it87_data *data = dev_get_drvdata(dev); 1716 int nr = sensor_attr->index; 1717 long val; 1718 int err; 1719 u8 reg; 1720 1721 if (kstrtol(buf, 10, &val) < 0) 1722 return -EINVAL; 1723 1724 if (nr >= 3) 1725 val -= 3; 1726 1727 switch (val) { 1728 case BIT(0): 1729 reg = 0x00; 1730 break; 1731 case BIT(1): 1732 reg = 0x01; 1733 break; 1734 case BIT(2): 1735 reg = 0x02; 1736 break; 1737 default: 1738 return -EINVAL; 1739 } 1740 1741 err = it87_lock(data); 1742 if (err) 1743 return err; 1744 1745 it87_update_pwm_ctrl(data, nr); 1746 data->pwm_temp_map[nr] = reg; 1747 /* 1748 * If we are in automatic mode, write the temp mapping immediately; 1749 * otherwise, just store it for later use. 1750 */ 1751 if (data->pwm_ctrl[nr] & 0x80) { 1752 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) | 1753 data->pwm_temp_map[nr]; 1754 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]); 1755 } 1756 it87_unlock(data); 1757 return count; 1758 } 1759 1760 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr, 1761 char *buf) 1762 { 1763 struct it87_data *data = it87_update_device(dev); 1764 struct sensor_device_attribute_2 *sensor_attr = 1765 to_sensor_dev_attr_2(attr); 1766 int nr = sensor_attr->nr; 1767 int point = sensor_attr->index; 1768 1769 if (IS_ERR(data)) 1770 return PTR_ERR(data); 1771 1772 return sprintf(buf, "%d\n", 1773 pwm_from_reg(data, data->auto_pwm[nr][point])); 1774 } 1775 1776 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr, 1777 const char *buf, size_t count) 1778 { 1779 struct it87_data *data = dev_get_drvdata(dev); 1780 struct sensor_device_attribute_2 *sensor_attr = 1781 to_sensor_dev_attr_2(attr); 1782 int nr = sensor_attr->nr; 1783 int point = sensor_attr->index; 1784 int regaddr; 1785 long val; 1786 int err; 1787 1788 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) 1789 return -EINVAL; 1790 1791 err = it87_lock(data); 1792 if (err) 1793 return err; 1794 1795 data->auto_pwm[nr][point] = pwm_to_reg(data, val); 1796 if (has_newer_autopwm(data)) 1797 regaddr = IT87_REG_AUTO_TEMP(nr, 3); 1798 else 1799 regaddr = IT87_REG_AUTO_PWM(nr, point); 1800 it87_write_value(data, regaddr, data->auto_pwm[nr][point]); 1801 it87_unlock(data); 1802 return count; 1803 } 1804 1805 static ssize_t show_auto_pwm_slope(struct device *dev, 1806 struct device_attribute *attr, char *buf) 1807 { 1808 struct it87_data *data = it87_update_device(dev); 1809 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1810 int nr = sensor_attr->index; 1811 1812 if (IS_ERR(data)) 1813 return PTR_ERR(data); 1814 1815 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f); 1816 } 1817 1818 static ssize_t set_auto_pwm_slope(struct device *dev, 1819 struct device_attribute *attr, 1820 const char *buf, size_t count) 1821 { 1822 struct it87_data *data = dev_get_drvdata(dev); 1823 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1824 int nr = sensor_attr->index; 1825 unsigned long val; 1826 int err; 1827 1828 if (kstrtoul(buf, 10, &val) < 0 || val > 127) 1829 return -EINVAL; 1830 1831 err = it87_lock(data); 1832 if (err) 1833 return err; 1834 1835 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val; 1836 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4), 1837 data->auto_pwm[nr][1]); 1838 it87_unlock(data); 1839 return count; 1840 } 1841 1842 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr, 1843 char *buf) 1844 { 1845 struct it87_data *data = it87_update_device(dev); 1846 struct sensor_device_attribute_2 *sensor_attr = 1847 to_sensor_dev_attr_2(attr); 1848 int nr = sensor_attr->nr; 1849 int point = sensor_attr->index; 1850 int reg; 1851 1852 if (IS_ERR(data)) 1853 return PTR_ERR(data); 1854 1855 if (has_old_autopwm(data) || point) 1856 reg = data->auto_temp[nr][point]; 1857 else 1858 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f); 1859 1860 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg)); 1861 } 1862 1863 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr, 1864 const char *buf, size_t count) 1865 { 1866 struct it87_data *data = dev_get_drvdata(dev); 1867 struct sensor_device_attribute_2 *sensor_attr = 1868 to_sensor_dev_attr_2(attr); 1869 int nr = sensor_attr->nr; 1870 int point = sensor_attr->index; 1871 long val; 1872 int reg; 1873 int err; 1874 1875 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000) 1876 return -EINVAL; 1877 1878 err = it87_lock(data); 1879 if (err) 1880 return err; 1881 1882 if (has_newer_autopwm(data) && !point) { 1883 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val); 1884 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0); 1885 data->auto_temp[nr][0] = reg; 1886 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg); 1887 } else { 1888 reg = TEMP_TO_REG(val); 1889 data->auto_temp[nr][point] = reg; 1890 if (has_newer_autopwm(data)) 1891 point--; 1892 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg); 1893 } 1894 it87_unlock(data); 1895 return count; 1896 } 1897 1898 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0); 1899 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1900 0, 1); 1901 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div, 1902 set_fan_div, 0); 1903 1904 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0); 1905 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1906 1, 1); 1907 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div, 1908 set_fan_div, 1); 1909 1910 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0); 1911 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1912 2, 1); 1913 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div, 1914 set_fan_div, 2); 1915 1916 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0); 1917 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1918 3, 1); 1919 1920 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0); 1921 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1922 4, 1); 1923 1924 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0); 1925 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1926 5, 1); 1927 1928 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, 1929 show_pwm_enable, set_pwm_enable, 0); 1930 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0); 1931 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, 1932 set_pwm_freq, 0); 1933 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO, 1934 show_pwm_temp_map, set_pwm_temp_map, 0); 1935 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR, 1936 show_auto_pwm, set_auto_pwm, 0, 0); 1937 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR, 1938 show_auto_pwm, set_auto_pwm, 0, 1); 1939 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR, 1940 show_auto_pwm, set_auto_pwm, 0, 2); 1941 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO, 1942 show_auto_pwm, NULL, 0, 3); 1943 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR, 1944 show_auto_temp, set_auto_temp, 0, 1); 1945 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1946 show_auto_temp, set_auto_temp, 0, 0); 1947 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR, 1948 show_auto_temp, set_auto_temp, 0, 2); 1949 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR, 1950 show_auto_temp, set_auto_temp, 0, 3); 1951 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR, 1952 show_auto_temp, set_auto_temp, 0, 4); 1953 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR, 1954 show_auto_pwm, set_auto_pwm, 0, 0); 1955 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR, 1956 show_auto_pwm_slope, set_auto_pwm_slope, 0); 1957 1958 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR, 1959 show_pwm_enable, set_pwm_enable, 1); 1960 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1); 1961 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1); 1962 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO, 1963 show_pwm_temp_map, set_pwm_temp_map, 1); 1964 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR, 1965 show_auto_pwm, set_auto_pwm, 1, 0); 1966 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR, 1967 show_auto_pwm, set_auto_pwm, 1, 1); 1968 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR, 1969 show_auto_pwm, set_auto_pwm, 1, 2); 1970 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO, 1971 show_auto_pwm, NULL, 1, 3); 1972 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR, 1973 show_auto_temp, set_auto_temp, 1, 1); 1974 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1975 show_auto_temp, set_auto_temp, 1, 0); 1976 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR, 1977 show_auto_temp, set_auto_temp, 1, 2); 1978 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR, 1979 show_auto_temp, set_auto_temp, 1, 3); 1980 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR, 1981 show_auto_temp, set_auto_temp, 1, 4); 1982 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR, 1983 show_auto_pwm, set_auto_pwm, 1, 0); 1984 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR, 1985 show_auto_pwm_slope, set_auto_pwm_slope, 1); 1986 1987 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR, 1988 show_pwm_enable, set_pwm_enable, 2); 1989 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2); 1990 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2); 1991 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO, 1992 show_pwm_temp_map, set_pwm_temp_map, 2); 1993 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR, 1994 show_auto_pwm, set_auto_pwm, 2, 0); 1995 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR, 1996 show_auto_pwm, set_auto_pwm, 2, 1); 1997 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR, 1998 show_auto_pwm, set_auto_pwm, 2, 2); 1999 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO, 2000 show_auto_pwm, NULL, 2, 3); 2001 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR, 2002 show_auto_temp, set_auto_temp, 2, 1); 2003 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 2004 show_auto_temp, set_auto_temp, 2, 0); 2005 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR, 2006 show_auto_temp, set_auto_temp, 2, 2); 2007 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR, 2008 show_auto_temp, set_auto_temp, 2, 3); 2009 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR, 2010 show_auto_temp, set_auto_temp, 2, 4); 2011 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR, 2012 show_auto_pwm, set_auto_pwm, 2, 0); 2013 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR, 2014 show_auto_pwm_slope, set_auto_pwm_slope, 2); 2015 2016 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR, 2017 show_pwm_enable, set_pwm_enable, 3); 2018 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3); 2019 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3); 2020 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO, 2021 show_pwm_temp_map, set_pwm_temp_map, 3); 2022 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR, 2023 show_auto_temp, set_auto_temp, 2, 1); 2024 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 2025 show_auto_temp, set_auto_temp, 2, 0); 2026 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR, 2027 show_auto_temp, set_auto_temp, 2, 2); 2028 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR, 2029 show_auto_temp, set_auto_temp, 2, 3); 2030 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR, 2031 show_auto_pwm, set_auto_pwm, 3, 0); 2032 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR, 2033 show_auto_pwm_slope, set_auto_pwm_slope, 3); 2034 2035 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR, 2036 show_pwm_enable, set_pwm_enable, 4); 2037 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4); 2038 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4); 2039 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO, 2040 show_pwm_temp_map, set_pwm_temp_map, 4); 2041 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR, 2042 show_auto_temp, set_auto_temp, 2, 1); 2043 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 2044 show_auto_temp, set_auto_temp, 2, 0); 2045 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR, 2046 show_auto_temp, set_auto_temp, 2, 2); 2047 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR, 2048 show_auto_temp, set_auto_temp, 2, 3); 2049 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR, 2050 show_auto_pwm, set_auto_pwm, 4, 0); 2051 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR, 2052 show_auto_pwm_slope, set_auto_pwm_slope, 4); 2053 2054 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR, 2055 show_pwm_enable, set_pwm_enable, 5); 2056 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5); 2057 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5); 2058 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO, 2059 show_pwm_temp_map, set_pwm_temp_map, 5); 2060 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR, 2061 show_auto_temp, set_auto_temp, 2, 1); 2062 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 2063 show_auto_temp, set_auto_temp, 2, 0); 2064 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR, 2065 show_auto_temp, set_auto_temp, 2, 2); 2066 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR, 2067 show_auto_temp, set_auto_temp, 2, 3); 2068 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR, 2069 show_auto_pwm, set_auto_pwm, 5, 0); 2070 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR, 2071 show_auto_pwm_slope, set_auto_pwm_slope, 5); 2072 2073 /* Alarms */ 2074 static ssize_t alarms_show(struct device *dev, struct device_attribute *attr, 2075 char *buf) 2076 { 2077 struct it87_data *data = it87_update_device(dev); 2078 2079 if (IS_ERR(data)) 2080 return PTR_ERR(data); 2081 2082 return sprintf(buf, "%u\n", data->alarms); 2083 } 2084 static DEVICE_ATTR_RO(alarms); 2085 2086 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, 2087 char *buf) 2088 { 2089 struct it87_data *data = it87_update_device(dev); 2090 int bitnr = to_sensor_dev_attr(attr)->index; 2091 2092 if (IS_ERR(data)) 2093 return PTR_ERR(data); 2094 2095 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1); 2096 } 2097 2098 static ssize_t clear_intrusion(struct device *dev, 2099 struct device_attribute *attr, const char *buf, 2100 size_t count) 2101 { 2102 struct it87_data *data = dev_get_drvdata(dev); 2103 int err, config; 2104 long val; 2105 2106 if (kstrtol(buf, 10, &val) < 0 || val != 0) 2107 return -EINVAL; 2108 2109 err = it87_lock(data); 2110 if (err) 2111 return err; 2112 2113 config = it87_read_value(data, IT87_REG_CONFIG); 2114 if (config < 0) { 2115 count = config; 2116 } else { 2117 config |= BIT(5); 2118 it87_write_value(data, IT87_REG_CONFIG, config); 2119 /* Invalidate cache to force re-read */ 2120 data->valid = false; 2121 } 2122 it87_unlock(data); 2123 return count; 2124 } 2125 2126 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8); 2127 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9); 2128 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10); 2129 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11); 2130 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12); 2131 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13); 2132 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14); 2133 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15); 2134 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0); 2135 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1); 2136 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2); 2137 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3); 2138 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6); 2139 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7); 2140 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16); 2141 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17); 2142 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18); 2143 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR, 2144 show_alarm, clear_intrusion, 4); 2145 2146 static ssize_t show_beep(struct device *dev, struct device_attribute *attr, 2147 char *buf) 2148 { 2149 struct it87_data *data = it87_update_device(dev); 2150 int bitnr = to_sensor_dev_attr(attr)->index; 2151 2152 if (IS_ERR(data)) 2153 return PTR_ERR(data); 2154 2155 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1); 2156 } 2157 2158 static ssize_t set_beep(struct device *dev, struct device_attribute *attr, 2159 const char *buf, size_t count) 2160 { 2161 int bitnr = to_sensor_dev_attr(attr)->index; 2162 struct it87_data *data = dev_get_drvdata(dev); 2163 long val; 2164 int err; 2165 2166 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1)) 2167 return -EINVAL; 2168 2169 err = it87_lock(data); 2170 if (err) 2171 return err; 2172 2173 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); 2174 if (val) 2175 data->beeps |= BIT(bitnr); 2176 else 2177 data->beeps &= ~BIT(bitnr); 2178 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps); 2179 it87_unlock(data); 2180 return count; 2181 } 2182 2183 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR, 2184 show_beep, set_beep, 1); 2185 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1); 2186 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1); 2187 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1); 2188 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1); 2189 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1); 2190 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1); 2191 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1); 2192 /* fanX_beep writability is set later */ 2193 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0); 2194 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0); 2195 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0); 2196 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0); 2197 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0); 2198 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0); 2199 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR, 2200 show_beep, set_beep, 2); 2201 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2); 2202 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2); 2203 2204 static ssize_t vrm_show(struct device *dev, struct device_attribute *attr, 2205 char *buf) 2206 { 2207 struct it87_data *data = dev_get_drvdata(dev); 2208 2209 return sprintf(buf, "%u\n", data->vrm); 2210 } 2211 2212 static ssize_t vrm_store(struct device *dev, struct device_attribute *attr, 2213 const char *buf, size_t count) 2214 { 2215 struct it87_data *data = dev_get_drvdata(dev); 2216 unsigned long val; 2217 2218 if (kstrtoul(buf, 10, &val) < 0) 2219 return -EINVAL; 2220 2221 data->vrm = val; 2222 2223 return count; 2224 } 2225 static DEVICE_ATTR_RW(vrm); 2226 2227 static ssize_t cpu0_vid_show(struct device *dev, 2228 struct device_attribute *attr, char *buf) 2229 { 2230 struct it87_data *data = it87_update_device(dev); 2231 2232 if (IS_ERR(data)) 2233 return PTR_ERR(data); 2234 2235 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm)); 2236 } 2237 static DEVICE_ATTR_RO(cpu0_vid); 2238 2239 static ssize_t show_label(struct device *dev, struct device_attribute *attr, 2240 char *buf) 2241 { 2242 static const char * const labels[] = { 2243 "+5V", 2244 "5VSB", 2245 "Vbat", 2246 "AVCC", 2247 }; 2248 static const char * const labels_it8721[] = { 2249 "+3.3V", 2250 "3VSB", 2251 "Vbat", 2252 "+3.3V", 2253 }; 2254 struct it87_data *data = dev_get_drvdata(dev); 2255 int nr = to_sensor_dev_attr(attr)->index; 2256 const char *label; 2257 2258 if (has_vin3_5v(data) && nr == 0) 2259 label = labels[0]; 2260 else if (has_scaling(data)) 2261 label = labels_it8721[nr]; 2262 else 2263 label = labels[nr]; 2264 2265 return sprintf(buf, "%s\n", label); 2266 } 2267 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0); 2268 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1); 2269 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2); 2270 /* AVCC3 */ 2271 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3); 2272 2273 static umode_t it87_in_is_visible(struct kobject *kobj, 2274 struct attribute *attr, int index) 2275 { 2276 struct device *dev = kobj_to_dev(kobj); 2277 struct it87_data *data = dev_get_drvdata(dev); 2278 int i = index / 5; /* voltage index */ 2279 int a = index % 5; /* attribute index */ 2280 2281 if (index >= 40) { /* in8 and higher only have input attributes */ 2282 i = index - 40 + 8; 2283 a = 0; 2284 } 2285 2286 if (!(data->has_in & BIT(i))) 2287 return 0; 2288 2289 if (a == 4 && !data->has_beep) 2290 return 0; 2291 2292 return attr->mode; 2293 } 2294 2295 static struct attribute *it87_attributes_in[] = { 2296 &sensor_dev_attr_in0_input.dev_attr.attr, 2297 &sensor_dev_attr_in0_min.dev_attr.attr, 2298 &sensor_dev_attr_in0_max.dev_attr.attr, 2299 &sensor_dev_attr_in0_alarm.dev_attr.attr, 2300 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */ 2301 2302 &sensor_dev_attr_in1_input.dev_attr.attr, 2303 &sensor_dev_attr_in1_min.dev_attr.attr, 2304 &sensor_dev_attr_in1_max.dev_attr.attr, 2305 &sensor_dev_attr_in1_alarm.dev_attr.attr, 2306 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */ 2307 2308 &sensor_dev_attr_in2_input.dev_attr.attr, 2309 &sensor_dev_attr_in2_min.dev_attr.attr, 2310 &sensor_dev_attr_in2_max.dev_attr.attr, 2311 &sensor_dev_attr_in2_alarm.dev_attr.attr, 2312 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */ 2313 2314 &sensor_dev_attr_in3_input.dev_attr.attr, 2315 &sensor_dev_attr_in3_min.dev_attr.attr, 2316 &sensor_dev_attr_in3_max.dev_attr.attr, 2317 &sensor_dev_attr_in3_alarm.dev_attr.attr, 2318 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */ 2319 2320 &sensor_dev_attr_in4_input.dev_attr.attr, 2321 &sensor_dev_attr_in4_min.dev_attr.attr, 2322 &sensor_dev_attr_in4_max.dev_attr.attr, 2323 &sensor_dev_attr_in4_alarm.dev_attr.attr, 2324 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */ 2325 2326 &sensor_dev_attr_in5_input.dev_attr.attr, 2327 &sensor_dev_attr_in5_min.dev_attr.attr, 2328 &sensor_dev_attr_in5_max.dev_attr.attr, 2329 &sensor_dev_attr_in5_alarm.dev_attr.attr, 2330 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */ 2331 2332 &sensor_dev_attr_in6_input.dev_attr.attr, 2333 &sensor_dev_attr_in6_min.dev_attr.attr, 2334 &sensor_dev_attr_in6_max.dev_attr.attr, 2335 &sensor_dev_attr_in6_alarm.dev_attr.attr, 2336 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */ 2337 2338 &sensor_dev_attr_in7_input.dev_attr.attr, 2339 &sensor_dev_attr_in7_min.dev_attr.attr, 2340 &sensor_dev_attr_in7_max.dev_attr.attr, 2341 &sensor_dev_attr_in7_alarm.dev_attr.attr, 2342 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */ 2343 2344 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */ 2345 &sensor_dev_attr_in9_input.dev_attr.attr, 2346 &sensor_dev_attr_in10_input.dev_attr.attr, 2347 &sensor_dev_attr_in11_input.dev_attr.attr, 2348 &sensor_dev_attr_in12_input.dev_attr.attr, 2349 NULL 2350 }; 2351 2352 static const struct attribute_group it87_group_in = { 2353 .attrs = it87_attributes_in, 2354 .is_visible = it87_in_is_visible, 2355 }; 2356 2357 static umode_t it87_temp_is_visible(struct kobject *kobj, 2358 struct attribute *attr, int index) 2359 { 2360 struct device *dev = kobj_to_dev(kobj); 2361 struct it87_data *data = dev_get_drvdata(dev); 2362 int i = index / 7; /* temperature index */ 2363 int a = index % 7; /* attribute index */ 2364 2365 if (index >= 21) { 2366 i = index - 21 + 3; 2367 a = 0; 2368 } 2369 2370 if (!(data->has_temp & BIT(i))) 2371 return 0; 2372 2373 if (a == 3) { 2374 if (get_temp_type(data, i) == 0) 2375 return 0; 2376 return attr->mode; 2377 } 2378 2379 if (a == 5 && !has_temp_offset(data)) 2380 return 0; 2381 2382 if (a == 6 && !data->has_beep) 2383 return 0; 2384 2385 return attr->mode; 2386 } 2387 2388 static struct attribute *it87_attributes_temp[] = { 2389 &sensor_dev_attr_temp1_input.dev_attr.attr, 2390 &sensor_dev_attr_temp1_max.dev_attr.attr, 2391 &sensor_dev_attr_temp1_min.dev_attr.attr, 2392 &sensor_dev_attr_temp1_type.dev_attr.attr, 2393 &sensor_dev_attr_temp1_alarm.dev_attr.attr, 2394 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */ 2395 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */ 2396 2397 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */ 2398 &sensor_dev_attr_temp2_max.dev_attr.attr, 2399 &sensor_dev_attr_temp2_min.dev_attr.attr, 2400 &sensor_dev_attr_temp2_type.dev_attr.attr, 2401 &sensor_dev_attr_temp2_alarm.dev_attr.attr, 2402 &sensor_dev_attr_temp2_offset.dev_attr.attr, 2403 &sensor_dev_attr_temp2_beep.dev_attr.attr, 2404 2405 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */ 2406 &sensor_dev_attr_temp3_max.dev_attr.attr, 2407 &sensor_dev_attr_temp3_min.dev_attr.attr, 2408 &sensor_dev_attr_temp3_type.dev_attr.attr, 2409 &sensor_dev_attr_temp3_alarm.dev_attr.attr, 2410 &sensor_dev_attr_temp3_offset.dev_attr.attr, 2411 &sensor_dev_attr_temp3_beep.dev_attr.attr, 2412 2413 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */ 2414 &sensor_dev_attr_temp5_input.dev_attr.attr, 2415 &sensor_dev_attr_temp6_input.dev_attr.attr, 2416 NULL 2417 }; 2418 2419 static const struct attribute_group it87_group_temp = { 2420 .attrs = it87_attributes_temp, 2421 .is_visible = it87_temp_is_visible, 2422 }; 2423 2424 static umode_t it87_is_visible(struct kobject *kobj, 2425 struct attribute *attr, int index) 2426 { 2427 struct device *dev = kobj_to_dev(kobj); 2428 struct it87_data *data = dev_get_drvdata(dev); 2429 2430 if ((index == 2 || index == 3) && !data->has_vid) 2431 return 0; 2432 2433 if (index > 3 && !(data->in_internal & BIT(index - 4))) 2434 return 0; 2435 2436 return attr->mode; 2437 } 2438 2439 static struct attribute *it87_attributes[] = { 2440 &dev_attr_alarms.attr, 2441 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, 2442 &dev_attr_vrm.attr, /* 2 */ 2443 &dev_attr_cpu0_vid.attr, /* 3 */ 2444 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */ 2445 &sensor_dev_attr_in7_label.dev_attr.attr, 2446 &sensor_dev_attr_in8_label.dev_attr.attr, 2447 &sensor_dev_attr_in9_label.dev_attr.attr, 2448 NULL 2449 }; 2450 2451 static const struct attribute_group it87_group = { 2452 .attrs = it87_attributes, 2453 .is_visible = it87_is_visible, 2454 }; 2455 2456 static umode_t it87_fan_is_visible(struct kobject *kobj, 2457 struct attribute *attr, int index) 2458 { 2459 struct device *dev = kobj_to_dev(kobj); 2460 struct it87_data *data = dev_get_drvdata(dev); 2461 int i = index / 5; /* fan index */ 2462 int a = index % 5; /* attribute index */ 2463 2464 if (index >= 15) { /* fan 4..6 don't have divisor attributes */ 2465 i = (index - 15) / 4 + 3; 2466 a = (index - 15) % 4; 2467 } 2468 2469 if (!(data->has_fan & BIT(i))) 2470 return 0; 2471 2472 if (a == 3) { /* beep */ 2473 if (!data->has_beep) 2474 return 0; 2475 /* first fan beep attribute is writable */ 2476 if (i == __ffs(data->has_fan)) 2477 return attr->mode | S_IWUSR; 2478 } 2479 2480 if (a == 4 && has_16bit_fans(data)) /* divisor */ 2481 return 0; 2482 2483 return attr->mode; 2484 } 2485 2486 static struct attribute *it87_attributes_fan[] = { 2487 &sensor_dev_attr_fan1_input.dev_attr.attr, 2488 &sensor_dev_attr_fan1_min.dev_attr.attr, 2489 &sensor_dev_attr_fan1_alarm.dev_attr.attr, 2490 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */ 2491 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */ 2492 2493 &sensor_dev_attr_fan2_input.dev_attr.attr, 2494 &sensor_dev_attr_fan2_min.dev_attr.attr, 2495 &sensor_dev_attr_fan2_alarm.dev_attr.attr, 2496 &sensor_dev_attr_fan2_beep.dev_attr.attr, 2497 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */ 2498 2499 &sensor_dev_attr_fan3_input.dev_attr.attr, 2500 &sensor_dev_attr_fan3_min.dev_attr.attr, 2501 &sensor_dev_attr_fan3_alarm.dev_attr.attr, 2502 &sensor_dev_attr_fan3_beep.dev_attr.attr, 2503 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */ 2504 2505 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */ 2506 &sensor_dev_attr_fan4_min.dev_attr.attr, 2507 &sensor_dev_attr_fan4_alarm.dev_attr.attr, 2508 &sensor_dev_attr_fan4_beep.dev_attr.attr, 2509 2510 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */ 2511 &sensor_dev_attr_fan5_min.dev_attr.attr, 2512 &sensor_dev_attr_fan5_alarm.dev_attr.attr, 2513 &sensor_dev_attr_fan5_beep.dev_attr.attr, 2514 2515 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */ 2516 &sensor_dev_attr_fan6_min.dev_attr.attr, 2517 &sensor_dev_attr_fan6_alarm.dev_attr.attr, 2518 &sensor_dev_attr_fan6_beep.dev_attr.attr, 2519 NULL 2520 }; 2521 2522 static const struct attribute_group it87_group_fan = { 2523 .attrs = it87_attributes_fan, 2524 .is_visible = it87_fan_is_visible, 2525 }; 2526 2527 static umode_t it87_pwm_is_visible(struct kobject *kobj, 2528 struct attribute *attr, int index) 2529 { 2530 struct device *dev = kobj_to_dev(kobj); 2531 struct it87_data *data = dev_get_drvdata(dev); 2532 int i = index / 4; /* pwm index */ 2533 int a = index % 4; /* attribute index */ 2534 2535 if (!(data->has_pwm & BIT(i))) 2536 return 0; 2537 2538 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */ 2539 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data))) 2540 return attr->mode | S_IWUSR; 2541 2542 /* pwm2_freq is writable if there are two pwm frequency selects */ 2543 if (has_pwm_freq2(data) && i == 1 && a == 2) 2544 return attr->mode | S_IWUSR; 2545 2546 return attr->mode; 2547 } 2548 2549 static struct attribute *it87_attributes_pwm[] = { 2550 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 2551 &sensor_dev_attr_pwm1.dev_attr.attr, 2552 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 2553 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr, 2554 2555 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 2556 &sensor_dev_attr_pwm2.dev_attr.attr, 2557 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 2558 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr, 2559 2560 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 2561 &sensor_dev_attr_pwm3.dev_attr.attr, 2562 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 2563 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr, 2564 2565 &sensor_dev_attr_pwm4_enable.dev_attr.attr, 2566 &sensor_dev_attr_pwm4.dev_attr.attr, 2567 &sensor_dev_attr_pwm4_freq.dev_attr.attr, 2568 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr, 2569 2570 &sensor_dev_attr_pwm5_enable.dev_attr.attr, 2571 &sensor_dev_attr_pwm5.dev_attr.attr, 2572 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 2573 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr, 2574 2575 &sensor_dev_attr_pwm6_enable.dev_attr.attr, 2576 &sensor_dev_attr_pwm6.dev_attr.attr, 2577 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 2578 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr, 2579 2580 NULL 2581 }; 2582 2583 static const struct attribute_group it87_group_pwm = { 2584 .attrs = it87_attributes_pwm, 2585 .is_visible = it87_pwm_is_visible, 2586 }; 2587 2588 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj, 2589 struct attribute *attr, int index) 2590 { 2591 struct device *dev = kobj_to_dev(kobj); 2592 struct it87_data *data = dev_get_drvdata(dev); 2593 int i = index / 11; /* pwm index */ 2594 int a = index % 11; /* attribute index */ 2595 2596 if (index >= 33) { /* pwm 4..6 */ 2597 i = (index - 33) / 6 + 3; 2598 a = (index - 33) % 6 + 4; 2599 } 2600 2601 if (!(data->has_pwm & BIT(i))) 2602 return 0; 2603 2604 if (has_newer_autopwm(data)) { 2605 if (a < 4) /* no auto point pwm */ 2606 return 0; 2607 if (a == 8) /* no auto_point4 */ 2608 return 0; 2609 } 2610 if (has_old_autopwm(data)) { 2611 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */ 2612 return 0; 2613 } 2614 2615 return attr->mode; 2616 } 2617 2618 static struct attribute *it87_attributes_auto_pwm[] = { 2619 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 2620 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, 2621 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr, 2622 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr, 2623 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr, 2624 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr, 2625 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr, 2626 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr, 2627 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr, 2628 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr, 2629 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr, 2630 2631 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */ 2632 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, 2633 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr, 2634 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr, 2635 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr, 2636 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr, 2637 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr, 2638 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr, 2639 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr, 2640 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr, 2641 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr, 2642 2643 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */ 2644 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, 2645 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr, 2646 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr, 2647 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr, 2648 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr, 2649 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr, 2650 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr, 2651 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr, 2652 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr, 2653 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr, 2654 2655 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */ 2656 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr, 2657 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr, 2658 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr, 2659 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr, 2660 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr, 2661 2662 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr, 2663 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr, 2664 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr, 2665 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr, 2666 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr, 2667 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr, 2668 2669 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr, 2670 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr, 2671 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr, 2672 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr, 2673 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr, 2674 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr, 2675 2676 NULL, 2677 }; 2678 2679 static const struct attribute_group it87_group_auto_pwm = { 2680 .attrs = it87_attributes_auto_pwm, 2681 .is_visible = it87_auto_pwm_is_visible, 2682 }; 2683 2684 /* 2685 * Original explanation: 2686 * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip 2687 * (IT8792E) needs to be in configuration mode before accessing the first 2688 * due to a bug in IT8792E which otherwise results in LPC bus access errors. 2689 * This needs to be done before accessing the first Super-IO chip since 2690 * the second chip may have been accessed prior to loading this driver. 2691 * 2692 * The problem is also reported to affect IT8795E, which is used on X299 boards 2693 * and has the same chip ID as IT8792E (0x8733). It also appears to affect 2694 * systems with IT8790E, which is used on some Z97X-Gaming boards as well as 2695 * Z87X-OC. 2696 * 2697 * From other information supplied: 2698 * ChipIDs 0x8733, 0x8695 (early ID for IT87952E) and 0x8790 are initialized 2699 * and left in configuration mode, and entering and/or exiting configuration 2700 * mode is what causes the crash. 2701 * 2702 * The recommendation is to look up the chipID before doing any mode swap 2703 * and then act accordingly. 2704 */ 2705 /* SuperIO detection - will change isa_address if a chip is found */ 2706 static int __init it87_find(int sioaddr, unsigned short *address, 2707 struct it87_sio_data *sio_data, int chip_cnt) 2708 { 2709 int err; 2710 u16 chip_type; 2711 const struct it87_devices *config = NULL; 2712 bool enabled = false; 2713 2714 /* First step, lock memory but don't enter configuration mode */ 2715 err = superio_enter(sioaddr, true); 2716 if (err) 2717 return err; 2718 2719 err = -ENODEV; 2720 chip_type = superio_inw(sioaddr, DEVID); 2721 /* Check for a valid chip before forcing chip id */ 2722 if (chip_type == 0xffff) { 2723 /* Enter configuration mode */ 2724 __superio_enter(sioaddr); 2725 enabled = true; 2726 /* and then try again */ 2727 chip_type = superio_inw(sioaddr, DEVID); 2728 if (chip_type == 0xffff) 2729 goto exit; 2730 } 2731 2732 if (force_id_cnt == 1) { 2733 /* If only one value given use for all chips */ 2734 if (force_id[0]) 2735 chip_type = force_id[0]; 2736 } else if (force_id[chip_cnt]) 2737 chip_type = force_id[chip_cnt]; 2738 2739 switch (chip_type) { 2740 case IT8705F_DEVID: 2741 sio_data->type = it87; 2742 break; 2743 case IT8712F_DEVID: 2744 sio_data->type = it8712; 2745 break; 2746 case IT8716F_DEVID: 2747 case IT8726F_DEVID: 2748 sio_data->type = it8716; 2749 break; 2750 case IT8718F_DEVID: 2751 sio_data->type = it8718; 2752 break; 2753 case IT8720F_DEVID: 2754 sio_data->type = it8720; 2755 break; 2756 case IT8721F_DEVID: 2757 sio_data->type = it8721; 2758 break; 2759 case IT8728F_DEVID: 2760 sio_data->type = it8728; 2761 break; 2762 case IT8732F_DEVID: 2763 sio_data->type = it8732; 2764 break; 2765 case IT8792E_DEVID: 2766 sio_data->type = it8792; 2767 break; 2768 case IT8771E_DEVID: 2769 sio_data->type = it8771; 2770 break; 2771 case IT8772E_DEVID: 2772 sio_data->type = it8772; 2773 break; 2774 case IT8781F_DEVID: 2775 sio_data->type = it8781; 2776 break; 2777 case IT8782F_DEVID: 2778 sio_data->type = it8782; 2779 break; 2780 case IT8783E_DEVID: 2781 sio_data->type = it8783; 2782 break; 2783 case IT8786E_DEVID: 2784 sio_data->type = it8786; 2785 break; 2786 case IT8790E_DEVID: 2787 sio_data->type = it8790; 2788 break; 2789 case IT8603E_DEVID: 2790 case IT8623E_DEVID: 2791 sio_data->type = it8603; 2792 break; 2793 case IT8620E_DEVID: 2794 sio_data->type = it8620; 2795 break; 2796 case IT8622E_DEVID: 2797 sio_data->type = it8622; 2798 break; 2799 case IT8628E_DEVID: 2800 sio_data->type = it8628; 2801 break; 2802 case IT8689E_DEVID: 2803 sio_data->type = it8689; 2804 break; 2805 case IT87952E_DEVID: 2806 sio_data->type = it87952; 2807 break; 2808 case 0xffff: /* No device at all */ 2809 goto exit; 2810 default: 2811 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type); 2812 goto exit; 2813 } 2814 2815 config = &it87_devices[sio_data->type]; 2816 2817 /* 2818 * If previously we didn't enter configuration mode and it isn't a 2819 * chip we know is initialised in configuration mode, then enter 2820 * configuration mode. 2821 * 2822 * I don't know if any such chips can exist but be defensive. 2823 */ 2824 if (!enabled && !has_noconf(config)) { 2825 __superio_enter(sioaddr); 2826 enabled = true; 2827 } 2828 2829 superio_select(sioaddr, PME); 2830 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) { 2831 pr_info("Device (chip %s ioreg 0x%x) not activated, skipping\n", 2832 config->model, sioaddr); 2833 goto exit; 2834 } 2835 2836 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1); 2837 if (*address == 0) { 2838 pr_info("Base address not set (chip %s ioreg 0x%x), skipping\n", 2839 config->model, sioaddr); 2840 goto exit; 2841 } 2842 2843 err = 0; 2844 sio_data->sioaddr = sioaddr; 2845 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f; 2846 pr_info("Found %s chip at 0x%x, revision %d\n", 2847 it87_devices[sio_data->type].model, 2848 *address, sio_data->revision); 2849 2850 /* in7 (VSB or VCCH5V) is always internal on some chips */ 2851 if (has_in7_internal(config)) 2852 sio_data->internal |= BIT(1); 2853 2854 /* in8 (Vbat) is always internal */ 2855 sio_data->internal |= BIT(2); 2856 2857 /* in9 (AVCC3), always internal if supported */ 2858 if (has_avcc3(config)) 2859 sio_data->internal |= BIT(3); /* in9 is AVCC */ 2860 else 2861 sio_data->skip_in |= BIT(9); 2862 2863 if (!has_four_pwm(config)) 2864 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5); 2865 else if (!has_five_pwm(config)) 2866 sio_data->skip_pwm |= BIT(4) | BIT(5); 2867 else if (!has_six_pwm(config)) 2868 sio_data->skip_pwm |= BIT(5); 2869 2870 if (!has_vid(config)) 2871 sio_data->skip_vid = 1; 2872 2873 /* Read GPIO config and VID value from LDN 7 (GPIO) */ 2874 if (sio_data->type == it87) { 2875 /* The IT8705F has a different LD number for GPIO */ 2876 superio_select(sioaddr, 5); 2877 sio_data->beep_pin = superio_inb(sioaddr, 2878 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2879 } else if (sio_data->type == it8783) { 2880 int reg25, reg27, reg2a, reg2c, regef; 2881 2882 superio_select(sioaddr, GPIO); 2883 2884 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 2885 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2886 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG); 2887 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 2888 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG); 2889 2890 /* Check if fan3 is there or not */ 2891 if ((reg27 & BIT(0)) || !(reg2c & BIT(2))) 2892 sio_data->skip_fan |= BIT(2); 2893 if ((reg25 & BIT(4)) || 2894 (!(reg2a & BIT(1)) && (regef & BIT(0)))) 2895 sio_data->skip_pwm |= BIT(2); 2896 2897 /* Check if fan2 is there or not */ 2898 if (reg27 & BIT(7)) 2899 sio_data->skip_fan |= BIT(1); 2900 if (reg27 & BIT(3)) 2901 sio_data->skip_pwm |= BIT(1); 2902 2903 /* VIN5 */ 2904 if ((reg27 & BIT(0)) || (reg2c & BIT(2))) 2905 sio_data->skip_in |= BIT(5); /* No VIN5 */ 2906 2907 /* VIN6 */ 2908 if (reg27 & BIT(1)) 2909 sio_data->skip_in |= BIT(6); /* No VIN6 */ 2910 2911 /* 2912 * VIN7 2913 * Does not depend on bit 2 of Reg2C, contrary to datasheet. 2914 */ 2915 if (reg27 & BIT(2)) { 2916 /* 2917 * The data sheet is a bit unclear regarding the 2918 * internal voltage divider for VCCH5V. It says 2919 * "This bit enables and switches VIN7 (pin 91) to the 2920 * internal voltage divider for VCCH5V". 2921 * This is different to other chips, where the internal 2922 * voltage divider would connect VIN7 to an internal 2923 * voltage source. Maybe that is the case here as well. 2924 * 2925 * Since we don't know for sure, re-route it if that is 2926 * not the case, and ask the user to report if the 2927 * resulting voltage is sane. 2928 */ 2929 if (!(reg2c & BIT(1))) { 2930 reg2c |= BIT(1); 2931 superio_outb(sioaddr, IT87_SIO_PINX2_REG, 2932 reg2c); 2933 sio_data->need_in7_reroute = true; 2934 pr_notice("Routing internal VCCH5V to in7.\n"); 2935 } 2936 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n"); 2937 pr_notice("Please report if it displays a reasonable voltage.\n"); 2938 } 2939 2940 if (reg2c & BIT(0)) 2941 sio_data->internal |= BIT(0); 2942 if (reg2c & BIT(1)) 2943 sio_data->internal |= BIT(1); 2944 2945 sio_data->beep_pin = superio_inb(sioaddr, 2946 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2947 } else if (sio_data->type == it8603) { 2948 int reg27, reg29; 2949 2950 superio_select(sioaddr, GPIO); 2951 2952 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2953 2954 /* Check if fan3 is there or not */ 2955 if (reg27 & BIT(6)) 2956 sio_data->skip_pwm |= BIT(2); 2957 if (reg27 & BIT(7)) 2958 sio_data->skip_fan |= BIT(2); 2959 2960 /* Check if fan2 is there or not */ 2961 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 2962 if (reg29 & BIT(1)) 2963 sio_data->skip_pwm |= BIT(1); 2964 if (reg29 & BIT(2)) 2965 sio_data->skip_fan |= BIT(1); 2966 2967 sio_data->skip_in |= BIT(5); /* No VIN5 */ 2968 sio_data->skip_in |= BIT(6); /* No VIN6 */ 2969 2970 sio_data->beep_pin = superio_inb(sioaddr, 2971 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2972 } else if (sio_data->type == it8620 || sio_data->type == it8628) { 2973 int reg; 2974 2975 superio_select(sioaddr, GPIO); 2976 2977 /* Check for pwm5 */ 2978 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 2979 if (reg & BIT(6)) 2980 sio_data->skip_pwm |= BIT(4); 2981 2982 /* Check for fan4, fan5 */ 2983 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); 2984 if (!(reg & BIT(5))) 2985 sio_data->skip_fan |= BIT(3); 2986 if (!(reg & BIT(4))) 2987 sio_data->skip_fan |= BIT(4); 2988 2989 /* Check for pwm3, fan3 */ 2990 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2991 if (reg & BIT(6)) 2992 sio_data->skip_pwm |= BIT(2); 2993 if (reg & BIT(7)) 2994 sio_data->skip_fan |= BIT(2); 2995 2996 /* Check for pwm4 */ 2997 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG); 2998 if (reg & BIT(2)) 2999 sio_data->skip_pwm |= BIT(3); 3000 3001 /* Check for pwm2, fan2 */ 3002 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 3003 if (reg & BIT(1)) 3004 sio_data->skip_pwm |= BIT(1); 3005 if (reg & BIT(2)) 3006 sio_data->skip_fan |= BIT(1); 3007 /* Check for pwm6, fan6 */ 3008 if (!(reg & BIT(7))) { 3009 sio_data->skip_pwm |= BIT(5); 3010 sio_data->skip_fan |= BIT(5); 3011 } 3012 3013 /* Check if AVCC is on VIN3 */ 3014 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 3015 if (reg & BIT(0)) 3016 sio_data->internal |= BIT(0); 3017 else 3018 sio_data->skip_in |= BIT(9); 3019 3020 sio_data->beep_pin = superio_inb(sioaddr, 3021 IT87_SIO_BEEP_PIN_REG) & 0x3f; 3022 } else if (sio_data->type == it8689) { 3023 int reg; 3024 3025 superio_select(sioaddr, GPIO); 3026 3027 /* Check for pwm5 */ 3028 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 3029 if (reg & BIT(6)) 3030 sio_data->skip_pwm |= BIT(4); 3031 3032 /* Check for fan4, fan5 */ 3033 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); 3034 if (!(reg & BIT(5))) 3035 sio_data->skip_fan |= BIT(3); 3036 if (!(reg & BIT(4))) 3037 sio_data->skip_fan |= BIT(4); 3038 3039 /* Check for pwm3, fan3 */ 3040 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 3041 if (reg & BIT(6)) 3042 sio_data->skip_pwm |= BIT(2); 3043 if (reg & BIT(7)) 3044 sio_data->skip_fan |= BIT(2); 3045 3046 /* Check for pwm4 */ 3047 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG); 3048 if (reg & BIT(2)) 3049 sio_data->skip_pwm |= BIT(3); 3050 3051 /* Check for pwm2, fan2 */ 3052 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 3053 if (reg & BIT(1)) 3054 sio_data->skip_pwm |= BIT(1); 3055 if (reg & BIT(2)) 3056 sio_data->skip_fan |= BIT(1); 3057 /* Check for pwm6, fan6 */ 3058 if (!(reg & BIT(7))) { 3059 sio_data->skip_pwm |= BIT(5); 3060 sio_data->skip_fan |= BIT(5); 3061 } 3062 3063 /* in9 (AVCC3) is always internal, no PINX2 check needed */ 3064 3065 sio_data->beep_pin = superio_inb(sioaddr, 3066 IT87_SIO_BEEP_PIN_REG) & 0x3f; 3067 } else if (sio_data->type == it8622) { 3068 int reg; 3069 3070 superio_select(sioaddr, GPIO); 3071 3072 /* Check for pwm4, fan4 */ 3073 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 3074 if (reg & BIT(6)) 3075 sio_data->skip_fan |= BIT(3); 3076 if (reg & BIT(5)) 3077 sio_data->skip_pwm |= BIT(3); 3078 3079 /* Check for pwm3, fan3, pwm5, fan5 */ 3080 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 3081 if (reg & BIT(6)) 3082 sio_data->skip_pwm |= BIT(2); 3083 if (reg & BIT(7)) 3084 sio_data->skip_fan |= BIT(2); 3085 if (reg & BIT(3)) 3086 sio_data->skip_pwm |= BIT(4); 3087 if (reg & BIT(1)) 3088 sio_data->skip_fan |= BIT(4); 3089 3090 /* Check for pwm2, fan2 */ 3091 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 3092 if (reg & BIT(1)) 3093 sio_data->skip_pwm |= BIT(1); 3094 if (reg & BIT(2)) 3095 sio_data->skip_fan |= BIT(1); 3096 3097 /* Check for AVCC */ 3098 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 3099 if (!(reg & BIT(0))) 3100 sio_data->skip_in |= BIT(9); 3101 3102 sio_data->beep_pin = superio_inb(sioaddr, 3103 IT87_SIO_BEEP_PIN_REG) & 0x3f; 3104 } else if (sio_data->type == it8732) { 3105 int reg; 3106 3107 superio_select(sioaddr, GPIO); 3108 3109 /* Check for pwm2, fan2 */ 3110 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 3111 if (reg & BIT(1)) 3112 sio_data->skip_pwm |= BIT(1); 3113 if (reg & BIT(2)) 3114 sio_data->skip_fan |= BIT(1); 3115 3116 /* Check for pwm3, fan3, fan4 */ 3117 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 3118 if (reg & BIT(6)) 3119 sio_data->skip_pwm |= BIT(2); 3120 if (reg & BIT(7)) 3121 sio_data->skip_fan |= BIT(2); 3122 if (reg & BIT(5)) 3123 sio_data->skip_fan |= BIT(3); 3124 3125 /* Check if AVCC is on VIN3 */ 3126 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 3127 if (reg & BIT(0)) 3128 sio_data->internal |= BIT(0); 3129 3130 sio_data->beep_pin = superio_inb(sioaddr, 3131 IT87_SIO_BEEP_PIN_REG) & 0x3f; 3132 } else { 3133 int reg; 3134 bool uart6; 3135 3136 superio_select(sioaddr, GPIO); 3137 3138 /* Check for fan4, fan5 */ 3139 if (has_five_fans(config)) { 3140 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); 3141 switch (sio_data->type) { 3142 case it8718: 3143 if (reg & BIT(5)) 3144 sio_data->skip_fan |= BIT(3); 3145 if (reg & BIT(4)) 3146 sio_data->skip_fan |= BIT(4); 3147 break; 3148 case it8720: 3149 case it8721: 3150 case it8728: 3151 if (!(reg & BIT(5))) 3152 sio_data->skip_fan |= BIT(3); 3153 if (!(reg & BIT(4))) 3154 sio_data->skip_fan |= BIT(4); 3155 break; 3156 default: 3157 break; 3158 } 3159 } 3160 3161 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 3162 if (!sio_data->skip_vid) { 3163 /* We need at least 4 VID pins */ 3164 if (reg & 0x0f) { 3165 pr_info("VID is disabled (pins used for GPIO)\n"); 3166 sio_data->skip_vid = 1; 3167 } 3168 } 3169 3170 /* Check if fan3 is there or not */ 3171 if (reg & BIT(6)) 3172 sio_data->skip_pwm |= BIT(2); 3173 if (reg & BIT(7)) 3174 sio_data->skip_fan |= BIT(2); 3175 3176 /* Check if fan2 is there or not */ 3177 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 3178 if (reg & BIT(1)) 3179 sio_data->skip_pwm |= BIT(1); 3180 if (reg & BIT(2)) 3181 sio_data->skip_fan |= BIT(1); 3182 3183 if ((sio_data->type == it8718 || sio_data->type == it8720) && 3184 !(sio_data->skip_vid)) 3185 sio_data->vid_value = superio_inb(sioaddr, 3186 IT87_SIO_VID_REG); 3187 3188 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 3189 3190 uart6 = sio_data->type == it8782 && (reg & BIT(2)); 3191 3192 /* 3193 * The IT8720F has no VIN7 pin, so VCCH5V should always be 3194 * routed internally to VIN7 with an internal divider. 3195 * Curiously, there still is a configuration bit to control 3196 * this, which means it can be set incorrectly. And even 3197 * more curiously, many boards out there are improperly 3198 * configured, even though the IT8720F datasheet claims 3199 * that the internal routing of VCCH5V to VIN7 is the default 3200 * setting. So we force the internal routing in this case. 3201 * 3202 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins. 3203 * If UART6 is enabled, re-route VIN7 to the internal divider 3204 * if that is not already the case. 3205 */ 3206 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) { 3207 reg |= BIT(1); 3208 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg); 3209 sio_data->need_in7_reroute = true; 3210 pr_notice("Routing internal VCCH5V to in7\n"); 3211 } 3212 if (reg & BIT(0)) 3213 sio_data->internal |= BIT(0); 3214 if (reg & BIT(1)) 3215 sio_data->internal |= BIT(1); 3216 3217 /* 3218 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7. 3219 * While VIN7 can be routed to the internal voltage divider, 3220 * VIN5 and VIN6 are not available if UART6 is enabled. 3221 * 3222 * Also, temp3 is not available if UART6 is enabled and TEMPIN3 3223 * is the temperature source. Since we can not read the 3224 * temperature source here, skip_temp is preliminary. 3225 */ 3226 if (uart6) { 3227 sio_data->skip_in |= BIT(5) | BIT(6); 3228 sio_data->skip_temp |= BIT(2); 3229 } 3230 3231 sio_data->beep_pin = superio_inb(sioaddr, 3232 IT87_SIO_BEEP_PIN_REG) & 0x3f; 3233 } 3234 if (sio_data->beep_pin) 3235 pr_info("Beeping is supported\n"); 3236 3237 /* Set values based on DMI matches */ 3238 if (dmi_data) 3239 sio_data->skip_pwm |= dmi_data->skip_pwm; 3240 3241 if (config->smbus_bitmap) { 3242 u8 reg; 3243 3244 superio_select(sioaddr, PME); 3245 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG); 3246 sio_data->ec_special_config = reg; 3247 sio_data->smbus_bitmap = reg & config->smbus_bitmap; 3248 } 3249 3250 exit: 3251 superio_exit(sioaddr, !enabled); 3252 return err; 3253 } 3254 3255 /* 3256 * Some chips seem to have default value 0xff for all limit 3257 * registers. For low voltage limits it makes no sense and triggers 3258 * alarms, so change to 0 instead. For high temperature limits, it 3259 * means -1 degree C, which surprisingly doesn't trigger an alarm, 3260 * but is still confusing, so change to 127 degrees C. 3261 */ 3262 static void it87_check_limit_regs(struct it87_data *data) 3263 { 3264 int i, reg; 3265 3266 for (i = 0; i < NUM_VIN_LIMIT; i++) { 3267 reg = it87_read_value(data, IT87_REG_VIN_MIN(i)); 3268 if (reg == 0xff) 3269 it87_write_value(data, IT87_REG_VIN_MIN(i), 0); 3270 } 3271 for (i = 0; i < NUM_TEMP_LIMIT; i++) { 3272 reg = it87_read_value(data, IT87_REG_TEMP_HIGH(i)); 3273 if (reg == 0xff) 3274 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127); 3275 } 3276 } 3277 3278 /* Check if voltage monitors are reset manually or by some reason */ 3279 static void it87_check_voltage_monitors_reset(struct it87_data *data) 3280 { 3281 int reg; 3282 3283 reg = it87_read_value(data, IT87_REG_VIN_ENABLE); 3284 if ((reg & 0xff) == 0) { 3285 /* Enable all voltage monitors */ 3286 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff); 3287 } 3288 } 3289 3290 /* Check if tachometers are reset manually or by some reason */ 3291 static void it87_check_tachometers_reset(struct platform_device *pdev) 3292 { 3293 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); 3294 struct it87_data *data = platform_get_drvdata(pdev); 3295 u8 mask, fan_main_ctrl; 3296 3297 mask = 0x70 & ~(sio_data->skip_fan << 4); 3298 fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); 3299 if ((fan_main_ctrl & mask) == 0) { 3300 /* Enable all fan tachometers */ 3301 fan_main_ctrl |= mask; 3302 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 3303 fan_main_ctrl); 3304 } 3305 } 3306 3307 /* Set tachometers to 16-bit mode if needed */ 3308 static void it87_check_tachometers_16bit_mode(struct platform_device *pdev) 3309 { 3310 struct it87_data *data = platform_get_drvdata(pdev); 3311 int reg; 3312 3313 if (!has_fan16_config(data)) 3314 return; 3315 3316 reg = it87_read_value(data, IT87_REG_FAN_16BIT); 3317 if (~reg & 0x07 & data->has_fan) { 3318 dev_dbg(&pdev->dev, 3319 "Setting fan1-3 to 16-bit mode\n"); 3320 it87_write_value(data, IT87_REG_FAN_16BIT, 3321 reg | 0x07); 3322 } 3323 } 3324 3325 static void it87_start_monitoring(struct it87_data *data) 3326 { 3327 it87_write_value(data, IT87_REG_CONFIG, 3328 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e) 3329 | (update_vbat ? 0x41 : 0x01)); 3330 } 3331 3332 /* Called when we have found a new IT87. */ 3333 static void it87_init_device(struct platform_device *pdev) 3334 { 3335 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); 3336 struct it87_data *data = platform_get_drvdata(pdev); 3337 int tmp, i; 3338 3339 /* 3340 * For each PWM channel: 3341 * - If it is in automatic mode, setting to manual mode should set 3342 * the fan to full speed by default. 3343 * - If it is in manual mode, we need a mapping to temperature 3344 * channels to use when later setting to automatic mode later. 3345 * Use a 1:1 mapping by default (we are clueless.) 3346 * In both cases, the value can (and should) be changed by the user 3347 * prior to switching to a different mode. 3348 * Note that this is no longer needed for the IT8721F and later, as 3349 * these have separate registers for the temperature mapping and the 3350 * manual duty cycle. 3351 */ 3352 for (i = 0; i < NUM_AUTO_PWM; i++) { 3353 data->pwm_temp_map[i] = i; 3354 data->pwm_duty[i] = 0x7f; /* Full speed */ 3355 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */ 3356 } 3357 3358 it87_check_limit_regs(data); 3359 3360 /* 3361 * Temperature channels are not forcibly enabled, as they can be 3362 * set to two different sensor types and we can't guess which one 3363 * is correct for a given system. These channels can be enabled at 3364 * run-time through the temp{1-3}_type sysfs accessors if needed. 3365 */ 3366 3367 it87_check_voltage_monitors_reset(data); 3368 3369 it87_check_tachometers_reset(pdev); 3370 3371 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); 3372 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07; 3373 3374 it87_check_tachometers_16bit_mode(pdev); 3375 3376 /* Check for additional fans */ 3377 tmp = it87_read_value(data, IT87_REG_FAN_16BIT); 3378 3379 if (has_four_fans(data) && (tmp & BIT(4))) 3380 data->has_fan |= BIT(3); /* fan4 enabled */ 3381 if (has_five_fans(data) && (tmp & BIT(5))) 3382 data->has_fan |= BIT(4); /* fan5 enabled */ 3383 if (has_six_fans(data) && (tmp & BIT(2))) 3384 data->has_fan |= BIT(5); /* fan6 enabled */ 3385 3386 /* Fan input pins may be used for alternative functions */ 3387 data->has_fan &= ~sio_data->skip_fan; 3388 3389 /* Check if pwm5, pwm6 are enabled */ 3390 if (has_six_pwm(data)) { 3391 /* The following code may be IT8620E specific */ 3392 tmp = it87_read_value(data, IT87_REG_FAN_DIV); 3393 if ((tmp & 0xc0) == 0xc0) 3394 sio_data->skip_pwm |= BIT(4); 3395 if (!(tmp & BIT(3))) 3396 sio_data->skip_pwm |= BIT(5); 3397 } 3398 3399 it87_start_monitoring(data); 3400 } 3401 3402 /* Return 1 if and only if the PWM interface is safe to use */ 3403 static int it87_check_pwm(struct device *dev) 3404 { 3405 struct it87_data *data = dev_get_drvdata(dev); 3406 /* 3407 * Some BIOSes fail to correctly configure the IT87 fans. All fans off 3408 * and polarity set to active low is sign that this is the case so we 3409 * disable pwm control to protect the user. 3410 */ 3411 int tmp = it87_read_value(data, IT87_REG_FAN_CTL); 3412 3413 if ((tmp & 0x87) == 0) { 3414 if (fix_pwm_polarity) { 3415 /* 3416 * The user asks us to attempt a chip reconfiguration. 3417 * This means switching to active high polarity and 3418 * inverting all fan speed values. 3419 */ 3420 int i; 3421 u8 pwm[3]; 3422 3423 for (i = 0; i < ARRAY_SIZE(pwm); i++) 3424 pwm[i] = it87_read_value(data, 3425 IT87_REG_PWM[i]); 3426 3427 /* 3428 * If any fan is in automatic pwm mode, the polarity 3429 * might be correct, as suspicious as it seems, so we 3430 * better don't change anything (but still disable the 3431 * PWM interface). 3432 */ 3433 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) { 3434 dev_info(dev, 3435 "Reconfiguring PWM to active high polarity\n"); 3436 it87_write_value(data, IT87_REG_FAN_CTL, 3437 tmp | 0x87); 3438 for (i = 0; i < 3; i++) 3439 it87_write_value(data, 3440 IT87_REG_PWM[i], 3441 0x7f & ~pwm[i]); 3442 return 1; 3443 } 3444 3445 dev_info(dev, 3446 "PWM configuration is too broken to be fixed\n"); 3447 } 3448 3449 return 0; 3450 } else if (fix_pwm_polarity) { 3451 dev_info(dev, 3452 "PWM configuration looks sane, won't touch\n"); 3453 } 3454 3455 return 1; 3456 } 3457 3458 static int it87_probe(struct platform_device *pdev) 3459 { 3460 struct it87_data *data; 3461 struct resource *res; 3462 struct device *dev = &pdev->dev; 3463 struct it87_sio_data *sio_data = dev_get_platdata(dev); 3464 int enable_pwm_interface; 3465 struct device *hwmon_dev; 3466 int err; 3467 3468 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 3469 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT, 3470 DRVNAME)) { 3471 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n", 3472 (unsigned long)res->start, 3473 (unsigned long)(res->start + IT87_EC_EXTENT - 1)); 3474 return -EBUSY; 3475 } 3476 3477 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL); 3478 if (!data) 3479 return -ENOMEM; 3480 3481 data->addr = res->start; 3482 data->sioaddr = sio_data->sioaddr; 3483 data->type = sio_data->type; 3484 data->smbus_bitmap = sio_data->smbus_bitmap; 3485 data->ec_special_config = sio_data->ec_special_config; 3486 data->features = it87_devices[sio_data->type].features; 3487 data->peci_mask = it87_devices[sio_data->type].peci_mask; 3488 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask; 3489 /* 3490 * IT8705F Datasheet 0.4.1, 3h == Version G. 3491 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J. 3492 * These are the first revisions with 16-bit tachometer support. 3493 */ 3494 switch (data->type) { 3495 case it87: 3496 if (sio_data->revision >= 0x03) { 3497 data->features &= ~FEAT_OLD_AUTOPWM; 3498 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS; 3499 } 3500 break; 3501 case it8712: 3502 if (sio_data->revision >= 0x08) { 3503 data->features &= ~FEAT_OLD_AUTOPWM; 3504 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS | 3505 FEAT_FIVE_FANS; 3506 } 3507 break; 3508 default: 3509 break; 3510 } 3511 3512 platform_set_drvdata(pdev, data); 3513 3514 mutex_init(&data->update_lock); 3515 3516 err = smbus_disable(data); 3517 if (err) 3518 return err; 3519 3520 /* Now, we do the remaining detection. */ 3521 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) || 3522 it87_read_value(data, IT87_REG_CHIPID) != 0x90) { 3523 smbus_enable(data); 3524 return -ENODEV; 3525 } 3526 3527 /* Check PWM configuration */ 3528 enable_pwm_interface = it87_check_pwm(dev); 3529 if (!enable_pwm_interface) 3530 dev_info(dev, 3531 "Detected broken BIOS defaults, disabling PWM interface\n"); 3532 3533 /* Starting with IT8721F, we handle scaling of internal voltages */ 3534 if (has_scaling(data)) { 3535 if (sio_data->internal & BIT(0)) 3536 data->in_scaled |= BIT(3); /* in3 is AVCC */ 3537 if (sio_data->internal & BIT(1)) 3538 data->in_scaled |= BIT(7); /* in7 is VSB */ 3539 if (sio_data->internal & BIT(2)) 3540 data->in_scaled |= BIT(8); /* in8 is Vbat */ 3541 if (sio_data->internal & BIT(3)) 3542 data->in_scaled |= BIT(9); /* in9 is AVCC */ 3543 } else if (sio_data->type == it8781 || sio_data->type == it8782 || 3544 sio_data->type == it8783) { 3545 if (sio_data->internal & BIT(0)) 3546 data->in_scaled |= BIT(3); /* in3 is VCC5V */ 3547 if (sio_data->internal & BIT(1)) 3548 data->in_scaled |= BIT(7); /* in7 is VCCH5V */ 3549 } 3550 3551 data->has_temp = 0x07; 3552 if (sio_data->skip_temp & BIT(2)) { 3553 if (sio_data->type == it8782 && 3554 !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80)) 3555 data->has_temp &= ~BIT(2); 3556 } 3557 3558 data->in_internal = sio_data->internal; 3559 data->need_in7_reroute = sio_data->need_in7_reroute; 3560 data->has_in = 0x3ff & ~sio_data->skip_in; 3561 3562 if (has_four_temp(data)) { 3563 data->has_temp |= BIT(3); 3564 } else if (has_six_temp(data)) { 3565 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE); 3566 3567 /* Check for additional temperature sensors */ 3568 if ((reg & 0x03) >= 0x02) 3569 data->has_temp |= BIT(3); 3570 if (((reg >> 2) & 0x03) >= 0x02) 3571 data->has_temp |= BIT(4); 3572 if (((reg >> 4) & 0x03) >= 0x02) 3573 data->has_temp |= BIT(5); 3574 3575 /* Check for additional voltage sensors */ 3576 if ((reg & 0x03) == 0x01) 3577 data->has_in |= BIT(10); 3578 if (((reg >> 2) & 0x03) == 0x01) 3579 data->has_in |= BIT(11); 3580 if (((reg >> 4) & 0x03) == 0x01) 3581 data->has_in |= BIT(12); 3582 } 3583 3584 data->has_beep = !!sio_data->beep_pin; 3585 3586 /* Initialize the IT87 chip */ 3587 it87_init_device(pdev); 3588 3589 smbus_enable(data); 3590 3591 if (!sio_data->skip_vid) { 3592 data->has_vid = true; 3593 data->vrm = vid_which_vrm(); 3594 /* VID reading from Super-I/O config space if available */ 3595 data->vid = sio_data->vid_value; 3596 } 3597 3598 /* Prepare for sysfs hooks */ 3599 data->groups[0] = &it87_group; 3600 data->groups[1] = &it87_group_in; 3601 data->groups[2] = &it87_group_temp; 3602 data->groups[3] = &it87_group_fan; 3603 3604 if (enable_pwm_interface) { 3605 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1; 3606 data->has_pwm &= ~sio_data->skip_pwm; 3607 3608 data->groups[4] = &it87_group_pwm; 3609 if (has_old_autopwm(data) || has_newer_autopwm(data)) 3610 data->groups[5] = &it87_group_auto_pwm; 3611 } 3612 3613 hwmon_dev = devm_hwmon_device_register_with_groups(dev, 3614 it87_devices[sio_data->type].name, 3615 data, data->groups); 3616 return PTR_ERR_OR_ZERO(hwmon_dev); 3617 } 3618 3619 static void it87_resume_sio(struct platform_device *pdev) 3620 { 3621 struct it87_data *data = dev_get_drvdata(&pdev->dev); 3622 int err; 3623 int reg2c; 3624 3625 if (!data->need_in7_reroute) 3626 return; 3627 3628 err = superio_enter(data->sioaddr, has_noconf(data)); 3629 if (err) { 3630 dev_warn(&pdev->dev, 3631 "Unable to enter Super I/O to reroute in7 (%d)", 3632 err); 3633 return; 3634 } 3635 3636 superio_select(data->sioaddr, GPIO); 3637 3638 reg2c = superio_inb(data->sioaddr, IT87_SIO_PINX2_REG); 3639 if (!(reg2c & BIT(1))) { 3640 dev_dbg(&pdev->dev, 3641 "Routing internal VCCH5V to in7 again"); 3642 3643 reg2c |= BIT(1); 3644 superio_outb(data->sioaddr, IT87_SIO_PINX2_REG, 3645 reg2c); 3646 } 3647 3648 superio_exit(data->sioaddr, has_noconf(data)); 3649 } 3650 3651 static int it87_resume(struct device *dev) 3652 { 3653 struct platform_device *pdev = to_platform_device(dev); 3654 struct it87_data *data = dev_get_drvdata(dev); 3655 int err; 3656 3657 it87_resume_sio(pdev); 3658 3659 err = it87_lock(data); 3660 if (err) 3661 return err; 3662 3663 it87_check_pwm(dev); 3664 it87_check_limit_regs(data); 3665 it87_check_voltage_monitors_reset(data); 3666 it87_check_tachometers_reset(pdev); 3667 it87_check_tachometers_16bit_mode(pdev); 3668 3669 it87_start_monitoring(data); 3670 3671 /* force update */ 3672 data->valid = false; 3673 3674 it87_unlock(data); 3675 3676 it87_update_device(dev); 3677 3678 return 0; 3679 } 3680 3681 static DEFINE_SIMPLE_DEV_PM_OPS(it87_dev_pm_ops, NULL, it87_resume); 3682 3683 static struct platform_driver it87_driver = { 3684 .driver = { 3685 .name = DRVNAME, 3686 .pm = pm_sleep_ptr(&it87_dev_pm_ops), 3687 }, 3688 .probe = it87_probe, 3689 }; 3690 3691 static int __init it87_device_add(int index, unsigned short address, 3692 const struct it87_sio_data *sio_data) 3693 { 3694 struct platform_device *pdev; 3695 struct resource res = { 3696 .start = address + IT87_EC_OFFSET, 3697 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1, 3698 .name = DRVNAME, 3699 .flags = IORESOURCE_IO, 3700 }; 3701 int err; 3702 3703 err = acpi_check_resource_conflict(&res); 3704 if (err) { 3705 if (!ignore_resource_conflict) 3706 return err; 3707 } 3708 3709 pdev = platform_device_alloc(DRVNAME, address); 3710 if (!pdev) 3711 return -ENOMEM; 3712 3713 err = platform_device_add_resources(pdev, &res, 1); 3714 if (err) { 3715 pr_err("Device resource addition failed (%d)\n", err); 3716 goto exit_device_put; 3717 } 3718 3719 err = platform_device_add_data(pdev, sio_data, 3720 sizeof(struct it87_sio_data)); 3721 if (err) { 3722 pr_err("Platform data allocation failed\n"); 3723 goto exit_device_put; 3724 } 3725 3726 err = platform_device_add(pdev); 3727 if (err) { 3728 pr_err("Device addition failed (%d)\n", err); 3729 goto exit_device_put; 3730 } 3731 3732 it87_pdev[index] = pdev; 3733 return 0; 3734 3735 exit_device_put: 3736 platform_device_put(pdev); 3737 return err; 3738 } 3739 3740 /* callback function for DMI */ 3741 static int it87_dmi_cb(const struct dmi_system_id *dmi_entry) 3742 { 3743 dmi_data = dmi_entry->driver_data; 3744 3745 if (dmi_data && dmi_data->skip_pwm) 3746 pr_info("Disabling pwm2 due to hardware constraints\n"); 3747 3748 return 1; 3749 } 3750 3751 /* 3752 * On the Shuttle SN68PT, FAN_CTL2 is apparently not 3753 * connected to a fan, but to something else. One user 3754 * has reported instant system power-off when changing 3755 * the PWM2 duty cycle, so we disable it. 3756 * I use the board name string as the trigger in case 3757 * the same board is ever used in other systems. 3758 */ 3759 static struct it87_dmi_data nvidia_fn68pt = { 3760 .skip_pwm = BIT(1), 3761 }; 3762 3763 #define IT87_DMI_MATCH_VND(vendor, name, cb, data) \ 3764 { \ 3765 .callback = cb, \ 3766 .matches = { \ 3767 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, vendor), \ 3768 DMI_EXACT_MATCH(DMI_BOARD_NAME, name), \ 3769 }, \ 3770 .driver_data = data, \ 3771 } 3772 3773 static const struct dmi_system_id it87_dmi_table[] __initconst = { 3774 IT87_DMI_MATCH_VND("nVIDIA", "FN68PT", it87_dmi_cb, &nvidia_fn68pt), 3775 { } 3776 3777 }; 3778 MODULE_DEVICE_TABLE(dmi, it87_dmi_table); 3779 3780 static int __init sm_it87_init(void) 3781 { 3782 int sioaddr[2] = { REG_2E, REG_4E }; 3783 struct it87_sio_data sio_data; 3784 unsigned short isa_address[2]; 3785 bool found = false; 3786 int i, err; 3787 3788 err = platform_driver_register(&it87_driver); 3789 if (err) 3790 return err; 3791 3792 dmi_check_system(it87_dmi_table); 3793 3794 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) { 3795 memset(&sio_data, 0, sizeof(struct it87_sio_data)); 3796 isa_address[i] = 0; 3797 err = it87_find(sioaddr[i], &isa_address[i], &sio_data, i); 3798 if (err || isa_address[i] == 0) 3799 continue; 3800 /* 3801 * Don't register second chip if its ISA address matches 3802 * the first chip's ISA address. 3803 */ 3804 if (i && isa_address[i] == isa_address[0]) 3805 break; 3806 3807 err = it87_device_add(i, isa_address[i], &sio_data); 3808 if (err) 3809 goto exit_dev_unregister; 3810 3811 found = true; 3812 3813 /* 3814 * IT8705F may respond on both SIO addresses. 3815 * Stop probing after finding one. 3816 */ 3817 if (sio_data.type == it87) 3818 break; 3819 } 3820 3821 if (!found) { 3822 err = -ENODEV; 3823 goto exit_unregister; 3824 } 3825 return 0; 3826 3827 exit_dev_unregister: 3828 /* NULL check handled by platform_device_unregister */ 3829 platform_device_unregister(it87_pdev[0]); 3830 exit_unregister: 3831 platform_driver_unregister(&it87_driver); 3832 return err; 3833 } 3834 3835 static void __exit sm_it87_exit(void) 3836 { 3837 /* NULL check handled by platform_device_unregister */ 3838 platform_device_unregister(it87_pdev[1]); 3839 platform_device_unregister(it87_pdev[0]); 3840 platform_driver_unregister(&it87_driver); 3841 } 3842 3843 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>"); 3844 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver"); 3845 3846 module_param_array(force_id, ushort, &force_id_cnt, 0); 3847 MODULE_PARM_DESC(force_id, "Override one or more detected device ID(s)"); 3848 3849 module_param(ignore_resource_conflict, bool, 0); 3850 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict"); 3851 3852 module_param(update_vbat, bool, 0); 3853 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value"); 3854 3855 module_param(fix_pwm_polarity, bool, 0); 3856 MODULE_PARM_DESC(fix_pwm_polarity, 3857 "Force PWM polarity to active high (DANGEROUS)"); 3858 3859 MODULE_LICENSE("GPL"); 3860 3861 module_init(sm_it87_init); 3862 module_exit(sm_it87_exit); 3863