1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // mt6359-accdet.c -- ALSA SoC mt6359 accdet driver 4 // 5 // Copyright (C) 2021 MediaTek Inc. 6 // Author: Argus Lin <argus.lin@mediatek.com> 7 // 8 9 #include <linux/cleanup.h> 10 #include <linux/of.h> 11 #include <linux/input.h> 12 #include <linux/kthread.h> 13 #include <linux/io.h> 14 #include <linux/sched/clock.h> 15 #include <linux/workqueue.h> 16 #include <linux/timer.h> 17 #include <linux/delay.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/init.h> 21 #include <linux/irqdomain.h> 22 #include <linux/irq.h> 23 #include <linux/regmap.h> 24 #include <sound/soc.h> 25 #include <sound/jack.h> 26 #include <linux/mfd/mt6397/core.h> 27 28 #include "mt6359-accdet.h" 29 #include "mt6359.h" 30 31 /* global variable definitions */ 32 #define REGISTER_VAL(x) ((x) - 1) 33 34 /* mt6359 accdet capability */ 35 #define ACCDET_PMIC_EINT_IRQ BIT(0) 36 #define ACCDET_AP_GPIO_EINT BIT(1) 37 38 #define ACCDET_PMIC_EINT0 BIT(2) 39 #define ACCDET_PMIC_EINT1 BIT(3) 40 #define ACCDET_PMIC_BI_EINT BIT(4) 41 42 #define ACCDET_PMIC_GPIO_TRIG_EINT BIT(5) 43 #define ACCDET_PMIC_INVERTER_TRIG_EINT BIT(6) 44 #define ACCDET_PMIC_RSV_EINT BIT(7) 45 46 #define ACCDET_THREE_KEY BIT(8) 47 #define ACCDET_FOUR_KEY BIT(9) 48 #define ACCDET_TRI_KEY_CDD BIT(10) 49 #define ACCDET_RSV_KEY BIT(11) 50 51 #define ACCDET_ANALOG_FASTDISCHARGE BIT(12) 52 #define ACCDET_DIGITAL_FASTDISCHARGE BIT(13) 53 #define ACCDET_AD_FASTDISCHRAGE BIT(14) 54 55 static struct platform_driver mt6359_accdet_driver; 56 static const struct snd_soc_component_driver mt6359_accdet_soc_driver; 57 58 /* local function declaration */ 59 static void accdet_set_debounce(struct mt6359_accdet *priv, int state, 60 unsigned int debounce); 61 static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv); 62 static void config_digital_init_by_mode(struct mt6359_accdet *priv); 63 static void config_eint_init_by_mode(struct mt6359_accdet *priv); 64 static inline void mt6359_accdet_init(struct mt6359_accdet *priv); 65 static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv); 66 static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv); 67 static void mt6359_accdet_jack_report(struct mt6359_accdet *priv); 68 static void recover_eint_analog_setting(struct mt6359_accdet *priv); 69 static void recover_eint_digital_setting(struct mt6359_accdet *priv); 70 static void recover_eint_setting(struct mt6359_accdet *priv); 71 72 static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv) 73 { 74 if (priv->data->eint_detect_mode == 0x3 || 75 priv->data->eint_detect_mode == 0x4) { 76 /* ESD switches off */ 77 regmap_update_bits(priv->regmap, 78 RG_ACCDETSPARE_ADDR, 1 << 8, 0); 79 } 80 if (priv->data->eint_detect_mode == 0x4) { 81 if (priv->caps & ACCDET_PMIC_EINT0) { 82 /* enable RG_EINT0CONFIGACCDET */ 83 regmap_update_bits(priv->regmap, 84 RG_EINT0CONFIGACCDET_ADDR, 85 RG_EINT0CONFIGACCDET_MASK_SFT, 86 BIT(RG_EINT0CONFIGACCDET_SFT)); 87 } else if (priv->caps & ACCDET_PMIC_EINT1) { 88 /* enable RG_EINT1CONFIGACCDET */ 89 regmap_update_bits(priv->regmap, 90 RG_EINT1CONFIGACCDET_ADDR, 91 RG_EINT1CONFIGACCDET_MASK_SFT, 92 BIT(RG_EINT1CONFIGACCDET_SFT)); 93 } 94 if (priv->data->eint_use_ext_res == 0x3 || 95 priv->data->eint_use_ext_res == 0x4) { 96 /*select 500k, use internal resistor */ 97 regmap_update_bits(priv->regmap, 98 RG_EINT0HIRENB_ADDR, 99 RG_EINT0HIRENB_MASK_SFT, 100 BIT(RG_EINT0HIRENB_SFT)); 101 } 102 } 103 return 0; 104 } 105 106 static unsigned int adjust_eint_digital_setting(struct mt6359_accdet *priv) 107 { 108 if (priv->caps & ACCDET_PMIC_EINT0) { 109 /* disable inverter */ 110 regmap_update_bits(priv->regmap, 111 ACCDET_EINT0_INVERTER_SW_EN_ADDR, 112 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 0); 113 } else if (priv->caps & ACCDET_PMIC_EINT1) { 114 /* disable inverter */ 115 regmap_update_bits(priv->regmap, 116 ACCDET_EINT1_INVERTER_SW_EN_ADDR, 117 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 0); 118 } 119 120 if (priv->data->eint_detect_mode == 0x4) { 121 if (priv->caps & ACCDET_PMIC_EINT0) { 122 /* set DA stable signal */ 123 regmap_update_bits(priv->regmap, 124 ACCDET_DA_STABLE_ADDR, 125 ACCDET_EINT0_CEN_STABLE_MASK_SFT, 0); 126 } else if (priv->caps & ACCDET_PMIC_EINT1) { 127 /* set DA stable signal */ 128 regmap_update_bits(priv->regmap, 129 ACCDET_DA_STABLE_ADDR, 130 ACCDET_EINT1_CEN_STABLE_MASK_SFT, 0); 131 } 132 } 133 return 0; 134 } 135 136 static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv) 137 { 138 if (priv->jd_sts == M_PLUG_IN) { 139 /* adjust digital setting */ 140 adjust_eint_digital_setting(priv); 141 /* adjust analog setting */ 142 adjust_eint_analog_setting(priv); 143 } else if (priv->jd_sts == M_PLUG_OUT) { 144 /* set debounce to 1ms */ 145 accdet_set_debounce(priv, eint_state000, 146 priv->data->pwm_deb->eint_debounce0); 147 } else { 148 dev_dbg(priv->dev, "should not be here %s()\n", __func__); 149 } 150 151 return 0; 152 } 153 154 static void recover_eint_analog_setting(struct mt6359_accdet *priv) 155 { 156 if (priv->data->eint_detect_mode == 0x3 || 157 priv->data->eint_detect_mode == 0x4) { 158 /* ESD switches on */ 159 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, 160 1 << 8, 1 << 8); 161 } 162 if (priv->data->eint_detect_mode == 0x4) { 163 if (priv->caps & ACCDET_PMIC_EINT0) { 164 /* disable RG_EINT0CONFIGACCDET */ 165 regmap_update_bits(priv->regmap, 166 RG_EINT0CONFIGACCDET_ADDR, 167 RG_EINT0CONFIGACCDET_MASK_SFT, 0); 168 } else if (priv->caps & ACCDET_PMIC_EINT1) { 169 /* disable RG_EINT1CONFIGACCDET */ 170 regmap_update_bits(priv->regmap, 171 RG_EINT1CONFIGACCDET_ADDR, 172 RG_EINT1CONFIGACCDET_MASK_SFT, 0); 173 } 174 regmap_update_bits(priv->regmap, RG_EINT0HIRENB_ADDR, 175 RG_EINT0HIRENB_MASK_SFT, 0); 176 } 177 } 178 179 static void recover_eint_digital_setting(struct mt6359_accdet *priv) 180 { 181 if (priv->caps & ACCDET_PMIC_EINT0) { 182 regmap_update_bits(priv->regmap, 183 ACCDET_EINT0_M_SW_EN_ADDR, 184 ACCDET_EINT0_M_SW_EN_MASK_SFT, 0); 185 } else if (priv->caps & ACCDET_PMIC_EINT1) { 186 regmap_update_bits(priv->regmap, 187 ACCDET_EINT1_M_SW_EN_ADDR, 188 ACCDET_EINT1_M_SW_EN_MASK_SFT, 0); 189 } 190 if (priv->data->eint_detect_mode == 0x4) { 191 /* enable eint0cen */ 192 if (priv->caps & ACCDET_PMIC_EINT0) { 193 /* enable eint0cen */ 194 regmap_update_bits(priv->regmap, 195 ACCDET_DA_STABLE_ADDR, 196 ACCDET_EINT0_CEN_STABLE_MASK_SFT, 197 BIT(ACCDET_EINT0_CEN_STABLE_SFT)); 198 } else if (priv->caps & ACCDET_PMIC_EINT1) { 199 /* enable eint1cen */ 200 regmap_update_bits(priv->regmap, 201 ACCDET_DA_STABLE_ADDR, 202 ACCDET_EINT1_CEN_STABLE_MASK_SFT, 203 BIT(ACCDET_EINT1_CEN_STABLE_SFT)); 204 } 205 } 206 207 if (priv->data->eint_detect_mode != 0x1) { 208 if (priv->caps & ACCDET_PMIC_EINT0) { 209 /* enable inverter */ 210 regmap_update_bits(priv->regmap, 211 ACCDET_EINT0_INVERTER_SW_EN_ADDR, 212 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 213 BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); 214 } else if (priv->caps & ACCDET_PMIC_EINT1) { 215 /* enable inverter */ 216 regmap_update_bits(priv->regmap, 217 ACCDET_EINT1_INVERTER_SW_EN_ADDR, 218 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 219 BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); 220 } 221 } 222 } 223 224 static void recover_eint_setting(struct mt6359_accdet *priv) 225 { 226 if (priv->jd_sts == M_PLUG_OUT) { 227 recover_eint_analog_setting(priv); 228 recover_eint_digital_setting(priv); 229 } 230 } 231 232 static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv) 233 { 234 int ret; 235 unsigned int value = 0; 236 237 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 238 ACCDET_IRQ_CLR_MASK_SFT, BIT(ACCDET_IRQ_CLR_SFT)); 239 usleep_range(200, 300); 240 ret = regmap_read_poll_timeout(priv->regmap, 241 ACCDET_IRQ_ADDR, 242 value, 243 (value & ACCDET_IRQ_MASK_SFT) == 0, 244 0, 245 1000); 246 if (ret) 247 dev_warn(priv->dev, "%s(), ret %d\n", __func__, ret); 248 /* clear accdet int, modify for fix interrupt trigger twice error */ 249 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 250 ACCDET_IRQ_CLR_MASK_SFT, 0); 251 regmap_update_bits(priv->regmap, RG_INT_STATUS_ACCDET_ADDR, 252 RG_INT_STATUS_ACCDET_MASK_SFT, 253 BIT(RG_INT_STATUS_ACCDET_SFT)); 254 255 /* recover accdet debounce0,3 */ 256 accdet_set_debounce(priv, accdet_state000, 257 priv->data->pwm_deb->debounce0); 258 accdet_set_debounce(priv, accdet_state001, 259 priv->data->pwm_deb->debounce1); 260 accdet_set_debounce(priv, accdet_state011, 261 priv->data->pwm_deb->debounce3); 262 263 priv->jack_type = 0; 264 priv->btn_type = 0; 265 priv->accdet_status = 0x3; 266 mt6359_accdet_jack_report(priv); 267 } 268 269 static void accdet_set_debounce(struct mt6359_accdet *priv, int state, 270 unsigned int debounce) 271 { 272 switch (state) { 273 case accdet_state000: 274 regmap_write(priv->regmap, ACCDET_DEBOUNCE0_ADDR, debounce); 275 break; 276 case accdet_state001: 277 regmap_write(priv->regmap, ACCDET_DEBOUNCE1_ADDR, debounce); 278 break; 279 case accdet_state010: 280 regmap_write(priv->regmap, ACCDET_DEBOUNCE2_ADDR, debounce); 281 break; 282 case accdet_state011: 283 regmap_write(priv->regmap, ACCDET_DEBOUNCE3_ADDR, debounce); 284 break; 285 case accdet_auxadc: 286 regmap_write(priv->regmap, 287 ACCDET_CONNECT_AUXADC_TIME_DIG_ADDR, debounce); 288 break; 289 case eint_state000: 290 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE0_ADDR, 291 0xF << ACCDET_EINT_DEBOUNCE0_SFT, 292 debounce << ACCDET_EINT_DEBOUNCE0_SFT); 293 break; 294 case eint_state001: 295 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE1_ADDR, 296 0xF << ACCDET_EINT_DEBOUNCE1_SFT, 297 debounce << ACCDET_EINT_DEBOUNCE1_SFT); 298 break; 299 case eint_state010: 300 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE2_ADDR, 301 0xF << ACCDET_EINT_DEBOUNCE2_SFT, 302 debounce << ACCDET_EINT_DEBOUNCE2_SFT); 303 break; 304 case eint_state011: 305 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE3_ADDR, 306 0xF << ACCDET_EINT_DEBOUNCE3_SFT, 307 debounce << ACCDET_EINT_DEBOUNCE3_SFT); 308 break; 309 case eint_inverter_state000: 310 regmap_write(priv->regmap, ACCDET_EINT_INVERTER_DEBOUNCE_ADDR, 311 debounce); 312 break; 313 default: 314 dev_warn(priv->dev, "Error: %s error state (%d)\n", __func__, 315 state); 316 break; 317 } 318 } 319 320 static void mt6359_accdet_jack_report(struct mt6359_accdet *priv) 321 { 322 int report = 0; 323 324 if (!priv->jack) 325 return; 326 327 report = priv->jack_type | priv->btn_type; 328 snd_soc_jack_report(priv->jack, report, MT6359_ACCDET_JACK_MASK); 329 } 330 331 static unsigned int check_button(struct mt6359_accdet *priv, unsigned int v) 332 { 333 if (priv->caps & ACCDET_FOUR_KEY) { 334 if (v < priv->data->four_key.down && 335 v >= priv->data->four_key.up) 336 priv->btn_type = SND_JACK_BTN_1; 337 if (v < priv->data->four_key.up && 338 v >= priv->data->four_key.voice) 339 priv->btn_type = SND_JACK_BTN_2; 340 if (v < priv->data->four_key.voice && 341 v >= priv->data->four_key.mid) 342 priv->btn_type = SND_JACK_BTN_3; 343 if (v < priv->data->four_key.mid) 344 priv->btn_type = SND_JACK_BTN_0; 345 } else { 346 if (v < priv->data->three_key.down && 347 v >= priv->data->three_key.up) 348 priv->btn_type = SND_JACK_BTN_1; 349 if (v < priv->data->three_key.up && 350 v >= priv->data->three_key.mid) 351 priv->btn_type = SND_JACK_BTN_2; 352 if (v < priv->data->three_key.mid) 353 priv->btn_type = SND_JACK_BTN_0; 354 } 355 return 0; 356 } 357 358 static void is_key_pressed(struct mt6359_accdet *priv, bool pressed) 359 { 360 priv->btn_type = priv->jack_type & ~MT6359_ACCDET_BTN_MASK; 361 362 if (pressed) 363 check_button(priv, priv->cali_voltage); 364 } 365 366 static inline void check_jack_btn_type(struct mt6359_accdet *priv) 367 { 368 unsigned int val = 0; 369 370 regmap_read(priv->regmap, ACCDET_MEM_IN_ADDR, &val); 371 372 priv->accdet_status = 373 (val >> ACCDET_STATE_MEM_IN_OFFSET) & ACCDET_STATE_AB_MASK; 374 375 switch (priv->accdet_status) { 376 case 0: 377 if (priv->jack_type == SND_JACK_HEADSET) 378 is_key_pressed(priv, true); 379 else 380 priv->jack_type = SND_JACK_HEADPHONE; 381 break; 382 case 1: 383 if (priv->jack_type == SND_JACK_HEADSET) { 384 is_key_pressed(priv, false); 385 } else { 386 priv->jack_type = SND_JACK_HEADSET; 387 accdet_set_debounce(priv, eint_state011, 0x1); 388 } 389 break; 390 case 3: 391 default: 392 priv->jack_type = 0; 393 break; 394 } 395 } 396 397 static void mt6359_accdet_work(struct work_struct *work) 398 { 399 struct mt6359_accdet *priv = 400 container_of(work, struct mt6359_accdet, accdet_work); 401 402 guard(mutex)(&priv->res_lock); 403 priv->pre_accdet_status = priv->accdet_status; 404 check_jack_btn_type(priv); 405 406 if (priv->jack_plugged && 407 priv->pre_accdet_status != priv->accdet_status) 408 mt6359_accdet_jack_report(priv); 409 } 410 411 static void mt6359_accdet_jd_work(struct work_struct *work) 412 { 413 int ret; 414 unsigned int value = 0; 415 416 struct mt6359_accdet *priv = 417 container_of(work, struct mt6359_accdet, jd_work); 418 419 guard(mutex)(&priv->res_lock); 420 if (priv->jd_sts == M_PLUG_IN) { 421 priv->jack_plugged = true; 422 423 /* set and clear initial bit every eint interrupt */ 424 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR, 425 ACCDET_SEQ_INIT_MASK_SFT, 426 BIT(ACCDET_SEQ_INIT_SFT)); 427 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR, 428 ACCDET_SEQ_INIT_MASK_SFT, 0); 429 ret = regmap_read_poll_timeout(priv->regmap, 430 ACCDET_SEQ_INIT_ADDR, 431 value, 432 (value & ACCDET_SEQ_INIT_MASK_SFT) == 0, 433 0, 434 1000); 435 if (ret) 436 dev_err(priv->dev, "%s(), ret %d\n", __func__, ret); 437 438 /* enable ACCDET unit */ 439 regmap_update_bits(priv->regmap, ACCDET_SW_EN_ADDR, 440 ACCDET_SW_EN_MASK_SFT, BIT(ACCDET_SW_EN_SFT)); 441 } else if (priv->jd_sts == M_PLUG_OUT) { 442 priv->jack_plugged = false; 443 444 accdet_set_debounce(priv, accdet_state011, 445 priv->data->pwm_deb->debounce3); 446 regmap_update_bits(priv->regmap, ACCDET_SW_EN_ADDR, 447 ACCDET_SW_EN_MASK_SFT, 0); 448 mt6359_accdet_recover_jd_setting(priv); 449 } 450 451 if (priv->caps & ACCDET_PMIC_EINT_IRQ) 452 recover_eint_setting(priv); 453 } 454 455 static irqreturn_t mt6359_accdet_irq(int irq, void *data) 456 { 457 struct mt6359_accdet *priv = data; 458 unsigned int irq_val = 0, val = 0, value = 0; 459 int ret; 460 461 guard(mutex)(&priv->res_lock); 462 regmap_read(priv->regmap, ACCDET_IRQ_ADDR, &irq_val); 463 464 if (irq_val & ACCDET_IRQ_MASK_SFT) { 465 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 466 ACCDET_IRQ_CLR_MASK_SFT, 467 BIT(ACCDET_IRQ_CLR_SFT)); 468 ret = regmap_read_poll_timeout(priv->regmap, 469 ACCDET_IRQ_ADDR, 470 value, 471 (value & ACCDET_IRQ_MASK_SFT) == 0, 472 0, 473 1000); 474 if (ret) { 475 dev_err(priv->dev, "%s(), ret %d\n", __func__, ret); 476 return IRQ_NONE; 477 } 478 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 479 ACCDET_IRQ_CLR_MASK_SFT, 0); 480 regmap_update_bits(priv->regmap, RG_INT_STATUS_ACCDET_ADDR, 481 RG_INT_STATUS_ACCDET_MASK_SFT, 482 BIT(RG_INT_STATUS_ACCDET_SFT)); 483 484 queue_work(priv->accdet_workqueue, &priv->accdet_work); 485 } else { 486 if (irq_val & ACCDET_EINT0_IRQ_MASK_SFT) { 487 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 488 ACCDET_EINT0_IRQ_CLR_MASK_SFT, 489 BIT(ACCDET_EINT0_IRQ_CLR_SFT)); 490 ret = regmap_read_poll_timeout(priv->regmap, 491 ACCDET_IRQ_ADDR, 492 value, 493 (value & ACCDET_EINT0_IRQ_MASK_SFT) == 0, 494 0, 495 1000); 496 if (ret) { 497 dev_err(priv->dev, "%s(), ret %d\n", __func__, 498 ret); 499 return IRQ_NONE; 500 } 501 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 502 ACCDET_EINT0_IRQ_CLR_MASK_SFT, 0); 503 regmap_update_bits(priv->regmap, 504 RG_INT_STATUS_ACCDET_ADDR, 505 RG_INT_STATUS_ACCDET_EINT0_MASK_SFT, 506 BIT(RG_INT_STATUS_ACCDET_EINT0_SFT)); 507 } 508 if (irq_val & ACCDET_EINT1_IRQ_MASK_SFT) { 509 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 510 ACCDET_EINT1_IRQ_CLR_MASK_SFT, 511 BIT(ACCDET_EINT1_IRQ_CLR_SFT)); 512 ret = regmap_read_poll_timeout(priv->regmap, 513 ACCDET_IRQ_ADDR, 514 value, 515 (value & ACCDET_EINT1_IRQ_MASK_SFT) == 0, 516 0, 517 1000); 518 if (ret) { 519 dev_err(priv->dev, "%s(), ret %d\n", __func__, 520 ret); 521 return IRQ_NONE; 522 } 523 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR, 524 ACCDET_EINT1_IRQ_CLR_MASK_SFT, 0); 525 regmap_update_bits(priv->regmap, 526 RG_INT_STATUS_ACCDET_ADDR, 527 RG_INT_STATUS_ACCDET_EINT1_MASK_SFT, 528 BIT(RG_INT_STATUS_ACCDET_EINT1_SFT)); 529 } 530 /* get jack detection status */ 531 regmap_read(priv->regmap, ACCDET_EINT0_MEM_IN_ADDR, &val); 532 priv->jd_sts = ((val >> ACCDET_EINT0_MEM_IN_SFT) & 533 ACCDET_EINT0_MEM_IN_MASK); 534 /* adjust eint digital/analog setting */ 535 mt6359_accdet_jd_setting(priv); 536 537 queue_work(priv->jd_workqueue, &priv->jd_work); 538 } 539 540 return IRQ_HANDLED; 541 } 542 543 static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv) 544 { 545 int ret; 546 struct device *dev = priv->dev; 547 struct device_node *node = NULL; 548 int pwm_deb[15] = {0}; 549 unsigned int tmp = 0; 550 551 node = of_get_child_by_name(dev->parent->of_node, "accdet"); 552 if (!node) 553 return -EINVAL; 554 555 ret = of_property_read_u32(node, "mediatek,mic-vol", 556 &priv->data->mic_vol); 557 if (ret) 558 priv->data->mic_vol = 8; 559 560 ret = of_property_read_u32(node, "mediatek,plugout-debounce", 561 &priv->data->plugout_deb); 562 if (ret) 563 priv->data->plugout_deb = 1; 564 565 ret = of_property_read_u32(node, "mediatek,mic-mode", 566 &priv->data->mic_mode); 567 if (ret) 568 priv->data->mic_mode = 2; 569 570 ret = of_property_read_u32_array(node, "mediatek,pwm-deb-setting", 571 pwm_deb, ARRAY_SIZE(pwm_deb)); 572 /* debounce8(auxadc debounce) is default, needn't get from dts */ 573 if (!ret) 574 memcpy(priv->data->pwm_deb, pwm_deb, sizeof(pwm_deb)); 575 576 ret = of_property_read_u32(node, "mediatek,eint-level-pol", 577 &priv->data->eint_pol); 578 if (ret) 579 priv->data->eint_pol = 8; 580 581 ret = of_property_read_u32(node, "mediatek,eint-use-ap", &tmp); 582 if (ret) 583 tmp = 0; 584 if (tmp == 0) 585 priv->caps |= ACCDET_PMIC_EINT_IRQ; 586 else if (tmp == 1) 587 priv->caps |= ACCDET_AP_GPIO_EINT; 588 589 ret = of_property_read_u32(node, "mediatek,eint-detect-mode", 590 &priv->data->eint_detect_mode); 591 if (ret) { 592 /* eint detection mode equals to EINT HW Mode */ 593 priv->data->eint_detect_mode = 0x4; 594 } 595 596 ret = of_property_read_u32(node, "mediatek,eint-num", &tmp); 597 if (ret) 598 tmp = 0; 599 if (tmp == 0) 600 priv->caps |= ACCDET_PMIC_EINT0; 601 else if (tmp == 1) 602 priv->caps |= ACCDET_PMIC_EINT1; 603 else if (tmp == 2) 604 priv->caps |= ACCDET_PMIC_BI_EINT; 605 606 ret = of_property_read_u32(node, "mediatek,eint-trig-mode", 607 &tmp); 608 if (ret) 609 tmp = 0; 610 if (tmp == 0) 611 priv->caps |= ACCDET_PMIC_GPIO_TRIG_EINT; 612 else if (tmp == 1) 613 priv->caps |= ACCDET_PMIC_INVERTER_TRIG_EINT; 614 615 ret = of_property_read_u32(node, "mediatek,eint-use-ext-res", 616 &priv->data->eint_use_ext_res); 617 if (ret) { 618 /* eint use internal resister */ 619 priv->data->eint_use_ext_res = 0x0; 620 } 621 622 ret = of_property_read_u32(node, "mediatek,eint-comp-vth", 623 &priv->data->eint_comp_vth); 624 if (ret) 625 priv->data->eint_comp_vth = 0x0; 626 627 ret = of_property_read_u32(node, "mediatek,key-mode", &tmp); 628 if (ret) 629 tmp = 0; 630 if (tmp == 0) { 631 int three_key[4]; 632 633 priv->caps |= ACCDET_THREE_KEY; 634 ret = of_property_read_u32_array(node, 635 "mediatek,three-key-thr", 636 three_key, 637 ARRAY_SIZE(three_key)); 638 if (!ret) 639 memcpy(&priv->data->three_key, three_key + 1, 640 sizeof(struct three_key_threshold)); 641 } else if (tmp == 1) { 642 int four_key[5]; 643 644 priv->caps |= ACCDET_FOUR_KEY; 645 ret = of_property_read_u32_array(node, 646 "mediatek,four-key-thr", 647 four_key, 648 ARRAY_SIZE(four_key)); 649 if (!ret) { 650 memcpy(&priv->data->four_key, four_key + 1, 651 sizeof(struct four_key_threshold)); 652 } else { 653 dev_warn(priv->dev, 654 "accdet no 4-key-thrsh dts, use efuse\n"); 655 } 656 } else if (tmp == 2) { 657 int three_key[4]; 658 659 priv->caps |= ACCDET_TRI_KEY_CDD; 660 ret = of_property_read_u32_array(node, 661 "mediatek,tri-key-cdd-thr", 662 three_key, 663 ARRAY_SIZE(three_key)); 664 if (!ret) 665 memcpy(&priv->data->three_key, three_key + 1, 666 sizeof(struct three_key_threshold)); 667 } 668 669 of_node_put(node); 670 dev_warn(priv->dev, "accdet caps=%x\n", priv->caps); 671 672 return 0; 673 } 674 675 static void config_digital_init_by_mode(struct mt6359_accdet *priv) 676 { 677 /* enable eint cmpmem pwm */ 678 regmap_write(priv->regmap, ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR, 679 (priv->data->pwm_deb->eint_pwm_width << 4 | 680 priv->data->pwm_deb->eint_pwm_thresh)); 681 /* DA signal stable */ 682 if (priv->caps & ACCDET_PMIC_EINT0) { 683 regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR, 684 ACCDET_EINT0_STABLE_VAL); 685 } else if (priv->caps & ACCDET_PMIC_EINT1) { 686 regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR, 687 ACCDET_EINT1_STABLE_VAL); 688 } 689 /* after receive n+1 number, interrupt issued. */ 690 regmap_update_bits(priv->regmap, ACCDET_EINT_M_PLUG_IN_NUM_ADDR, 691 ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT, 692 BIT(ACCDET_EINT_M_PLUG_IN_NUM_SFT)); 693 /* setting HW mode, enable digital fast discharge 694 * if use EINT0 & EINT1 detection, please modify 695 * ACCDET_HWMODE_EN_ADDR[2:1] 696 */ 697 regmap_write(priv->regmap, ACCDET_HWMODE_EN_ADDR, 0x100); 698 699 regmap_update_bits(priv->regmap, ACCDET_EINT_M_DETECT_EN_ADDR, 700 ACCDET_EINT_M_DETECT_EN_MASK_SFT, 0); 701 702 /* enable PWM */ 703 regmap_write(priv->regmap, ACCDET_CMP_PWM_EN_ADDR, 0x67); 704 /* enable inverter detection */ 705 if (priv->data->eint_detect_mode == 0x1) { 706 /* disable inverter detection */ 707 if (priv->caps & ACCDET_PMIC_EINT0) { 708 regmap_update_bits(priv->regmap, 709 ACCDET_EINT0_INVERTER_SW_EN_ADDR, 710 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 711 0); 712 } else if (priv->caps & ACCDET_PMIC_EINT1) { 713 regmap_update_bits(priv->regmap, 714 ACCDET_EINT1_INVERTER_SW_EN_ADDR, 715 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 716 0); 717 } 718 } else { 719 if (priv->caps & ACCDET_PMIC_EINT0) { 720 regmap_update_bits(priv->regmap, 721 ACCDET_EINT0_INVERTER_SW_EN_ADDR, 722 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 723 BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); 724 } else if (priv->caps & ACCDET_PMIC_EINT1) { 725 regmap_update_bits(priv->regmap, 726 ACCDET_EINT1_INVERTER_SW_EN_ADDR, 727 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 728 BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); 729 } 730 } 731 } 732 733 static void config_eint_init_by_mode(struct mt6359_accdet *priv) 734 { 735 unsigned int val = 0; 736 737 if (priv->caps & ACCDET_PMIC_EINT0) { 738 regmap_update_bits(priv->regmap, RG_EINT0EN_ADDR, 739 RG_EINT0EN_MASK_SFT, BIT(RG_EINT0EN_SFT)); 740 } else if (priv->caps & ACCDET_PMIC_EINT1) { 741 regmap_update_bits(priv->regmap, RG_EINT1EN_ADDR, 742 RG_EINT1EN_MASK_SFT, BIT(RG_EINT1EN_SFT)); 743 } 744 /* ESD switches on */ 745 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, 746 1 << 8, 1 << 8); 747 /* before playback, set NCP pull low before nagative voltage */ 748 regmap_update_bits(priv->regmap, RG_NCP_PDDIS_EN_ADDR, 749 RG_NCP_PDDIS_EN_MASK_SFT, BIT(RG_NCP_PDDIS_EN_SFT)); 750 751 if (priv->data->eint_detect_mode == 0x1 || 752 priv->data->eint_detect_mode == 0x2 || 753 priv->data->eint_detect_mode == 0x3) { 754 if (priv->data->eint_use_ext_res == 0x1) { 755 if (priv->caps & ACCDET_PMIC_EINT0) { 756 regmap_update_bits(priv->regmap, 757 RG_EINT0CONFIGACCDET_ADDR, 758 RG_EINT0CONFIGACCDET_MASK_SFT, 759 0); 760 } else if (priv->caps & ACCDET_PMIC_EINT1) { 761 regmap_update_bits(priv->regmap, 762 RG_EINT1CONFIGACCDET_ADDR, 763 RG_EINT1CONFIGACCDET_MASK_SFT, 764 0); 765 } 766 } else { 767 if (priv->caps & ACCDET_PMIC_EINT0) { 768 regmap_update_bits(priv->regmap, 769 RG_EINT0CONFIGACCDET_ADDR, 770 RG_EINT0CONFIGACCDET_MASK_SFT, 771 BIT(RG_EINT0CONFIGACCDET_SFT)); 772 } else if (priv->caps & ACCDET_PMIC_EINT1) { 773 regmap_update_bits(priv->regmap, 774 RG_EINT1CONFIGACCDET_ADDR, 775 RG_EINT1CONFIGACCDET_MASK_SFT, 776 BIT(RG_EINT1CONFIGACCDET_SFT)); 777 } 778 } 779 } 780 781 if (priv->data->eint_detect_mode != 0x1) { 782 /* current detect set 0.25uA */ 783 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, 784 0x3 << RG_ACCDETSPARE_SFT, 785 0x3 << RG_ACCDETSPARE_SFT); 786 } 787 regmap_write(priv->regmap, RG_EINTCOMPVTH_ADDR, 788 val | priv->data->eint_comp_vth << RG_EINTCOMPVTH_SFT); 789 } 790 791 static void mt6359_accdet_init(struct mt6359_accdet *priv) 792 { 793 unsigned int reg = 0; 794 795 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR, 796 ACCDET_SEQ_INIT_MASK_SFT, BIT(ACCDET_SEQ_INIT_SFT)); 797 mdelay(2); 798 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR, 799 ACCDET_SEQ_INIT_MASK_SFT, 0); 800 mdelay(1); 801 /* init the debounce time (debounce/32768)sec */ 802 accdet_set_debounce(priv, accdet_state000, 803 priv->data->pwm_deb->debounce0); 804 accdet_set_debounce(priv, accdet_state001, 805 priv->data->pwm_deb->debounce1); 806 accdet_set_debounce(priv, accdet_state011, 807 priv->data->pwm_deb->debounce3); 808 accdet_set_debounce(priv, accdet_auxadc, 809 priv->data->pwm_deb->debounce4); 810 811 accdet_set_debounce(priv, eint_state000, 812 priv->data->pwm_deb->eint_debounce0); 813 accdet_set_debounce(priv, eint_state001, 814 priv->data->pwm_deb->eint_debounce1); 815 accdet_set_debounce(priv, eint_state011, 816 priv->data->pwm_deb->eint_debounce3); 817 accdet_set_debounce(priv, eint_inverter_state000, 818 priv->data->pwm_deb->eint_inverter_debounce); 819 820 regmap_update_bits(priv->regmap, RG_ACCDET_RST_ADDR, 821 RG_ACCDET_RST_MASK_SFT, BIT(RG_ACCDET_RST_SFT)); 822 regmap_update_bits(priv->regmap, RG_ACCDET_RST_ADDR, 823 RG_ACCDET_RST_MASK_SFT, 0); 824 825 /* clear high micbias1 voltage setting */ 826 regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, 827 0x3 << RG_AUDMICBIAS1HVEN_SFT, 0); 828 regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, 829 0x7 << RG_AUDMICBIAS1VREF_SFT, 0); 830 831 /* init pwm frequency, duty & rise/falling delay */ 832 regmap_write(priv->regmap, ACCDET_PWM_WIDTH_ADDR, 833 REGISTER_VAL(priv->data->pwm_deb->pwm_width)); 834 regmap_write(priv->regmap, ACCDET_PWM_THRESH_ADDR, 835 REGISTER_VAL(priv->data->pwm_deb->pwm_thresh)); 836 regmap_write(priv->regmap, ACCDET_RISE_DELAY_ADDR, 837 (priv->data->pwm_deb->fall_delay << 15 | 838 priv->data->pwm_deb->rise_delay)); 839 840 regmap_read(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, ®); 841 if (priv->data->mic_vol <= 7) { 842 /* micbias1 <= 2.7V */ 843 regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, 844 reg | (priv->data->mic_vol << RG_AUDMICBIAS1VREF_SFT) | 845 RG_AUDMICBIAS1LOWPEN_MASK_SFT); 846 } else if (priv->data->mic_vol == 8) { 847 /* micbias1 = 2.8v */ 848 regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, 849 reg | (3 << RG_AUDMICBIAS1HVEN_SFT) | 850 RG_AUDMICBIAS1LOWPEN_MASK_SFT); 851 } else if (priv->data->mic_vol == 9) { 852 /* micbias1 = 2.85v */ 853 regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, 854 reg | (1 << RG_AUDMICBIAS1HVEN_SFT) | 855 RG_AUDMICBIAS1LOWPEN_MASK_SFT); 856 } 857 /* mic mode setting */ 858 regmap_read(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, ®); 859 if (priv->data->mic_mode == HEADSET_MODE_1) { 860 /* ACC mode*/ 861 regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, 862 reg | RG_ACCDET_MODE_ANA11_MODE1); 863 /* enable analog fast discharge */ 864 regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR, 865 RG_ANALOGFDEN_MASK_SFT, 866 BIT(RG_ANALOGFDEN_SFT)); 867 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, 868 0x3 << 11, 0x3 << 11); 869 } else if (priv->data->mic_mode == HEADSET_MODE_2) { 870 /* DCC mode Low cost mode without internal bias */ 871 regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, 872 reg | RG_ACCDET_MODE_ANA11_MODE2); 873 /* enable analog fast discharge */ 874 regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR, 875 0x3 << RG_ANALOGFDEN_SFT, 876 0x3 << RG_ANALOGFDEN_SFT); 877 } else if (priv->data->mic_mode == HEADSET_MODE_6) { 878 /* DCC mode Low cost mode with internal bias, 879 * bit8 = 1 to use internal bias 880 */ 881 regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, 882 reg | RG_ACCDET_MODE_ANA11_MODE6); 883 regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, 884 RG_AUDMICBIAS1DCSW1PEN_MASK_SFT, 885 BIT(RG_AUDMICBIAS1DCSW1PEN_SFT)); 886 /* enable analog fast discharge */ 887 regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR, 888 0x3 << RG_ANALOGFDEN_SFT, 889 0x3 << RG_ANALOGFDEN_SFT); 890 } 891 892 if (priv->caps & ACCDET_PMIC_EINT_IRQ) { 893 config_eint_init_by_mode(priv); 894 config_digital_init_by_mode(priv); 895 } 896 } 897 898 int mt6359_accdet_enable_jack_detect(struct snd_soc_component *component, 899 struct snd_soc_jack *jack) 900 { 901 struct mt6359_accdet *priv = 902 snd_soc_component_get_drvdata(component); 903 904 snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE); 905 snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEDOWN); 906 snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP); 907 snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOICECOMMAND); 908 909 priv->jack = jack; 910 911 mt6359_accdet_jack_report(priv); 912 913 return 0; 914 } 915 EXPORT_SYMBOL_GPL(mt6359_accdet_enable_jack_detect); 916 917 static int mt6359_accdet_probe(struct platform_device *pdev) 918 { 919 struct mt6359_accdet *priv; 920 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); 921 int ret; 922 923 dev_dbg(&pdev->dev, "%s(), dev name %s\n", 924 __func__, dev_name(&pdev->dev)); 925 926 priv = devm_kzalloc(&pdev->dev, sizeof(struct mt6359_accdet), 927 GFP_KERNEL); 928 if (!priv) 929 return -ENOMEM; 930 931 priv->data = devm_kzalloc(&pdev->dev, sizeof(struct dts_data), 932 GFP_KERNEL); 933 if (!priv->data) 934 return -ENOMEM; 935 936 priv->data->pwm_deb = devm_kzalloc(&pdev->dev, 937 sizeof(struct pwm_deb_settings), 938 GFP_KERNEL); 939 if (!priv->data->pwm_deb) 940 return -ENOMEM; 941 942 priv->regmap = mt6397->regmap; 943 if (IS_ERR(priv->regmap)) { 944 ret = PTR_ERR(priv->regmap); 945 dev_err(&pdev->dev, "Failed to allocate register map: %d\n", 946 ret); 947 return ret; 948 } 949 priv->dev = &pdev->dev; 950 951 ret = mt6359_accdet_parse_dt(priv); 952 if (ret) { 953 dev_err(&pdev->dev, "Failed to parse dts\n"); 954 return ret; 955 } 956 mutex_init(&priv->res_lock); 957 958 priv->accdet_irq = platform_get_irq(pdev, 0); 959 if (priv->accdet_irq >= 0) { 960 ret = devm_request_threaded_irq(&pdev->dev, priv->accdet_irq, 961 NULL, mt6359_accdet_irq, 962 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 963 "ACCDET_IRQ", priv); 964 if (ret) { 965 dev_err(&pdev->dev, 966 "Failed to request IRQ: (%d)\n", ret); 967 return ret; 968 } 969 } 970 971 if (priv->caps & ACCDET_PMIC_EINT0) { 972 priv->accdet_eint0 = platform_get_irq(pdev, 1); 973 if (priv->accdet_eint0 >= 0) { 974 ret = devm_request_threaded_irq(&pdev->dev, 975 priv->accdet_eint0, 976 NULL, mt6359_accdet_irq, 977 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 978 "ACCDET_EINT0", priv); 979 if (ret) { 980 dev_err(&pdev->dev, 981 "Failed to request eint0 IRQ (%d)\n", 982 ret); 983 return ret; 984 } 985 } 986 } else if (priv->caps & ACCDET_PMIC_EINT1) { 987 priv->accdet_eint1 = platform_get_irq(pdev, 2); 988 if (priv->accdet_eint1 >= 0) { 989 ret = devm_request_threaded_irq(&pdev->dev, 990 priv->accdet_eint1, 991 NULL, mt6359_accdet_irq, 992 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 993 "ACCDET_EINT1", priv); 994 if (ret) { 995 dev_err(&pdev->dev, 996 "Failed to request eint1 IRQ (%d)\n", 997 ret); 998 return ret; 999 } 1000 } 1001 } 1002 1003 priv->accdet_workqueue = create_singlethread_workqueue("accdet"); 1004 INIT_WORK(&priv->accdet_work, mt6359_accdet_work); 1005 if (!priv->accdet_workqueue) { 1006 dev_err(&pdev->dev, "Failed to create accdet workqueue\n"); 1007 ret = -1; 1008 goto err_accdet_wq; 1009 } 1010 1011 priv->jd_workqueue = create_singlethread_workqueue("mt6359_accdet_jd"); 1012 INIT_WORK(&priv->jd_work, mt6359_accdet_jd_work); 1013 if (!priv->jd_workqueue) { 1014 dev_err(&pdev->dev, "Failed to create jack detect workqueue\n"); 1015 ret = -1; 1016 goto err_eint_wq; 1017 } 1018 1019 platform_set_drvdata(pdev, priv); 1020 ret = devm_snd_soc_register_component(&pdev->dev, 1021 &mt6359_accdet_soc_driver, 1022 NULL, 0); 1023 if (ret) { 1024 dev_err(&pdev->dev, "Failed to register component\n"); 1025 return ret; 1026 } 1027 1028 priv->jd_sts = M_PLUG_OUT; 1029 priv->jack_type = 0; 1030 priv->btn_type = 0; 1031 priv->accdet_status = 0x3; 1032 mt6359_accdet_init(priv); 1033 1034 mt6359_accdet_jack_report(priv); 1035 1036 return 0; 1037 1038 err_eint_wq: 1039 destroy_workqueue(priv->accdet_workqueue); 1040 err_accdet_wq: 1041 dev_err(&pdev->dev, "%s error. now exit.!\n", __func__); 1042 return ret; 1043 } 1044 1045 static struct platform_driver mt6359_accdet_driver = { 1046 .driver = { 1047 .name = "pmic-codec-accdet", 1048 }, 1049 .probe = mt6359_accdet_probe, 1050 }; 1051 1052 module_platform_driver(mt6359_accdet_driver) 1053 1054 /* Module information */ 1055 MODULE_DESCRIPTION("MT6359 ALSA SoC codec jack driver"); 1056 MODULE_AUTHOR("Argus Lin <argus.lin@mediatek.com>"); 1057 MODULE_LICENSE("GPL v2"); 1058