1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 CGX driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/phy.h>
16 #include <linux/of.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
19
20 #include "cgx.h"
21 #include "rvu.h"
22 #include "lmac_common.h"
23
24 #define DRV_NAME "Marvell-CGX-RPM"
25
26 #define CGX_RX_STAT_GLOBAL_INDEX 9
27
28 static LIST_HEAD(cgx_list);
29
30 /* Convert firmware speed encoding to user format(Mbps) */
31 static const u32 cgx_speed_mbps[CGX_LINK_SPEED_MAX] = {
32 [CGX_LINK_NONE] = 0,
33 [CGX_LINK_10M] = 10,
34 [CGX_LINK_100M] = 100,
35 [CGX_LINK_1G] = 1000,
36 [CGX_LINK_2HG] = 2500,
37 [CGX_LINK_5G] = 5000,
38 [CGX_LINK_10G] = 10000,
39 [CGX_LINK_20G] = 20000,
40 [CGX_LINK_25G] = 25000,
41 [CGX_LINK_40G] = 40000,
42 [CGX_LINK_50G] = 50000,
43 [CGX_LINK_80G] = 80000,
44 [CGX_LINK_100G] = 100000,
45 };
46
47 /* Convert firmware lmac type encoding to string */
48 static const char *cgx_lmactype_string[LMAC_MODE_MAX] = {
49 [LMAC_MODE_SGMII] = "SGMII",
50 [LMAC_MODE_XAUI] = "XAUI",
51 [LMAC_MODE_RXAUI] = "RXAUI",
52 [LMAC_MODE_10G_R] = "10G_R",
53 [LMAC_MODE_40G_R] = "40G_R",
54 [LMAC_MODE_QSGMII] = "QSGMII",
55 [LMAC_MODE_25G_R] = "25G_R",
56 [LMAC_MODE_50G_R] = "50G_R",
57 [LMAC_MODE_100G_R] = "100G_R",
58 [LMAC_MODE_USXGMII] = "USXGMII",
59 [LMAC_MODE_USGMII] = "USGMII",
60 };
61
62 /* CGX PHY management internal APIs */
63 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en);
64
65 /* Supported devices */
66 static const struct pci_device_id cgx_id_table[] = {
67 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) },
68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM,
69 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN10K_A) },
70 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM,
71 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF10K_A) },
72 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM,
73 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF10K_B) },
74 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM,
75 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN10K_B) },
76 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM,
77 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN20KA) },
78 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM,
79 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF20KA) },
80 { 0, } /* end of table */
81 };
82
83 MODULE_DEVICE_TABLE(pci, cgx_id_table);
84
is_dev_rpm(void * cgxd)85 static bool is_dev_rpm(void *cgxd)
86 {
87 struct cgx *cgx = cgxd;
88
89 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM) ||
90 (cgx->pdev->device == PCI_DEVID_CN10KB_RPM);
91 }
92
is_lmac_valid(struct cgx * cgx,int lmac_id)93 bool is_lmac_valid(struct cgx *cgx, int lmac_id)
94 {
95 if (!cgx || lmac_id < 0 || lmac_id >= cgx->max_lmac_per_mac)
96 return false;
97 return test_bit(lmac_id, &cgx->lmac_bmap);
98 }
99
100 /* Helper function to get sequential index
101 * given the enabled LMAC of a CGX
102 */
get_sequence_id_of_lmac(struct cgx * cgx,int lmac_id)103 static int get_sequence_id_of_lmac(struct cgx *cgx, int lmac_id)
104 {
105 int tmp, id = 0;
106
107 for_each_set_bit(tmp, &cgx->lmac_bmap, cgx->max_lmac_per_mac) {
108 if (tmp == lmac_id)
109 break;
110 id++;
111 }
112
113 return id;
114 }
115
get_mac_ops(void * cgxd)116 struct mac_ops *get_mac_ops(void *cgxd)
117 {
118 if (!cgxd)
119 return cgxd;
120
121 return ((struct cgx *)cgxd)->mac_ops;
122 }
123
cgx_get_fifo_len(void * cgxd)124 u32 cgx_get_fifo_len(void *cgxd)
125 {
126 return ((struct cgx *)cgxd)->fifo_len;
127 }
128
cgx_write(struct cgx * cgx,u64 lmac,u64 offset,u64 val)129 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val)
130 {
131 writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +
132 offset);
133 }
134
cgx_read(struct cgx * cgx,u64 lmac,u64 offset)135 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset)
136 {
137 return readq(cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +
138 offset);
139 }
140
lmac_pdata(u8 lmac_id,struct cgx * cgx)141 struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx)
142 {
143 if (!cgx || lmac_id >= cgx->max_lmac_per_mac)
144 return NULL;
145
146 return cgx->lmac_idmap[lmac_id];
147 }
148
cgx_get_cgxcnt_max(void)149 int cgx_get_cgxcnt_max(void)
150 {
151 struct cgx *cgx_dev;
152 int idmax = -ENODEV;
153
154 list_for_each_entry(cgx_dev, &cgx_list, cgx_list)
155 if (cgx_dev->cgx_id > idmax)
156 idmax = cgx_dev->cgx_id;
157
158 if (idmax < 0)
159 return 0;
160
161 return idmax + 1;
162 }
163
cgx_get_lmac_cnt(void * cgxd)164 int cgx_get_lmac_cnt(void *cgxd)
165 {
166 struct cgx *cgx = cgxd;
167
168 if (!cgx)
169 return -ENODEV;
170
171 return cgx->lmac_count;
172 }
173
cgx_get_pdata(int cgx_id)174 void *cgx_get_pdata(int cgx_id)
175 {
176 struct cgx *cgx_dev;
177
178 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) {
179 if (cgx_dev->cgx_id == cgx_id)
180 return cgx_dev;
181 }
182 return NULL;
183 }
184
cgx_lmac_write(int cgx_id,int lmac_id,u64 offset,u64 val)185 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val)
186 {
187 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
188
189 /* Software must not access disabled LMAC registers */
190 if (!is_lmac_valid(cgx_dev, lmac_id))
191 return;
192 cgx_write(cgx_dev, lmac_id, offset, val);
193 }
194
cgx_lmac_read(int cgx_id,int lmac_id,u64 offset)195 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset)
196 {
197 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
198
199 /* Software must not access disabled LMAC registers */
200 if (!is_lmac_valid(cgx_dev, lmac_id))
201 return 0;
202
203 return cgx_read(cgx_dev, lmac_id, offset);
204 }
205
cgx_get_cgxid(void * cgxd)206 int cgx_get_cgxid(void *cgxd)
207 {
208 struct cgx *cgx = cgxd;
209
210 if (!cgx)
211 return -EINVAL;
212
213 return cgx->cgx_id;
214 }
215
cgx_lmac_get_p2x(int cgx_id,int lmac_id)216 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id)
217 {
218 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
219 u64 cfg;
220
221 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG);
222
223 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT;
224 }
225
cgx_get_nix_resetbit(struct cgx * cgx)226 static u8 cgx_get_nix_resetbit(struct cgx *cgx)
227 {
228 int first_lmac;
229 u8 p2x;
230
231 /* non 98XX silicons supports only NIX0 block */
232 if (cgx->pdev->subsystem_device != PCI_SUBSYS_DEVID_98XX)
233 return CGX_NIX0_RESET;
234
235 first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac);
236 p2x = cgx_lmac_get_p2x(cgx->cgx_id, first_lmac);
237
238 if (p2x == CMR_P2X_SEL_NIX1)
239 return CGX_NIX1_RESET;
240 else
241 return CGX_NIX0_RESET;
242 }
243
244 /* Ensure the required lock for event queue(where asynchronous events are
245 * posted) is acquired before calling this API. Else an asynchronous event(with
246 * latest link status) can reach the destination before this function returns
247 * and could make the link status appear wrong.
248 */
cgx_get_link_info(void * cgxd,int lmac_id,struct cgx_link_user_info * linfo)249 int cgx_get_link_info(void *cgxd, int lmac_id,
250 struct cgx_link_user_info *linfo)
251 {
252 struct lmac *lmac = lmac_pdata(lmac_id, cgxd);
253
254 if (!lmac)
255 return -ENODEV;
256
257 *linfo = lmac->link_info;
258 return 0;
259 }
260
cgx_lmac_addr_set(u8 cgx_id,u8 lmac_id,u8 * mac_addr)261 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr)
262 {
263 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
264 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
265 struct mac_ops *mac_ops;
266 int index, id;
267 u64 cfg;
268
269 if (!lmac)
270 return -ENODEV;
271
272 /* access mac_ops to know csr_offset */
273 mac_ops = cgx_dev->mac_ops;
274
275 /* copy 6bytes from macaddr */
276 /* memcpy(&cfg, mac_addr, 6); */
277
278 cfg = ether_addr_to_u64(mac_addr);
279
280 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
281
282 index = id * lmac->mac_to_index_bmap.max;
283
284 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)),
285 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49));
286
287 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
288 cfg |= (CGX_DMAC_CTL0_CAM_ENABLE | CGX_DMAC_BCAST_MODE |
289 CGX_DMAC_MCAST_MODE);
290 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
291
292 return 0;
293 }
294
cgx_read_dmac_ctrl(void * cgxd,int lmac_id)295 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id)
296 {
297 struct mac_ops *mac_ops;
298 struct cgx *cgx = cgxd;
299
300 if (!cgxd || !is_lmac_valid(cgxd, lmac_id))
301 return 0;
302
303 cgx = cgxd;
304 /* Get mac_ops to know csr offset */
305 mac_ops = cgx->mac_ops;
306
307 return cgx_read(cgxd, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
308 }
309
cgx_read_dmac_entry(void * cgxd,int index)310 u64 cgx_read_dmac_entry(void *cgxd, int index)
311 {
312 struct mac_ops *mac_ops;
313 struct cgx *cgx;
314
315 if (!cgxd)
316 return 0;
317
318 cgx = cgxd;
319 mac_ops = cgx->mac_ops;
320 return cgx_read(cgx, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 8)));
321 }
322
cgx_lmac_addr_add(u8 cgx_id,u8 lmac_id,u8 * mac_addr)323 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr)
324 {
325 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
326 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
327 struct mac_ops *mac_ops;
328 int index, idx;
329 u64 cfg = 0;
330 int id;
331
332 if (!lmac)
333 return -ENODEV;
334
335 mac_ops = cgx_dev->mac_ops;
336 /* Get available index where entry is to be installed */
337 idx = rvu_alloc_rsrc(&lmac->mac_to_index_bmap);
338 if (idx < 0)
339 return idx;
340
341 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
342
343 index = id * lmac->mac_to_index_bmap.max + idx;
344
345 cfg = ether_addr_to_u64(mac_addr);
346 cfg |= CGX_DMAC_CAM_ADDR_ENABLE;
347 cfg |= ((u64)lmac_id << 49);
348 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
349
350 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
351 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_CAM_ACCEPT);
352
353 if (is_multicast_ether_addr(mac_addr)) {
354 cfg &= ~GENMASK_ULL(2, 1);
355 cfg |= CGX_DMAC_MCAST_MODE_CAM;
356 lmac->mcast_filters_count++;
357 } else if (!lmac->mcast_filters_count) {
358 cfg |= CGX_DMAC_MCAST_MODE;
359 }
360
361 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
362
363 return idx;
364 }
365
cgx_lmac_addr_reset(u8 cgx_id,u8 lmac_id)366 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id)
367 {
368 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
369 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
370 struct mac_ops *mac_ops;
371 u8 index = 0, id;
372 u64 cfg;
373
374 if (!lmac)
375 return -ENODEV;
376
377 mac_ops = cgx_dev->mac_ops;
378 /* Restore index 0 to its default init value as done during
379 * cgx_lmac_init
380 */
381 set_bit(0, lmac->mac_to_index_bmap.bmap);
382
383 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
384
385 index = id * lmac->mac_to_index_bmap.max + index;
386 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
387
388 /* Reset CGXX_CMRX_RX_DMAC_CTL0 register to default state */
389 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
390 cfg &= ~CGX_DMAC_CAM_ACCEPT;
391 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE);
392 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
393
394 return 0;
395 }
396
397 /* Allows caller to change macaddress associated with index
398 * in dmac filter table including index 0 reserved for
399 * interface mac address
400 */
cgx_lmac_addr_update(u8 cgx_id,u8 lmac_id,u8 * mac_addr,u8 index)401 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index)
402 {
403 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
404 struct mac_ops *mac_ops;
405 struct lmac *lmac;
406 u64 cfg;
407 int id;
408
409 lmac = lmac_pdata(lmac_id, cgx_dev);
410 if (!lmac)
411 return -ENODEV;
412
413 mac_ops = cgx_dev->mac_ops;
414 /* Validate the index */
415 if (index >= lmac->mac_to_index_bmap.max)
416 return -EINVAL;
417
418 /* ensure index is already set */
419 if (!test_bit(index, lmac->mac_to_index_bmap.bmap))
420 return -EINVAL;
421
422 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
423
424 index = id * lmac->mac_to_index_bmap.max + index;
425
426 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)));
427 cfg &= ~CGX_RX_DMAC_ADR_MASK;
428 cfg |= ether_addr_to_u64(mac_addr);
429
430 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
431 return 0;
432 }
433
cgx_lmac_addr_del(u8 cgx_id,u8 lmac_id,u8 index)434 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index)
435 {
436 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
437 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
438 struct mac_ops *mac_ops;
439 u8 mac[ETH_ALEN];
440 u64 cfg;
441 int id;
442
443 if (!lmac)
444 return -ENODEV;
445
446 mac_ops = cgx_dev->mac_ops;
447 /* Validate the index */
448 if (index >= lmac->mac_to_index_bmap.max)
449 return -EINVAL;
450
451 /* Skip deletion for reserved index i.e. index 0 */
452 if (index == 0)
453 return 0;
454
455 rvu_free_rsrc(&lmac->mac_to_index_bmap, index);
456
457 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
458
459 index = id * lmac->mac_to_index_bmap.max + index;
460
461 /* Read MAC address to check whether it is ucast or mcast */
462 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)));
463
464 u64_to_ether_addr(cfg, mac);
465 if (is_multicast_ether_addr(mac))
466 lmac->mcast_filters_count--;
467
468 if (!lmac->mcast_filters_count) {
469 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
470 cfg &= ~GENMASK_ULL(2, 1);
471 cfg |= CGX_DMAC_MCAST_MODE;
472 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
473 }
474
475 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
476
477 return 0;
478 }
479
cgx_lmac_addr_max_entries_get(u8 cgx_id,u8 lmac_id)480 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id)
481 {
482 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
483 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
484
485 if (lmac)
486 return lmac->mac_to_index_bmap.max;
487
488 return 0;
489 }
490
cgx_lmac_addr_get(u8 cgx_id,u8 lmac_id)491 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id)
492 {
493 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
494 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
495 struct mac_ops *mac_ops;
496 int index;
497 u64 cfg;
498 int id;
499
500 mac_ops = cgx_dev->mac_ops;
501
502 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
503
504 index = id * lmac->mac_to_index_bmap.max;
505
506 cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8);
507 return cfg & CGX_RX_DMAC_ADR_MASK;
508 }
509
cgx_set_pkind(void * cgxd,u8 lmac_id,int pkind)510 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind)
511 {
512 struct cgx *cgx = cgxd;
513
514 if (!is_lmac_valid(cgx, lmac_id))
515 return -ENODEV;
516
517 cgx_write(cgx, lmac_id, cgx->mac_ops->rxid_map_offset, (pkind & 0x3F));
518 return 0;
519 }
520
cgx_get_pkind(void * cgxd,u8 lmac_id,int * pkind)521 int cgx_get_pkind(void *cgxd, u8 lmac_id, int *pkind)
522 {
523 struct cgx *cgx = cgxd;
524
525 if (!is_lmac_valid(cgx, lmac_id))
526 return -ENODEV;
527
528 *pkind = cgx_read(cgx, lmac_id, cgx->mac_ops->rxid_map_offset);
529 *pkind = *pkind & 0x3F;
530 return 0;
531 }
532
cgx_get_lmac_type(void * cgxd,int lmac_id)533 static u8 cgx_get_lmac_type(void *cgxd, int lmac_id)
534 {
535 struct cgx *cgx = cgxd;
536 u64 cfg;
537
538 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
539 return (cfg >> CGX_LMAC_TYPE_SHIFT) & CGX_LMAC_TYPE_MASK;
540 }
541
cgx_get_lmac_fifo_len(void * cgxd,int lmac_id)542 static u32 cgx_get_lmac_fifo_len(void *cgxd, int lmac_id)
543 {
544 struct cgx *cgx = cgxd;
545 u8 num_lmacs;
546 u32 fifo_len;
547
548 fifo_len = cgx->fifo_len;
549 num_lmacs = cgx->mac_ops->get_nr_lmacs(cgx);
550
551 switch (num_lmacs) {
552 case 1:
553 return fifo_len;
554 case 2:
555 return fifo_len / 2;
556 case 3:
557 /* LMAC0 gets half of the FIFO, reset 1/4th */
558 if (lmac_id == 0)
559 return fifo_len / 2;
560 return fifo_len / 4;
561 case 4:
562 default:
563 return fifo_len / 4;
564 }
565 return 0;
566 }
567
568 /* Configure CGX LMAC in internal loopback mode */
cgx_lmac_internal_loopback(void * cgxd,int lmac_id,bool enable)569 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable)
570 {
571 struct cgx *cgx = cgxd;
572 struct lmac *lmac;
573 u64 cfg;
574
575 if (!is_lmac_valid(cgx, lmac_id))
576 return -ENODEV;
577
578 lmac = lmac_pdata(lmac_id, cgx);
579 if (lmac->lmac_type == LMAC_MODE_SGMII ||
580 lmac->lmac_type == LMAC_MODE_QSGMII) {
581 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL);
582 if (enable)
583 cfg |= CGXX_GMP_PCS_MRX_CTL_LBK;
584 else
585 cfg &= ~CGXX_GMP_PCS_MRX_CTL_LBK;
586 cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg);
587 } else {
588 cfg = cgx_read(cgx, lmac_id, CGXX_SPUX_CONTROL1);
589 if (enable)
590 cfg |= CGXX_SPUX_CONTROL1_LBK;
591 else
592 cfg &= ~CGXX_SPUX_CONTROL1_LBK;
593 cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg);
594 }
595 return 0;
596 }
597
cgx_lmac_promisc_config(int cgx_id,int lmac_id,bool enable)598 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable)
599 {
600 struct cgx *cgx = cgx_get_pdata(cgx_id);
601 struct lmac *lmac = lmac_pdata(lmac_id, cgx);
602 struct mac_ops *mac_ops;
603 u16 max_dmac;
604 int index, i;
605 u64 cfg = 0;
606 int id;
607
608 if (!cgx || !lmac)
609 return;
610
611 max_dmac = lmac->mac_to_index_bmap.max;
612 id = get_sequence_id_of_lmac(cgx, lmac_id);
613
614 mac_ops = cgx->mac_ops;
615 if (enable) {
616 /* Enable promiscuous mode on LMAC */
617 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
618 cfg &= ~CGX_DMAC_CAM_ACCEPT;
619 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE);
620 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
621
622 for (i = 0; i < max_dmac; i++) {
623 index = id * max_dmac + i;
624 cfg = cgx_read(cgx, 0,
625 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8));
626 cfg &= ~CGX_DMAC_CAM_ADDR_ENABLE;
627 cgx_write(cgx, 0,
628 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8), cfg);
629 }
630 } else {
631 /* Disable promiscuous mode */
632 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
633 cfg |= CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE;
634 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
635 for (i = 0; i < max_dmac; i++) {
636 index = id * max_dmac + i;
637 cfg = cgx_read(cgx, 0,
638 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8));
639 if ((cfg & CGX_RX_DMAC_ADR_MASK) != 0) {
640 cfg |= CGX_DMAC_CAM_ADDR_ENABLE;
641 cgx_write(cgx, 0,
642 (CGXX_CMRX_RX_DMAC_CAM0 +
643 index * 0x8),
644 cfg);
645 }
646 }
647 }
648 }
649
cgx_lmac_get_pause_frm_status(void * cgxd,int lmac_id,u8 * tx_pause,u8 * rx_pause)650 static int cgx_lmac_get_pause_frm_status(void *cgxd, int lmac_id,
651 u8 *tx_pause, u8 *rx_pause)
652 {
653 struct cgx *cgx = cgxd;
654 u64 cfg;
655
656 if (is_dev_rpm(cgx))
657 return 0;
658
659 if (!is_lmac_valid(cgx, lmac_id))
660 return -ENODEV;
661
662 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
663 *rx_pause = !!(cfg & CGX_SMUX_RX_FRM_CTL_CTL_BCK);
664
665 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
666 *tx_pause = !!(cfg & CGX_SMUX_TX_CTL_L2P_BP_CONV);
667 return 0;
668 }
669
670 /* Enable or disable forwarding received pause frames to Tx block */
cgx_lmac_enadis_rx_pause_fwding(void * cgxd,int lmac_id,bool enable)671 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable)
672 {
673 struct cgx *cgx = cgxd;
674 u8 rx_pause, tx_pause;
675 bool is_pfc_enabled;
676 struct lmac *lmac;
677 u64 cfg;
678
679 if (!cgx)
680 return;
681
682 lmac = lmac_pdata(lmac_id, cgx);
683 if (!lmac)
684 return;
685
686 /* Pause frames are not enabled just return */
687 if (!bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max))
688 return;
689
690 cgx_lmac_get_pause_frm_status(cgx, lmac_id, &rx_pause, &tx_pause);
691 is_pfc_enabled = rx_pause ? false : true;
692
693 if (enable) {
694 if (!is_pfc_enabled) {
695 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
696 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
697 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
698
699 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
700 cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK;
701 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
702 } else {
703 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
704 cfg |= CGXX_SMUX_CBFC_CTL_BCK_EN;
705 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
706 }
707 } else {
708
709 if (!is_pfc_enabled) {
710 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
711 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
712 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
713
714 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
715 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
716 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
717 } else {
718 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
719 cfg &= ~CGXX_SMUX_CBFC_CTL_BCK_EN;
720 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
721 }
722 }
723 }
724
cgx_get_rx_stats(void * cgxd,int lmac_id,int idx,u64 * rx_stat)725 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat)
726 {
727 struct cgx *cgx = cgxd;
728
729 if (!is_lmac_valid(cgx, lmac_id))
730 return -ENODEV;
731
732 /* pass lmac as 0 for CGX_CMR_RX_STAT9-12 */
733 if (idx >= CGX_RX_STAT_GLOBAL_INDEX)
734 lmac_id = 0;
735
736 *rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8));
737 return 0;
738 }
739
cgx_get_tx_stats(void * cgxd,int lmac_id,int idx,u64 * tx_stat)740 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat)
741 {
742 struct cgx *cgx = cgxd;
743
744 if (!is_lmac_valid(cgx, lmac_id))
745 return -ENODEV;
746 *tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8));
747 return 0;
748 }
749
cgx_features_get(void * cgxd)750 u64 cgx_features_get(void *cgxd)
751 {
752 return ((struct cgx *)cgxd)->hw_features;
753 }
754
cgx_stats_reset(void * cgxd,int lmac_id)755 int cgx_stats_reset(void *cgxd, int lmac_id)
756 {
757 struct cgx *cgx = cgxd;
758 int stat_id;
759
760 if (!is_lmac_valid(cgx, lmac_id))
761 return -ENODEV;
762
763 for (stat_id = 0 ; stat_id < CGX_RX_STATS_COUNT; stat_id++) {
764 if (stat_id >= CGX_RX_STAT_GLOBAL_INDEX)
765 /* pass lmac as 0 for CGX_CMR_RX_STAT9-12 */
766 cgx_write(cgx, 0,
767 (CGXX_CMRX_RX_STAT0 + (stat_id * 8)), 0);
768 else
769 cgx_write(cgx, lmac_id,
770 (CGXX_CMRX_RX_STAT0 + (stat_id * 8)), 0);
771 }
772
773 for (stat_id = 0 ; stat_id < CGX_TX_STATS_COUNT; stat_id++)
774 cgx_write(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (stat_id * 8), 0);
775
776 return 0;
777 }
778
cgx_set_fec_stats_count(struct cgx_link_user_info * linfo)779 static int cgx_set_fec_stats_count(struct cgx_link_user_info *linfo)
780 {
781 if (!linfo->fec)
782 return 0;
783
784 switch (linfo->lmac_type_id) {
785 case LMAC_MODE_SGMII:
786 case LMAC_MODE_XAUI:
787 case LMAC_MODE_RXAUI:
788 case LMAC_MODE_QSGMII:
789 return 0;
790 case LMAC_MODE_10G_R:
791 case LMAC_MODE_25G_R:
792 case LMAC_MODE_100G_R:
793 case LMAC_MODE_USXGMII:
794 return 1;
795 case LMAC_MODE_40G_R:
796 return 4;
797 case LMAC_MODE_50G_R:
798 if (linfo->fec == OTX2_FEC_BASER)
799 return 2;
800 else
801 return 1;
802 default:
803 return 0;
804 }
805 }
806
cgx_get_fec_stats(void * cgxd,int lmac_id,struct cgx_fec_stats_rsp * rsp)807 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp)
808 {
809 int stats, fec_stats_count = 0;
810 int corr_reg, uncorr_reg;
811 struct cgx *cgx = cgxd;
812
813 if (!is_lmac_valid(cgx, lmac_id))
814 return -ENODEV;
815
816 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_NONE)
817 return 0;
818
819 fec_stats_count =
820 cgx_set_fec_stats_count(&cgx->lmac_idmap[lmac_id]->link_info);
821 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) {
822 corr_reg = CGXX_SPUX_LNX_FEC_CORR_BLOCKS;
823 uncorr_reg = CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS;
824 } else {
825 corr_reg = CGXX_SPUX_RSFEC_CORR;
826 uncorr_reg = CGXX_SPUX_RSFEC_UNCORR;
827 }
828 for (stats = 0; stats < fec_stats_count; stats++) {
829 rsp->fec_corr_blks +=
830 cgx_read(cgx, lmac_id, corr_reg + (stats * 8));
831 rsp->fec_uncorr_blks +=
832 cgx_read(cgx, lmac_id, uncorr_reg + (stats * 8));
833 }
834 return 0;
835 }
836
cgx_lmac_rx_tx_enable(void * cgxd,int lmac_id,bool enable)837 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable)
838 {
839 struct cgx *cgx = cgxd;
840 u64 cfg;
841
842 if (!is_lmac_valid(cgx, lmac_id))
843 return -ENODEV;
844
845 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
846 if (enable)
847 cfg |= DATA_PKT_RX_EN | DATA_PKT_TX_EN;
848 else
849 cfg &= ~(DATA_PKT_RX_EN | DATA_PKT_TX_EN);
850 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
851 return 0;
852 }
853
cgx_lmac_tx_enable(void * cgxd,int lmac_id,bool enable)854 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable)
855 {
856 struct cgx *cgx = cgxd;
857 u64 cfg, last;
858
859 if (!is_lmac_valid(cgx, lmac_id))
860 return -ENODEV;
861
862 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
863 last = cfg;
864 if (enable)
865 cfg |= DATA_PKT_TX_EN;
866 else
867 cfg &= ~DATA_PKT_TX_EN;
868
869 if (cfg != last)
870 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
871 return !!(last & DATA_PKT_TX_EN);
872 }
873
cgx_lmac_enadis_pause_frm(void * cgxd,int lmac_id,u8 tx_pause,u8 rx_pause)874 static int cgx_lmac_enadis_pause_frm(void *cgxd, int lmac_id,
875 u8 tx_pause, u8 rx_pause)
876 {
877 struct cgx *cgx = cgxd;
878 u64 cfg;
879
880 if (is_dev_rpm(cgx))
881 return 0;
882
883 if (!is_lmac_valid(cgx, lmac_id))
884 return -ENODEV;
885
886 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
887 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
888 cfg |= rx_pause ? CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK : 0x0;
889 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
890
891 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
892 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
893 cfg |= rx_pause ? CGX_SMUX_RX_FRM_CTL_CTL_BCK : 0x0;
894 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
895
896 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
897 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV;
898 cfg |= tx_pause ? CGX_SMUX_TX_CTL_L2P_BP_CONV : 0x0;
899 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
900
901 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP);
902 if (tx_pause) {
903 cfg &= ~CGX_CMR_RX_OVR_BP_EN(lmac_id);
904 } else {
905 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id);
906 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id);
907 }
908 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg);
909 return 0;
910 }
911
cgx_lmac_pause_frm_config(void * cgxd,int lmac_id,bool enable)912 static void cgx_lmac_pause_frm_config(void *cgxd, int lmac_id, bool enable)
913 {
914 struct cgx *cgx = cgxd;
915 u64 cfg;
916
917 if (!is_lmac_valid(cgx, lmac_id))
918 return;
919
920 if (enable) {
921 /* Set pause time and interval */
922 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_TIME,
923 DEFAULT_PAUSE_TIME);
924 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL);
925 cfg &= ~0xFFFFULL;
926 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL,
927 cfg | (DEFAULT_PAUSE_TIME / 2));
928
929 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_TIME,
930 DEFAULT_PAUSE_TIME);
931
932 cfg = cgx_read(cgx, lmac_id,
933 CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL);
934 cfg &= ~0xFFFFULL;
935 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL,
936 cfg | (DEFAULT_PAUSE_TIME / 2));
937 }
938
939 /* ALL pause frames received are completely ignored */
940 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
941 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
942 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
943
944 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
945 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
946 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
947
948 /* Disable pause frames transmission */
949 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
950 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV;
951 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
952
953 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP);
954 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id);
955 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id);
956 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg);
957
958 /* Disable all PFC classes by default */
959 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
960 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg);
961 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
962 }
963
verify_lmac_fc_cfg(void * cgxd,int lmac_id,u8 tx_pause,u8 rx_pause,int pfvf_idx)964 int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
965 int pfvf_idx)
966 {
967 struct cgx *cgx = cgxd;
968 struct lmac *lmac;
969
970 lmac = lmac_pdata(lmac_id, cgx);
971 if (!lmac)
972 return -ENODEV;
973
974 if (!rx_pause)
975 clear_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap);
976 else
977 set_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap);
978
979 if (!tx_pause)
980 clear_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap);
981 else
982 set_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap);
983
984 /* check if other pfvfs are using flow control */
985 if (!rx_pause && bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) {
986 dev_warn(&cgx->pdev->dev,
987 "Receive Flow control disable not permitted as its used by other PFVFs\n");
988 return -EPERM;
989 }
990
991 if (!tx_pause && bitmap_weight(lmac->tx_fc_pfvf_bmap.bmap, lmac->tx_fc_pfvf_bmap.max)) {
992 dev_warn(&cgx->pdev->dev,
993 "Transmit Flow control disable not permitted as its used by other PFVFs\n");
994 return -EPERM;
995 }
996
997 return 0;
998 }
999
cgx_lmac_pfc_config(void * cgxd,int lmac_id,u8 tx_pause,u8 rx_pause,u16 pfc_en)1000 int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause,
1001 u8 rx_pause, u16 pfc_en)
1002 {
1003 struct cgx *cgx = cgxd;
1004 u64 cfg;
1005
1006 if (!is_lmac_valid(cgx, lmac_id))
1007 return -ENODEV;
1008
1009 /* Return as no traffic classes are requested */
1010 if (tx_pause && !pfc_en)
1011 return 0;
1012
1013 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
1014 pfc_en |= FIELD_GET(CGX_PFC_CLASS_MASK, cfg);
1015
1016 if (rx_pause) {
1017 cfg |= (CGXX_SMUX_CBFC_CTL_RX_EN |
1018 CGXX_SMUX_CBFC_CTL_BCK_EN |
1019 CGXX_SMUX_CBFC_CTL_DRP_EN);
1020 } else {
1021 cfg &= ~(CGXX_SMUX_CBFC_CTL_RX_EN |
1022 CGXX_SMUX_CBFC_CTL_BCK_EN |
1023 CGXX_SMUX_CBFC_CTL_DRP_EN);
1024 }
1025
1026 if (tx_pause) {
1027 cfg |= CGXX_SMUX_CBFC_CTL_TX_EN;
1028 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, pfc_en, cfg);
1029 } else {
1030 cfg &= ~CGXX_SMUX_CBFC_CTL_TX_EN;
1031 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg);
1032 }
1033
1034 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
1035
1036 /* Write source MAC address which will be filled into PFC packet */
1037 cfg = cgx_lmac_addr_get(cgx->cgx_id, lmac_id);
1038 cgx_write(cgx, lmac_id, CGXX_SMUX_SMAC, cfg);
1039
1040 return 0;
1041 }
1042
cgx_lmac_get_pfc_frm_cfg(void * cgxd,int lmac_id,u8 * tx_pause,u8 * rx_pause)1043 int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause,
1044 u8 *rx_pause)
1045 {
1046 struct cgx *cgx = cgxd;
1047 u64 cfg;
1048
1049 if (!is_lmac_valid(cgx, lmac_id))
1050 return -ENODEV;
1051
1052 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
1053
1054 *rx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_RX_EN);
1055 *tx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_TX_EN);
1056
1057 return 0;
1058 }
1059
cgx_lmac_ptp_config(void * cgxd,int lmac_id,bool enable)1060 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable)
1061 {
1062 struct cgx *cgx = cgxd;
1063 u64 cfg;
1064
1065 if (!cgx)
1066 return;
1067
1068 if (enable) {
1069 /* Enable inbound PTP timestamping */
1070 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
1071 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE;
1072 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
1073
1074 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
1075 cfg |= CGX_SMUX_RX_FRM_CTL_PTP_MODE;
1076 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
1077 } else {
1078 /* Disable inbound PTP stamping */
1079 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
1080 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE;
1081 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
1082
1083 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
1084 cfg &= ~CGX_SMUX_RX_FRM_CTL_PTP_MODE;
1085 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
1086 }
1087 }
1088
1089 /* CGX Firmware interface low level support */
cgx_fwi_cmd_send(u64 req,u64 * resp,struct lmac * lmac)1090 int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac)
1091 {
1092 struct cgx *cgx = lmac->cgx;
1093 struct device *dev;
1094 int err = 0;
1095 u64 cmd;
1096
1097 /* Ensure no other command is in progress */
1098 err = mutex_lock_interruptible(&lmac->cmd_lock);
1099 if (err)
1100 return err;
1101
1102 /* Ensure command register is free */
1103 cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG);
1104 if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) {
1105 err = -EBUSY;
1106 goto unlock;
1107 }
1108
1109 /* Update ownership in command request */
1110 req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req);
1111
1112 /* Mark this lmac as pending, before we start */
1113 lmac->cmd_pend = true;
1114
1115 /* Start command in hardware */
1116 cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req);
1117
1118 /* Ensure command is completed without errors */
1119 if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend,
1120 msecs_to_jiffies(CGX_CMD_TIMEOUT))) {
1121 dev = &cgx->pdev->dev;
1122 dev_err(dev, "cgx port %d:%d cmd %lld timeout\n",
1123 cgx->cgx_id, lmac->lmac_id, FIELD_GET(CMDREG_ID, req));
1124 err = LMAC_AF_ERR_CMD_TIMEOUT;
1125 goto unlock;
1126 }
1127
1128 /* we have a valid command response */
1129 smp_rmb(); /* Ensure the latest updates are visible */
1130 *resp = lmac->resp;
1131
1132 unlock:
1133 mutex_unlock(&lmac->cmd_lock);
1134
1135 return err;
1136 }
1137
cgx_fwi_cmd_generic(u64 req,u64 * resp,struct cgx * cgx,int lmac_id)1138 int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id)
1139 {
1140 struct lmac *lmac;
1141 int err;
1142
1143 lmac = lmac_pdata(lmac_id, cgx);
1144 if (!lmac)
1145 return -ENODEV;
1146
1147 err = cgx_fwi_cmd_send(req, resp, lmac);
1148
1149 /* Check for valid response */
1150 if (!err) {
1151 if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL)
1152 return -EIO;
1153 else
1154 return 0;
1155 }
1156
1157 return err;
1158 }
1159
cgx_link_usertable_index_map(int speed)1160 static int cgx_link_usertable_index_map(int speed)
1161 {
1162 switch (speed) {
1163 case SPEED_10:
1164 return CGX_LINK_10M;
1165 case SPEED_100:
1166 return CGX_LINK_100M;
1167 case SPEED_1000:
1168 return CGX_LINK_1G;
1169 case SPEED_2500:
1170 return CGX_LINK_2HG;
1171 case SPEED_5000:
1172 return CGX_LINK_5G;
1173 case SPEED_10000:
1174 return CGX_LINK_10G;
1175 case SPEED_20000:
1176 return CGX_LINK_20G;
1177 case SPEED_25000:
1178 return CGX_LINK_25G;
1179 case SPEED_40000:
1180 return CGX_LINK_40G;
1181 case SPEED_50000:
1182 return CGX_LINK_50G;
1183 case 80000:
1184 return CGX_LINK_80G;
1185 case SPEED_100000:
1186 return CGX_LINK_100G;
1187 case SPEED_UNKNOWN:
1188 return CGX_LINK_NONE;
1189 }
1190 return CGX_LINK_NONE;
1191 }
1192
set_mod_args(struct cgx_set_link_mode_args * args,u32 speed,u8 duplex,u8 autoneg,u64 mode)1193 static void set_mod_args(struct cgx_set_link_mode_args *args,
1194 u32 speed, u8 duplex, u8 autoneg, u64 mode)
1195 {
1196 int mode_baseidx;
1197 u8 cgx_mode;
1198
1199 if (args->multimode) {
1200 args->mode |= mode;
1201 return;
1202 }
1203
1204 /* Derive mode_base_idx and mode fields based
1205 * on cgx_mode value
1206 */
1207 cgx_mode = find_first_bit((unsigned long *)&mode,
1208 CGX_MODE_MAX);
1209 args->mode = mode;
1210 mode_baseidx = cgx_mode - 41;
1211 if (mode_baseidx > 0) {
1212 args->mode_baseidx = 1;
1213 args->mode = BIT_ULL(mode_baseidx);
1214 }
1215 }
1216
otx2_map_ethtool_link_modes(u64 bitmask,struct cgx_set_link_mode_args * args)1217 static void otx2_map_ethtool_link_modes(u64 bitmask,
1218 struct cgx_set_link_mode_args *args)
1219 {
1220 switch (bitmask) {
1221 case ETHTOOL_LINK_MODE_10baseT_Half_BIT:
1222 set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT));
1223 break;
1224 case ETHTOOL_LINK_MODE_10baseT_Full_BIT:
1225 set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT));
1226 break;
1227 case ETHTOOL_LINK_MODE_100baseT_Half_BIT:
1228 set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT));
1229 break;
1230 case ETHTOOL_LINK_MODE_100baseT_Full_BIT:
1231 set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT));
1232 break;
1233 case ETHTOOL_LINK_MODE_1000baseT_Half_BIT:
1234 set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1235 break;
1236 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT:
1237 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1238 break;
1239 case ETHTOOL_LINK_MODE_1000baseX_Full_BIT:
1240 set_mod_args(args, 1000, 0, 0, BIT_ULL(CGX_MODE_1000_BASEX));
1241 break;
1242 case ETHTOOL_LINK_MODE_10000baseT_Full_BIT:
1243 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_QSGMII));
1244 break;
1245 case ETHTOOL_LINK_MODE_10000baseSR_Full_BIT:
1246 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2C));
1247 break;
1248 case ETHTOOL_LINK_MODE_10000baseLR_Full_BIT:
1249 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2M));
1250 break;
1251 case ETHTOOL_LINK_MODE_10000baseKR_Full_BIT:
1252 set_mod_args(args, 10000, 0, 1, BIT_ULL(CGX_MODE_10G_KR));
1253 break;
1254 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
1255 set_mod_args(args, 25000, 0, 0, BIT_ULL(CGX_MODE_25G_C2C));
1256 break;
1257 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
1258 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_CR));
1259 break;
1260 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
1261 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_KR));
1262 break;
1263 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
1264 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2C));
1265 break;
1266 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
1267 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2M));
1268 break;
1269 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
1270 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_CR4));
1271 break;
1272 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
1273 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_KR4));
1274 break;
1275 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
1276 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2C));
1277 break;
1278 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
1279 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2M));
1280 break;
1281 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
1282 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_CR));
1283 break;
1284 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
1285 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_KR));
1286 break;
1287 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
1288 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2C));
1289 break;
1290 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
1291 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2M));
1292 break;
1293 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
1294 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_CR4));
1295 break;
1296 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
1297 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_KR4));
1298 break;
1299 default:
1300 set_mod_args(args, 0, 1, 0, BIT_ULL(CGX_MODE_MAX));
1301 break;
1302 }
1303 }
1304
link_status_user_format(u64 lstat,struct cgx_link_user_info * linfo,struct cgx * cgx,u8 lmac_id)1305 static inline void link_status_user_format(u64 lstat,
1306 struct cgx_link_user_info *linfo,
1307 struct cgx *cgx, u8 lmac_id)
1308 {
1309 unsigned int speed;
1310
1311 linfo->link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat);
1312 linfo->full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat);
1313 linfo->an = FIELD_GET(RESP_LINKSTAT_AN, lstat);
1314 linfo->fec = FIELD_GET(RESP_LINKSTAT_FEC, lstat);
1315 linfo->lmac_type_id = FIELD_GET(RESP_LINKSTAT_LMAC_TYPE, lstat);
1316
1317 speed = FIELD_GET(RESP_LINKSTAT_SPEED, lstat);
1318 linfo->speed = speed < ARRAY_SIZE(cgx_speed_mbps) ?
1319 cgx_speed_mbps[speed] : 0;
1320
1321 if (linfo->lmac_type_id >= LMAC_MODE_MAX) {
1322 dev_err(&cgx->pdev->dev, "Unknown lmac_type_id %d reported by firmware on cgx port%d:%d",
1323 linfo->lmac_type_id, cgx->cgx_id, lmac_id);
1324 strscpy(linfo->lmac_type, "Unknown", sizeof(linfo->lmac_type));
1325 return;
1326 }
1327
1328 strscpy(linfo->lmac_type, cgx_lmactype_string[linfo->lmac_type_id],
1329 sizeof(linfo->lmac_type));
1330 }
1331
1332 /* Hardware event handlers */
cgx_link_change_handler(u64 lstat,struct lmac * lmac)1333 static inline void cgx_link_change_handler(u64 lstat,
1334 struct lmac *lmac)
1335 {
1336 struct cgx_link_user_info *linfo;
1337 struct cgx *cgx = lmac->cgx;
1338 struct cgx_link_event event;
1339 struct device *dev;
1340 int err_type;
1341
1342 dev = &cgx->pdev->dev;
1343
1344 link_status_user_format(lstat, &event.link_uinfo, cgx, lmac->lmac_id);
1345 err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat);
1346
1347 event.cgx_id = cgx->cgx_id;
1348 event.lmac_id = lmac->lmac_id;
1349
1350 /* update the local copy of link status */
1351 lmac->link_info = event.link_uinfo;
1352 linfo = &lmac->link_info;
1353
1354 if (err_type == CGX_ERR_SPEED_CHANGE_INVALID)
1355 return;
1356
1357 /* Ensure callback doesn't get unregistered until we finish it */
1358 spin_lock(&lmac->event_cb_lock);
1359
1360 if (!lmac->event_cb.notify_link_chg) {
1361 dev_dbg(dev, "cgx port %d:%d Link change handler null",
1362 cgx->cgx_id, lmac->lmac_id);
1363 if (err_type != CGX_ERR_NONE) {
1364 dev_err(dev, "cgx port %d:%d Link error %d\n",
1365 cgx->cgx_id, lmac->lmac_id, err_type);
1366 }
1367 dev_info(dev, "cgx port %d:%d Link is %s %d Mbps\n",
1368 cgx->cgx_id, lmac->lmac_id,
1369 linfo->link_up ? "UP" : "DOWN", linfo->speed);
1370 goto err;
1371 }
1372
1373 if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data))
1374 dev_err(dev, "event notification failure\n");
1375 err:
1376 spin_unlock(&lmac->event_cb_lock);
1377 }
1378
cgx_cmdresp_is_linkevent(u64 event)1379 static inline bool cgx_cmdresp_is_linkevent(u64 event)
1380 {
1381 u8 id;
1382
1383 id = FIELD_GET(EVTREG_ID, event);
1384 if (id == CGX_CMD_LINK_BRING_UP ||
1385 id == CGX_CMD_LINK_BRING_DOWN ||
1386 id == CGX_CMD_MODE_CHANGE)
1387 return true;
1388 else
1389 return false;
1390 }
1391
cgx_event_is_linkevent(u64 event)1392 static inline bool cgx_event_is_linkevent(u64 event)
1393 {
1394 if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE)
1395 return true;
1396 else
1397 return false;
1398 }
1399
cgx_fwi_event_handler(int irq,void * data)1400 static irqreturn_t cgx_fwi_event_handler(int irq, void *data)
1401 {
1402 u64 event, offset, clear_bit;
1403 struct lmac *lmac = data;
1404 struct cgx *cgx;
1405
1406 cgx = lmac->cgx;
1407
1408 /* Clear SW_INT for RPM and CMR_INT for CGX */
1409 offset = cgx->mac_ops->int_register;
1410 clear_bit = cgx->mac_ops->int_ena_bit;
1411
1412 event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG);
1413
1414 if (!FIELD_GET(EVTREG_ACK, event))
1415 return IRQ_NONE;
1416
1417 switch (FIELD_GET(EVTREG_EVT_TYPE, event)) {
1418 case CGX_EVT_CMD_RESP:
1419 /* Copy the response. Since only one command is active at a
1420 * time, there is no way a response can get overwritten
1421 */
1422 lmac->resp = event;
1423 /* Ensure response is updated before thread context starts */
1424 smp_wmb();
1425
1426 /* There wont be separate events for link change initiated from
1427 * software; Hence report the command responses as events
1428 */
1429 if (cgx_cmdresp_is_linkevent(event))
1430 cgx_link_change_handler(event, lmac);
1431
1432 /* Release thread waiting for completion */
1433 lmac->cmd_pend = false;
1434 wake_up(&lmac->wq_cmd_cmplt);
1435 break;
1436 case CGX_EVT_ASYNC:
1437 if (cgx_event_is_linkevent(event))
1438 cgx_link_change_handler(event, lmac);
1439 break;
1440 }
1441
1442 /* Any new event or command response will be posted by firmware
1443 * only after the current status is acked.
1444 * Ack the interrupt register as well.
1445 */
1446 cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0);
1447 cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit);
1448
1449 return IRQ_HANDLED;
1450 }
1451
1452 /* APIs for PHY management using CGX firmware interface */
1453
1454 /* callback registration for hardware events like link change */
cgx_lmac_evh_register(struct cgx_event_cb * cb,void * cgxd,int lmac_id)1455 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id)
1456 {
1457 struct cgx *cgx = cgxd;
1458 struct lmac *lmac;
1459
1460 lmac = lmac_pdata(lmac_id, cgx);
1461 if (!lmac)
1462 return -ENODEV;
1463
1464 lmac->event_cb = *cb;
1465
1466 return 0;
1467 }
1468
cgx_lmac_evh_unregister(void * cgxd,int lmac_id)1469 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id)
1470 {
1471 struct lmac *lmac;
1472 unsigned long flags;
1473 struct cgx *cgx = cgxd;
1474
1475 lmac = lmac_pdata(lmac_id, cgx);
1476 if (!lmac)
1477 return -ENODEV;
1478
1479 spin_lock_irqsave(&lmac->event_cb_lock, flags);
1480 lmac->event_cb.notify_link_chg = NULL;
1481 lmac->event_cb.data = NULL;
1482 spin_unlock_irqrestore(&lmac->event_cb_lock, flags);
1483
1484 return 0;
1485 }
1486
cgx_get_fwdata_base(u64 * base)1487 int cgx_get_fwdata_base(u64 *base)
1488 {
1489 u64 req = 0, resp;
1490 struct cgx *cgx;
1491 int first_lmac;
1492 int err;
1493
1494 cgx = list_first_entry_or_null(&cgx_list, struct cgx, cgx_list);
1495 if (!cgx)
1496 return -ENXIO;
1497
1498 first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac);
1499 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FWD_BASE, req);
1500 err = cgx_fwi_cmd_generic(req, &resp, cgx, first_lmac);
1501 if (!err)
1502 *base = FIELD_GET(RESP_FWD_BASE, resp);
1503
1504 return err;
1505 }
1506
cgx_set_link_mode(void * cgxd,struct cgx_set_link_mode_args args,struct cgx_lmac_fwdata_s * linkmodes,int cgx_id,int lmac_id)1507 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
1508 struct cgx_lmac_fwdata_s *linkmodes,
1509 int cgx_id, int lmac_id)
1510 {
1511 struct cgx *cgx = cgxd;
1512 u64 req = 0, resp;
1513 u8 bit;
1514
1515 if (!cgx)
1516 return -ENODEV;
1517
1518 for_each_set_bit(bit, args.advertising,
1519 __ETHTOOL_LINK_MODE_MASK_NBITS)
1520 otx2_map_ethtool_link_modes(bit, &args);
1521
1522 if (args.multimode) {
1523 if (linkmodes->advertised_link_modes_own != CGX_CMD_OWN_NS)
1524 return -EBUSY;
1525
1526 linkmodes->advertised_link_modes = args.mode;
1527 /* Update ownership */
1528 linkmodes->advertised_link_modes_own = CGX_CMD_OWN_FIRMWARE;
1529 args.mode = GENMASK_ULL(41, 0);
1530 }
1531
1532 req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req);
1533 req = FIELD_SET(CMDMODECHANGE_SPEED,
1534 cgx_link_usertable_index_map(args.speed), req);
1535 req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req);
1536 req = FIELD_SET(CMDMODECHANGE_AN, args.an, req);
1537 req = FIELD_SET(CMDMODECHANGE_MODE_BASEIDX, args.mode_baseidx, req);
1538 req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req);
1539
1540 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1541 }
cgx_set_fec(u64 fec,int cgx_id,int lmac_id)1542 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id)
1543 {
1544 u64 req = 0, resp;
1545 struct cgx *cgx;
1546 int err = 0;
1547
1548 cgx = cgx_get_pdata(cgx_id);
1549 if (!cgx)
1550 return -ENXIO;
1551
1552 req = FIELD_SET(CMDREG_ID, CGX_CMD_SET_FEC, req);
1553 req = FIELD_SET(CMDSETFEC, fec, req);
1554 err = cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1555 if (err)
1556 return err;
1557
1558 cgx->lmac_idmap[lmac_id]->link_info.fec =
1559 FIELD_GET(RESP_LINKSTAT_FEC, resp);
1560 return cgx->lmac_idmap[lmac_id]->link_info.fec;
1561 }
1562
cgx_get_phy_fec_stats(void * cgxd,int lmac_id)1563 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id)
1564 {
1565 struct cgx *cgx = cgxd;
1566 u64 req = 0, resp;
1567
1568 if (!cgx)
1569 return -ENODEV;
1570
1571 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_PHY_FEC_STATS, req);
1572 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1573 }
1574
cgx_fwi_link_change(struct cgx * cgx,int lmac_id,bool enable)1575 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable)
1576 {
1577 u64 req = 0;
1578 u64 resp;
1579
1580 if (enable) {
1581 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req);
1582 /* On CN10K firmware offloads link bring up/down operations to ECP
1583 * On Octeontx2 link operations are handled by firmware itself
1584 * which can cause mbox errors so configure maximum time firmware
1585 * poll for Link as 1000 ms
1586 */
1587 if (!is_dev_rpm(cgx))
1588 req = FIELD_SET(LINKCFG_TIMEOUT, 1000, req);
1589
1590 } else {
1591 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req);
1592 }
1593 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1594 }
1595
cgx_fwi_read_version(u64 * resp,struct cgx * cgx)1596 static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx)
1597 {
1598 int first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac);
1599 u64 req = 0;
1600
1601 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req);
1602 return cgx_fwi_cmd_generic(req, resp, cgx, first_lmac);
1603 }
1604
cgx_lmac_verify_fwi_version(struct cgx * cgx)1605 static int cgx_lmac_verify_fwi_version(struct cgx *cgx)
1606 {
1607 struct device *dev = &cgx->pdev->dev;
1608 int major_ver, minor_ver;
1609 u64 resp;
1610 int err;
1611
1612 if (!cgx->lmac_count)
1613 return 0;
1614
1615 err = cgx_fwi_read_version(&resp, cgx);
1616 if (err)
1617 return err;
1618
1619 major_ver = FIELD_GET(RESP_MAJOR_VER, resp);
1620 minor_ver = FIELD_GET(RESP_MINOR_VER, resp);
1621 dev_dbg(dev, "Firmware command interface version = %d.%d\n",
1622 major_ver, minor_ver);
1623 if (major_ver != CGX_FIRMWARE_MAJOR_VER)
1624 return -EIO;
1625 else
1626 return 0;
1627 }
1628
cgx_lmac_linkup_work(struct work_struct * work)1629 static void cgx_lmac_linkup_work(struct work_struct *work)
1630 {
1631 struct cgx *cgx = container_of(work, struct cgx, cgx_cmd_work);
1632 struct device *dev = &cgx->pdev->dev;
1633 int i, err;
1634
1635 /* Do Link up for all the enabled lmacs */
1636 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) {
1637 err = cgx_fwi_link_change(cgx, i, true);
1638 if (err)
1639 dev_info(dev, "cgx port %d:%d Link up command failed\n",
1640 cgx->cgx_id, i);
1641 }
1642 }
1643
cgx_lmac_linkup_start(void * cgxd)1644 int cgx_lmac_linkup_start(void *cgxd)
1645 {
1646 struct cgx *cgx = cgxd;
1647
1648 if (!cgx)
1649 return -ENODEV;
1650
1651 queue_work(cgx->cgx_cmd_workq, &cgx->cgx_cmd_work);
1652
1653 return 0;
1654 }
1655
cgx_lmac_reset(void * cgxd,int lmac_id,u8 pf_req_flr)1656 int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr)
1657 {
1658 struct cgx *cgx = cgxd;
1659 u64 cfg;
1660
1661 if (!is_lmac_valid(cgx, lmac_id))
1662 return -ENODEV;
1663
1664 /* Resetting PFC related CSRs */
1665 cfg = 0xff;
1666 cgx_write(cgxd, lmac_id, CGXX_CMRX_RX_LOGL_XON, cfg);
1667
1668 if (pf_req_flr)
1669 cgx_lmac_internal_loopback(cgxd, lmac_id, false);
1670 return 0;
1671 }
1672
cgx_configure_interrupt(struct cgx * cgx,struct lmac * lmac,int cnt,bool req_free)1673 static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac,
1674 int cnt, bool req_free)
1675 {
1676 struct mac_ops *mac_ops = cgx->mac_ops;
1677 u64 offset, ena_bit;
1678 unsigned int irq;
1679 int err;
1680
1681 irq = pci_irq_vector(cgx->pdev, mac_ops->lmac_fwi +
1682 cnt * mac_ops->irq_offset);
1683 offset = mac_ops->int_set_reg;
1684 ena_bit = mac_ops->int_ena_bit;
1685
1686 if (req_free) {
1687 free_irq(irq, lmac);
1688 return 0;
1689 }
1690
1691 err = request_irq(irq, cgx_fwi_event_handler, 0, lmac->name, lmac);
1692 if (err)
1693 return err;
1694
1695 /* Enable interrupt */
1696 cgx_write(cgx, lmac->lmac_id, offset, ena_bit);
1697 return 0;
1698 }
1699
cgx_get_nr_lmacs(void * cgxd)1700 int cgx_get_nr_lmacs(void *cgxd)
1701 {
1702 struct cgx *cgx = cgxd;
1703
1704 return cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7ULL;
1705 }
1706
cgx_get_lmacid(void * cgxd,u8 lmac_index)1707 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index)
1708 {
1709 struct cgx *cgx = cgxd;
1710
1711 return cgx->lmac_idmap[lmac_index]->lmac_id;
1712 }
1713
cgx_get_lmac_bmap(void * cgxd)1714 unsigned long cgx_get_lmac_bmap(void *cgxd)
1715 {
1716 struct cgx *cgx = cgxd;
1717
1718 return cgx->lmac_bmap;
1719 }
1720
cgx_lmac_init(struct cgx * cgx)1721 static int cgx_lmac_init(struct cgx *cgx)
1722 {
1723 u8 max_dmac_filters;
1724 struct lmac *lmac;
1725 int err, filter;
1726 unsigned int i;
1727 u64 lmac_list;
1728
1729 /* lmac_list specifies which lmacs are enabled
1730 * when bit n is set to 1, LMAC[n] is enabled
1731 */
1732 if (cgx->mac_ops->non_contiguous_serdes_lane) {
1733 if (is_dev_rpm2(cgx))
1734 lmac_list =
1735 cgx_read(cgx, 0, RPM2_CMRX_RX_LMACS) & 0xFFULL;
1736 else
1737 lmac_list =
1738 cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0xFULL;
1739 }
1740
1741 if (cgx->lmac_count > cgx->max_lmac_per_mac)
1742 cgx->lmac_count = cgx->max_lmac_per_mac;
1743
1744 for (i = 0; i < cgx->lmac_count; i++) {
1745 lmac = kzalloc_obj(struct lmac);
1746 if (!lmac)
1747 return -ENOMEM;
1748 lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL);
1749 if (!lmac->name) {
1750 err = -ENOMEM;
1751 goto err_lmac_free;
1752 }
1753 sprintf(lmac->name, "cgx_fwi_%u_%u", cgx->cgx_id, i);
1754 if (cgx->mac_ops->non_contiguous_serdes_lane) {
1755 lmac->lmac_id = __ffs64(lmac_list);
1756 lmac_list &= ~BIT_ULL(lmac->lmac_id);
1757 } else {
1758 lmac->lmac_id = i;
1759 }
1760
1761 lmac->cgx = cgx;
1762 lmac->mac_to_index_bmap.max =
1763 cgx->mac_ops->dmac_filter_count /
1764 cgx->lmac_count;
1765
1766 max_dmac_filters = lmac->mac_to_index_bmap.max;
1767
1768 err = rvu_alloc_bitmap(&lmac->mac_to_index_bmap);
1769 if (err)
1770 goto err_name_free;
1771
1772 /* Reserve first entry for default MAC address */
1773 set_bit(0, lmac->mac_to_index_bmap.bmap);
1774
1775 lmac->rx_fc_pfvf_bmap.max = 128;
1776 err = rvu_alloc_bitmap(&lmac->rx_fc_pfvf_bmap);
1777 if (err)
1778 goto err_dmac_bmap_free;
1779
1780 lmac->tx_fc_pfvf_bmap.max = 128;
1781 err = rvu_alloc_bitmap(&lmac->tx_fc_pfvf_bmap);
1782 if (err)
1783 goto err_rx_fc_bmap_free;
1784
1785 init_waitqueue_head(&lmac->wq_cmd_cmplt);
1786 mutex_init(&lmac->cmd_lock);
1787 spin_lock_init(&lmac->event_cb_lock);
1788 err = cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, false);
1789 if (err)
1790 goto err_bitmap_free;
1791
1792 /* Add reference */
1793 cgx->lmac_idmap[lmac->lmac_id] = lmac;
1794 set_bit(lmac->lmac_id, &cgx->lmac_bmap);
1795 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true);
1796 lmac->lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac->lmac_id);
1797
1798 /* Disable stale DMAC filters for sane state */
1799 for (filter = 0; filter < max_dmac_filters; filter++)
1800 cgx_lmac_addr_del(cgx->cgx_id, lmac->lmac_id, filter);
1801
1802 /* As cgx_lmac_addr_del does not clear entry for index 0
1803 * so it needs to be done explicitly
1804 */
1805 cgx_lmac_addr_reset(cgx->cgx_id, lmac->lmac_id);
1806 }
1807
1808 /* Start X2P reset on given MAC block */
1809 cgx->mac_ops->mac_x2p_reset(cgx, true);
1810 return cgx_lmac_verify_fwi_version(cgx);
1811
1812 err_bitmap_free:
1813 rvu_free_bitmap(&lmac->tx_fc_pfvf_bmap);
1814 err_rx_fc_bmap_free:
1815 rvu_free_bitmap(&lmac->rx_fc_pfvf_bmap);
1816 err_dmac_bmap_free:
1817 rvu_free_bitmap(&lmac->mac_to_index_bmap);
1818 err_name_free:
1819 kfree(lmac->name);
1820 err_lmac_free:
1821 kfree(lmac);
1822 return err;
1823 }
1824
cgx_lmac_exit(struct cgx * cgx)1825 static int cgx_lmac_exit(struct cgx *cgx)
1826 {
1827 struct lmac *lmac;
1828 int i;
1829
1830 if (cgx->cgx_cmd_workq) {
1831 destroy_workqueue(cgx->cgx_cmd_workq);
1832 cgx->cgx_cmd_workq = NULL;
1833 }
1834
1835 /* Free all lmac related resources */
1836 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) {
1837 lmac = cgx->lmac_idmap[i];
1838 if (!lmac)
1839 continue;
1840 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, false);
1841 cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, true);
1842 rvu_free_bitmap(&lmac->mac_to_index_bmap);
1843 rvu_free_bitmap(&lmac->rx_fc_pfvf_bmap);
1844 rvu_free_bitmap(&lmac->tx_fc_pfvf_bmap);
1845 kfree(lmac->name);
1846 kfree(lmac);
1847 }
1848
1849 return 0;
1850 }
1851
cgx_populate_features(struct cgx * cgx)1852 static void cgx_populate_features(struct cgx *cgx)
1853 {
1854 u64 cfg;
1855
1856 cfg = cgx_read(cgx, 0, CGX_CONST);
1857 cgx->fifo_len = FIELD_GET(CGX_CONST_RXFIFO_SIZE, cfg);
1858 cgx->max_lmac_per_mac = FIELD_GET(CGX_CONST_MAX_LMACS, cfg);
1859
1860 if (is_dev_rpm(cgx))
1861 cgx->hw_features = (RVU_LMAC_FEAT_DMACF | RVU_MAC_RPM |
1862 RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP);
1863 else
1864 cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_HIGIG2 |
1865 RVU_LMAC_FEAT_PTP | RVU_LMAC_FEAT_DMACF);
1866 }
1867
cgx_get_rxid_mapoffset(struct cgx * cgx)1868 static u8 cgx_get_rxid_mapoffset(struct cgx *cgx)
1869 {
1870 if (cgx->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10KB_RPM ||
1871 is_dev_rpm2(cgx))
1872 return 0x80;
1873 else
1874 return 0x60;
1875 }
1876
cgx_x2p_reset(void * cgxd,bool enable)1877 static void cgx_x2p_reset(void *cgxd, bool enable)
1878 {
1879 struct cgx *cgx = cgxd;
1880 int lmac_id;
1881 u64 cfg;
1882
1883 if (enable) {
1884 for_each_set_bit(lmac_id, &cgx->lmac_bmap, cgx->max_lmac_per_mac)
1885 cgx->mac_ops->mac_enadis_rx(cgx, lmac_id, false);
1886
1887 usleep_range(1000, 2000);
1888
1889 cfg = cgx_read(cgx, 0, CGXX_CMR_GLOBAL_CONFIG);
1890 cfg |= cgx_get_nix_resetbit(cgx) | CGX_NSCI_DROP;
1891 cgx_write(cgx, 0, CGXX_CMR_GLOBAL_CONFIG, cfg);
1892 } else {
1893 cfg = cgx_read(cgx, 0, CGXX_CMR_GLOBAL_CONFIG);
1894 cfg &= ~(cgx_get_nix_resetbit(cgx) | CGX_NSCI_DROP);
1895 cgx_write(cgx, 0, CGXX_CMR_GLOBAL_CONFIG, cfg);
1896 }
1897 }
1898
cgx_enadis_rx(void * cgxd,int lmac_id,bool enable)1899 static int cgx_enadis_rx(void *cgxd, int lmac_id, bool enable)
1900 {
1901 struct cgx *cgx = cgxd;
1902 u64 cfg;
1903
1904 if (!is_lmac_valid(cgx, lmac_id))
1905 return -ENODEV;
1906
1907 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
1908 if (enable)
1909 cfg |= DATA_PKT_RX_EN;
1910 else
1911 cfg &= ~DATA_PKT_RX_EN;
1912 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
1913 return 0;
1914 }
1915
1916 static struct mac_ops cgx_mac_ops = {
1917 .name = "cgx",
1918 .csr_offset = 0,
1919 .lmac_offset = 18,
1920 .int_register = CGXX_CMRX_INT,
1921 .int_set_reg = CGXX_CMRX_INT_ENA_W1S,
1922 .irq_offset = 9,
1923 .int_ena_bit = FW_CGX_INT,
1924 .lmac_fwi = CGX_LMAC_FWI,
1925 .non_contiguous_serdes_lane = false,
1926 .rx_stats_cnt = 9,
1927 .tx_stats_cnt = 18,
1928 .dmac_filter_count = 32,
1929 .get_nr_lmacs = cgx_get_nr_lmacs,
1930 .get_lmac_type = cgx_get_lmac_type,
1931 .lmac_fifo_len = cgx_get_lmac_fifo_len,
1932 .mac_lmac_intl_lbk = cgx_lmac_internal_loopback,
1933 .mac_get_rx_stats = cgx_get_rx_stats,
1934 .mac_get_tx_stats = cgx_get_tx_stats,
1935 .get_fec_stats = cgx_get_fec_stats,
1936 .mac_enadis_rx_pause_fwding = cgx_lmac_enadis_rx_pause_fwding,
1937 .mac_get_pause_frm_status = cgx_lmac_get_pause_frm_status,
1938 .mac_enadis_pause_frm = cgx_lmac_enadis_pause_frm,
1939 .mac_pause_frm_config = cgx_lmac_pause_frm_config,
1940 .mac_enadis_ptp_config = cgx_lmac_ptp_config,
1941 .mac_rx_tx_enable = cgx_lmac_rx_tx_enable,
1942 .mac_tx_enable = cgx_lmac_tx_enable,
1943 .pfc_config = cgx_lmac_pfc_config,
1944 .mac_get_pfc_frm_cfg = cgx_lmac_get_pfc_frm_cfg,
1945 .mac_reset = cgx_lmac_reset,
1946 .mac_stats_reset = cgx_stats_reset,
1947 .mac_x2p_reset = cgx_x2p_reset,
1948 .mac_enadis_rx = cgx_enadis_rx,
1949 };
1950
cgx_probe(struct pci_dev * pdev,const struct pci_device_id * id)1951 static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1952 {
1953 struct device *dev = &pdev->dev;
1954 struct cgx *cgx;
1955 int err, nvec;
1956
1957 cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL);
1958 if (!cgx)
1959 return -ENOMEM;
1960 cgx->pdev = pdev;
1961
1962 pci_set_drvdata(pdev, cgx);
1963
1964 /* Use mac_ops to get MAC specific features */
1965 if (is_dev_rpm(cgx))
1966 cgx->mac_ops = rpm_get_mac_ops(cgx);
1967 else
1968 cgx->mac_ops = &cgx_mac_ops;
1969
1970 cgx->mac_ops->rxid_map_offset = cgx_get_rxid_mapoffset(cgx);
1971
1972 err = pci_enable_device(pdev);
1973 if (err) {
1974 dev_err(dev, "Failed to enable PCI device\n");
1975 pci_set_drvdata(pdev, NULL);
1976 return err;
1977 }
1978
1979 err = pci_request_regions(pdev, DRV_NAME);
1980 if (err) {
1981 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1982 goto err_disable_device;
1983 }
1984
1985 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
1986 if (err) {
1987 dev_err(dev, "DMA mask config failed, abort\n");
1988 goto err_release_regions;
1989 }
1990
1991 /* MAP configuration registers */
1992 cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1993 if (!cgx->reg_base) {
1994 dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n");
1995 err = -ENOMEM;
1996 goto err_release_regions;
1997 }
1998
1999 if (!is_cn20k(pdev) &&
2000 !is_cgx_mapped_to_nix(pdev->subsystem_device, cgx->cgx_id)) {
2001 dev_notice(dev, "CGX %d not mapped to NIX, skipping probe\n",
2002 cgx->cgx_id);
2003 err = -ENODEV;
2004 goto err_release_regions;
2005 }
2006
2007 cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx);
2008 if (!cgx->lmac_count) {
2009 dev_notice(dev, "CGX %d LMAC count is zero, skipping probe\n", cgx->cgx_id);
2010 err = -EOPNOTSUPP;
2011 goto err_release_regions;
2012 }
2013
2014 nvec = pci_msix_vec_count(cgx->pdev);
2015 err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX);
2016 if (err < 0) {
2017 dev_err(dev, "Request for %d msix vectors failed, err %d\n",
2018 nvec, err);
2019 goto err_release_regions;
2020 }
2021
2022 cgx->cgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24)
2023 & CGX_ID_MASK;
2024
2025 /* init wq for processing linkup requests */
2026 INIT_WORK(&cgx->cgx_cmd_work, cgx_lmac_linkup_work);
2027 cgx->cgx_cmd_workq = alloc_workqueue("cgx_cmd_workq", WQ_PERCPU, 0);
2028 if (!cgx->cgx_cmd_workq) {
2029 dev_err(dev, "alloc workqueue failed for cgx cmd");
2030 err = -ENOMEM;
2031 goto err_free_irq_vectors;
2032 }
2033
2034 list_add(&cgx->cgx_list, &cgx_list);
2035
2036
2037 cgx_populate_features(cgx);
2038
2039 mutex_init(&cgx->lock);
2040
2041 err = cgx_lmac_init(cgx);
2042 if (err)
2043 goto err_release_lmac;
2044
2045 return 0;
2046
2047 err_release_lmac:
2048 cgx_lmac_exit(cgx);
2049 list_del(&cgx->cgx_list);
2050 err_free_irq_vectors:
2051 pci_free_irq_vectors(pdev);
2052 err_release_regions:
2053 pci_release_regions(pdev);
2054 err_disable_device:
2055 pci_disable_device(pdev);
2056 pci_set_drvdata(pdev, NULL);
2057 return err;
2058 }
2059
cgx_remove(struct pci_dev * pdev)2060 static void cgx_remove(struct pci_dev *pdev)
2061 {
2062 struct cgx *cgx = pci_get_drvdata(pdev);
2063
2064 if (cgx) {
2065 cgx_lmac_exit(cgx);
2066 list_del(&cgx->cgx_list);
2067 }
2068 pci_free_irq_vectors(pdev);
2069 pci_release_regions(pdev);
2070 pci_disable_device(pdev);
2071 pci_set_drvdata(pdev, NULL);
2072 }
2073
2074 struct pci_driver cgx_driver = {
2075 .name = DRV_NAME,
2076 .id_table = cgx_id_table,
2077 .probe = cgx_probe,
2078 .remove = cgx_remove,
2079 };
2080