1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Loongson PCI Host Controller Driver
4 *
5 * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
6 */
7
8 #include <linux/of.h>
9 #include <linux/of_pci.h>
10 #include <linux/pci.h>
11 #include <linux/pci_ids.h>
12 #include <linux/pci-acpi.h>
13 #include <linux/pci-ecam.h>
14
15 #include "../pci.h"
16
17 /* Device IDs */
18 #define DEV_LS2K_PCIE_PORT0 0x1a05
19 #define DEV_LS7A_PCIE_PORT0 0x7a09
20 #define DEV_LS7A_PCIE_PORT1 0x7a19
21 #define DEV_LS7A_PCIE_PORT2 0x7a29
22 #define DEV_LS7A_PCIE_PORT3 0x7a39
23 #define DEV_LS7A_PCIE_PORT4 0x7a49
24 #define DEV_LS7A_PCIE_PORT5 0x7a59
25 #define DEV_LS7A_PCIE_PORT6 0x7a69
26
27 #define DEV_LS2K_APB 0x7a02
28 #define DEV_LS7A_GMAC 0x7a03
29 #define DEV_LS7A_DC1 0x7a06
30 #define DEV_LS7A_LPC 0x7a0c
31 #define DEV_LS7A_AHCI 0x7a08
32 #define DEV_LS7A_CONF 0x7a10
33 #define DEV_LS7A_GNET 0x7a13
34 #define DEV_LS7A_EHCI 0x7a14
35 #define DEV_LS7A_DC2 0x7a36
36 #define DEV_LS7A_HDMI 0x7a37
37
38 #define FLAG_CFG0 BIT(0)
39 #define FLAG_CFG1 BIT(1)
40 #define FLAG_DEV_FIX BIT(2)
41 #define FLAG_DEV_HIDDEN BIT(3)
42
43 struct loongson_pci_data {
44 u32 flags;
45 struct pci_ops *ops;
46 };
47
48 struct loongson_pci {
49 void __iomem *cfg0_base;
50 void __iomem *cfg1_base;
51 struct platform_device *pdev;
52 const struct loongson_pci_data *data;
53 };
54
55 /* Fixup wrong class code in PCIe bridges */
bridge_class_quirk(struct pci_dev * dev)56 static void bridge_class_quirk(struct pci_dev *dev)
57 {
58 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
59 }
60 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
61 DEV_LS7A_PCIE_PORT0, bridge_class_quirk);
62 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
63 DEV_LS7A_PCIE_PORT1, bridge_class_quirk);
64 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
65 DEV_LS7A_PCIE_PORT2, bridge_class_quirk);
66
system_bus_quirk(struct pci_dev * pdev)67 static void system_bus_quirk(struct pci_dev *pdev)
68 {
69 /*
70 * The address space consumed by these devices is outside the
71 * resources of the host bridge.
72 */
73 pdev->mmio_always_on = 1;
74 pdev->non_compliant_bars = 1;
75 }
76 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
77 DEV_LS2K_APB, system_bus_quirk);
78 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
79 DEV_LS7A_CONF, system_bus_quirk);
80 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
81 DEV_LS7A_LPC, system_bus_quirk);
82
83 static const struct pci_device_id loongson_internal_bridge_devids[] = {
84 { PCI_VDEVICE(LOONGSON, DEV_LS2K_PCIE_PORT0) },
85 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT0) },
86 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT1) },
87 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT2) },
88 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT3) },
89 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT4) },
90 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT5) },
91 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT6) },
92 { 0, },
93 };
94
95 /*
96 * Some Loongson PCIe ports have hardware limitations on their Maximum Read
97 * Request Size. They can't handle anything larger than this. Sane
98 * firmware will set proper MRRS at boot, so we only need no_inc_mrrs for
99 * bridges. However, some MIPS Loongson firmware doesn't set MRRS properly,
100 * so we have to enforce maximum safe MRRS, which is 256 bytes.
101 */
102 #ifdef CONFIG_MIPS
loongson_set_min_mrrs_quirk(struct pci_dev * pdev)103 static void loongson_set_min_mrrs_quirk(struct pci_dev *pdev)
104 {
105 struct pci_bus *bus = pdev->bus;
106 struct pci_dev *bridge;
107
108 /* look for the matching bridge */
109 while (!pci_is_root_bus(bus)) {
110 bridge = bus->self;
111 bus = bus->parent;
112
113 if (pci_match_id(loongson_internal_bridge_devids, bridge)) {
114 if (pcie_get_readrq(pdev) > 256) {
115 pci_info(pdev, "limiting MRRS to 256\n");
116 pcie_set_readrq(pdev, 256);
117 }
118 break;
119 }
120 }
121 }
122 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_set_min_mrrs_quirk);
123 #endif
124
loongson_mrrs_quirk(struct pci_dev * pdev)125 static void loongson_mrrs_quirk(struct pci_dev *pdev)
126 {
127 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
128
129 bridge->no_inc_mrrs = 1;
130 }
131 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
132 DEV_LS2K_PCIE_PORT0, loongson_mrrs_quirk);
133 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
134 DEV_LS7A_PCIE_PORT0, loongson_mrrs_quirk);
135 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
136 DEV_LS7A_PCIE_PORT1, loongson_mrrs_quirk);
137 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
138 DEV_LS7A_PCIE_PORT2, loongson_mrrs_quirk);
139 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
140 DEV_LS7A_PCIE_PORT3, loongson_mrrs_quirk);
141 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
142 DEV_LS7A_PCIE_PORT4, loongson_mrrs_quirk);
143 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
144 DEV_LS7A_PCIE_PORT5, loongson_mrrs_quirk);
145 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
146 DEV_LS7A_PCIE_PORT6, loongson_mrrs_quirk);
147
loongson_pci_pin_quirk(struct pci_dev * pdev)148 static void loongson_pci_pin_quirk(struct pci_dev *pdev)
149 {
150 pdev->pin = 1 + (PCI_FUNC(pdev->devfn) & 3);
151 }
152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
153 DEV_LS7A_DC1, loongson_pci_pin_quirk);
154 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
155 DEV_LS7A_DC2, loongson_pci_pin_quirk);
156 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
157 DEV_LS7A_GMAC, loongson_pci_pin_quirk);
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
159 DEV_LS7A_AHCI, loongson_pci_pin_quirk);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
161 DEV_LS7A_EHCI, loongson_pci_pin_quirk);
162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
163 DEV_LS7A_GNET, loongson_pci_pin_quirk);
164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
165 DEV_LS7A_HDMI, loongson_pci_pin_quirk);
166
loongson_pci_msi_quirk(struct pci_dev * dev)167 static void loongson_pci_msi_quirk(struct pci_dev *dev)
168 {
169 u16 val, class = dev->class >> 8;
170
171 if (class != PCI_CLASS_BRIDGE_HOST)
172 return;
173
174 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &val);
175 val |= PCI_MSI_FLAGS_ENABLE;
176 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, val);
177 }
178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, DEV_LS7A_PCIE_PORT5, loongson_pci_msi_quirk);
179
180 /*
181 * Older steppings of the Loongson-3C6000 series incorrectly report the
182 * supported link speeds on their PCIe bridges (device IDs 0x3c19,
183 * 0x3c29) as only 2.5 GT/s, despite the upstream bus supporting speeds
184 * from 2.5 GT/s up to 16 GT/s.
185 */
loongson_pci_bridge_speed_quirk(struct pci_dev * pdev)186 static void loongson_pci_bridge_speed_quirk(struct pci_dev *pdev)
187 {
188 u8 old_supported_speeds = pdev->supported_speeds;
189
190 switch (pdev->bus->max_bus_speed) {
191 case PCIE_SPEED_16_0GT:
192 pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_16_0GB;
193 fallthrough;
194 case PCIE_SPEED_8_0GT:
195 pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_8_0GB;
196 fallthrough;
197 case PCIE_SPEED_5_0GT:
198 pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_5_0GB;
199 fallthrough;
200 case PCIE_SPEED_2_5GT:
201 pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_2_5GB;
202 break;
203 default:
204 pci_warn(pdev, "unexpected max bus speed");
205
206 return;
207 }
208
209 if (pdev->supported_speeds != old_supported_speeds)
210 pci_info(pdev, "fixed up supported link speeds: 0x%x => 0x%x",
211 old_supported_speeds, pdev->supported_speeds);
212 }
213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c19, loongson_pci_bridge_speed_quirk);
214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c29, loongson_pci_bridge_speed_quirk);
215
pci_bus_to_loongson_pci(struct pci_bus * bus)216 static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)
217 {
218 struct pci_config_window *cfg;
219
220 if (acpi_disabled)
221 return (struct loongson_pci *)(bus->sysdata);
222
223 cfg = bus->sysdata;
224 return (struct loongson_pci *)(cfg->priv);
225 }
226
cfg0_map(struct loongson_pci * priv,struct pci_bus * bus,unsigned int devfn,int where)227 static void __iomem *cfg0_map(struct loongson_pci *priv, struct pci_bus *bus,
228 unsigned int devfn, int where)
229 {
230 unsigned long addroff = 0x0;
231 unsigned char busnum = bus->number;
232
233 if (!pci_is_root_bus(bus)) {
234 addroff |= BIT(24); /* Type 1 Access */
235 addroff |= (busnum << 16);
236 }
237 addroff |= (devfn << 8) | where;
238 return priv->cfg0_base + addroff;
239 }
240
cfg1_map(struct loongson_pci * priv,struct pci_bus * bus,unsigned int devfn,int where)241 static void __iomem *cfg1_map(struct loongson_pci *priv, struct pci_bus *bus,
242 unsigned int devfn, int where)
243 {
244 unsigned long addroff = 0x0;
245 unsigned char busnum = bus->number;
246
247 if (!pci_is_root_bus(bus)) {
248 addroff |= BIT(28); /* Type 1 Access */
249 addroff |= (busnum << 16);
250 }
251 addroff |= (devfn << 8) | (where & 0xff) | ((where & 0xf00) << 16);
252 return priv->cfg1_base + addroff;
253 }
254
pdev_may_exist(struct pci_bus * bus,unsigned int device,unsigned int function)255 static bool pdev_may_exist(struct pci_bus *bus, unsigned int device,
256 unsigned int function)
257 {
258 return !(pci_is_root_bus(bus) &&
259 (device >= 9 && device <= 20) && (function > 0));
260 }
261
pci_loongson_map_bus(struct pci_bus * bus,unsigned int devfn,int where)262 static void __iomem *pci_loongson_map_bus(struct pci_bus *bus,
263 unsigned int devfn, int where)
264 {
265 unsigned int device = PCI_SLOT(devfn);
266 unsigned int function = PCI_FUNC(devfn);
267 struct loongson_pci *priv = pci_bus_to_loongson_pci(bus);
268
269 /*
270 * Do not read more than one device on the internal bridges.
271 */
272 if ((priv->data->flags & FLAG_DEV_FIX) && bus->self) {
273 if (!pci_is_root_bus(bus) && (device > 0) &&
274 pci_match_id(loongson_internal_bridge_devids, bus->self))
275 return NULL;
276 }
277
278 /* Don't access non-existent devices */
279 if (priv->data->flags & FLAG_DEV_HIDDEN) {
280 if (!pdev_may_exist(bus, device, function))
281 return NULL;
282 }
283
284 /* CFG0 can only access standard space */
285 if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
286 return cfg0_map(priv, bus, devfn, where);
287
288 /* CFG1 can access extended space */
289 if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
290 return cfg1_map(priv, bus, devfn, where);
291
292 return NULL;
293 }
294
295 #ifdef CONFIG_OF
296
loongson_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)297 static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
298 {
299 int irq;
300 u8 val;
301
302 irq = of_irq_parse_and_map_pci(dev, slot, pin);
303 if (irq > 0)
304 return irq;
305
306 /* Care i8259 legacy systems */
307 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
308 /* i8259 only have 15 IRQs */
309 if (val > 15)
310 return 0;
311
312 return val;
313 }
314
315 /* LS2K/LS7A accept 8/16/32-bit PCI config operations */
316 static struct pci_ops loongson_pci_ops = {
317 .map_bus = pci_loongson_map_bus,
318 .read = pci_generic_config_read,
319 .write = pci_generic_config_write,
320 };
321
322 /* RS780/SR5690 only accept 32-bit PCI config operations */
323 static struct pci_ops loongson_pci_ops32 = {
324 .map_bus = pci_loongson_map_bus,
325 .read = pci_generic_config_read32,
326 .write = pci_generic_config_write32,
327 };
328
329 static const struct loongson_pci_data ls2k_pci_data = {
330 .flags = FLAG_CFG1 | FLAG_DEV_FIX | FLAG_DEV_HIDDEN,
331 .ops = &loongson_pci_ops,
332 };
333
334 static const struct loongson_pci_data ls7a_pci_data = {
335 .flags = FLAG_CFG1 | FLAG_DEV_FIX | FLAG_DEV_HIDDEN,
336 .ops = &loongson_pci_ops,
337 };
338
339 static const struct loongson_pci_data rs780e_pci_data = {
340 .flags = FLAG_CFG0,
341 .ops = &loongson_pci_ops32,
342 };
343
344 static const struct of_device_id loongson_pci_of_match[] = {
345 { .compatible = "loongson,ls2k-pci",
346 .data = &ls2k_pci_data, },
347 { .compatible = "loongson,ls7a-pci",
348 .data = &ls7a_pci_data, },
349 { .compatible = "loongson,rs780e-pci",
350 .data = &rs780e_pci_data, },
351 {}
352 };
353
loongson_pci_probe(struct platform_device * pdev)354 static int loongson_pci_probe(struct platform_device *pdev)
355 {
356 struct loongson_pci *priv;
357 struct device *dev = &pdev->dev;
358 struct device_node *node = dev->of_node;
359 struct pci_host_bridge *bridge;
360 struct resource *regs;
361
362 if (!node)
363 return -ENODEV;
364
365 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
366 if (!bridge)
367 return -ENODEV;
368
369 priv = pci_host_bridge_priv(bridge);
370 priv->pdev = pdev;
371 priv->data = of_device_get_match_data(dev);
372
373 if (priv->data->flags & FLAG_CFG0) {
374 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
375 if (!regs)
376 dev_err(dev, "missing mem resources for cfg0\n");
377 else {
378 priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
379 if (IS_ERR(priv->cfg0_base))
380 return PTR_ERR(priv->cfg0_base);
381 }
382 }
383
384 if (priv->data->flags & FLAG_CFG1) {
385 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
386 if (!regs)
387 dev_info(dev, "missing mem resource for cfg1\n");
388 else {
389 priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
390 if (IS_ERR(priv->cfg1_base))
391 priv->cfg1_base = NULL;
392 }
393 }
394
395 bridge->sysdata = priv;
396 bridge->ops = priv->data->ops;
397 bridge->map_irq = loongson_map_irq;
398
399 return pci_host_probe(bridge);
400 }
401
402 static struct platform_driver loongson_pci_driver = {
403 .driver = {
404 .name = "loongson-pci",
405 .of_match_table = loongson_pci_of_match,
406 },
407 .probe = loongson_pci_probe,
408 };
409 builtin_platform_driver(loongson_pci_driver);
410
411 #endif
412
413 #ifdef CONFIG_ACPI
414
loongson_pci_ecam_init(struct pci_config_window * cfg)415 static int loongson_pci_ecam_init(struct pci_config_window *cfg)
416 {
417 struct device *dev = cfg->parent;
418 struct loongson_pci *priv;
419 struct loongson_pci_data *data;
420
421 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
422 if (!priv)
423 return -ENOMEM;
424
425 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
426 if (!data)
427 return -ENOMEM;
428
429 cfg->priv = priv;
430 data->flags = FLAG_CFG1 | FLAG_DEV_HIDDEN;
431 priv->data = data;
432 priv->cfg1_base = cfg->win - (cfg->busr.start << 16);
433
434 return 0;
435 }
436
437 const struct pci_ecam_ops loongson_pci_ecam_ops = {
438 .bus_shift = 16,
439 .init = loongson_pci_ecam_init,
440 .pci_ops = {
441 .map_bus = pci_loongson_map_bus,
442 .read = pci_generic_config_read,
443 .write = pci_generic_config_write,
444 }
445 };
446
447 #endif
448