1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DMA driver for Xilinx Video DMA Engine 4 * 5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved. 6 * 7 * Based on the Freescale DMA driver. 8 * 9 * Description: 10 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP 11 * core that provides high-bandwidth direct memory access between memory 12 * and AXI4-Stream type video target peripherals. The core provides efficient 13 * two dimensional DMA operations with independent asynchronous read (S2MM) 14 * and write (MM2S) channel operation. It can be configured to have either 15 * one channel or two channels. If configured as two channels, one is to 16 * transmit to the video device (MM2S) and another is to receive from the 17 * video device (S2MM). Initialization, status, interrupt and management 18 * registers are accessed through an AXI4-Lite slave interface. 19 * 20 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that 21 * provides high-bandwidth one dimensional direct memory access between memory 22 * and AXI4-Stream target peripherals. It supports one receive and one 23 * transmit channel, both of them optional at synthesis time. 24 * 25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory 26 * Access (DMA) between a memory-mapped source address and a memory-mapped 27 * destination address. 28 * 29 * The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft 30 * Xilinx IP that provides high-bandwidth direct memory access between 31 * memory and AXI4-Stream target peripherals. It provides scatter gather 32 * (SG) interface with multiple channels independent configuration support. 33 * 34 */ 35 36 #include <linux/bitops.h> 37 #include <linux/dmapool.h> 38 #include <linux/dma/xilinx_dma.h> 39 #include <linux/init.h> 40 #include <linux/interrupt.h> 41 #include <linux/io.h> 42 #include <linux/iopoll.h> 43 #include <linux/module.h> 44 #include <linux/of.h> 45 #include <linux/of_dma.h> 46 #include <linux/of_irq.h> 47 #include <linux/platform_device.h> 48 #include <linux/slab.h> 49 #include <linux/string_choices.h> 50 #include <linux/clk.h> 51 #include <linux/io-64-nonatomic-lo-hi.h> 52 53 #include "../dmaengine.h" 54 55 /* Register/Descriptor Offsets */ 56 #define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000 57 #define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030 58 #define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050 59 #define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0 60 61 /* Control Registers */ 62 #define XILINX_DMA_REG_DMACR 0x0000 63 #define XILINX_DMA_DMACR_DELAY_MAX 0xff 64 #define XILINX_DMA_DMACR_DELAY_SHIFT 24 65 #define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff 66 #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16 67 #define XILINX_DMA_DMACR_ERR_IRQ BIT(14) 68 #define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13) 69 #define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12) 70 #define XILINX_DMA_DMACR_MASTER_SHIFT 8 71 #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5 72 #define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4) 73 #define XILINX_DMA_DMACR_GENLOCK_EN BIT(3) 74 #define XILINX_DMA_DMACR_RESET BIT(2) 75 #define XILINX_DMA_DMACR_CIRC_EN BIT(1) 76 #define XILINX_DMA_DMACR_RUNSTOP BIT(0) 77 #define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5) 78 #define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24) 79 #define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16) 80 #define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8) 81 82 #define XILINX_DMA_REG_DMASR 0x0004 83 #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15) 84 #define XILINX_DMA_DMASR_ERR_IRQ BIT(14) 85 #define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13) 86 #define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12) 87 #define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11) 88 #define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10) 89 #define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9) 90 #define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8) 91 #define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7) 92 #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6) 93 #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5) 94 #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4) 95 #define XILINX_DMA_DMASR_SG_MASK BIT(3) 96 #define XILINX_DMA_DMASR_IDLE BIT(1) 97 #define XILINX_DMA_DMASR_HALTED BIT(0) 98 #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24) 99 #define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16) 100 101 #define XILINX_DMA_REG_CURDESC 0x0008 102 #define XILINX_DMA_REG_TAILDESC 0x0010 103 #define XILINX_DMA_REG_REG_INDEX 0x0014 104 #define XILINX_DMA_REG_FRMSTORE 0x0018 105 #define XILINX_DMA_REG_THRESHOLD 0x001c 106 #define XILINX_DMA_REG_FRMPTR_STS 0x0024 107 #define XILINX_DMA_REG_PARK_PTR 0x0028 108 #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8 109 #define XILINX_DMA_PARK_PTR_WR_REF_MASK GENMASK(12, 8) 110 #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0 111 #define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0) 112 #define XILINX_DMA_REG_VDMA_VERSION 0x002c 113 114 /* Register Direct Mode Registers */ 115 #define XILINX_DMA_REG_VSIZE 0x0000 116 #define XILINX_DMA_VSIZE_MASK GENMASK(12, 0) 117 #define XILINX_DMA_REG_HSIZE 0x0004 118 #define XILINX_DMA_HSIZE_MASK GENMASK(15, 0) 119 120 #define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008 121 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24 122 #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0 123 124 #define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n)) 125 #define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n)) 126 127 #define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP 0x00ec 128 #define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0) 129 130 /* HW specific definitions */ 131 #define XILINX_MCDMA_MAX_CHANS_PER_DEVICE 0x20 132 #define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2 133 #define XILINX_CDMA_MAX_CHANS_PER_DEVICE 0x1 134 #define XILINX_DMA_DFAULT_ADDRWIDTH 0x20 135 136 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \ 137 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \ 138 XILINX_DMA_DMASR_DLY_CNT_IRQ | \ 139 XILINX_DMA_DMASR_ERR_IRQ) 140 141 #define XILINX_DMA_DMASR_ALL_ERR_MASK \ 142 (XILINX_DMA_DMASR_EOL_LATE_ERR | \ 143 XILINX_DMA_DMASR_SOF_LATE_ERR | \ 144 XILINX_DMA_DMASR_SG_DEC_ERR | \ 145 XILINX_DMA_DMASR_SG_SLV_ERR | \ 146 XILINX_DMA_DMASR_EOF_EARLY_ERR | \ 147 XILINX_DMA_DMASR_SOF_EARLY_ERR | \ 148 XILINX_DMA_DMASR_DMA_DEC_ERR | \ 149 XILINX_DMA_DMASR_DMA_SLAVE_ERR | \ 150 XILINX_DMA_DMASR_DMA_INT_ERR) 151 152 /* 153 * Recoverable errors are DMA Internal error, SOF Early, EOF Early 154 * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC 155 * is enabled in the h/w system. 156 */ 157 #define XILINX_DMA_DMASR_ERR_RECOVER_MASK \ 158 (XILINX_DMA_DMASR_SOF_LATE_ERR | \ 159 XILINX_DMA_DMASR_EOF_EARLY_ERR | \ 160 XILINX_DMA_DMASR_SOF_EARLY_ERR | \ 161 XILINX_DMA_DMASR_DMA_INT_ERR) 162 163 /* Axi VDMA Flush on Fsync bits */ 164 #define XILINX_DMA_FLUSH_S2MM 3 165 #define XILINX_DMA_FLUSH_MM2S 2 166 #define XILINX_DMA_FLUSH_BOTH 1 167 168 /* Timeout for polling various registers */ 169 #define XILINX_DMA_POLL_TIMEOUT_US 1000000 170 /* Delay between polls (avoid a delay of 0 to prevent CPU stalls) */ 171 #define XILINX_DMA_POLL_DELAY_US 10 172 173 /* AXI DMA Specific Registers/Offsets */ 174 #define XILINX_DMA_REG_SRCDSTADDR 0x18 175 #define XILINX_DMA_REG_BTT 0x28 176 177 /* AXI DMA Specific Masks/Bit fields */ 178 #define XILINX_DMA_MAX_TRANS_LEN_MIN 8 179 #define XILINX_DMA_MAX_TRANS_LEN_MAX 23 180 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26 181 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) 182 #define XILINX_DMA_CR_DELAY_MAX GENMASK(31, 24) 183 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) 184 #define XILINX_DMA_CR_COALESCE_SHIFT 16 185 #define XILINX_DMA_CR_DELAY_SHIFT 24 186 #define XILINX_DMA_BD_SOP BIT(27) 187 #define XILINX_DMA_BD_EOP BIT(26) 188 #define XILINX_DMA_BD_COMP_MASK BIT(31) 189 #define XILINX_DMA_COALESCE_MAX 255 190 #define XILINX_DMA_NUM_DESCS 512 191 #define XILINX_DMA_NUM_APP_WORDS 5 192 193 /* AXI CDMA Specific Registers/Offsets */ 194 #define XILINX_CDMA_REG_SRCADDR 0x18 195 #define XILINX_CDMA_REG_DSTADDR 0x20 196 197 /* AXI CDMA Specific Masks */ 198 #define XILINX_CDMA_CR_SGMODE BIT(3) 199 200 #define xilinx_prep_dma_addr_t(addr) \ 201 ((dma_addr_t)((u64)addr##_##msb << 32 | (addr))) 202 203 /* AXI MCDMA Specific Registers/Offsets */ 204 #define XILINX_MCDMA_MM2S_CTRL_OFFSET 0x0000 205 #define XILINX_MCDMA_S2MM_CTRL_OFFSET 0x0500 206 #define XILINX_MCDMA_CHEN_OFFSET 0x0008 207 #define XILINX_MCDMA_CH_ERR_OFFSET 0x0010 208 #define XILINX_MCDMA_RXINT_SER_OFFSET 0x0020 209 #define XILINX_MCDMA_TXINT_SER_OFFSET 0x0028 210 #define XILINX_MCDMA_CHAN_CR_OFFSET(x) (0x40 + (x) * 0x40) 211 #define XILINX_MCDMA_CHAN_SR_OFFSET(x) (0x44 + (x) * 0x40) 212 #define XILINX_MCDMA_CHAN_CDESC_OFFSET(x) (0x48 + (x) * 0x40) 213 #define XILINX_MCDMA_CHAN_TDESC_OFFSET(x) (0x50 + (x) * 0x40) 214 215 /* AXI MCDMA Specific Masks/Shifts */ 216 #define XILINX_MCDMA_COALESCE_SHIFT 16 217 #define XILINX_MCDMA_COALESCE_MAX 24 218 #define XILINX_MCDMA_IRQ_ALL_MASK GENMASK(7, 5) 219 #define XILINX_MCDMA_COALESCE_MASK GENMASK(23, 16) 220 #define XILINX_MCDMA_CR_RUNSTOP_MASK BIT(0) 221 #define XILINX_MCDMA_IRQ_IOC_MASK BIT(5) 222 #define XILINX_MCDMA_IRQ_DELAY_MASK BIT(6) 223 #define XILINX_MCDMA_IRQ_ERR_MASK BIT(7) 224 #define XILINX_MCDMA_BD_EOP BIT(30) 225 #define XILINX_MCDMA_BD_SOP BIT(31) 226 #define XILINX_MCDMA_BD_HW_SIZE 64 227 228 /** 229 * struct xilinx_vdma_desc_hw - Hardware Descriptor 230 * @next_desc: Next Descriptor Pointer @0x00 231 * @pad1: Reserved @0x04 232 * @buf_addr: Buffer address @0x08 233 * @buf_addr_msb: MSB of Buffer address @0x0C 234 * @vsize: Vertical Size @0x10 235 * @hsize: Horizontal Size @0x14 236 * @stride: Number of bytes between the first 237 * pixels of each horizontal line @0x18 238 */ 239 struct xilinx_vdma_desc_hw { 240 u32 next_desc; 241 u32 pad1; 242 u32 buf_addr; 243 u32 buf_addr_msb; 244 u32 vsize; 245 u32 hsize; 246 u32 stride; 247 } __aligned(64); 248 249 /** 250 * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA 251 * @next_desc: Next Descriptor Pointer @0x00 252 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 253 * @buf_addr: Buffer address @0x08 254 * @buf_addr_msb: MSB of Buffer address @0x0C 255 * @reserved1: Reserved @0x10 256 * @reserved2: Reserved @0x14 257 * @control: Control field @0x18 258 * @status: Status field @0x1C 259 * @app: APP Fields @0x20 - 0x30 260 */ 261 struct xilinx_axidma_desc_hw { 262 u32 next_desc; 263 u32 next_desc_msb; 264 u32 buf_addr; 265 u32 buf_addr_msb; 266 u32 reserved1; 267 u32 reserved2; 268 u32 control; 269 u32 status; 270 u32 app[XILINX_DMA_NUM_APP_WORDS]; 271 } __aligned(64); 272 273 /** 274 * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA 275 * @next_desc: Next Descriptor Pointer @0x00 276 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 277 * @buf_addr: Buffer address @0x08 278 * @buf_addr_msb: MSB of Buffer address @0x0C 279 * @rsvd: Reserved field @0x10 280 * @control: Control Information field @0x14 281 * @mm2s_ctrl_sideband: Sideband control info for mm2s @0x18 282 * @s2mm_status: Status field for s2mm @0x18 283 * @mm2s_status: Status field for mm2s @0x1C 284 * @s2mm_sideband_status: Sideband status for s2mm @0x1C 285 * @app: APP Fields @0x20 - 0x30 286 */ 287 struct xilinx_aximcdma_desc_hw { 288 u32 next_desc; 289 u32 next_desc_msb; 290 u32 buf_addr; 291 u32 buf_addr_msb; 292 u32 rsvd; 293 u32 control; 294 union { 295 u32 mm2s_ctrl_sideband; 296 u32 s2mm_status; 297 }; 298 union { 299 u32 mm2s_status; 300 u32 s2mm_sideband_status; 301 }; 302 u32 app[XILINX_DMA_NUM_APP_WORDS]; 303 } __aligned(64); 304 static_assert(sizeof(struct xilinx_aximcdma_desc_hw) == XILINX_MCDMA_BD_HW_SIZE); 305 306 /** 307 * struct xilinx_cdma_desc_hw - Hardware Descriptor 308 * @next_desc: Next Descriptor Pointer @0x00 309 * @next_desc_msb: Next Descriptor Pointer MSB @0x04 310 * @src_addr: Source address @0x08 311 * @src_addr_msb: Source address MSB @0x0C 312 * @dest_addr: Destination address @0x10 313 * @dest_addr_msb: Destination address MSB @0x14 314 * @control: Control field @0x18 315 * @status: Status field @0x1C 316 */ 317 struct xilinx_cdma_desc_hw { 318 u32 next_desc; 319 u32 next_desc_msb; 320 u32 src_addr; 321 u32 src_addr_msb; 322 u32 dest_addr; 323 u32 dest_addr_msb; 324 u32 control; 325 u32 status; 326 } __aligned(64); 327 328 /** 329 * struct xilinx_vdma_tx_segment - Descriptor segment 330 * @hw: Hardware descriptor 331 * @node: Node in the descriptor segments list 332 * @phys: Physical address of segment 333 */ 334 struct xilinx_vdma_tx_segment { 335 struct xilinx_vdma_desc_hw hw; 336 struct list_head node; 337 dma_addr_t phys; 338 } __aligned(64); 339 340 /** 341 * struct xilinx_axidma_tx_segment - Descriptor segment 342 * @hw: Hardware descriptor 343 * @node: Node in the descriptor segments list 344 * @phys: Physical address of segment 345 */ 346 struct xilinx_axidma_tx_segment { 347 struct xilinx_axidma_desc_hw hw; 348 struct list_head node; 349 dma_addr_t phys; 350 } __aligned(64); 351 352 /** 353 * struct xilinx_aximcdma_tx_segment - Descriptor segment 354 * @hw: Hardware descriptor 355 * @node: Node in the descriptor segments list 356 * @phys: Physical address of segment 357 */ 358 struct xilinx_aximcdma_tx_segment { 359 struct xilinx_aximcdma_desc_hw hw; 360 struct list_head node; 361 dma_addr_t phys; 362 } __aligned(64); 363 364 /** 365 * struct xilinx_cdma_tx_segment - Descriptor segment 366 * @hw: Hardware descriptor 367 * @node: Node in the descriptor segments list 368 * @phys: Physical address of segment 369 */ 370 struct xilinx_cdma_tx_segment { 371 struct xilinx_cdma_desc_hw hw; 372 struct list_head node; 373 dma_addr_t phys; 374 } __aligned(64); 375 376 /** 377 * struct xilinx_dma_tx_descriptor - Per Transaction structure 378 * @async_tx: Async transaction descriptor 379 * @segments: TX segments list 380 * @node: Node in the channel descriptors list 381 * @cyclic: Check for cyclic transfers. 382 * @err: Whether the descriptor has an error. 383 * @residue: Residue of the completed descriptor 384 */ 385 struct xilinx_dma_tx_descriptor { 386 struct dma_async_tx_descriptor async_tx; 387 struct list_head segments; 388 struct list_head node; 389 bool cyclic; 390 bool err; 391 u32 residue; 392 }; 393 394 /** 395 * struct xilinx_dma_chan - Driver specific DMA channel structure 396 * @xdev: Driver specific device structure 397 * @ctrl_offset: Control registers offset 398 * @desc_offset: TX descriptor registers offset 399 * @lock: Descriptor operation lock 400 * @pending_list: Descriptors waiting 401 * @active_list: Descriptors ready to submit 402 * @done_list: Complete descriptors 403 * @free_seg_list: Free descriptors 404 * @common: DMA common channel 405 * @desc_pool: Descriptors pool 406 * @dev: The dma device 407 * @irq: Channel IRQ 408 * @id: Channel ID 409 * @direction: Transfer direction 410 * @num_frms: Number of frames 411 * @has_sg: Support scatter transfers 412 * @cyclic: Check for cyclic transfers. 413 * @genlock: Support genlock mode 414 * @err: Channel has errors 415 * @idle: Check for channel idle 416 * @terminating: Check for channel being synchronized by user 417 * @tasklet: Cleanup work after irq 418 * @config: Device configuration info 419 * @flush_on_fsync: Flush on Frame sync 420 * @desc_pendingcount: Descriptor pending count 421 * @ext_addr: Indicates 64 bit addressing is supported by dma channel 422 * @desc_submitcount: Descriptor h/w submitted count 423 * @seg_v: Statically allocated segments base 424 * @seg_mv: Statically allocated segments base for MCDMA 425 * @seg_p: Physical allocated segments base 426 * @cyclic_seg_v: Statically allocated segment base for cyclic transfers 427 * @cyclic_seg_p: Physical allocated segments base for cyclic dma 428 * @start_transfer: Differentiate b/w DMA IP's transfer 429 * @stop_transfer: Differentiate b/w DMA IP's quiesce 430 * @tdest: TDEST value for mcdma 431 * @has_vflip: S2MM vertical flip 432 * @irq_delay: Interrupt delay timeout 433 */ 434 struct xilinx_dma_chan { 435 struct xilinx_dma_device *xdev; 436 u32 ctrl_offset; 437 u32 desc_offset; 438 spinlock_t lock; 439 struct list_head pending_list; 440 struct list_head active_list; 441 struct list_head done_list; 442 struct list_head free_seg_list; 443 struct dma_chan common; 444 struct dma_pool *desc_pool; 445 struct device *dev; 446 int irq; 447 int id; 448 enum dma_transfer_direction direction; 449 int num_frms; 450 bool has_sg; 451 bool cyclic; 452 bool genlock; 453 bool err; 454 bool idle; 455 bool terminating; 456 struct tasklet_struct tasklet; 457 struct xilinx_vdma_config config; 458 bool flush_on_fsync; 459 u32 desc_pendingcount; 460 bool ext_addr; 461 u32 desc_submitcount; 462 struct xilinx_axidma_tx_segment *seg_v; 463 struct xilinx_aximcdma_tx_segment *seg_mv; 464 dma_addr_t seg_p; 465 struct xilinx_axidma_tx_segment *cyclic_seg_v; 466 dma_addr_t cyclic_seg_p; 467 void (*start_transfer)(struct xilinx_dma_chan *chan); 468 int (*stop_transfer)(struct xilinx_dma_chan *chan); 469 u16 tdest; 470 bool has_vflip; 471 u8 irq_delay; 472 }; 473 474 /** 475 * enum xdma_ip_type - DMA IP type. 476 * 477 * @XDMA_TYPE_AXIDMA: Axi dma ip. 478 * @XDMA_TYPE_CDMA: Axi cdma ip. 479 * @XDMA_TYPE_VDMA: Axi vdma ip. 480 * @XDMA_TYPE_AXIMCDMA: Axi MCDMA ip. 481 * 482 */ 483 enum xdma_ip_type { 484 XDMA_TYPE_AXIDMA = 0, 485 XDMA_TYPE_CDMA, 486 XDMA_TYPE_VDMA, 487 XDMA_TYPE_AXIMCDMA 488 }; 489 490 struct xilinx_dma_config { 491 enum xdma_ip_type dmatype; 492 int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk, 493 struct clk **tx_clk, struct clk **txs_clk, 494 struct clk **rx_clk, struct clk **rxs_clk); 495 irqreturn_t (*irq_handler)(int irq, void *data); 496 const int max_channels; 497 }; 498 499 /** 500 * struct xilinx_dma_device - DMA device structure 501 * @regs: I/O mapped base address 502 * @dev: Device Structure 503 * @common: DMA device structure 504 * @chan: Driver specific DMA channel 505 * @flush_on_fsync: Flush on frame sync 506 * @ext_addr: Indicates 64 bit addressing is supported by dma device 507 * @pdev: Platform device structure pointer 508 * @dma_config: DMA config structure 509 * @axi_clk: DMA Axi4-lite interace clock 510 * @tx_clk: DMA mm2s clock 511 * @txs_clk: DMA mm2s stream clock 512 * @rx_clk: DMA s2mm clock 513 * @rxs_clk: DMA s2mm stream clock 514 * @s2mm_chan_id: DMA s2mm channel identifier 515 * @mm2s_chan_id: DMA mm2s channel identifier 516 * @max_buffer_len: Max buffer length 517 * @has_axistream_connected: AXI DMA connected to AXI Stream IP 518 */ 519 struct xilinx_dma_device { 520 void __iomem *regs; 521 struct device *dev; 522 struct dma_device common; 523 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE]; 524 u32 flush_on_fsync; 525 bool ext_addr; 526 struct platform_device *pdev; 527 const struct xilinx_dma_config *dma_config; 528 struct clk *axi_clk; 529 struct clk *tx_clk; 530 struct clk *txs_clk; 531 struct clk *rx_clk; 532 struct clk *rxs_clk; 533 u32 s2mm_chan_id; 534 u32 mm2s_chan_id; 535 u32 max_buffer_len; 536 bool has_axistream_connected; 537 }; 538 539 /* Macros */ 540 #define to_xilinx_chan(chan) \ 541 container_of(chan, struct xilinx_dma_chan, common) 542 #define to_dma_tx_descriptor(tx) \ 543 container_of(tx, struct xilinx_dma_tx_descriptor, async_tx) 544 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ 545 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \ 546 val, cond, delay_us, timeout_us) 547 548 /* IO accessors */ 549 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) 550 { 551 return ioread32(chan->xdev->regs + reg); 552 } 553 554 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) 555 { 556 iowrite32(value, chan->xdev->regs + reg); 557 } 558 559 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg, 560 u32 value) 561 { 562 dma_write(chan, chan->desc_offset + reg, value); 563 } 564 565 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg) 566 { 567 return dma_read(chan, chan->ctrl_offset + reg); 568 } 569 570 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg, 571 u32 value) 572 { 573 dma_write(chan, chan->ctrl_offset + reg, value); 574 } 575 576 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg, 577 u32 clr) 578 { 579 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr); 580 } 581 582 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg, 583 u32 set) 584 { 585 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set); 586 } 587 588 /** 589 * vdma_desc_write_64 - 64-bit descriptor write 590 * @chan: Driver specific VDMA channel 591 * @reg: Register to write 592 * @value_lsb: lower address of the descriptor. 593 * @value_msb: upper address of the descriptor. 594 * 595 * Since vdma driver is trying to write to a register offset which is not a 596 * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits 597 * instead of a single 64 bit register write. 598 */ 599 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg, 600 u32 value_lsb, u32 value_msb) 601 { 602 /* Write the lsb 32 bits*/ 603 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg); 604 605 /* Write the msb 32 bits */ 606 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4); 607 } 608 609 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value) 610 { 611 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg); 612 } 613 614 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg, 615 dma_addr_t addr) 616 { 617 if (chan->ext_addr) 618 dma_writeq(chan, reg, addr); 619 else 620 dma_ctrl_write(chan, reg, addr); 621 } 622 623 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan, 624 struct xilinx_axidma_desc_hw *hw, 625 dma_addr_t buf_addr, size_t sg_used, 626 size_t period_len) 627 { 628 if (chan->ext_addr) { 629 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len); 630 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used + 631 period_len); 632 } else { 633 hw->buf_addr = buf_addr + sg_used + period_len; 634 } 635 } 636 637 static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, 638 struct xilinx_aximcdma_desc_hw *hw, 639 dma_addr_t buf_addr, size_t sg_used) 640 { 641 if (chan->ext_addr) { 642 hw->buf_addr = lower_32_bits(buf_addr + sg_used); 643 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used); 644 } else { 645 hw->buf_addr = buf_addr + sg_used; 646 } 647 } 648 649 /** 650 * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length 651 * @tx: async transaction descriptor 652 * @payload_len: metadata payload length 653 * @max_len: metadata max length 654 * 655 * The metadata lives in the SOP descriptor for TX and the EOF descriptor for RX. 656 * Field order depends on dmatype and direction: 657 * 658 * AXI DMA: [0..] app 659 * AXI MCDMA (TX): [0] ctrl_sideband, [1] status, [2..] app 660 * AXI MCDMA (RX): [0] status, [1] sideband, [2..] app 661 * 662 * Return: Pointer to the first metadata word. 663 */ 664 static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx, 665 size_t *payload_len, size_t *max_len) 666 { 667 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); 668 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); 669 670 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 671 struct xilinx_aximcdma_tx_segment *seg; 672 673 if (chan->direction == DMA_DEV_TO_MEM) { 674 seg = list_last_entry(&desc->segments, 675 struct xilinx_aximcdma_tx_segment, node); 676 *max_len = *payload_len = sizeof(seg->hw.s2mm_status) + 677 sizeof(seg->hw.s2mm_sideband_status) + 678 sizeof(seg->hw.app); 679 return &seg->hw.s2mm_status; 680 } 681 seg = list_first_entry(&desc->segments, 682 struct xilinx_aximcdma_tx_segment, node); 683 *max_len = *payload_len = sizeof(seg->hw.mm2s_ctrl_sideband) + 684 sizeof(seg->hw.mm2s_status) + 685 sizeof(seg->hw.app); 686 return &seg->hw.mm2s_ctrl_sideband; 687 } 688 689 struct xilinx_axidma_tx_segment *seg; 690 691 if (chan->direction == DMA_DEV_TO_MEM) 692 seg = list_last_entry(&desc->segments, 693 struct xilinx_axidma_tx_segment, node); 694 else 695 seg = list_first_entry(&desc->segments, 696 struct xilinx_axidma_tx_segment, node); 697 698 *max_len = *payload_len = sizeof(seg->hw.app); 699 return seg->hw.app; 700 } 701 702 static const struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = { 703 .get_ptr = xilinx_dma_get_metadata_ptr, 704 }; 705 706 /* ----------------------------------------------------------------------------- 707 * Descriptors and segments alloc and free 708 */ 709 710 /** 711 * xilinx_vdma_alloc_tx_segment - Allocate transaction segment 712 * @chan: Driver specific DMA channel 713 * 714 * Return: The allocated segment on success and NULL on failure. 715 */ 716 static struct xilinx_vdma_tx_segment * 717 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 718 { 719 struct xilinx_vdma_tx_segment *segment; 720 dma_addr_t phys; 721 722 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); 723 if (!segment) 724 return NULL; 725 726 segment->phys = phys; 727 728 return segment; 729 } 730 731 /** 732 * xilinx_cdma_alloc_tx_segment - Allocate transaction segment 733 * @chan: Driver specific DMA channel 734 * 735 * Return: The allocated segment on success and NULL on failure. 736 */ 737 static struct xilinx_cdma_tx_segment * 738 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 739 { 740 struct xilinx_cdma_tx_segment *segment; 741 dma_addr_t phys; 742 743 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); 744 if (!segment) 745 return NULL; 746 747 segment->phys = phys; 748 749 return segment; 750 } 751 752 /** 753 * xilinx_axidma_alloc_tx_segment - Allocate transaction segment 754 * @chan: Driver specific DMA channel 755 * 756 * Return: The allocated segment on success and NULL on failure. 757 */ 758 static struct xilinx_axidma_tx_segment * 759 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan) 760 { 761 struct xilinx_axidma_tx_segment *segment = NULL; 762 unsigned long flags; 763 764 spin_lock_irqsave(&chan->lock, flags); 765 if (!list_empty(&chan->free_seg_list)) { 766 segment = list_first_entry(&chan->free_seg_list, 767 struct xilinx_axidma_tx_segment, 768 node); 769 list_del(&segment->node); 770 } 771 spin_unlock_irqrestore(&chan->lock, flags); 772 773 if (!segment) 774 dev_dbg(chan->dev, "Could not find free tx segment\n"); 775 776 return segment; 777 } 778 779 /** 780 * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment 781 * @chan: Driver specific DMA channel 782 * 783 * Return: The allocated segment on success and NULL on failure. 784 */ 785 static struct xilinx_aximcdma_tx_segment * 786 xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 787 { 788 struct xilinx_aximcdma_tx_segment *segment = NULL; 789 unsigned long flags; 790 791 spin_lock_irqsave(&chan->lock, flags); 792 if (!list_empty(&chan->free_seg_list)) { 793 segment = list_first_entry(&chan->free_seg_list, 794 struct xilinx_aximcdma_tx_segment, 795 node); 796 list_del(&segment->node); 797 } 798 spin_unlock_irqrestore(&chan->lock, flags); 799 800 return segment; 801 } 802 803 static void xilinx_dma_clean_hw_desc(struct xilinx_dma_chan *chan, 804 struct xilinx_axidma_tx_segment *segment) 805 { 806 dma_addr_t next; 807 u32 i; 808 809 /* 810 * Restore the buffer descriptor's next descriptor pointer to the value 811 * set up in xilinx_dma_alloc_chan_resources(). Otherwise using the DMA 812 * in cyclic mode leaves the next descriptor pointer altered and 813 * prevents subsequent non-cyclic transfers. 814 */ 815 i = segment - chan->seg_v; 816 next = chan->seg_p + 817 sizeof(*chan->seg_v) * ((i + 1) % XILINX_DMA_NUM_DESCS); 818 819 memset(&segment->hw, 0, sizeof(segment->hw)); 820 segment->hw.next_desc = lower_32_bits(next); 821 segment->hw.next_desc_msb = upper_32_bits(next); 822 } 823 824 static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw) 825 { 826 u32 next_desc = hw->next_desc; 827 u32 next_desc_msb = hw->next_desc_msb; 828 829 memset(hw, 0, sizeof(struct xilinx_aximcdma_desc_hw)); 830 831 hw->next_desc = next_desc; 832 hw->next_desc_msb = next_desc_msb; 833 } 834 835 /** 836 * xilinx_dma_free_tx_segment - Free transaction segment 837 * @chan: Driver specific DMA channel 838 * @segment: DMA transaction segment 839 */ 840 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan, 841 struct xilinx_axidma_tx_segment *segment) 842 { 843 xilinx_dma_clean_hw_desc(chan, segment); 844 845 list_add_tail(&segment->node, &chan->free_seg_list); 846 } 847 848 /** 849 * xilinx_mcdma_free_tx_segment - Free transaction segment 850 * @chan: Driver specific DMA channel 851 * @segment: DMA transaction segment 852 */ 853 static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan, 854 struct xilinx_aximcdma_tx_segment * 855 segment) 856 { 857 xilinx_mcdma_clean_hw_desc(&segment->hw); 858 859 list_add_tail(&segment->node, &chan->free_seg_list); 860 } 861 862 /** 863 * xilinx_cdma_free_tx_segment - Free transaction segment 864 * @chan: Driver specific DMA channel 865 * @segment: DMA transaction segment 866 */ 867 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan, 868 struct xilinx_cdma_tx_segment *segment) 869 { 870 dma_pool_free(chan->desc_pool, segment, segment->phys); 871 } 872 873 /** 874 * xilinx_vdma_free_tx_segment - Free transaction segment 875 * @chan: Driver specific DMA channel 876 * @segment: DMA transaction segment 877 */ 878 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan, 879 struct xilinx_vdma_tx_segment *segment) 880 { 881 dma_pool_free(chan->desc_pool, segment, segment->phys); 882 } 883 884 /** 885 * xilinx_dma_alloc_tx_descriptor - Allocate transaction descriptor 886 * @chan: Driver specific DMA channel 887 * 888 * Return: The allocated descriptor on success and NULL on failure. 889 */ 890 static struct xilinx_dma_tx_descriptor * 891 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan) 892 { 893 struct xilinx_dma_tx_descriptor *desc; 894 895 desc = kzalloc_obj(*desc, GFP_NOWAIT); 896 if (!desc) 897 return NULL; 898 899 INIT_LIST_HEAD(&desc->segments); 900 901 return desc; 902 } 903 904 /** 905 * xilinx_dma_free_tx_descriptor - Free transaction descriptor 906 * @chan: Driver specific DMA channel 907 * @desc: DMA transaction descriptor 908 */ 909 static void 910 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan, 911 struct xilinx_dma_tx_descriptor *desc) 912 { 913 struct xilinx_vdma_tx_segment *segment, *next; 914 struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next; 915 struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next; 916 struct xilinx_aximcdma_tx_segment *aximcdma_segment, *aximcdma_next; 917 918 if (!desc) 919 return; 920 921 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 922 list_for_each_entry_safe(segment, next, &desc->segments, node) { 923 list_del(&segment->node); 924 xilinx_vdma_free_tx_segment(chan, segment); 925 } 926 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 927 list_for_each_entry_safe(cdma_segment, cdma_next, 928 &desc->segments, node) { 929 list_del(&cdma_segment->node); 930 xilinx_cdma_free_tx_segment(chan, cdma_segment); 931 } 932 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 933 list_for_each_entry_safe(axidma_segment, axidma_next, 934 &desc->segments, node) { 935 list_del(&axidma_segment->node); 936 xilinx_dma_free_tx_segment(chan, axidma_segment); 937 } 938 } else { 939 list_for_each_entry_safe(aximcdma_segment, aximcdma_next, 940 &desc->segments, node) { 941 list_del(&aximcdma_segment->node); 942 xilinx_mcdma_free_tx_segment(chan, aximcdma_segment); 943 } 944 } 945 946 kfree(desc); 947 } 948 949 /* Required functions */ 950 951 /** 952 * xilinx_dma_free_desc_list - Free descriptors list 953 * @chan: Driver specific DMA channel 954 * @list: List to parse and delete the descriptor 955 */ 956 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan, 957 struct list_head *list) 958 { 959 struct xilinx_dma_tx_descriptor *desc, *next; 960 961 list_for_each_entry_safe(desc, next, list, node) { 962 list_del(&desc->node); 963 xilinx_dma_free_tx_descriptor(chan, desc); 964 } 965 } 966 967 /** 968 * xilinx_dma_free_descriptors - Free channel descriptors 969 * @chan: Driver specific DMA channel 970 */ 971 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan) 972 { 973 unsigned long flags; 974 975 spin_lock_irqsave(&chan->lock, flags); 976 977 xilinx_dma_free_desc_list(chan, &chan->done_list); 978 xilinx_dma_free_desc_list(chan, &chan->active_list); 979 xilinx_dma_free_desc_list(chan, &chan->pending_list); 980 981 spin_unlock_irqrestore(&chan->lock, flags); 982 } 983 984 /** 985 * xilinx_dma_free_chan_resources - Free channel resources 986 * @dchan: DMA channel 987 */ 988 static void xilinx_dma_free_chan_resources(struct dma_chan *dchan) 989 { 990 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 991 unsigned long flags; 992 993 dev_dbg(chan->dev, "Free all channel resources.\n"); 994 995 xilinx_dma_free_descriptors(chan); 996 997 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 998 spin_lock_irqsave(&chan->lock, flags); 999 INIT_LIST_HEAD(&chan->free_seg_list); 1000 spin_unlock_irqrestore(&chan->lock, flags); 1001 1002 /* Free memory that is allocated for BD */ 1003 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * 1004 XILINX_DMA_NUM_DESCS, chan->seg_v, 1005 chan->seg_p); 1006 1007 /* Free Memory that is allocated for cyclic DMA Mode */ 1008 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v), 1009 chan->cyclic_seg_v, chan->cyclic_seg_p); 1010 } 1011 1012 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 1013 spin_lock_irqsave(&chan->lock, flags); 1014 INIT_LIST_HEAD(&chan->free_seg_list); 1015 spin_unlock_irqrestore(&chan->lock, flags); 1016 1017 /* Free memory that is allocated for BD */ 1018 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) * 1019 XILINX_DMA_NUM_DESCS, chan->seg_mv, 1020 chan->seg_p); 1021 } 1022 1023 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA && 1024 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) { 1025 dma_pool_destroy(chan->desc_pool); 1026 chan->desc_pool = NULL; 1027 } 1028 1029 } 1030 1031 /** 1032 * xilinx_dma_get_residue - Compute residue for a given descriptor 1033 * @chan: Driver specific dma channel 1034 * @desc: dma transaction descriptor 1035 * 1036 * Return: The number of residue bytes for the descriptor. 1037 */ 1038 static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan, 1039 struct xilinx_dma_tx_descriptor *desc) 1040 { 1041 struct xilinx_cdma_tx_segment *cdma_seg; 1042 struct xilinx_axidma_tx_segment *axidma_seg; 1043 struct xilinx_aximcdma_tx_segment *aximcdma_seg; 1044 struct xilinx_cdma_desc_hw *cdma_hw; 1045 struct xilinx_axidma_desc_hw *axidma_hw; 1046 struct xilinx_aximcdma_desc_hw *aximcdma_hw; 1047 struct list_head *entry; 1048 u32 residue = 0; 1049 1050 list_for_each(entry, &desc->segments) { 1051 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 1052 cdma_seg = list_entry(entry, 1053 struct xilinx_cdma_tx_segment, 1054 node); 1055 cdma_hw = &cdma_seg->hw; 1056 residue += (cdma_hw->control & chan->xdev->max_buffer_len) - 1057 (cdma_hw->status & chan->xdev->max_buffer_len); 1058 } else if (chan->xdev->dma_config->dmatype == 1059 XDMA_TYPE_AXIDMA) { 1060 axidma_seg = list_entry(entry, 1061 struct xilinx_axidma_tx_segment, 1062 node); 1063 axidma_hw = &axidma_seg->hw; 1064 residue += (axidma_hw->control & chan->xdev->max_buffer_len) - 1065 (axidma_hw->status & chan->xdev->max_buffer_len); 1066 } else { 1067 aximcdma_seg = 1068 list_entry(entry, 1069 struct xilinx_aximcdma_tx_segment, 1070 node); 1071 aximcdma_hw = &aximcdma_seg->hw; 1072 residue += aximcdma_hw->control & chan->xdev->max_buffer_len; 1073 if (chan->direction == DMA_DEV_TO_MEM) 1074 residue -= aximcdma_hw->s2mm_status & chan->xdev->max_buffer_len; 1075 else 1076 residue -= aximcdma_hw->mm2s_status & chan->xdev->max_buffer_len; 1077 } 1078 } 1079 1080 return residue; 1081 } 1082 1083 static u32 1084 xilinx_dma_get_residue_axidma_direct_s2mm(struct xilinx_dma_chan *chan, 1085 struct xilinx_dma_tx_descriptor *desc) 1086 { 1087 struct xilinx_axidma_tx_segment *seg; 1088 struct xilinx_axidma_desc_hw *hw; 1089 u32 finished_len; 1090 1091 finished_len = dma_ctrl_read(chan, XILINX_DMA_REG_BTT); 1092 1093 seg = list_first_entry(&desc->segments, struct xilinx_axidma_tx_segment, 1094 node); 1095 1096 hw = &seg->hw; 1097 1098 return hw->control - finished_len; 1099 } 1100 1101 /** 1102 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback 1103 * @chan: Driver specific dma channel 1104 * @desc: dma transaction descriptor 1105 * @flags: flags for spin lock 1106 */ 1107 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan, 1108 struct xilinx_dma_tx_descriptor *desc, 1109 unsigned long *flags) 1110 { 1111 struct dmaengine_desc_callback cb; 1112 1113 dmaengine_desc_get_callback(&desc->async_tx, &cb); 1114 if (dmaengine_desc_callback_valid(&cb)) { 1115 spin_unlock_irqrestore(&chan->lock, *flags); 1116 dmaengine_desc_callback_invoke(&cb, NULL); 1117 spin_lock_irqsave(&chan->lock, *flags); 1118 } 1119 } 1120 1121 /** 1122 * xilinx_dma_chan_desc_cleanup - Clean channel descriptors 1123 * @chan: Driver specific DMA channel 1124 */ 1125 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan) 1126 { 1127 struct xilinx_dma_tx_descriptor *desc, *next; 1128 unsigned long flags; 1129 1130 spin_lock_irqsave(&chan->lock, flags); 1131 1132 list_for_each_entry_safe(desc, next, &chan->done_list, node) { 1133 struct dmaengine_result result; 1134 1135 if (desc->cyclic) { 1136 xilinx_dma_chan_handle_cyclic(chan, desc, &flags); 1137 break; 1138 } 1139 1140 /* Remove from the list of running transactions */ 1141 list_del(&desc->node); 1142 1143 if (unlikely(desc->err)) { 1144 if (chan->direction == DMA_DEV_TO_MEM) 1145 result.result = DMA_TRANS_READ_FAILED; 1146 else 1147 result.result = DMA_TRANS_WRITE_FAILED; 1148 } else { 1149 result.result = DMA_TRANS_NOERROR; 1150 } 1151 1152 result.residue = desc->residue; 1153 1154 /* Run the link descriptor callback function */ 1155 spin_unlock_irqrestore(&chan->lock, flags); 1156 dmaengine_desc_get_callback_invoke(&desc->async_tx, &result); 1157 spin_lock_irqsave(&chan->lock, flags); 1158 1159 /* Run any dependencies, then free the descriptor */ 1160 dma_run_dependencies(&desc->async_tx); 1161 xilinx_dma_free_tx_descriptor(chan, desc); 1162 1163 /* 1164 * While we ran a callback the user called a terminate function, 1165 * which takes care of cleaning up any remaining descriptors 1166 */ 1167 if (chan->terminating) 1168 break; 1169 } 1170 1171 spin_unlock_irqrestore(&chan->lock, flags); 1172 } 1173 1174 /** 1175 * xilinx_dma_do_tasklet - Schedule completion tasklet 1176 * @t: Pointer to the Xilinx DMA channel structure 1177 */ 1178 static void xilinx_dma_do_tasklet(struct tasklet_struct *t) 1179 { 1180 struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet); 1181 1182 xilinx_dma_chan_desc_cleanup(chan); 1183 } 1184 1185 /** 1186 * xilinx_dma_alloc_chan_resources - Allocate channel resources 1187 * @dchan: DMA channel 1188 * 1189 * Return: '0' on success and failure value on error 1190 */ 1191 static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) 1192 { 1193 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1194 int i; 1195 1196 /* Has this channel already been allocated? */ 1197 if (chan->desc_pool) 1198 return 0; 1199 1200 /* 1201 * We need the descriptor to be aligned to 64bytes 1202 * for meeting Xilinx VDMA specification requirement. 1203 */ 1204 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1205 /* Allocate the buffer descriptors. */ 1206 chan->seg_v = dma_alloc_coherent(chan->dev, 1207 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS, 1208 &chan->seg_p, GFP_KERNEL); 1209 if (!chan->seg_v) { 1210 dev_err(chan->dev, 1211 "unable to allocate channel %d descriptors\n", 1212 chan->id); 1213 return -ENOMEM; 1214 } 1215 /* 1216 * For cyclic DMA mode we need to program the tail Descriptor 1217 * register with a value which is not a part of the BD chain 1218 * so allocating a desc segment during channel allocation for 1219 * programming tail descriptor. 1220 */ 1221 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev, 1222 sizeof(*chan->cyclic_seg_v), 1223 &chan->cyclic_seg_p, 1224 GFP_KERNEL); 1225 if (!chan->cyclic_seg_v) { 1226 dev_err(chan->dev, 1227 "unable to allocate desc segment for cyclic DMA\n"); 1228 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * 1229 XILINX_DMA_NUM_DESCS, chan->seg_v, 1230 chan->seg_p); 1231 return -ENOMEM; 1232 } 1233 chan->cyclic_seg_v->phys = chan->cyclic_seg_p; 1234 1235 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { 1236 chan->seg_v[i].hw.next_desc = 1237 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) * 1238 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1239 chan->seg_v[i].hw.next_desc_msb = 1240 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) * 1241 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1242 chan->seg_v[i].phys = chan->seg_p + 1243 sizeof(*chan->seg_v) * i; 1244 list_add_tail(&chan->seg_v[i].node, 1245 &chan->free_seg_list); 1246 } 1247 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 1248 /* Allocate the buffer descriptors. */ 1249 chan->seg_mv = dma_alloc_coherent(chan->dev, 1250 sizeof(*chan->seg_mv) * 1251 XILINX_DMA_NUM_DESCS, 1252 &chan->seg_p, GFP_KERNEL); 1253 if (!chan->seg_mv) { 1254 dev_err(chan->dev, 1255 "unable to allocate channel %d descriptors\n", 1256 chan->id); 1257 return -ENOMEM; 1258 } 1259 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { 1260 chan->seg_mv[i].hw.next_desc = 1261 lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * 1262 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1263 chan->seg_mv[i].hw.next_desc_msb = 1264 upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * 1265 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1266 chan->seg_mv[i].phys = chan->seg_p + 1267 sizeof(*chan->seg_mv) * i; 1268 list_add_tail(&chan->seg_mv[i].node, 1269 &chan->free_seg_list); 1270 } 1271 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 1272 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool", 1273 chan->dev, 1274 sizeof(struct xilinx_cdma_tx_segment), 1275 __alignof__(struct xilinx_cdma_tx_segment), 1276 0); 1277 } else { 1278 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool", 1279 chan->dev, 1280 sizeof(struct xilinx_vdma_tx_segment), 1281 __alignof__(struct xilinx_vdma_tx_segment), 1282 0); 1283 } 1284 1285 if (!chan->desc_pool && 1286 ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) && 1287 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) { 1288 dev_err(chan->dev, 1289 "unable to allocate channel %d descriptor pool\n", 1290 chan->id); 1291 return -ENOMEM; 1292 } 1293 1294 dma_cookie_init(dchan); 1295 1296 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) 1297 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1298 XILINX_CDMA_CR_SGMODE); 1299 1300 return 0; 1301 } 1302 1303 /** 1304 * xilinx_dma_calc_copysize - Calculate the amount of data to copy 1305 * @chan: Driver specific DMA channel 1306 * @size: Total data that needs to be copied 1307 * @done: Amount of data that has been already copied 1308 * 1309 * Return: Amount of data that has to be copied 1310 */ 1311 static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, 1312 int size, int done) 1313 { 1314 size_t copy; 1315 1316 copy = min_t(size_t, size - done, 1317 chan->xdev->max_buffer_len); 1318 1319 if ((copy + done < size) && 1320 chan->xdev->common.copy_align) { 1321 /* 1322 * If this is not the last descriptor, make sure 1323 * the next one will be properly aligned 1324 */ 1325 copy = rounddown(copy, 1326 (1 << chan->xdev->common.copy_align)); 1327 } 1328 return copy; 1329 } 1330 1331 /** 1332 * xilinx_dma_tx_status - Get DMA transaction status 1333 * @dchan: DMA channel 1334 * @cookie: Transaction identifier 1335 * @txstate: Transaction state 1336 * 1337 * Return: DMA transaction status 1338 */ 1339 static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan, 1340 dma_cookie_t cookie, 1341 struct dma_tx_state *txstate) 1342 { 1343 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1344 struct xilinx_dma_tx_descriptor *desc; 1345 enum dma_status ret; 1346 unsigned long flags; 1347 u32 residue = 0; 1348 1349 ret = dma_cookie_status(dchan, cookie, txstate); 1350 if (ret == DMA_COMPLETE || !txstate) 1351 return ret; 1352 1353 spin_lock_irqsave(&chan->lock, flags); 1354 if (!list_empty(&chan->active_list)) { 1355 desc = list_last_entry(&chan->active_list, 1356 struct xilinx_dma_tx_descriptor, node); 1357 /* 1358 * VDMA and simple mode do not support residue reporting, so the 1359 * residue field will always be 0. 1360 */ 1361 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA) 1362 residue = xilinx_dma_get_residue(chan, desc); 1363 } 1364 spin_unlock_irqrestore(&chan->lock, flags); 1365 1366 dma_set_residue(txstate, residue); 1367 1368 return ret; 1369 } 1370 1371 /** 1372 * xilinx_dma_stop_transfer - Halt DMA channel 1373 * @chan: Driver specific DMA channel 1374 * 1375 * Return: '0' on success and failure value on error 1376 */ 1377 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan) 1378 { 1379 u32 val; 1380 1381 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); 1382 1383 /* Wait for the hardware to halt */ 1384 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1385 val & XILINX_DMA_DMASR_HALTED, 1386 XILINX_DMA_POLL_DELAY_US, 1387 XILINX_DMA_POLL_TIMEOUT_US); 1388 } 1389 1390 /** 1391 * xilinx_cdma_stop_transfer - Wait for the current transfer to complete 1392 * @chan: Driver specific DMA channel 1393 * 1394 * Return: '0' on success and failure value on error 1395 */ 1396 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan) 1397 { 1398 u32 val; 1399 1400 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1401 val & XILINX_DMA_DMASR_IDLE, 1402 XILINX_DMA_POLL_DELAY_US, 1403 XILINX_DMA_POLL_TIMEOUT_US); 1404 } 1405 1406 /** 1407 * xilinx_dma_start - Start DMA channel 1408 * @chan: Driver specific DMA channel 1409 */ 1410 static void xilinx_dma_start(struct xilinx_dma_chan *chan) 1411 { 1412 int err; 1413 u32 val; 1414 1415 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); 1416 1417 /* Wait for the hardware to start */ 1418 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1419 !(val & XILINX_DMA_DMASR_HALTED), 1420 XILINX_DMA_POLL_DELAY_US, 1421 XILINX_DMA_POLL_TIMEOUT_US); 1422 1423 if (err) { 1424 dev_err(chan->dev, "Cannot start channel %p: %x\n", 1425 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); 1426 1427 chan->err = true; 1428 } 1429 } 1430 1431 /** 1432 * xilinx_vdma_start_transfer - Starts VDMA transfer 1433 * @chan: Driver specific channel struct pointer 1434 */ 1435 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) 1436 { 1437 struct xilinx_vdma_config *config = &chan->config; 1438 struct xilinx_dma_tx_descriptor *desc; 1439 u32 reg, j; 1440 struct xilinx_vdma_tx_segment *segment, *last = NULL; 1441 int i = 0; 1442 1443 /* This function was invoked with lock held */ 1444 if (chan->err) 1445 return; 1446 1447 if (!chan->idle) 1448 return; 1449 1450 if (list_empty(&chan->pending_list)) 1451 return; 1452 1453 desc = list_first_entry(&chan->pending_list, 1454 struct xilinx_dma_tx_descriptor, node); 1455 1456 /* Configure the hardware using info in the config structure */ 1457 if (chan->has_vflip) { 1458 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP); 1459 reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP; 1460 reg |= config->vflip_en; 1461 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP, 1462 reg); 1463 } 1464 1465 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 1466 1467 if (config->frm_cnt_en) 1468 reg |= XILINX_DMA_DMACR_FRAMECNT_EN; 1469 else 1470 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; 1471 1472 /* If not parking, enable circular mode */ 1473 if (config->park) 1474 reg &= ~XILINX_DMA_DMACR_CIRC_EN; 1475 else 1476 reg |= XILINX_DMA_DMACR_CIRC_EN; 1477 1478 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 1479 1480 if (config->park) { 1481 j = chan->desc_submitcount; 1482 reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR); 1483 if (chan->direction == DMA_MEM_TO_DEV) { 1484 reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK; 1485 reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT; 1486 } else { 1487 reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK; 1488 reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT; 1489 } 1490 dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg); 1491 } 1492 1493 /* Start the hardware */ 1494 xilinx_dma_start(chan); 1495 1496 if (chan->err) 1497 return; 1498 1499 /* Start the transfer */ 1500 if (chan->desc_submitcount < chan->num_frms) 1501 i = chan->desc_submitcount; 1502 1503 list_for_each_entry(segment, &desc->segments, node) { 1504 if (chan->ext_addr) 1505 vdma_desc_write_64(chan, 1506 XILINX_VDMA_REG_START_ADDRESS_64(i++), 1507 segment->hw.buf_addr, 1508 segment->hw.buf_addr_msb); 1509 else 1510 vdma_desc_write(chan, 1511 XILINX_VDMA_REG_START_ADDRESS(i++), 1512 segment->hw.buf_addr); 1513 1514 last = segment; 1515 } 1516 1517 if (!last) 1518 return; 1519 1520 /* HW expects these parameters to be same for one transaction */ 1521 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); 1522 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, 1523 last->hw.stride); 1524 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); 1525 1526 chan->desc_submitcount++; 1527 chan->desc_pendingcount--; 1528 list_move_tail(&desc->node, &chan->active_list); 1529 if (chan->desc_submitcount == chan->num_frms) 1530 chan->desc_submitcount = 0; 1531 1532 chan->idle = false; 1533 } 1534 1535 /** 1536 * xilinx_cdma_start_transfer - Starts cdma transfer 1537 * @chan: Driver specific channel struct pointer 1538 */ 1539 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan) 1540 { 1541 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1542 struct xilinx_cdma_tx_segment *tail_segment; 1543 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR); 1544 1545 if (chan->err) 1546 return; 1547 1548 if (!chan->idle) 1549 return; 1550 1551 if (list_empty(&chan->pending_list)) 1552 return; 1553 1554 head_desc = list_first_entry(&chan->pending_list, 1555 struct xilinx_dma_tx_descriptor, node); 1556 tail_desc = list_last_entry(&chan->pending_list, 1557 struct xilinx_dma_tx_descriptor, node); 1558 tail_segment = list_last_entry(&tail_desc->segments, 1559 struct xilinx_cdma_tx_segment, node); 1560 1561 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { 1562 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX; 1563 ctrl_reg |= chan->desc_pendingcount << 1564 XILINX_DMA_CR_COALESCE_SHIFT; 1565 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg); 1566 } 1567 1568 if (chan->has_sg) { 1569 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 1570 XILINX_CDMA_CR_SGMODE); 1571 1572 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1573 XILINX_CDMA_CR_SGMODE); 1574 1575 xilinx_write(chan, XILINX_DMA_REG_CURDESC, 1576 head_desc->async_tx.phys); 1577 1578 /* Update tail ptr register which will start the transfer */ 1579 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1580 tail_segment->phys); 1581 } else { 1582 /* In simple mode */ 1583 struct xilinx_cdma_tx_segment *segment; 1584 struct xilinx_cdma_desc_hw *hw; 1585 1586 segment = list_first_entry(&head_desc->segments, 1587 struct xilinx_cdma_tx_segment, 1588 node); 1589 1590 hw = &segment->hw; 1591 1592 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, 1593 xilinx_prep_dma_addr_t(hw->src_addr)); 1594 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, 1595 xilinx_prep_dma_addr_t(hw->dest_addr)); 1596 1597 /* Start the transfer */ 1598 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, 1599 hw->control & chan->xdev->max_buffer_len); 1600 } 1601 1602 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1603 chan->desc_pendingcount = 0; 1604 chan->idle = false; 1605 } 1606 1607 /** 1608 * xilinx_dma_start_transfer - Starts DMA transfer 1609 * @chan: Driver specific channel struct pointer 1610 */ 1611 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) 1612 { 1613 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1614 struct xilinx_axidma_tx_segment *tail_segment; 1615 u32 reg; 1616 1617 if (chan->err) 1618 return; 1619 1620 if (list_empty(&chan->pending_list)) { 1621 if (chan->cyclic) { 1622 struct xilinx_dma_tx_descriptor *desc; 1623 struct list_head *entry; 1624 1625 desc = list_last_entry(&chan->done_list, 1626 struct xilinx_dma_tx_descriptor, node); 1627 list_for_each(entry, &desc->segments) { 1628 struct xilinx_axidma_tx_segment *axidma_seg; 1629 struct xilinx_axidma_desc_hw *axidma_hw; 1630 axidma_seg = list_entry(entry, 1631 struct xilinx_axidma_tx_segment, 1632 node); 1633 axidma_hw = &axidma_seg->hw; 1634 axidma_hw->status = 0; 1635 } 1636 1637 list_splice_tail_init(&chan->done_list, &chan->active_list); 1638 chan->desc_pendingcount = 0; 1639 chan->idle = false; 1640 } 1641 return; 1642 } 1643 1644 /* 1645 * Direct (non-SG) mode has no descriptor queue: writing the BTT 1646 * register launches a transfer immediately, so a new transfer must 1647 * not be programmed while one is in flight. Keep such transfers 1648 * serialized. SG mode supports chaining onto a running transfer via 1649 * tail-pointer extension, so it is allowed to proceed when busy. 1650 */ 1651 if (!chan->has_sg && !chan->idle) 1652 return; 1653 1654 head_desc = list_first_entry(&chan->pending_list, 1655 struct xilinx_dma_tx_descriptor, node); 1656 tail_desc = list_last_entry(&chan->pending_list, 1657 struct xilinx_dma_tx_descriptor, node); 1658 tail_segment = list_last_entry(&tail_desc->segments, 1659 struct xilinx_axidma_tx_segment, node); 1660 1661 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 1662 1663 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { 1664 reg &= ~XILINX_DMA_CR_COALESCE_MAX; 1665 reg |= chan->desc_pendingcount << 1666 XILINX_DMA_CR_COALESCE_SHIFT; 1667 } 1668 1669 if (chan->has_sg && list_empty(&chan->active_list)) 1670 xilinx_write(chan, XILINX_DMA_REG_CURDESC, 1671 head_desc->async_tx.phys); 1672 reg &= ~XILINX_DMA_CR_DELAY_MAX; 1673 reg |= chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; 1674 reg |= XILINX_DMA_DMAXR_ALL_IRQ_MASK; 1675 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 1676 1677 if (chan->idle) 1678 xilinx_dma_start(chan); 1679 1680 if (chan->err) 1681 return; 1682 1683 /* Start the transfer */ 1684 if (chan->has_sg) { 1685 if (chan->cyclic) 1686 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1687 chan->cyclic_seg_v->phys); 1688 else 1689 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1690 tail_segment->phys); 1691 } else { 1692 struct xilinx_axidma_tx_segment *segment; 1693 struct xilinx_axidma_desc_hw *hw; 1694 1695 segment = list_first_entry(&head_desc->segments, 1696 struct xilinx_axidma_tx_segment, 1697 node); 1698 hw = &segment->hw; 1699 1700 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, 1701 xilinx_prep_dma_addr_t(hw->buf_addr)); 1702 1703 /* Start the transfer */ 1704 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, 1705 hw->control & chan->xdev->max_buffer_len); 1706 } 1707 1708 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1709 chan->desc_pendingcount = 0; 1710 chan->idle = false; 1711 } 1712 1713 /** 1714 * xilinx_mcdma_start_transfer - Starts MCDMA transfer 1715 * @chan: Driver specific channel struct pointer 1716 */ 1717 static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan) 1718 { 1719 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1720 struct xilinx_aximcdma_tx_segment *tail_segment; 1721 u32 reg; 1722 1723 /* 1724 * lock has been held by calling functions, so we don't need it 1725 * to take it here again. 1726 */ 1727 1728 if (chan->err) 1729 return; 1730 1731 if (list_empty(&chan->pending_list)) 1732 return; 1733 1734 head_desc = list_first_entry(&chan->pending_list, 1735 struct xilinx_dma_tx_descriptor, node); 1736 tail_desc = list_last_entry(&chan->pending_list, 1737 struct xilinx_dma_tx_descriptor, node); 1738 tail_segment = list_last_entry(&tail_desc->segments, 1739 struct xilinx_aximcdma_tx_segment, node); 1740 1741 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); 1742 1743 if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) { 1744 reg &= ~XILINX_MCDMA_COALESCE_MASK; 1745 reg |= chan->desc_pendingcount << 1746 XILINX_MCDMA_COALESCE_SHIFT; 1747 } 1748 1749 reg |= XILINX_MCDMA_IRQ_ALL_MASK; 1750 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); 1751 1752 /* Program current descriptor */ 1753 if (chan->has_sg && list_empty(&chan->active_list)) 1754 xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), 1755 head_desc->async_tx.phys); 1756 1757 /* Program channel enable register */ 1758 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET); 1759 reg |= BIT(chan->tdest); 1760 dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg); 1761 1762 /* Start the fetch of BDs for the channel */ 1763 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); 1764 reg |= XILINX_MCDMA_CR_RUNSTOP_MASK; 1765 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); 1766 1767 if (chan->idle) 1768 xilinx_dma_start(chan); 1769 1770 if (chan->err) 1771 return; 1772 1773 /* Start the transfer */ 1774 xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest), 1775 tail_segment->phys); 1776 1777 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1778 chan->desc_pendingcount = 0; 1779 chan->idle = false; 1780 } 1781 1782 /** 1783 * xilinx_dma_issue_pending - Issue pending transactions 1784 * @dchan: DMA channel 1785 */ 1786 static void xilinx_dma_issue_pending(struct dma_chan *dchan) 1787 { 1788 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1789 unsigned long flags; 1790 1791 spin_lock_irqsave(&chan->lock, flags); 1792 chan->start_transfer(chan); 1793 spin_unlock_irqrestore(&chan->lock, flags); 1794 } 1795 1796 /** 1797 * xilinx_dma_device_config - Configure the DMA channel 1798 * @dchan: DMA channel 1799 * @config: channel configuration 1800 * 1801 * Return: 0 always. 1802 */ 1803 static int xilinx_dma_device_config(struct dma_chan *dchan, 1804 struct dma_slave_config *config) 1805 { 1806 return 0; 1807 } 1808 1809 /** 1810 * xilinx_dma_complete_descriptor - Mark the active descriptor as complete 1811 * @chan : xilinx DMA channel 1812 * 1813 * CONTEXT: hardirq 1814 */ 1815 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) 1816 { 1817 struct xilinx_dma_tx_descriptor *desc, *next; 1818 1819 /* This function was invoked with lock held */ 1820 if (list_empty(&chan->active_list)) 1821 return; 1822 1823 list_for_each_entry_safe(desc, next, &chan->active_list, node) { 1824 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1825 struct xilinx_axidma_tx_segment *seg; 1826 1827 seg = list_last_entry(&desc->segments, 1828 struct xilinx_axidma_tx_segment, node); 1829 if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg) 1830 break; 1831 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 1832 struct xilinx_aximcdma_tx_segment *seg; 1833 u32 status; 1834 1835 seg = list_last_entry(&desc->segments, 1836 struct xilinx_aximcdma_tx_segment, 1837 node); 1838 status = (chan->direction == DMA_DEV_TO_MEM) ? 1839 seg->hw.s2mm_status : seg->hw.mm2s_status; 1840 if (!(status & XILINX_DMA_BD_COMP_MASK)) 1841 break; 1842 } 1843 if (chan->has_sg && chan->xdev->dma_config->dmatype != 1844 XDMA_TYPE_VDMA) 1845 desc->residue = xilinx_dma_get_residue(chan, desc); 1846 else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA && 1847 chan->direction == DMA_DEV_TO_MEM && !chan->has_sg) 1848 desc->residue = xilinx_dma_get_residue_axidma_direct_s2mm(chan, desc); 1849 else 1850 desc->residue = 0; 1851 desc->err = chan->err; 1852 1853 list_del(&desc->node); 1854 if (!desc->cyclic) 1855 dma_cookie_complete(&desc->async_tx); 1856 list_add_tail(&desc->node, &chan->done_list); 1857 } 1858 } 1859 1860 /** 1861 * xilinx_dma_reset - Reset DMA channel 1862 * @chan: Driver specific DMA channel 1863 * 1864 * Return: '0' on success and failure value on error 1865 */ 1866 static int xilinx_dma_reset(struct xilinx_dma_chan *chan) 1867 { 1868 int err; 1869 u32 tmp; 1870 1871 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET); 1872 1873 /* Wait for the hardware to finish reset */ 1874 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp, 1875 !(tmp & XILINX_DMA_DMACR_RESET), 1876 XILINX_DMA_POLL_DELAY_US, 1877 XILINX_DMA_POLL_TIMEOUT_US); 1878 1879 if (err) { 1880 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", 1881 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR), 1882 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); 1883 return -ETIMEDOUT; 1884 } 1885 1886 chan->err = false; 1887 chan->idle = true; 1888 chan->desc_pendingcount = 0; 1889 chan->desc_submitcount = 0; 1890 1891 return err; 1892 } 1893 1894 /** 1895 * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts 1896 * @chan: Driver specific DMA channel 1897 * 1898 * Return: '0' on success and failure value on error 1899 */ 1900 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan) 1901 { 1902 int err; 1903 1904 /* Reset VDMA */ 1905 err = xilinx_dma_reset(chan); 1906 if (err) 1907 return err; 1908 1909 /* Enable interrupts */ 1910 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1911 XILINX_DMA_DMAXR_ALL_IRQ_MASK); 1912 1913 return 0; 1914 } 1915 1916 /** 1917 * xilinx_mcdma_irq_handler - MCDMA Interrupt handler 1918 * @irq: IRQ number 1919 * @data: Pointer to the Xilinx MCDMA channel structure 1920 * 1921 * Return: IRQ_HANDLED/IRQ_NONE 1922 */ 1923 static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data) 1924 { 1925 struct xilinx_dma_chan *chan = data; 1926 u32 status, ser_offset, chan_sermask, chan_offset = 0, chan_id; 1927 1928 if (chan->direction == DMA_DEV_TO_MEM) 1929 ser_offset = XILINX_MCDMA_RXINT_SER_OFFSET; 1930 else 1931 ser_offset = XILINX_MCDMA_TXINT_SER_OFFSET; 1932 1933 /* Read the channel id raising the interrupt*/ 1934 chan_sermask = dma_ctrl_read(chan, ser_offset); 1935 chan_id = ffs(chan_sermask); 1936 1937 if (!chan_id) 1938 return IRQ_NONE; 1939 1940 if (chan->direction == DMA_DEV_TO_MEM) 1941 chan_offset = chan->xdev->dma_config->max_channels / 2; 1942 1943 chan_offset = chan_offset + (chan_id - 1); 1944 chan = chan->xdev->chan[chan_offset]; 1945 /* Read the status and ack the interrupts. */ 1946 status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest)); 1947 if (!(status & XILINX_MCDMA_IRQ_ALL_MASK)) 1948 return IRQ_NONE; 1949 1950 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest), 1951 status & XILINX_MCDMA_IRQ_ALL_MASK); 1952 1953 if (status & XILINX_MCDMA_IRQ_ERR_MASK) { 1954 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n", 1955 chan, 1956 dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET), 1957 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET 1958 (chan->tdest)), 1959 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET 1960 (chan->tdest))); 1961 chan->err = true; 1962 } 1963 1964 if (status & XILINX_MCDMA_IRQ_DELAY_MASK) { 1965 /* 1966 * Device takes too long to do the transfer when user requires 1967 * responsiveness. 1968 */ 1969 dev_dbg(chan->dev, "Inter-packet latency too long\n"); 1970 } 1971 1972 if (status & XILINX_MCDMA_IRQ_IOC_MASK) { 1973 spin_lock(&chan->lock); 1974 xilinx_dma_complete_descriptor(chan); 1975 if (list_empty(&chan->active_list)) { 1976 chan->idle = true; 1977 chan->start_transfer(chan); 1978 } 1979 spin_unlock(&chan->lock); 1980 } 1981 1982 tasklet_hi_schedule(&chan->tasklet); 1983 return IRQ_HANDLED; 1984 } 1985 1986 /** 1987 * xilinx_dma_irq_handler - DMA Interrupt handler 1988 * @irq: IRQ number 1989 * @data: Pointer to the Xilinx DMA channel structure 1990 * 1991 * Return: IRQ_HANDLED/IRQ_NONE 1992 */ 1993 static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) 1994 { 1995 struct xilinx_dma_chan *chan = data; 1996 u32 status; 1997 1998 /* Read the status and ack the interrupts. */ 1999 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR); 2000 if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK)) 2001 return IRQ_NONE; 2002 2003 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, 2004 status & XILINX_DMA_DMAXR_ALL_IRQ_MASK); 2005 2006 if (status & XILINX_DMA_DMASR_ERR_IRQ) { 2007 /* 2008 * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the 2009 * error is recoverable, ignore it. Otherwise flag the error. 2010 * 2011 * Only recoverable errors can be cleared in the DMASR register, 2012 * make sure not to write to other error bits to 1. 2013 */ 2014 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK; 2015 2016 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, 2017 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK); 2018 2019 if (!chan->flush_on_fsync || 2020 (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) { 2021 dev_err(chan->dev, 2022 "Channel %p has errors %x, cdr %x tdr %x\n", 2023 chan, errors, 2024 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC), 2025 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC)); 2026 chan->err = true; 2027 } 2028 } 2029 2030 if (status & (XILINX_DMA_DMASR_FRM_CNT_IRQ | 2031 XILINX_DMA_DMASR_DLY_CNT_IRQ)) { 2032 spin_lock(&chan->lock); 2033 xilinx_dma_complete_descriptor(chan); 2034 if (list_empty(&chan->active_list)) { 2035 chan->idle = true; 2036 chan->start_transfer(chan); 2037 } 2038 spin_unlock(&chan->lock); 2039 } 2040 2041 tasklet_schedule(&chan->tasklet); 2042 return IRQ_HANDLED; 2043 } 2044 2045 /** 2046 * append_desc_queue - Queuing descriptor 2047 * @chan: Driver specific dma channel 2048 * @desc: dma transaction descriptor 2049 */ 2050 static void append_desc_queue(struct xilinx_dma_chan *chan, 2051 struct xilinx_dma_tx_descriptor *desc) 2052 { 2053 struct xilinx_vdma_tx_segment *tail_segment; 2054 struct xilinx_dma_tx_descriptor *tail_desc; 2055 struct xilinx_axidma_tx_segment *axidma_tail_segment; 2056 struct xilinx_aximcdma_tx_segment *aximcdma_tail_segment; 2057 struct xilinx_cdma_tx_segment *cdma_tail_segment; 2058 2059 if (list_empty(&chan->pending_list)) 2060 goto append; 2061 2062 /* 2063 * Add the hardware descriptor to the chain of hardware descriptors 2064 * that already exists in memory. 2065 */ 2066 tail_desc = list_last_entry(&chan->pending_list, 2067 struct xilinx_dma_tx_descriptor, node); 2068 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 2069 tail_segment = list_last_entry(&tail_desc->segments, 2070 struct xilinx_vdma_tx_segment, 2071 node); 2072 tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 2073 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 2074 cdma_tail_segment = list_last_entry(&tail_desc->segments, 2075 struct xilinx_cdma_tx_segment, 2076 node); 2077 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 2078 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 2079 axidma_tail_segment = list_last_entry(&tail_desc->segments, 2080 struct xilinx_axidma_tx_segment, 2081 node); 2082 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 2083 } else { 2084 aximcdma_tail_segment = 2085 list_last_entry(&tail_desc->segments, 2086 struct xilinx_aximcdma_tx_segment, 2087 node); 2088 aximcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 2089 } 2090 2091 /* 2092 * Add the software descriptor and all children to the list 2093 * of pending transactions 2094 */ 2095 append: 2096 list_add_tail(&desc->node, &chan->pending_list); 2097 chan->desc_pendingcount++; 2098 2099 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) 2100 && unlikely(chan->desc_pendingcount > chan->num_frms)) { 2101 dev_dbg(chan->dev, "desc pendingcount is too high\n"); 2102 chan->desc_pendingcount = chan->num_frms; 2103 } 2104 } 2105 2106 /** 2107 * xilinx_dma_tx_submit - Submit DMA transaction 2108 * @tx: Async transaction descriptor 2109 * 2110 * Return: cookie value on success and failure value on error 2111 */ 2112 static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx) 2113 { 2114 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); 2115 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); 2116 dma_cookie_t cookie; 2117 unsigned long flags; 2118 int err; 2119 2120 if (chan->cyclic) { 2121 xilinx_dma_free_tx_descriptor(chan, desc); 2122 return -EBUSY; 2123 } 2124 2125 if (chan->err) { 2126 /* 2127 * If reset fails, need to hard reset the system. 2128 * Channel is no longer functional 2129 */ 2130 err = xilinx_dma_chan_reset(chan); 2131 if (err < 0) 2132 return err; 2133 } 2134 2135 spin_lock_irqsave(&chan->lock, flags); 2136 2137 cookie = dma_cookie_assign(tx); 2138 2139 /* Put this transaction onto the tail of the pending queue */ 2140 append_desc_queue(chan, desc); 2141 2142 if (desc->cyclic) 2143 chan->cyclic = true; 2144 2145 chan->terminating = false; 2146 2147 spin_unlock_irqrestore(&chan->lock, flags); 2148 2149 return cookie; 2150 } 2151 2152 /** 2153 * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a 2154 * DMA_SLAVE transaction 2155 * @dchan: DMA channel 2156 * @xt: Interleaved template pointer 2157 * @flags: transfer ack flags 2158 * 2159 * Return: Async transaction descriptor on success and NULL on failure 2160 */ 2161 static struct dma_async_tx_descriptor * 2162 xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan, 2163 struct dma_interleaved_template *xt, 2164 unsigned long flags) 2165 { 2166 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2167 struct xilinx_dma_tx_descriptor *desc; 2168 struct xilinx_vdma_tx_segment *segment; 2169 struct xilinx_vdma_desc_hw *hw; 2170 2171 if (!is_slave_direction(xt->dir)) 2172 return NULL; 2173 2174 if (!xt->numf || !xt->sgl[0].size) 2175 return NULL; 2176 2177 if (xt->numf & ~XILINX_DMA_VSIZE_MASK || 2178 xt->sgl[0].size & ~XILINX_DMA_HSIZE_MASK) 2179 return NULL; 2180 2181 if (xt->frame_size != 1) 2182 return NULL; 2183 2184 /* Allocate a transaction descriptor. */ 2185 desc = xilinx_dma_alloc_tx_descriptor(chan); 2186 if (!desc) 2187 return NULL; 2188 2189 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2190 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2191 async_tx_ack(&desc->async_tx); 2192 2193 /* Allocate the link descriptor from DMA pool */ 2194 segment = xilinx_vdma_alloc_tx_segment(chan); 2195 if (!segment) 2196 goto error; 2197 2198 /* Fill in the hardware descriptor */ 2199 hw = &segment->hw; 2200 hw->vsize = xt->numf; 2201 hw->hsize = xt->sgl[0].size; 2202 hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) << 2203 XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT; 2204 hw->stride |= chan->config.frm_dly << 2205 XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT; 2206 2207 if (xt->dir != DMA_MEM_TO_DEV) { 2208 if (chan->ext_addr) { 2209 hw->buf_addr = lower_32_bits(xt->dst_start); 2210 hw->buf_addr_msb = upper_32_bits(xt->dst_start); 2211 } else { 2212 hw->buf_addr = xt->dst_start; 2213 } 2214 } else { 2215 if (chan->ext_addr) { 2216 hw->buf_addr = lower_32_bits(xt->src_start); 2217 hw->buf_addr_msb = upper_32_bits(xt->src_start); 2218 } else { 2219 hw->buf_addr = xt->src_start; 2220 } 2221 } 2222 2223 /* Insert the segment into the descriptor segments list. */ 2224 list_add_tail(&segment->node, &desc->segments); 2225 2226 /* Link the last hardware descriptor with the first. */ 2227 segment = list_first_entry(&desc->segments, 2228 struct xilinx_vdma_tx_segment, node); 2229 desc->async_tx.phys = segment->phys; 2230 2231 return &desc->async_tx; 2232 2233 error: 2234 xilinx_dma_free_tx_descriptor(chan, desc); 2235 return NULL; 2236 } 2237 2238 /** 2239 * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction 2240 * @dchan: DMA channel 2241 * @dma_dst: destination address 2242 * @dma_src: source address 2243 * @len: transfer length 2244 * @flags: transfer ack flags 2245 * 2246 * Return: Async transaction descriptor on success and NULL on failure 2247 */ 2248 static struct dma_async_tx_descriptor * 2249 xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst, 2250 dma_addr_t dma_src, size_t len, unsigned long flags) 2251 { 2252 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2253 struct xilinx_dma_tx_descriptor *desc; 2254 struct xilinx_cdma_tx_segment *segment; 2255 struct xilinx_cdma_desc_hw *hw; 2256 2257 if (!len || len > chan->xdev->max_buffer_len) 2258 return NULL; 2259 2260 desc = xilinx_dma_alloc_tx_descriptor(chan); 2261 if (!desc) 2262 return NULL; 2263 2264 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2265 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2266 2267 /* Allocate the link descriptor from DMA pool */ 2268 segment = xilinx_cdma_alloc_tx_segment(chan); 2269 if (!segment) 2270 goto error; 2271 2272 hw = &segment->hw; 2273 hw->control = len; 2274 hw->src_addr = dma_src; 2275 hw->dest_addr = dma_dst; 2276 if (chan->ext_addr) { 2277 hw->src_addr_msb = upper_32_bits(dma_src); 2278 hw->dest_addr_msb = upper_32_bits(dma_dst); 2279 } 2280 2281 /* Insert the segment into the descriptor segments list. */ 2282 list_add_tail(&segment->node, &desc->segments); 2283 2284 desc->async_tx.phys = segment->phys; 2285 hw->next_desc = segment->phys; 2286 2287 return &desc->async_tx; 2288 2289 error: 2290 xilinx_dma_free_tx_descriptor(chan, desc); 2291 return NULL; 2292 } 2293 2294 /** 2295 * xilinx_dma_prep_peripheral_dma_vec - prepare descriptors for a DMA_SLAVE 2296 * transaction from DMA vectors 2297 * @dchan: DMA channel 2298 * @vecs: Array of DMA vectors that should be transferred 2299 * @nb: number of entries in @vecs 2300 * @direction: DMA direction 2301 * @flags: transfer ack flags 2302 * 2303 * Return: Async transaction descriptor on success and NULL on failure 2304 */ 2305 static struct dma_async_tx_descriptor *xilinx_dma_prep_peripheral_dma_vec( 2306 struct dma_chan *dchan, const struct dma_vec *vecs, size_t nb, 2307 enum dma_transfer_direction direction, unsigned long flags) 2308 { 2309 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2310 struct xilinx_dma_tx_descriptor *desc; 2311 struct xilinx_axidma_tx_segment *segment, *head, *prev = NULL; 2312 size_t copy; 2313 size_t sg_used; 2314 unsigned int i; 2315 2316 if (!is_slave_direction(direction) || direction != chan->direction) 2317 return NULL; 2318 2319 desc = xilinx_dma_alloc_tx_descriptor(chan); 2320 if (!desc) 2321 return NULL; 2322 2323 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2324 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2325 2326 /* Build transactions using information from DMA vectors */ 2327 for (i = 0; i < nb; i++) { 2328 sg_used = 0; 2329 2330 /* Loop until the entire dma_vec entry is used */ 2331 while (sg_used < vecs[i].len) { 2332 struct xilinx_axidma_desc_hw *hw; 2333 2334 /* Get a free segment */ 2335 segment = xilinx_axidma_alloc_tx_segment(chan); 2336 if (!segment) 2337 goto error; 2338 2339 /* 2340 * Calculate the maximum number of bytes to transfer, 2341 * making sure it is less than the hw limit 2342 */ 2343 copy = xilinx_dma_calc_copysize(chan, vecs[i].len, 2344 sg_used); 2345 hw = &segment->hw; 2346 2347 /* Fill in the descriptor */ 2348 xilinx_axidma_buf(chan, hw, vecs[i].addr, sg_used, 0); 2349 hw->control = copy; 2350 2351 if (prev) 2352 prev->hw.next_desc = segment->phys; 2353 2354 prev = segment; 2355 sg_used += copy; 2356 2357 /* 2358 * Insert the segment into the descriptor segments 2359 * list. 2360 */ 2361 list_add_tail(&segment->node, &desc->segments); 2362 } 2363 } 2364 2365 head = list_first_entry(&desc->segments, struct xilinx_axidma_tx_segment, node); 2366 desc->async_tx.phys = head->phys; 2367 2368 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2369 if (chan->direction == DMA_MEM_TO_DEV) { 2370 segment->hw.control |= XILINX_DMA_BD_SOP; 2371 segment = list_last_entry(&desc->segments, 2372 struct xilinx_axidma_tx_segment, 2373 node); 2374 segment->hw.control |= XILINX_DMA_BD_EOP; 2375 } 2376 2377 if (chan->xdev->has_axistream_connected) 2378 desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; 2379 2380 return &desc->async_tx; 2381 2382 error: 2383 xilinx_dma_free_tx_descriptor(chan, desc); 2384 return NULL; 2385 } 2386 2387 /** 2388 * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 2389 * @dchan: DMA channel 2390 * @sgl: scatterlist to transfer to/from 2391 * @sg_len: number of entries in @scatterlist 2392 * @direction: DMA direction 2393 * @flags: transfer ack flags 2394 * @context: APP words of the descriptor 2395 * 2396 * Return: Async transaction descriptor on success and NULL on failure 2397 */ 2398 static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( 2399 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, 2400 enum dma_transfer_direction direction, unsigned long flags, 2401 void *context) 2402 { 2403 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2404 struct xilinx_dma_tx_descriptor *desc; 2405 struct xilinx_axidma_tx_segment *segment = NULL; 2406 u32 *app_w = (u32 *)context; 2407 struct scatterlist *sg; 2408 size_t copy; 2409 size_t sg_used; 2410 unsigned int i; 2411 2412 if (!is_slave_direction(direction)) 2413 return NULL; 2414 2415 /* Allocate a transaction descriptor. */ 2416 desc = xilinx_dma_alloc_tx_descriptor(chan); 2417 if (!desc) 2418 return NULL; 2419 2420 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2421 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2422 2423 /* Build transactions using information in the scatter gather list */ 2424 for_each_sg(sgl, sg, sg_len, i) { 2425 sg_used = 0; 2426 2427 /* Loop until the entire scatterlist entry is used */ 2428 while (sg_used < sg_dma_len(sg)) { 2429 struct xilinx_axidma_desc_hw *hw; 2430 2431 /* Get a free segment */ 2432 segment = xilinx_axidma_alloc_tx_segment(chan); 2433 if (!segment) 2434 goto error; 2435 2436 /* 2437 * Calculate the maximum number of bytes to transfer, 2438 * making sure it is less than the hw limit 2439 */ 2440 copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), 2441 sg_used); 2442 hw = &segment->hw; 2443 2444 /* Fill in the descriptor */ 2445 xilinx_axidma_buf(chan, hw, sg_dma_address(sg), 2446 sg_used, 0); 2447 2448 hw->control = copy; 2449 2450 if (chan->direction == DMA_MEM_TO_DEV) { 2451 if (app_w) 2452 memcpy(hw->app, app_w, sizeof(u32) * 2453 XILINX_DMA_NUM_APP_WORDS); 2454 } 2455 2456 sg_used += copy; 2457 2458 /* 2459 * Insert the segment into the descriptor segments 2460 * list. 2461 */ 2462 list_add_tail(&segment->node, &desc->segments); 2463 } 2464 } 2465 2466 segment = list_first_entry(&desc->segments, 2467 struct xilinx_axidma_tx_segment, node); 2468 desc->async_tx.phys = segment->phys; 2469 2470 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2471 if (chan->direction == DMA_MEM_TO_DEV) { 2472 segment->hw.control |= XILINX_DMA_BD_SOP; 2473 segment = list_last_entry(&desc->segments, 2474 struct xilinx_axidma_tx_segment, 2475 node); 2476 segment->hw.control |= XILINX_DMA_BD_EOP; 2477 } 2478 2479 if (chan->xdev->has_axistream_connected) 2480 desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; 2481 2482 return &desc->async_tx; 2483 2484 error: 2485 xilinx_dma_free_tx_descriptor(chan, desc); 2486 return NULL; 2487 } 2488 2489 /** 2490 * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction 2491 * @dchan: DMA channel 2492 * @buf_addr: Physical address of the buffer 2493 * @buf_len: Total length of the cyclic buffers 2494 * @period_len: length of individual cyclic buffer 2495 * @direction: DMA direction 2496 * @flags: transfer ack flags 2497 * 2498 * Return: Async transaction descriptor on success and NULL on failure 2499 */ 2500 static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( 2501 struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len, 2502 size_t period_len, enum dma_transfer_direction direction, 2503 unsigned long flags) 2504 { 2505 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2506 struct xilinx_dma_tx_descriptor *desc; 2507 struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL; 2508 size_t copy, sg_used; 2509 unsigned int num_periods; 2510 int i; 2511 u32 reg; 2512 2513 if (!period_len) 2514 return NULL; 2515 2516 num_periods = buf_len / period_len; 2517 2518 if (!num_periods) 2519 return NULL; 2520 2521 if (!is_slave_direction(direction)) 2522 return NULL; 2523 2524 /* Allocate a transaction descriptor. */ 2525 desc = xilinx_dma_alloc_tx_descriptor(chan); 2526 if (!desc) 2527 return NULL; 2528 2529 chan->direction = direction; 2530 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2531 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2532 2533 for (i = 0; i < num_periods; ++i) { 2534 sg_used = 0; 2535 2536 while (sg_used < period_len) { 2537 struct xilinx_axidma_desc_hw *hw; 2538 2539 /* Get a free segment */ 2540 segment = xilinx_axidma_alloc_tx_segment(chan); 2541 if (!segment) 2542 goto error; 2543 2544 /* 2545 * Calculate the maximum number of bytes to transfer, 2546 * making sure it is less than the hw limit 2547 */ 2548 copy = xilinx_dma_calc_copysize(chan, period_len, 2549 sg_used); 2550 hw = &segment->hw; 2551 xilinx_axidma_buf(chan, hw, buf_addr, sg_used, 2552 period_len * i); 2553 hw->control = copy; 2554 2555 if (prev) 2556 prev->hw.next_desc = segment->phys; 2557 2558 prev = segment; 2559 sg_used += copy; 2560 2561 /* 2562 * Insert the segment into the descriptor segments 2563 * list. 2564 */ 2565 list_add_tail(&segment->node, &desc->segments); 2566 } 2567 } 2568 2569 head_segment = list_first_entry(&desc->segments, 2570 struct xilinx_axidma_tx_segment, node); 2571 desc->async_tx.phys = head_segment->phys; 2572 2573 desc->cyclic = true; 2574 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2575 reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK; 2576 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 2577 2578 segment = list_last_entry(&desc->segments, 2579 struct xilinx_axidma_tx_segment, 2580 node); 2581 segment->hw.next_desc = (u32) head_segment->phys; 2582 2583 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2584 if (direction == DMA_MEM_TO_DEV) { 2585 head_segment->hw.control |= XILINX_DMA_BD_SOP; 2586 segment->hw.control |= XILINX_DMA_BD_EOP; 2587 } 2588 2589 return &desc->async_tx; 2590 2591 error: 2592 xilinx_dma_free_tx_descriptor(chan, desc); 2593 return NULL; 2594 } 2595 2596 /** 2597 * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 2598 * @dchan: DMA channel 2599 * @sgl: scatterlist to transfer to/from 2600 * @sg_len: number of entries in @scatterlist 2601 * @direction: DMA direction 2602 * @flags: transfer ack flags 2603 * @context: APP words of the descriptor 2604 * 2605 * Return: Async transaction descriptor on success and NULL on failure 2606 */ 2607 static struct dma_async_tx_descriptor * 2608 xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, 2609 unsigned int sg_len, 2610 enum dma_transfer_direction direction, 2611 unsigned long flags, void *context) 2612 { 2613 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2614 struct xilinx_dma_tx_descriptor *desc; 2615 struct xilinx_aximcdma_tx_segment *segment = NULL; 2616 u32 *app_w = (u32 *)context; 2617 struct scatterlist *sg; 2618 size_t copy; 2619 size_t sg_used; 2620 unsigned int i; 2621 2622 if (!is_slave_direction(direction)) 2623 return NULL; 2624 2625 /* Allocate a transaction descriptor. */ 2626 desc = xilinx_dma_alloc_tx_descriptor(chan); 2627 if (!desc) 2628 return NULL; 2629 2630 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2631 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2632 2633 /* Build transactions using information in the scatter gather list */ 2634 for_each_sg(sgl, sg, sg_len, i) { 2635 sg_used = 0; 2636 2637 /* Loop until the entire scatterlist entry is used */ 2638 while (sg_used < sg_dma_len(sg)) { 2639 struct xilinx_aximcdma_desc_hw *hw; 2640 2641 /* Get a free segment */ 2642 segment = xilinx_aximcdma_alloc_tx_segment(chan); 2643 if (!segment) 2644 goto error; 2645 2646 /* 2647 * Calculate the maximum number of bytes to transfer, 2648 * making sure it is less than the hw limit 2649 */ 2650 copy = min_t(size_t, sg_dma_len(sg) - sg_used, 2651 chan->xdev->max_buffer_len); 2652 hw = &segment->hw; 2653 2654 /* Fill in the descriptor */ 2655 xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg), 2656 sg_used); 2657 hw->control = copy; 2658 2659 if (chan->direction == DMA_MEM_TO_DEV && app_w) { 2660 memcpy(hw->app, app_w, sizeof(u32) * 2661 XILINX_DMA_NUM_APP_WORDS); 2662 } 2663 2664 sg_used += copy; 2665 /* 2666 * Insert the segment into the descriptor segments 2667 * list. 2668 */ 2669 list_add_tail(&segment->node, &desc->segments); 2670 } 2671 } 2672 2673 segment = list_first_entry(&desc->segments, 2674 struct xilinx_aximcdma_tx_segment, node); 2675 desc->async_tx.phys = segment->phys; 2676 2677 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2678 if (chan->direction == DMA_MEM_TO_DEV) { 2679 segment->hw.control |= XILINX_MCDMA_BD_SOP; 2680 segment = list_last_entry(&desc->segments, 2681 struct xilinx_aximcdma_tx_segment, 2682 node); 2683 segment->hw.control |= XILINX_MCDMA_BD_EOP; 2684 } 2685 2686 if (chan->xdev->has_axistream_connected) 2687 desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; 2688 2689 return &desc->async_tx; 2690 2691 error: 2692 xilinx_dma_free_tx_descriptor(chan, desc); 2693 2694 return NULL; 2695 } 2696 2697 /** 2698 * xilinx_dma_terminate_all - Halt the channel and free descriptors 2699 * @dchan: Driver specific DMA Channel pointer 2700 * 2701 * Return: '0' always. 2702 */ 2703 static int xilinx_dma_terminate_all(struct dma_chan *dchan) 2704 { 2705 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2706 u32 reg; 2707 int err; 2708 2709 if (!chan->cyclic) { 2710 err = chan->stop_transfer(chan); 2711 if (err) { 2712 dev_err(chan->dev, "Cannot stop channel %p: %x\n", 2713 chan, dma_ctrl_read(chan, 2714 XILINX_DMA_REG_DMASR)); 2715 chan->err = true; 2716 } 2717 } 2718 2719 xilinx_dma_chan_reset(chan); 2720 /* Remove and free all of the descriptors in the lists */ 2721 chan->terminating = true; 2722 xilinx_dma_free_descriptors(chan); 2723 chan->idle = true; 2724 2725 if (chan->cyclic) { 2726 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2727 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK; 2728 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 2729 chan->cyclic = false; 2730 } 2731 2732 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) 2733 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 2734 XILINX_CDMA_CR_SGMODE); 2735 2736 return 0; 2737 } 2738 2739 static void xilinx_dma_synchronize(struct dma_chan *dchan) 2740 { 2741 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2742 2743 tasklet_kill(&chan->tasklet); 2744 } 2745 2746 /** 2747 * xilinx_vdma_channel_set_config - Configure VDMA channel 2748 * Run-time configuration for Axi VDMA, supports: 2749 * . halt the channel 2750 * . configure interrupt coalescing and inter-packet delay threshold 2751 * . start/stop parking 2752 * . enable genlock 2753 * 2754 * @dchan: DMA channel 2755 * @cfg: VDMA device configuration pointer 2756 * 2757 * Return: '0' on success and failure value on error 2758 */ 2759 int xilinx_vdma_channel_set_config(struct dma_chan *dchan, 2760 struct xilinx_vdma_config *cfg) 2761 { 2762 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2763 u32 dmacr; 2764 2765 if (cfg->reset) 2766 return xilinx_dma_chan_reset(chan); 2767 2768 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2769 2770 chan->config.frm_dly = cfg->frm_dly; 2771 chan->config.park = cfg->park; 2772 2773 /* genlock settings */ 2774 chan->config.gen_lock = cfg->gen_lock; 2775 chan->config.master = cfg->master; 2776 2777 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN; 2778 if (cfg->gen_lock && chan->genlock) { 2779 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN; 2780 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK; 2781 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; 2782 } 2783 2784 chan->config.frm_cnt_en = cfg->frm_cnt_en; 2785 chan->config.vflip_en = cfg->vflip_en; 2786 2787 if (cfg->park) 2788 chan->config.park_frm = cfg->park_frm; 2789 else 2790 chan->config.park_frm = -1; 2791 2792 chan->config.coalesc = cfg->coalesc; 2793 chan->config.delay = cfg->delay; 2794 2795 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) { 2796 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK; 2797 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT; 2798 chan->config.coalesc = cfg->coalesc; 2799 } 2800 2801 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) { 2802 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK; 2803 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; 2804 chan->config.delay = cfg->delay; 2805 } 2806 2807 /* FSync Source selection */ 2808 dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK; 2809 dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT; 2810 2811 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr); 2812 2813 return 0; 2814 } 2815 EXPORT_SYMBOL(xilinx_vdma_channel_set_config); 2816 2817 /* ----------------------------------------------------------------------------- 2818 * Probe and remove 2819 */ 2820 2821 /** 2822 * xilinx_dma_chan_remove - Per Channel remove function 2823 * @chan: Driver specific DMA channel 2824 */ 2825 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan) 2826 { 2827 /* Disable all interrupts */ 2828 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 2829 XILINX_DMA_DMAXR_ALL_IRQ_MASK); 2830 2831 if (chan->irq > 0) 2832 free_irq(chan->irq, chan); 2833 2834 tasklet_kill(&chan->tasklet); 2835 2836 list_del(&chan->common.device_node); 2837 } 2838 2839 static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2840 struct clk **tx_clk, struct clk **rx_clk, 2841 struct clk **sg_clk, struct clk **tmp_clk) 2842 { 2843 int err; 2844 2845 *tmp_clk = NULL; 2846 2847 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2848 if (IS_ERR(*axi_clk)) 2849 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2850 2851 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); 2852 if (IS_ERR(*tx_clk)) 2853 *tx_clk = NULL; 2854 2855 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); 2856 if (IS_ERR(*rx_clk)) 2857 *rx_clk = NULL; 2858 2859 *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk"); 2860 if (IS_ERR(*sg_clk)) 2861 *sg_clk = NULL; 2862 2863 err = clk_prepare_enable(*axi_clk); 2864 if (err) { 2865 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); 2866 return err; 2867 } 2868 2869 err = clk_prepare_enable(*tx_clk); 2870 if (err) { 2871 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); 2872 goto err_disable_axiclk; 2873 } 2874 2875 err = clk_prepare_enable(*rx_clk); 2876 if (err) { 2877 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); 2878 goto err_disable_txclk; 2879 } 2880 2881 err = clk_prepare_enable(*sg_clk); 2882 if (err) { 2883 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err); 2884 goto err_disable_rxclk; 2885 } 2886 2887 return 0; 2888 2889 err_disable_rxclk: 2890 clk_disable_unprepare(*rx_clk); 2891 err_disable_txclk: 2892 clk_disable_unprepare(*tx_clk); 2893 err_disable_axiclk: 2894 clk_disable_unprepare(*axi_clk); 2895 2896 return err; 2897 } 2898 2899 static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2900 struct clk **dev_clk, struct clk **tmp_clk, 2901 struct clk **tmp1_clk, struct clk **tmp2_clk) 2902 { 2903 int err; 2904 2905 *tmp_clk = NULL; 2906 *tmp1_clk = NULL; 2907 *tmp2_clk = NULL; 2908 2909 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2910 if (IS_ERR(*axi_clk)) 2911 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2912 2913 *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk"); 2914 if (IS_ERR(*dev_clk)) 2915 return dev_err_probe(&pdev->dev, PTR_ERR(*dev_clk), "failed to get dev_clk\n"); 2916 2917 err = clk_prepare_enable(*axi_clk); 2918 if (err) { 2919 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); 2920 return err; 2921 } 2922 2923 err = clk_prepare_enable(*dev_clk); 2924 if (err) { 2925 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err); 2926 goto err_disable_axiclk; 2927 } 2928 2929 return 0; 2930 2931 err_disable_axiclk: 2932 clk_disable_unprepare(*axi_clk); 2933 2934 return err; 2935 } 2936 2937 static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2938 struct clk **tx_clk, struct clk **txs_clk, 2939 struct clk **rx_clk, struct clk **rxs_clk) 2940 { 2941 int err; 2942 2943 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2944 if (IS_ERR(*axi_clk)) 2945 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2946 2947 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); 2948 if (IS_ERR(*tx_clk)) 2949 *tx_clk = NULL; 2950 2951 *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk"); 2952 if (IS_ERR(*txs_clk)) 2953 *txs_clk = NULL; 2954 2955 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); 2956 if (IS_ERR(*rx_clk)) 2957 *rx_clk = NULL; 2958 2959 *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk"); 2960 if (IS_ERR(*rxs_clk)) 2961 *rxs_clk = NULL; 2962 2963 err = clk_prepare_enable(*axi_clk); 2964 if (err) { 2965 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", 2966 err); 2967 return err; 2968 } 2969 2970 err = clk_prepare_enable(*tx_clk); 2971 if (err) { 2972 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); 2973 goto err_disable_axiclk; 2974 } 2975 2976 err = clk_prepare_enable(*txs_clk); 2977 if (err) { 2978 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err); 2979 goto err_disable_txclk; 2980 } 2981 2982 err = clk_prepare_enable(*rx_clk); 2983 if (err) { 2984 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); 2985 goto err_disable_txsclk; 2986 } 2987 2988 err = clk_prepare_enable(*rxs_clk); 2989 if (err) { 2990 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err); 2991 goto err_disable_rxclk; 2992 } 2993 2994 return 0; 2995 2996 err_disable_rxclk: 2997 clk_disable_unprepare(*rx_clk); 2998 err_disable_txsclk: 2999 clk_disable_unprepare(*txs_clk); 3000 err_disable_txclk: 3001 clk_disable_unprepare(*tx_clk); 3002 err_disable_axiclk: 3003 clk_disable_unprepare(*axi_clk); 3004 3005 return err; 3006 } 3007 3008 static void xdma_disable_allclks(struct xilinx_dma_device *xdev) 3009 { 3010 clk_disable_unprepare(xdev->rxs_clk); 3011 clk_disable_unprepare(xdev->rx_clk); 3012 clk_disable_unprepare(xdev->txs_clk); 3013 clk_disable_unprepare(xdev->tx_clk); 3014 clk_disable_unprepare(xdev->axi_clk); 3015 } 3016 3017 /** 3018 * xilinx_dma_chan_probe - Per Channel Probing 3019 * It get channel features from the device tree entry and 3020 * initialize special channel handling routines 3021 * 3022 * @xdev: Driver specific device structure 3023 * @node: Device node 3024 * 3025 * Return: '0' on success and failure value on error 3026 */ 3027 static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, 3028 struct device_node *node) 3029 { 3030 struct xilinx_dma_chan *chan; 3031 bool has_dre = false; 3032 u32 value, width; 3033 int err; 3034 3035 /* Allocate and initialize the channel structure */ 3036 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); 3037 if (!chan) 3038 return -ENOMEM; 3039 3040 chan->dev = xdev->dev; 3041 chan->xdev = xdev; 3042 chan->desc_pendingcount = 0x0; 3043 chan->ext_addr = xdev->ext_addr; 3044 /* This variable ensures that descriptors are not 3045 * Submitted when dma engine is in progress. This variable is 3046 * Added to avoid polling for a bit in the status register to 3047 * Know dma state in the driver hot path. 3048 */ 3049 chan->idle = true; 3050 3051 spin_lock_init(&chan->lock); 3052 INIT_LIST_HEAD(&chan->pending_list); 3053 INIT_LIST_HEAD(&chan->done_list); 3054 INIT_LIST_HEAD(&chan->active_list); 3055 INIT_LIST_HEAD(&chan->free_seg_list); 3056 3057 /* Retrieve the channel properties from the device tree */ 3058 has_dre = of_property_read_bool(node, "xlnx,include-dre"); 3059 3060 of_property_read_u8(node, "xlnx,irq-delay", &chan->irq_delay); 3061 3062 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); 3063 3064 err = of_property_read_u32(node, "xlnx,datawidth", &value); 3065 if (err) { 3066 dev_err(xdev->dev, "missing xlnx,datawidth property\n"); 3067 return err; 3068 } 3069 width = value >> 3; /* Convert bits to bytes */ 3070 3071 /* If data width is greater than 8 bytes, DRE is not in hw */ 3072 if (width > 8) 3073 has_dre = false; 3074 3075 if (!has_dre) 3076 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1); 3077 3078 if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") || 3079 of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") || 3080 of_device_is_compatible(node, "xlnx,axi-cdma-channel")) { 3081 chan->direction = DMA_MEM_TO_DEV; 3082 chan->id = xdev->mm2s_chan_id++; 3083 chan->tdest = chan->id; 3084 3085 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; 3086 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3087 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; 3088 chan->config.park = 1; 3089 3090 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || 3091 xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S) 3092 chan->flush_on_fsync = true; 3093 } 3094 } else if (of_device_is_compatible(node, 3095 "xlnx,axi-vdma-s2mm-channel") || 3096 of_device_is_compatible(node, 3097 "xlnx,axi-dma-s2mm-channel")) { 3098 chan->direction = DMA_DEV_TO_MEM; 3099 chan->id = xdev->s2mm_chan_id++; 3100 chan->tdest = chan->id - xdev->dma_config->max_channels / 2; 3101 chan->has_vflip = of_property_read_bool(node, 3102 "xlnx,enable-vert-flip"); 3103 if (chan->has_vflip) { 3104 chan->config.vflip_en = dma_read(chan, 3105 XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) & 3106 XILINX_VDMA_ENABLE_VERTICAL_FLIP; 3107 } 3108 3109 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) 3110 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET; 3111 else 3112 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; 3113 3114 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3115 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; 3116 chan->config.park = 1; 3117 3118 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || 3119 xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM) 3120 chan->flush_on_fsync = true; 3121 } 3122 } else { 3123 dev_err(xdev->dev, "Invalid channel compatible node\n"); 3124 return -EINVAL; 3125 } 3126 3127 xdev->common.directions |= BIT(chan->direction); 3128 3129 /* Request the interrupt */ 3130 chan->irq = of_irq_get(node, chan->tdest); 3131 if (chan->irq < 0) 3132 return dev_err_probe(xdev->dev, chan->irq, "failed to get irq\n"); 3133 err = request_irq(chan->irq, xdev->dma_config->irq_handler, 3134 IRQF_SHARED, "xilinx-dma-controller", chan); 3135 if (err) { 3136 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq); 3137 return err; 3138 } 3139 3140 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 3141 chan->start_transfer = xilinx_dma_start_transfer; 3142 chan->stop_transfer = xilinx_dma_stop_transfer; 3143 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3144 chan->start_transfer = xilinx_mcdma_start_transfer; 3145 chan->stop_transfer = xilinx_dma_stop_transfer; 3146 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 3147 chan->start_transfer = xilinx_cdma_start_transfer; 3148 chan->stop_transfer = xilinx_cdma_stop_transfer; 3149 } else { 3150 chan->start_transfer = xilinx_vdma_start_transfer; 3151 chan->stop_transfer = xilinx_dma_stop_transfer; 3152 } 3153 3154 /* check if SG is enabled (only for AXIDMA, AXIMCDMA, and CDMA) */ 3155 if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) { 3156 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA || 3157 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & 3158 XILINX_DMA_DMASR_SG_MASK) 3159 chan->has_sg = true; 3160 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id, 3161 str_enabled_disabled(chan->has_sg)); 3162 } 3163 3164 /* Initialize the tasklet */ 3165 tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet); 3166 3167 /* 3168 * Initialize the DMA channel and add it to the DMA engine channels 3169 * list. 3170 */ 3171 chan->common.device = &xdev->common; 3172 3173 list_add_tail(&chan->common.device_node, &xdev->common.channels); 3174 xdev->chan[chan->id] = chan; 3175 3176 /* Reset the channel */ 3177 err = xilinx_dma_chan_reset(chan); 3178 if (err < 0) { 3179 dev_err(xdev->dev, "Reset channel failed\n"); 3180 return err; 3181 } 3182 3183 return 0; 3184 } 3185 3186 /** 3187 * xilinx_dma_child_probe - Per child node probe 3188 * It get number of dma-channels per child node from 3189 * device-tree and initializes all the channels. 3190 * 3191 * @xdev: Driver specific device structure 3192 * @node: Device node 3193 * 3194 * Return: '0' on success and failure value on error. 3195 */ 3196 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev, 3197 struct device_node *node) 3198 { 3199 int ret, i; 3200 u32 nr_channels = 1; 3201 3202 ret = of_property_read_u32(node, "dma-channels", &nr_channels); 3203 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0) 3204 dev_warn(xdev->dev, "missing dma-channels property\n"); 3205 3206 for (i = 0; i < nr_channels; i++) { 3207 ret = xilinx_dma_chan_probe(xdev, node); 3208 if (ret) 3209 return ret; 3210 } 3211 3212 return 0; 3213 } 3214 3215 /** 3216 * of_dma_xilinx_xlate - Translation function 3217 * @dma_spec: Pointer to DMA specifier as found in the device tree 3218 * @ofdma: Pointer to DMA controller data 3219 * 3220 * Return: DMA channel pointer on success and NULL on error 3221 */ 3222 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, 3223 struct of_dma *ofdma) 3224 { 3225 struct xilinx_dma_device *xdev = ofdma->of_dma_data; 3226 int chan_id = dma_spec->args[0]; 3227 3228 if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id]) 3229 return NULL; 3230 3231 return dma_get_slave_channel(&xdev->chan[chan_id]->common); 3232 } 3233 3234 static const struct xilinx_dma_config axidma_config = { 3235 .dmatype = XDMA_TYPE_AXIDMA, 3236 .clk_init = axidma_clk_init, 3237 .irq_handler = xilinx_dma_irq_handler, 3238 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE, 3239 }; 3240 3241 static const struct xilinx_dma_config aximcdma_config = { 3242 .dmatype = XDMA_TYPE_AXIMCDMA, 3243 .clk_init = axidma_clk_init, 3244 .irq_handler = xilinx_mcdma_irq_handler, 3245 .max_channels = XILINX_MCDMA_MAX_CHANS_PER_DEVICE, 3246 }; 3247 static const struct xilinx_dma_config axicdma_config = { 3248 .dmatype = XDMA_TYPE_CDMA, 3249 .clk_init = axicdma_clk_init, 3250 .irq_handler = xilinx_dma_irq_handler, 3251 .max_channels = XILINX_CDMA_MAX_CHANS_PER_DEVICE, 3252 }; 3253 3254 static const struct xilinx_dma_config axivdma_config = { 3255 .dmatype = XDMA_TYPE_VDMA, 3256 .clk_init = axivdma_clk_init, 3257 .irq_handler = xilinx_dma_irq_handler, 3258 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE, 3259 }; 3260 3261 static const struct of_device_id xilinx_dma_of_ids[] = { 3262 { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config }, 3263 { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config }, 3264 { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config }, 3265 { .compatible = "xlnx,axi-mcdma-1.00.a", .data = &aximcdma_config }, 3266 {} 3267 }; 3268 MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids); 3269 3270 /** 3271 * xilinx_dma_probe - Driver probe function 3272 * @pdev: Pointer to the platform_device structure 3273 * 3274 * Return: '0' on success and failure value on error 3275 */ 3276 static int xilinx_dma_probe(struct platform_device *pdev) 3277 { 3278 int (*clk_init)(struct platform_device *, struct clk **, struct clk **, 3279 struct clk **, struct clk **, struct clk **) 3280 = axivdma_clk_init; 3281 struct device_node *node = pdev->dev.of_node; 3282 struct xilinx_dma_device *xdev; 3283 struct device_node *np = pdev->dev.of_node; 3284 u32 num_frames, addr_width = XILINX_DMA_DFAULT_ADDRWIDTH, len_width; 3285 int i, err; 3286 3287 /* Allocate and initialize the DMA engine structure */ 3288 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); 3289 if (!xdev) 3290 return -ENOMEM; 3291 3292 xdev->dev = &pdev->dev; 3293 if (np) { 3294 const struct of_device_id *match; 3295 3296 match = of_match_node(xilinx_dma_of_ids, np); 3297 if (match && match->data) { 3298 xdev->dma_config = match->data; 3299 clk_init = xdev->dma_config->clk_init; 3300 } 3301 } 3302 3303 err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk, 3304 &xdev->rx_clk, &xdev->rxs_clk); 3305 if (err) 3306 return err; 3307 3308 /* Request and map I/O memory */ 3309 xdev->regs = devm_platform_ioremap_resource(pdev, 0); 3310 if (IS_ERR(xdev->regs)) { 3311 err = PTR_ERR(xdev->regs); 3312 goto disable_clks; 3313 } 3314 /* Retrieve the DMA engine properties from the device tree */ 3315 xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); 3316 xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2; 3317 3318 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA || 3319 xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3320 if (!of_property_read_u32(node, "xlnx,sg-length-width", 3321 &len_width)) { 3322 if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN || 3323 len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) { 3324 dev_warn(xdev->dev, 3325 "invalid xlnx,sg-length-width property value. Using default width\n"); 3326 } else { 3327 if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX) 3328 dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n"); 3329 xdev->max_buffer_len = 3330 GENMASK(len_width - 1, 0); 3331 } 3332 } 3333 } 3334 3335 dma_set_max_seg_size(xdev->dev, xdev->max_buffer_len); 3336 3337 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA || 3338 xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3339 xdev->has_axistream_connected = 3340 of_property_read_bool(node, "xlnx,axistream-connected"); 3341 } 3342 3343 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3344 err = of_property_read_u32(node, "xlnx,num-fstores", 3345 &num_frames); 3346 if (err < 0) { 3347 dev_err(xdev->dev, 3348 "missing xlnx,num-fstores property\n"); 3349 goto disable_clks; 3350 } 3351 3352 err = of_property_read_u32(node, "xlnx,flush-fsync", 3353 &xdev->flush_on_fsync); 3354 if (err < 0) 3355 dev_warn(xdev->dev, 3356 "missing xlnx,flush-fsync property\n"); 3357 } 3358 3359 err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width); 3360 if (err < 0) 3361 dev_warn(xdev->dev, 3362 "missing xlnx,addrwidth property, using default value %d\n", 3363 XILINX_DMA_DFAULT_ADDRWIDTH); 3364 3365 if (addr_width > 32) 3366 xdev->ext_addr = true; 3367 else 3368 xdev->ext_addr = false; 3369 3370 /* Set metadata mode */ 3371 if (xdev->has_axistream_connected) 3372 xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE; 3373 3374 /* Set the dma mask bits */ 3375 err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); 3376 if (err < 0) { 3377 dev_err(xdev->dev, "DMA mask error %d\n", err); 3378 goto disable_clks; 3379 } 3380 3381 /* Initialize the DMA engine */ 3382 xdev->common.dev = &pdev->dev; 3383 3384 INIT_LIST_HEAD(&xdev->common.channels); 3385 if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) { 3386 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask); 3387 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); 3388 } 3389 3390 xdev->common.device_alloc_chan_resources = 3391 xilinx_dma_alloc_chan_resources; 3392 xdev->common.device_free_chan_resources = 3393 xilinx_dma_free_chan_resources; 3394 xdev->common.device_terminate_all = xilinx_dma_terminate_all; 3395 xdev->common.device_synchronize = xilinx_dma_synchronize; 3396 xdev->common.device_tx_status = xilinx_dma_tx_status; 3397 xdev->common.device_issue_pending = xilinx_dma_issue_pending; 3398 xdev->common.device_config = xilinx_dma_device_config; 3399 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 3400 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask); 3401 xdev->common.device_prep_peripheral_dma_vec = xilinx_dma_prep_peripheral_dma_vec; 3402 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg; 3403 xdev->common.device_prep_dma_cyclic = 3404 xilinx_dma_prep_dma_cyclic; 3405 /* Residue calculation is supported by only AXI DMA and CDMA */ 3406 xdev->common.residue_granularity = 3407 DMA_RESIDUE_GRANULARITY_SEGMENT; 3408 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 3409 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask); 3410 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy; 3411 /* Residue calculation is supported by only AXI DMA and CDMA */ 3412 xdev->common.residue_granularity = 3413 DMA_RESIDUE_GRANULARITY_SEGMENT; 3414 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3415 xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg; 3416 } else { 3417 xdev->common.device_prep_interleaved_dma = 3418 xilinx_vdma_dma_prep_interleaved; 3419 } 3420 3421 platform_set_drvdata(pdev, xdev); 3422 3423 /* Initialize the channels */ 3424 for_each_child_of_node_scoped(node, child) { 3425 err = xilinx_dma_child_probe(xdev, child); 3426 if (err < 0) 3427 goto error; 3428 } 3429 3430 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3431 for (i = 0; i < xdev->dma_config->max_channels; i++) 3432 if (xdev->chan[i]) 3433 xdev->chan[i]->num_frms = num_frames; 3434 } 3435 3436 /* Register the DMA engine with the core */ 3437 err = dma_async_device_register(&xdev->common); 3438 if (err) { 3439 dev_err(xdev->dev, "failed to register the dma device\n"); 3440 goto error; 3441 } 3442 3443 err = of_dma_controller_register(node, of_dma_xilinx_xlate, 3444 xdev); 3445 if (err < 0) { 3446 dev_err(&pdev->dev, "Unable to register DMA to DT\n"); 3447 dma_async_device_unregister(&xdev->common); 3448 goto error; 3449 } 3450 3451 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) 3452 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n"); 3453 else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) 3454 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n"); 3455 else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) 3456 dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n"); 3457 else 3458 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n"); 3459 3460 return 0; 3461 3462 error: 3463 for (i = 0; i < xdev->dma_config->max_channels; i++) 3464 if (xdev->chan[i]) 3465 xilinx_dma_chan_remove(xdev->chan[i]); 3466 disable_clks: 3467 xdma_disable_allclks(xdev); 3468 3469 return err; 3470 } 3471 3472 /** 3473 * xilinx_dma_remove - Driver remove function 3474 * @pdev: Pointer to the platform_device structure 3475 */ 3476 static void xilinx_dma_remove(struct platform_device *pdev) 3477 { 3478 struct xilinx_dma_device *xdev = platform_get_drvdata(pdev); 3479 int i; 3480 3481 of_dma_controller_free(pdev->dev.of_node); 3482 3483 dma_async_device_unregister(&xdev->common); 3484 3485 for (i = 0; i < xdev->dma_config->max_channels; i++) 3486 if (xdev->chan[i]) 3487 xilinx_dma_chan_remove(xdev->chan[i]); 3488 3489 xdma_disable_allclks(xdev); 3490 } 3491 3492 static struct platform_driver xilinx_vdma_driver = { 3493 .driver = { 3494 .name = "xilinx-vdma", 3495 .of_match_table = xilinx_dma_of_ids, 3496 }, 3497 .probe = xilinx_dma_probe, 3498 .remove = xilinx_dma_remove, 3499 }; 3500 3501 module_platform_driver(xilinx_vdma_driver); 3502 3503 MODULE_AUTHOR("Xilinx, Inc."); 3504 MODULE_DESCRIPTION("Xilinx VDMA driver"); 3505 MODULE_LICENSE("GPL v2"); 3506