1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 #include <linux/iopoll.h> 26 #include <linux/time.h> 27 28 #include <drm/drm_fixed.h> 29 #include <drm/drm_print.h> 30 #include <drm/intel/intel_pcode_regs.h> 31 #include <drm/intel/pci_config.h> 32 #include <drm/intel/step.h> 33 34 #include "hsw_ips.h" 35 #include "intel_atomic.h" 36 #include "intel_audio.h" 37 #include "intel_cdclk.h" 38 #include "intel_crtc.h" 39 #include "intel_dbuf_bw.h" 40 #include "intel_de.h" 41 #include "intel_display_regs.h" 42 #include "intel_display_types.h" 43 #include "intel_display_utils.h" 44 #include "intel_display_wa.h" 45 #include "intel_dram.h" 46 #include "intel_mchbar.h" 47 #include "intel_parent.h" 48 #include "intel_plane.h" 49 #include "intel_psr.h" 50 #include "intel_vdsc.h" 51 #include "skl_watermark.h" 52 #include "skl_watermark_regs.h" 53 #include "vlv_clock.h" 54 #include "vlv_dsi.h" 55 #include "vlv_sideband.h" 56 57 /** 58 * DOC: CDCLK / RAWCLK 59 * 60 * The display engine uses several different clocks to do its work. There 61 * are two main clocks involved that aren't directly related to the actual 62 * pixel clock or any symbol/bit clock of the actual output port. These 63 * are the core display clock (CDCLK) and RAWCLK. 64 * 65 * CDCLK clocks most of the display pipe logic, and thus its frequency 66 * must be high enough to support the rate at which pixels are flowing 67 * through the pipes. Downscaling must also be accounted as that increases 68 * the effective pixel rate. 69 * 70 * On several platforms the CDCLK frequency can be changed dynamically 71 * to minimize power consumption for a given display configuration. 72 * Typically changes to the CDCLK frequency require all the display pipes 73 * to be shut down while the frequency is being changed. 74 * 75 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 76 * DMC will not change the active CDCLK frequency however, so that part 77 * will still be performed by the driver directly. 78 * 79 * There are multiple components involved in the generation of the CDCLK 80 * frequency: 81 * 82 * - We have the CDCLK PLL, which generates an output clock based on a 83 * reference clock and a ratio parameter. 84 * - The CD2X Divider, which divides the output of the PLL based on a 85 * divisor selected from a set of pre-defined choices. 86 * - The CD2X Squasher, which further divides the output based on a 87 * waveform represented as a sequence of bits where each zero 88 * "squashes out" a clock cycle. 89 * - And, finally, a fixed divider that divides the output frequency by 2. 90 * 91 * As such, the resulting CDCLK frequency can be calculated with the 92 * following formula: 93 * 94 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 95 * 96 * , where vco is the frequency generated by the PLL; cd2x_div 97 * represents the CD2X Divider; sq_len and sq_div are the bit length 98 * and the number of high bits for the CD2X Squasher waveform, respectively; 99 * and 2 represents the fixed divider. 100 * 101 * Note that some older platforms do not contain the CD2X Divider 102 * and/or CD2X Squasher, in which case we can ignore their respective 103 * factors in the formula above. 104 * 105 * Several methods exist to change the CDCLK frequency, which ones are 106 * supported depends on the platform: 107 * 108 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive. 109 * - CD2X divider update. Single pipe can be active as the divider update 110 * can be synchronized with the pipe's start of vblank. 111 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active. 112 * - Squash waveform update. Pipes can be active. 113 * - Crawl and squash can also be done back to back. Pipes can be active. 114 * 115 * RAWCLK is a fixed frequency clock, often used by various auxiliary 116 * blocks such as AUX CH or backlight PWM. Hence the only thing we 117 * really need to know about RAWCLK is its frequency so that various 118 * dividers can be programmed correctly. 119 */ 120 121 struct intel_cdclk_state { 122 struct intel_global_state base; 123 124 /* 125 * Logical configuration of cdclk (used for all scaling, 126 * watermark, etc. calculations and checks). This is 127 * computed as if all enabled crtcs were active. 128 */ 129 struct intel_cdclk_config logical; 130 131 /* 132 * Actual configuration of cdclk, can be different from the 133 * logical configuration only when all crtc's are DPMS off. 134 */ 135 struct intel_cdclk_config actual; 136 137 /* minimum acceptable cdclk to satisfy DBUF bandwidth requirements */ 138 int dbuf_bw_min_cdclk; 139 /* minimum acceptable cdclk for each pipe */ 140 int min_cdclk[I915_MAX_PIPES]; 141 /* minimum acceptable voltage level for each pipe */ 142 u8 min_voltage_level[I915_MAX_PIPES]; 143 144 /* pipe to which cd2x update is synchronized */ 145 enum pipe pipe; 146 147 /* forced minimum cdclk for glk+ audio w/a */ 148 int force_min_cdclk; 149 150 /* bitmask of enabled pipes */ 151 u8 enabled_pipes; 152 153 /* bitmask of active pipes */ 154 u8 active_pipes; 155 156 /* update cdclk with pipes disabled */ 157 bool disable_pipes; 158 }; 159 160 struct intel_cdclk_funcs { 161 void (*get_cdclk)(struct intel_display *display, 162 struct intel_cdclk_config *cdclk_config); 163 void (*set_cdclk)(struct intel_display *display, 164 const struct intel_cdclk_config *cdclk_config, 165 enum pipe pipe); 166 int (*pre_notify)(struct intel_display *display); 167 int (*post_notify)(struct intel_display *display, 168 const struct intel_cdclk_config *cdclk_config); 169 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 170 u8 (*calc_voltage_level)(int cdclk); 171 }; 172 173 void intel_cdclk_get_cdclk(struct intel_display *display, 174 struct intel_cdclk_config *cdclk_config) 175 { 176 display->cdclk.funcs->get_cdclk(display, cdclk_config); 177 } 178 179 static int intel_cdclk_pre_notify(struct intel_display *display) 180 { 181 int ret; 182 183 if (!display->cdclk.funcs->pre_notify) 184 return 0; 185 186 ret = display->cdclk.funcs->pre_notify(display); 187 if (ret) 188 drm_err(display->drm, 189 "Failed to inform system about start of CDCLK change (%d)\n", ret); 190 191 return ret; 192 } 193 194 static void intel_cdclk_post_notify(struct intel_display *display, 195 const struct intel_cdclk_config *cdclk_config) 196 { 197 int ret; 198 199 if (!display->cdclk.funcs->post_notify) 200 return; 201 202 ret = display->cdclk.funcs->post_notify(display, cdclk_config); 203 if (ret) 204 drm_err(display->drm, 205 "Failed to inform system about end of CDCLK change (%d)\n", ret); 206 } 207 208 static void intel_cdclk_set_cdclk(struct intel_display *display, 209 const struct intel_cdclk_config *cdclk_config, 210 enum pipe pipe) 211 { 212 if (intel_cdclk_pre_notify(display)) 213 return; 214 215 display->cdclk.funcs->set_cdclk(display, cdclk_config, pipe); 216 217 intel_cdclk_post_notify(display, cdclk_config); 218 } 219 220 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) 221 { 222 struct intel_display *display = to_intel_display(state); 223 224 return display->cdclk.funcs->modeset_calc_cdclk(state); 225 } 226 227 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, 228 int cdclk) 229 { 230 return display->cdclk.funcs->calc_voltage_level(cdclk); 231 } 232 233 static void fixed_133mhz_get_cdclk(struct intel_display *display, 234 struct intel_cdclk_config *cdclk_config) 235 { 236 cdclk_config->cdclk = 133333; 237 } 238 239 static void fixed_200mhz_get_cdclk(struct intel_display *display, 240 struct intel_cdclk_config *cdclk_config) 241 { 242 cdclk_config->cdclk = 200000; 243 } 244 245 static void fixed_266mhz_get_cdclk(struct intel_display *display, 246 struct intel_cdclk_config *cdclk_config) 247 { 248 cdclk_config->cdclk = 266667; 249 } 250 251 static void fixed_333mhz_get_cdclk(struct intel_display *display, 252 struct intel_cdclk_config *cdclk_config) 253 { 254 cdclk_config->cdclk = 333333; 255 } 256 257 static void fixed_400mhz_get_cdclk(struct intel_display *display, 258 struct intel_cdclk_config *cdclk_config) 259 { 260 cdclk_config->cdclk = 400000; 261 } 262 263 static void fixed_450mhz_get_cdclk(struct intel_display *display, 264 struct intel_cdclk_config *cdclk_config) 265 { 266 cdclk_config->cdclk = 450000; 267 } 268 269 static void i85x_get_cdclk(struct intel_display *display, 270 struct intel_cdclk_config *cdclk_config) 271 { 272 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 273 u16 hpllcc = 0; 274 275 /* 276 * 852GM/852GMV only supports 133 MHz and the HPLLCC 277 * encoding is different :( 278 * FIXME is this the right way to detect 852GM/852GMV? 279 */ 280 if (pdev->revision == 0x1) { 281 cdclk_config->cdclk = 133333; 282 return; 283 } 284 285 pci_bus_read_config_word(pdev->bus, 286 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 287 288 /* Assume that the hardware is in the high speed state. This 289 * should be the default. 290 */ 291 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 292 case GC_CLOCK_133_200: 293 case GC_CLOCK_133_200_2: 294 case GC_CLOCK_100_200: 295 cdclk_config->cdclk = 200000; 296 break; 297 case GC_CLOCK_166_250: 298 cdclk_config->cdclk = 250000; 299 break; 300 case GC_CLOCK_100_133: 301 cdclk_config->cdclk = 133333; 302 break; 303 case GC_CLOCK_133_266: 304 case GC_CLOCK_133_266_2: 305 case GC_CLOCK_166_266: 306 cdclk_config->cdclk = 266667; 307 break; 308 } 309 } 310 311 static void i915gm_get_cdclk(struct intel_display *display, 312 struct intel_cdclk_config *cdclk_config) 313 { 314 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 315 u16 gcfgc = 0; 316 317 pci_read_config_word(pdev, GCFGC, &gcfgc); 318 319 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 320 cdclk_config->cdclk = 133333; 321 return; 322 } 323 324 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 325 case GC_DISPLAY_CLOCK_333_320_MHZ: 326 cdclk_config->cdclk = 333333; 327 break; 328 default: 329 case GC_DISPLAY_CLOCK_190_200_MHZ: 330 cdclk_config->cdclk = 190000; 331 break; 332 } 333 } 334 335 static void i945gm_get_cdclk(struct intel_display *display, 336 struct intel_cdclk_config *cdclk_config) 337 { 338 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 339 u16 gcfgc = 0; 340 341 pci_read_config_word(pdev, GCFGC, &gcfgc); 342 343 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 344 cdclk_config->cdclk = 133333; 345 return; 346 } 347 348 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 349 case GC_DISPLAY_CLOCK_333_320_MHZ: 350 cdclk_config->cdclk = 320000; 351 break; 352 default: 353 case GC_DISPLAY_CLOCK_190_200_MHZ: 354 cdclk_config->cdclk = 200000; 355 break; 356 } 357 } 358 359 static unsigned int intel_hpll_vco(struct intel_display *display) 360 { 361 static const unsigned int blb_vco[8] = { 362 [0] = 3200000, 363 [1] = 4000000, 364 [2] = 5333333, 365 [3] = 4800000, 366 [4] = 6400000, 367 }; 368 static const unsigned int pnv_vco[8] = { 369 [0] = 3200000, 370 [1] = 4000000, 371 [2] = 5333333, 372 [3] = 4800000, 373 [4] = 2666667, 374 }; 375 static const unsigned int cl_vco[8] = { 376 [0] = 3200000, 377 [1] = 4000000, 378 [2] = 5333333, 379 [3] = 6400000, 380 [4] = 3333333, 381 [5] = 3566667, 382 [6] = 4266667, 383 }; 384 static const unsigned int elk_vco[8] = { 385 [0] = 3200000, 386 [1] = 4000000, 387 [2] = 5333333, 388 [3] = 4800000, 389 }; 390 static const unsigned int ctg_vco[8] = { 391 [0] = 3200000, 392 [1] = 4000000, 393 [2] = 5333333, 394 [3] = 6400000, 395 [4] = 2666667, 396 [5] = 4266667, 397 }; 398 const unsigned int *vco_table; 399 unsigned int vco; 400 u8 tmp = 0; 401 402 /* FIXME other chipsets? */ 403 if (display->platform.gm45) 404 vco_table = ctg_vco; 405 else if (display->platform.g45) 406 vco_table = elk_vco; 407 else if (display->platform.i965gm) 408 vco_table = cl_vco; 409 else if (display->platform.pineview) 410 vco_table = pnv_vco; 411 else if (display->platform.g33) 412 vco_table = blb_vco; 413 else 414 return 0; 415 416 tmp = intel_mchbar_read(display, display->platform.pineview || 417 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO); 418 419 vco = vco_table[tmp & 0x7]; 420 if (vco == 0) 421 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 422 tmp); 423 else 424 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); 425 426 return vco; 427 } 428 429 static void g33_get_cdclk(struct intel_display *display, 430 struct intel_cdclk_config *cdclk_config) 431 { 432 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 433 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 434 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 435 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 436 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 437 const u8 *div_table; 438 unsigned int cdclk_sel; 439 u16 tmp = 0; 440 441 cdclk_config->vco = intel_hpll_vco(display); 442 443 pci_read_config_word(pdev, GCFGC, &tmp); 444 445 cdclk_sel = (tmp >> 4) & 0x7; 446 447 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 448 goto fail; 449 450 switch (cdclk_config->vco) { 451 case 3200000: 452 div_table = div_3200; 453 break; 454 case 4000000: 455 div_table = div_4000; 456 break; 457 case 4800000: 458 div_table = div_4800; 459 break; 460 case 5333333: 461 div_table = div_5333; 462 break; 463 default: 464 goto fail; 465 } 466 467 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 468 div_table[cdclk_sel]); 469 return; 470 471 fail: 472 drm_err(display->drm, 473 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 474 cdclk_config->vco, tmp); 475 cdclk_config->cdclk = 190476; 476 } 477 478 static void pnv_get_cdclk(struct intel_display *display, 479 struct intel_cdclk_config *cdclk_config) 480 { 481 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 482 u16 gcfgc = 0; 483 484 pci_read_config_word(pdev, GCFGC, &gcfgc); 485 486 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 487 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 488 cdclk_config->cdclk = 266667; 489 break; 490 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 491 cdclk_config->cdclk = 333333; 492 break; 493 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 494 cdclk_config->cdclk = 444444; 495 break; 496 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 497 cdclk_config->cdclk = 200000; 498 break; 499 default: 500 drm_err(display->drm, 501 "Unknown pnv display core clock 0x%04x\n", gcfgc); 502 fallthrough; 503 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 504 cdclk_config->cdclk = 133333; 505 break; 506 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 507 cdclk_config->cdclk = 166667; 508 break; 509 } 510 } 511 512 static void i965gm_get_cdclk(struct intel_display *display, 513 struct intel_cdclk_config *cdclk_config) 514 { 515 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 516 static const u8 div_3200[] = { 16, 10, 8 }; 517 static const u8 div_4000[] = { 20, 12, 10 }; 518 static const u8 div_5333[] = { 24, 16, 14 }; 519 const u8 *div_table; 520 unsigned int cdclk_sel; 521 u16 tmp = 0; 522 523 cdclk_config->vco = intel_hpll_vco(display); 524 525 pci_read_config_word(pdev, GCFGC, &tmp); 526 527 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 528 529 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 530 goto fail; 531 532 switch (cdclk_config->vco) { 533 case 3200000: 534 div_table = div_3200; 535 break; 536 case 4000000: 537 div_table = div_4000; 538 break; 539 case 5333333: 540 div_table = div_5333; 541 break; 542 default: 543 goto fail; 544 } 545 546 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 547 div_table[cdclk_sel]); 548 return; 549 550 fail: 551 drm_err(display->drm, 552 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 553 cdclk_config->vco, tmp); 554 cdclk_config->cdclk = 200000; 555 } 556 557 static void gm45_get_cdclk(struct intel_display *display, 558 struct intel_cdclk_config *cdclk_config) 559 { 560 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 561 unsigned int cdclk_sel; 562 u16 tmp = 0; 563 564 cdclk_config->vco = intel_hpll_vco(display); 565 566 pci_read_config_word(pdev, GCFGC, &tmp); 567 568 cdclk_sel = (tmp >> 12) & 0x1; 569 570 switch (cdclk_config->vco) { 571 case 2666667: 572 case 4000000: 573 case 5333333: 574 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 575 break; 576 case 3200000: 577 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 578 break; 579 default: 580 drm_err(display->drm, 581 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 582 cdclk_config->vco, tmp); 583 cdclk_config->cdclk = 222222; 584 break; 585 } 586 } 587 588 static void hsw_get_cdclk(struct intel_display *display, 589 struct intel_cdclk_config *cdclk_config) 590 { 591 u32 lcpll = intel_de_read(display, LCPLL_CTL); 592 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 593 594 if (lcpll & LCPLL_CD_SOURCE_FCLK) 595 cdclk_config->cdclk = 800000; 596 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 597 cdclk_config->cdclk = 450000; 598 else if (freq == LCPLL_CLK_FREQ_450) 599 cdclk_config->cdclk = 450000; 600 else if (display->platform.haswell_ult) 601 cdclk_config->cdclk = 337500; 602 else 603 cdclk_config->cdclk = 540000; 604 } 605 606 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) 607 { 608 int freq_320 = (vlv_clock_get_hpll_vco(display->drm) << 1) % 320000 != 0 ? 609 333333 : 320000; 610 611 /* 612 * We seem to get an unstable or solid color picture at 200MHz. 613 * Not sure what's wrong. For now use 200MHz only when all pipes 614 * are off. 615 */ 616 if (display->platform.valleyview && min_cdclk > freq_320) 617 return 400000; 618 else if (min_cdclk > 266667) 619 return freq_320; 620 else if (min_cdclk > 0) 621 return 266667; 622 else 623 return 200000; 624 } 625 626 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) 627 { 628 if (display->platform.valleyview) { 629 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 630 return 2; 631 else if (cdclk >= 266667) 632 return 1; 633 else 634 return 0; 635 } else { 636 /* 637 * Specs are full of misinformation, but testing on actual 638 * hardware has shown that we just need to write the desired 639 * CCK divider into the Punit register. 640 */ 641 return DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, cdclk) - 1; 642 } 643 } 644 645 static void vlv_get_cdclk(struct intel_display *display, 646 struct intel_cdclk_config *cdclk_config) 647 { 648 u32 val; 649 650 cdclk_config->vco = vlv_clock_get_hpll_vco(display->drm); 651 cdclk_config->cdclk = vlv_clock_get_cdclk(display->drm); 652 653 vlv_punit_get(display); 654 val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); 655 vlv_punit_put(display); 656 657 if (display->platform.valleyview) 658 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 659 DSPFREQGUAR_SHIFT; 660 else 661 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 662 DSPFREQGUAR_SHIFT_CHV; 663 } 664 665 static void vlv_program_pfi_credits(struct intel_display *display) 666 { 667 unsigned int credits, default_credits; 668 669 if (display->platform.cherryview) 670 default_credits = PFI_CREDIT(12); 671 else 672 default_credits = PFI_CREDIT(8); 673 674 if (display->cdclk.hw.cdclk >= vlv_clock_get_czclk(display->drm)) { 675 /* CHV suggested value is 31 or 63 */ 676 if (display->platform.cherryview) 677 credits = PFI_CREDIT_63; 678 else 679 credits = PFI_CREDIT(15); 680 } else { 681 credits = default_credits; 682 } 683 684 /* 685 * WA - write default credits before re-programming 686 * FIXME: should we also set the resend bit here? 687 */ 688 intel_de_write(display, GCI_CONTROL, 689 VGA_FAST_MODE_DISABLE | default_credits); 690 691 intel_de_write(display, GCI_CONTROL, 692 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 693 694 /* 695 * FIXME is this guaranteed to clear 696 * immediately or should we poll for it? 697 */ 698 drm_WARN_ON(display->drm, 699 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); 700 } 701 702 static void vlv_set_cdclk(struct intel_display *display, 703 const struct intel_cdclk_config *cdclk_config, 704 enum pipe pipe) 705 { 706 int cdclk = cdclk_config->cdclk; 707 u32 val, cmd = cdclk_config->voltage_level; 708 struct ref_tracker *wakeref; 709 int ret; 710 711 switch (cdclk) { 712 case 400000: 713 case 333333: 714 case 320000: 715 case 266667: 716 case 200000: 717 break; 718 default: 719 MISSING_CASE(cdclk); 720 return; 721 } 722 723 /* There are cases where we can end up here with power domains 724 * off and a CDCLK frequency other than the minimum, like when 725 * issuing a modeset without actually changing any display after 726 * a system suspend. So grab the display core domain, which covers 727 * the HW blocks needed for the following programming. 728 */ 729 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 730 731 intel_parent_vlv_iosf_get(display, 732 BIT(VLV_IOSF_SB_CCK) | 733 BIT(VLV_IOSF_SB_BUNIT) | 734 BIT(VLV_IOSF_SB_PUNIT)); 735 736 val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); 737 val &= ~DSPFREQGUAR_MASK; 738 val |= (cmd << DSPFREQGUAR_SHIFT); 739 vlv_punit_write(display, PUNIT_REG_DSPSSPM, val); 740 741 ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DSPSSPM), 742 (val & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 743 500, 50 * 1000, false); 744 if (ret) 745 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 746 747 if (cdclk == 400000) { 748 u32 divider; 749 750 divider = DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, 751 cdclk) - 1; 752 753 /* adjust cdclk divider */ 754 val = vlv_cck_read(display, CCK_DISPLAY_CLOCK_CONTROL); 755 val &= ~CCK_FREQUENCY_VALUES; 756 val |= divider; 757 vlv_cck_write(display, CCK_DISPLAY_CLOCK_CONTROL, val); 758 759 ret = poll_timeout_us(val = vlv_cck_read(display, CCK_DISPLAY_CLOCK_CONTROL), 760 (val & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 761 500, 50 * 1000, false); 762 if (ret) 763 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 764 } 765 766 /* adjust self-refresh exit latency value */ 767 val = vlv_bunit_read(display, BUNIT_REG_BISOC); 768 val &= ~0x7f; 769 770 /* 771 * For high bandwidth configs, we set a higher latency in the bunit 772 * so that the core display fetch happens in time to avoid underruns. 773 */ 774 if (cdclk == 400000) 775 val |= 4500 / 250; /* 4.5 usec */ 776 else 777 val |= 3000 / 250; /* 3.0 usec */ 778 vlv_bunit_write(display, BUNIT_REG_BISOC, val); 779 780 intel_parent_vlv_iosf_put(display, 781 BIT(VLV_IOSF_SB_CCK) | 782 BIT(VLV_IOSF_SB_BUNIT) | 783 BIT(VLV_IOSF_SB_PUNIT)); 784 785 intel_update_cdclk(display); 786 787 vlv_program_pfi_credits(display); 788 789 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 790 } 791 792 static void chv_set_cdclk(struct intel_display *display, 793 const struct intel_cdclk_config *cdclk_config, 794 enum pipe pipe) 795 { 796 int cdclk = cdclk_config->cdclk; 797 u32 val, cmd = cdclk_config->voltage_level; 798 struct ref_tracker *wakeref; 799 int ret; 800 801 switch (cdclk) { 802 case 333333: 803 case 320000: 804 case 266667: 805 case 200000: 806 break; 807 default: 808 MISSING_CASE(cdclk); 809 return; 810 } 811 812 /* There are cases where we can end up here with power domains 813 * off and a CDCLK frequency other than the minimum, like when 814 * issuing a modeset without actually changing any display after 815 * a system suspend. So grab the display core domain, which covers 816 * the HW blocks needed for the following programming. 817 */ 818 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 819 820 vlv_punit_get(display); 821 val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); 822 val &= ~DSPFREQGUAR_MASK_CHV; 823 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 824 vlv_punit_write(display, PUNIT_REG_DSPSSPM, val); 825 826 ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DSPSSPM), 827 (val & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 828 500, 50 * 1000, false); 829 if (ret) 830 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 831 832 vlv_punit_put(display); 833 834 intel_update_cdclk(display); 835 836 vlv_program_pfi_credits(display); 837 838 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 839 } 840 841 static int bdw_calc_cdclk(int min_cdclk) 842 { 843 if (min_cdclk > 540000) 844 return 675000; 845 else if (min_cdclk > 450000) 846 return 540000; 847 else if (min_cdclk > 337500) 848 return 450000; 849 else 850 return 337500; 851 } 852 853 static u8 bdw_calc_voltage_level(int cdclk) 854 { 855 switch (cdclk) { 856 default: 857 case 337500: 858 return 2; 859 case 450000: 860 return 0; 861 case 540000: 862 return 1; 863 case 675000: 864 return 3; 865 } 866 } 867 868 static void bdw_get_cdclk(struct intel_display *display, 869 struct intel_cdclk_config *cdclk_config) 870 { 871 u32 lcpll = intel_de_read(display, LCPLL_CTL); 872 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 873 874 if (lcpll & LCPLL_CD_SOURCE_FCLK) 875 cdclk_config->cdclk = 800000; 876 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 877 cdclk_config->cdclk = 450000; 878 else if (freq == LCPLL_CLK_FREQ_450) 879 cdclk_config->cdclk = 450000; 880 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 881 cdclk_config->cdclk = 540000; 882 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 883 cdclk_config->cdclk = 337500; 884 else 885 cdclk_config->cdclk = 675000; 886 887 /* 888 * Can't read this out :( Let's assume it's 889 * at least what the CDCLK frequency requires. 890 */ 891 cdclk_config->voltage_level = 892 bdw_calc_voltage_level(cdclk_config->cdclk); 893 } 894 895 static u32 bdw_cdclk_freq_sel(int cdclk) 896 { 897 switch (cdclk) { 898 default: 899 MISSING_CASE(cdclk); 900 fallthrough; 901 case 337500: 902 return LCPLL_CLK_FREQ_337_5_BDW; 903 case 450000: 904 return LCPLL_CLK_FREQ_450; 905 case 540000: 906 return LCPLL_CLK_FREQ_54O_BDW; 907 case 675000: 908 return LCPLL_CLK_FREQ_675_BDW; 909 } 910 } 911 912 static int bdw_cdclk_pcode_pre_notify(struct intel_display *display) 913 { 914 return intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 915 0x0); 916 } 917 918 static int bdw_cdclk_pcode_post_notify(struct intel_display *display, 919 const struct intel_cdclk_config *cdclk_config) 920 { 921 return intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ, 922 cdclk_config->voltage_level); 923 } 924 925 static void bdw_set_cdclk(struct intel_display *display, 926 const struct intel_cdclk_config *cdclk_config, 927 enum pipe pipe) 928 { 929 int cdclk = cdclk_config->cdclk; 930 int ret; 931 932 if (drm_WARN(display->drm, 933 (intel_de_read(display, LCPLL_CTL) & 934 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 935 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 936 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 937 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 938 "trying to change cdclk frequency with cdclk not enabled\n")) 939 return; 940 941 intel_de_rmw(display, LCPLL_CTL, 942 0, LCPLL_CD_SOURCE_FCLK); 943 944 /* 945 * According to the spec, it should be enough to poll for this 1 us. 946 * However, extensive testing shows that this can take longer. 947 */ 948 ret = intel_de_wait_for_set_us(display, LCPLL_CTL, 949 LCPLL_CD_SOURCE_FCLK_DONE, 100); 950 if (ret) 951 drm_err(display->drm, "Switching to FCLK failed\n"); 952 953 intel_de_rmw(display, LCPLL_CTL, 954 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 955 956 intel_de_rmw(display, LCPLL_CTL, 957 LCPLL_CD_SOURCE_FCLK, 0); 958 959 ret = intel_de_wait_for_clear_us(display, LCPLL_CTL, 960 LCPLL_CD_SOURCE_FCLK_DONE, 1); 961 if (ret) 962 drm_err(display->drm, "Switching back to LCPLL failed\n"); 963 964 intel_de_write(display, CDCLK_FREQ, 965 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 966 967 intel_update_cdclk(display); 968 } 969 970 static int skl_calc_cdclk(int min_cdclk, int vco) 971 { 972 if (vco == 8640000) { 973 if (min_cdclk > 540000) 974 return 617143; 975 else if (min_cdclk > 432000) 976 return 540000; 977 else if (min_cdclk > 308571) 978 return 432000; 979 else 980 return 308571; 981 } else { 982 if (min_cdclk > 540000) 983 return 675000; 984 else if (min_cdclk > 450000) 985 return 540000; 986 else if (min_cdclk > 337500) 987 return 450000; 988 else 989 return 337500; 990 } 991 } 992 993 static u8 skl_calc_voltage_level(int cdclk) 994 { 995 if (cdclk > 540000) 996 return 3; 997 else if (cdclk > 450000) 998 return 2; 999 else if (cdclk > 337500) 1000 return 1; 1001 else 1002 return 0; 1003 } 1004 1005 static void skl_dpll0_update(struct intel_display *display, 1006 struct intel_cdclk_config *cdclk_config) 1007 { 1008 u32 val; 1009 1010 cdclk_config->ref = 24000; 1011 cdclk_config->vco = 0; 1012 1013 val = intel_de_read(display, LCPLL1_CTL); 1014 if ((val & LCPLL_PLL_ENABLE) == 0) 1015 return; 1016 1017 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) 1018 return; 1019 1020 val = intel_de_read(display, DPLL_CTRL1); 1021 1022 if (drm_WARN_ON(display->drm, 1023 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1024 DPLL_CTRL1_SSC(SKL_DPLL0) | 1025 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 1026 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 1027 return; 1028 1029 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 1030 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 1031 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 1032 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 1033 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 1034 cdclk_config->vco = 8100000; 1035 break; 1036 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 1037 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 1038 cdclk_config->vco = 8640000; 1039 break; 1040 default: 1041 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 1042 break; 1043 } 1044 } 1045 1046 static void skl_get_cdclk(struct intel_display *display, 1047 struct intel_cdclk_config *cdclk_config) 1048 { 1049 u32 cdctl; 1050 1051 skl_dpll0_update(display, cdclk_config); 1052 1053 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 1054 1055 if (cdclk_config->vco == 0) 1056 goto out; 1057 1058 cdctl = intel_de_read(display, CDCLK_CTL); 1059 1060 if (cdclk_config->vco == 8640000) { 1061 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1062 case CDCLK_FREQ_450_432: 1063 cdclk_config->cdclk = 432000; 1064 break; 1065 case CDCLK_FREQ_337_308: 1066 cdclk_config->cdclk = 308571; 1067 break; 1068 case CDCLK_FREQ_540: 1069 cdclk_config->cdclk = 540000; 1070 break; 1071 case CDCLK_FREQ_675_617: 1072 cdclk_config->cdclk = 617143; 1073 break; 1074 default: 1075 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1076 break; 1077 } 1078 } else { 1079 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1080 case CDCLK_FREQ_450_432: 1081 cdclk_config->cdclk = 450000; 1082 break; 1083 case CDCLK_FREQ_337_308: 1084 cdclk_config->cdclk = 337500; 1085 break; 1086 case CDCLK_FREQ_540: 1087 cdclk_config->cdclk = 540000; 1088 break; 1089 case CDCLK_FREQ_675_617: 1090 cdclk_config->cdclk = 675000; 1091 break; 1092 default: 1093 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1094 break; 1095 } 1096 } 1097 1098 out: 1099 /* 1100 * Can't read this out :( Let's assume it's 1101 * at least what the CDCLK frequency requires. 1102 */ 1103 cdclk_config->voltage_level = 1104 skl_calc_voltage_level(cdclk_config->cdclk); 1105 } 1106 1107 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 1108 static int skl_cdclk_decimal(int cdclk) 1109 { 1110 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 1111 } 1112 1113 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) 1114 { 1115 bool changed = display->cdclk.skl_preferred_vco_freq != vco; 1116 1117 display->cdclk.skl_preferred_vco_freq = vco; 1118 1119 if (changed) 1120 intel_update_max_cdclk(display); 1121 } 1122 1123 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) 1124 { 1125 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 1126 1127 /* 1128 * We always enable DPLL0 with the lowest link rate possible, but still 1129 * taking into account the VCO required to operate the eDP panel at the 1130 * desired frequency. The usual DP link rates operate with a VCO of 1131 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1132 * The modeset code is responsible for the selection of the exact link 1133 * rate later on, with the constraint of choosing a frequency that 1134 * works with vco. 1135 */ 1136 if (vco == 8640000) 1137 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1138 else 1139 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1140 } 1141 1142 static void skl_dpll0_enable(struct intel_display *display, int vco) 1143 { 1144 intel_de_rmw(display, DPLL_CTRL1, 1145 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1146 DPLL_CTRL1_SSC(SKL_DPLL0) | 1147 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1148 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1149 skl_dpll0_link_rate(display, vco)); 1150 intel_de_posting_read(display, DPLL_CTRL1); 1151 1152 intel_de_rmw(display, LCPLL1_CTL, 1153 0, LCPLL_PLL_ENABLE); 1154 1155 if (intel_de_wait_for_set_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1156 drm_err(display->drm, "DPLL0 not locked\n"); 1157 1158 display->cdclk.hw.vco = vco; 1159 1160 /* We'll want to keep using the current vco from now on. */ 1161 skl_set_preferred_cdclk_vco(display, vco); 1162 } 1163 1164 static void skl_dpll0_disable(struct intel_display *display) 1165 { 1166 intel_de_rmw(display, LCPLL1_CTL, 1167 LCPLL_PLL_ENABLE, 0); 1168 1169 if (intel_de_wait_for_clear_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1170 drm_err(display->drm, "Couldn't disable DPLL0\n"); 1171 1172 display->cdclk.hw.vco = 0; 1173 } 1174 1175 static u32 skl_cdclk_freq_sel(struct intel_display *display, 1176 int cdclk, int vco) 1177 { 1178 switch (cdclk) { 1179 default: 1180 drm_WARN_ON(display->drm, 1181 cdclk != display->cdclk.hw.bypass); 1182 drm_WARN_ON(display->drm, vco != 0); 1183 fallthrough; 1184 case 308571: 1185 case 337500: 1186 return CDCLK_FREQ_337_308; 1187 case 450000: 1188 case 432000: 1189 return CDCLK_FREQ_450_432; 1190 case 540000: 1191 return CDCLK_FREQ_540; 1192 case 617143: 1193 case 675000: 1194 return CDCLK_FREQ_675_617; 1195 } 1196 } 1197 1198 static int skl_cdclk_pcode_pre_notify(struct intel_display *display) 1199 { 1200 return intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL, 1201 SKL_CDCLK_PREPARE_FOR_CHANGE, 1202 SKL_CDCLK_READY_FOR_CHANGE, 1203 SKL_CDCLK_READY_FOR_CHANGE, 3); 1204 } 1205 1206 static int skl_cdclk_pcode_post_notify(struct intel_display *display, 1207 const struct intel_cdclk_config *cdclk_config) 1208 { 1209 return intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL, 1210 cdclk_config->voltage_level); 1211 } 1212 1213 static void skl_set_cdclk(struct intel_display *display, 1214 const struct intel_cdclk_config *cdclk_config, 1215 enum pipe pipe) 1216 { 1217 int cdclk = cdclk_config->cdclk; 1218 int vco = cdclk_config->vco; 1219 u32 freq_select, cdclk_ctl; 1220 1221 /* 1222 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1223 * unsupported on SKL. In theory this should never happen since only 1224 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1225 * supported on SKL either, see the above WA. WARN whenever trying to 1226 * use the corresponding VCO freq as that always leads to using the 1227 * minimum 308MHz CDCLK. 1228 */ 1229 drm_WARN_ON_ONCE(display->drm, 1230 display->platform.skylake && vco == 8640000); 1231 1232 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); 1233 1234 if (display->cdclk.hw.vco != 0 && 1235 display->cdclk.hw.vco != vco) 1236 skl_dpll0_disable(display); 1237 1238 cdclk_ctl = intel_de_read(display, CDCLK_CTL); 1239 1240 if (display->cdclk.hw.vco != vco) { 1241 /* Wa Display #1183: skl,kbl,cfl */ 1242 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1243 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1244 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1245 } 1246 1247 /* Wa Display #1183: skl,kbl,cfl */ 1248 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1249 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1250 intel_de_posting_read(display, CDCLK_CTL); 1251 1252 if (display->cdclk.hw.vco != vco) 1253 skl_dpll0_enable(display, vco); 1254 1255 /* Wa Display #1183: skl,kbl,cfl */ 1256 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1257 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1258 1259 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1260 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1261 1262 /* Wa Display #1183: skl,kbl,cfl */ 1263 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1264 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1265 intel_de_posting_read(display, CDCLK_CTL); 1266 1267 intel_update_cdclk(display); 1268 } 1269 1270 static void skl_sanitize_cdclk(struct intel_display *display) 1271 { 1272 u32 cdctl, expected, swf18; 1273 1274 /* 1275 * check if the pre-os initialized the display 1276 * There is SWF18 scratchpad register defined which is set by the 1277 * pre-os which can be used by the OS drivers to check the status 1278 */ 1279 swf18 = intel_de_read(display, SWF_ILK(0x18)); 1280 if ((swf18 & 0x00FFFFFF) == 0) { 1281 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to SWF18 0x%x\n", swf18); 1282 goto sanitize; 1283 } 1284 1285 intel_update_cdclk(display); 1286 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1287 1288 /* Is PLL enabled and locked ? */ 1289 if (display->cdclk.hw.vco == 0 || 1290 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) { 1291 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to PLL not enabled/locked\n"); 1292 goto sanitize; 1293 } 1294 1295 /* DPLL okay; verify the cdclock 1296 * 1297 * Noticed in some instances that the freq selection is correct but 1298 * decimal part is programmed wrong from BIOS where pre-os does not 1299 * enable display. Verify the same as well. 1300 */ 1301 cdctl = intel_de_read(display, CDCLK_CTL); 1302 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1303 skl_cdclk_decimal(display->cdclk.hw.cdclk); 1304 1305 if (cdctl != expected) { 1306 cdctl &= ~CDCLK_FREQ_DECIMAL_MASK; 1307 cdctl |= expected & CDCLK_FREQ_DECIMAL_MASK; 1308 1309 if (cdctl != expected) { 1310 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to CDCLK_CTL 0x%x, expected 0x%x)\n", 1311 intel_de_read(display, CDCLK_CTL), expected); 1312 goto sanitize; 1313 } 1314 1315 drm_dbg_kms(display->drm, "Sanitizing CDCLK decimal divider (CDCLK_CTL 0x%x, expected 0x%x)\n", 1316 intel_de_read(display, CDCLK_CTL), expected); 1317 1318 intel_de_write(display, CDCLK_CTL, expected); 1319 } 1320 1321 /* All well; nothing to sanitize */ 1322 return; 1323 1324 sanitize: 1325 /* force cdclk programming */ 1326 display->cdclk.hw.cdclk = 0; 1327 /* force full PLL disable + enable */ 1328 display->cdclk.hw.vco = ~0; 1329 } 1330 1331 static void skl_cdclk_init_hw(struct intel_display *display) 1332 { 1333 struct intel_cdclk_config cdclk_config; 1334 1335 skl_sanitize_cdclk(display); 1336 1337 if (display->cdclk.hw.cdclk != 0 && 1338 display->cdclk.hw.vco != 0) { 1339 /* 1340 * Use the current vco as our initial 1341 * guess as to what the preferred vco is. 1342 */ 1343 if (display->cdclk.skl_preferred_vco_freq == 0) 1344 skl_set_preferred_cdclk_vco(display, 1345 display->cdclk.hw.vco); 1346 return; 1347 } 1348 1349 cdclk_config = display->cdclk.hw; 1350 1351 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; 1352 if (cdclk_config.vco == 0) 1353 cdclk_config.vco = 8100000; 1354 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1355 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1356 1357 intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1358 } 1359 1360 static void skl_cdclk_uninit_hw(struct intel_display *display) 1361 { 1362 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 1363 1364 cdclk_config.cdclk = cdclk_config.bypass; 1365 cdclk_config.vco = 0; 1366 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1367 1368 intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1369 } 1370 1371 struct intel_cdclk_vals { 1372 u32 cdclk; 1373 u16 refclk; 1374 u16 waveform; 1375 u8 ratio; 1376 }; 1377 1378 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1379 { .refclk = 19200, .cdclk = 144000, .ratio = 60 }, 1380 { .refclk = 19200, .cdclk = 288000, .ratio = 60 }, 1381 { .refclk = 19200, .cdclk = 384000, .ratio = 60 }, 1382 { .refclk = 19200, .cdclk = 576000, .ratio = 60 }, 1383 { .refclk = 19200, .cdclk = 624000, .ratio = 65 }, 1384 {} 1385 }; 1386 1387 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1388 { .refclk = 19200, .cdclk = 79200, .ratio = 33 }, 1389 { .refclk = 19200, .cdclk = 158400, .ratio = 33 }, 1390 { .refclk = 19200, .cdclk = 316800, .ratio = 33 }, 1391 {} 1392 }; 1393 1394 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1395 { .refclk = 19200, .cdclk = 172800, .ratio = 18 }, 1396 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1397 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1398 { .refclk = 19200, .cdclk = 326400, .ratio = 68 }, 1399 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1400 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1401 1402 { .refclk = 24000, .cdclk = 180000, .ratio = 15 }, 1403 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1404 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1405 { .refclk = 24000, .cdclk = 324000, .ratio = 54 }, 1406 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1407 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1408 1409 { .refclk = 38400, .cdclk = 172800, .ratio = 9 }, 1410 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1411 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1412 { .refclk = 38400, .cdclk = 326400, .ratio = 34 }, 1413 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1414 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1415 {} 1416 }; 1417 1418 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1419 { .refclk = 19200, .cdclk = 172800, .ratio = 36 }, 1420 { .refclk = 19200, .cdclk = 192000, .ratio = 40 }, 1421 { .refclk = 19200, .cdclk = 307200, .ratio = 64 }, 1422 { .refclk = 19200, .cdclk = 326400, .ratio = 136 }, 1423 { .refclk = 19200, .cdclk = 556800, .ratio = 116 }, 1424 { .refclk = 19200, .cdclk = 652800, .ratio = 136 }, 1425 1426 { .refclk = 24000, .cdclk = 180000, .ratio = 30 }, 1427 { .refclk = 24000, .cdclk = 192000, .ratio = 32 }, 1428 { .refclk = 24000, .cdclk = 312000, .ratio = 52 }, 1429 { .refclk = 24000, .cdclk = 324000, .ratio = 108 }, 1430 { .refclk = 24000, .cdclk = 552000, .ratio = 92 }, 1431 { .refclk = 24000, .cdclk = 648000, .ratio = 108 }, 1432 1433 { .refclk = 38400, .cdclk = 172800, .ratio = 18 }, 1434 { .refclk = 38400, .cdclk = 192000, .ratio = 20 }, 1435 { .refclk = 38400, .cdclk = 307200, .ratio = 32 }, 1436 { .refclk = 38400, .cdclk = 326400, .ratio = 68 }, 1437 { .refclk = 38400, .cdclk = 556800, .ratio = 58 }, 1438 { .refclk = 38400, .cdclk = 652800, .ratio = 68 }, 1439 {} 1440 }; 1441 1442 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1443 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1444 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1445 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1446 1447 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1448 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1449 { .refclk = 24400, .cdclk = 648000, .ratio = 54 }, 1450 1451 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1452 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1453 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1454 {} 1455 }; 1456 1457 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1458 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1459 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1460 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1461 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1462 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1463 1464 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1465 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1466 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1467 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1468 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1469 1470 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1471 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1472 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1473 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1474 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1475 {} 1476 }; 1477 1478 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1479 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1480 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1481 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1482 { .refclk = 19200, .cdclk = 480000, .ratio = 50 }, 1483 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1484 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1485 1486 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1487 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1488 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1489 { .refclk = 24000, .cdclk = 480000, .ratio = 40 }, 1490 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1491 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1492 1493 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1494 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1495 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1496 { .refclk = 38400, .cdclk = 480000, .ratio = 25 }, 1497 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1498 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1499 {} 1500 }; 1501 1502 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1503 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 }, 1504 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 }, 1505 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 }, 1506 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a }, 1507 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa }, 1508 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a }, 1509 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 }, 1510 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 }, 1511 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee }, 1512 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de }, 1513 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1514 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1515 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1516 {} 1517 }; 1518 1519 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1520 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1521 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1522 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 }, 1523 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 }, 1524 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 }, 1525 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 }, 1526 {} 1527 }; 1528 1529 static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { 1530 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1531 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1532 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1533 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1534 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1535 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1536 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1537 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1538 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1539 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, 1540 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, 1541 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, 1542 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, 1543 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, 1544 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1545 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, 1546 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, 1547 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1548 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1549 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1550 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1551 {} 1552 }; 1553 1554 /* 1555 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 1556 */ 1557 static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { 1558 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1559 {} 1560 }; 1561 1562 static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = { 1563 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1564 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1565 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1566 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1567 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1568 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1569 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1570 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1571 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1572 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff }, 1573 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff }, 1574 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff }, 1575 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff }, 1576 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, 1577 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, 1578 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, 1579 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, 1580 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1581 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, 1582 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, 1583 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, 1584 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1585 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, 1586 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, 1587 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, 1588 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, 1589 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1590 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, 1591 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, 1592 {} 1593 }; 1594 1595 static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = { 1596 { .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 }, 1597 { .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 }, 1598 { .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa }, 1599 { .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a }, 1600 { .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 }, 1601 { .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 }, 1602 { .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee }, 1603 { .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de }, 1604 { .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe }, 1605 { .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe }, 1606 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, 1607 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, 1608 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, 1609 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, 1610 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1611 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, 1612 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, 1613 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, 1614 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1615 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, 1616 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, 1617 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, 1618 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, 1619 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1620 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, 1621 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, 1622 { .refclk = 38400, .cdclk = 710400, .ratio = 37, .waveform = 0xffff }, 1623 { .refclk = 38400, .cdclk = 729600, .ratio = 38, .waveform = 0xffff }, 1624 { .refclk = 38400, .cdclk = 748800, .ratio = 39, .waveform = 0xffff }, 1625 { .refclk = 38400, .cdclk = 768000, .ratio = 40, .waveform = 0xffff }, 1626 { .refclk = 38400, .cdclk = 787200, .ratio = 41, .waveform = 0xffff }, 1627 {} 1628 }; 1629 1630 static const int cdclk_squash_len = 16; 1631 1632 static int cdclk_squash_divider(u16 waveform) 1633 { 1634 return hweight16(waveform ?: 0xffff); 1635 } 1636 1637 static int cdclk_divider(int cdclk, int vco, u16 waveform) 1638 { 1639 /* 2 * cd2x divider */ 1640 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform), 1641 cdclk * cdclk_squash_len); 1642 } 1643 1644 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) 1645 { 1646 const struct intel_cdclk_vals *table = display->cdclk.table; 1647 int i; 1648 1649 for (i = 0; table[i].refclk; i++) 1650 if (table[i].refclk == display->cdclk.hw.ref && 1651 table[i].cdclk >= min_cdclk) 1652 return table[i].cdclk; 1653 1654 drm_WARN(display->drm, 1, 1655 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1656 min_cdclk, display->cdclk.hw.ref); 1657 return display->cdclk.max_cdclk_freq; 1658 } 1659 1660 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) 1661 { 1662 const struct intel_cdclk_vals *table = display->cdclk.table; 1663 int i; 1664 1665 if (cdclk == display->cdclk.hw.bypass) 1666 return 0; 1667 1668 for (i = 0; table[i].refclk; i++) 1669 if (table[i].refclk == display->cdclk.hw.ref && 1670 table[i].cdclk == cdclk) 1671 return display->cdclk.hw.ref * table[i].ratio; 1672 1673 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1674 cdclk, display->cdclk.hw.ref); 1675 return 0; 1676 } 1677 1678 static u8 bxt_calc_voltage_level(int cdclk) 1679 { 1680 return DIV_ROUND_UP(cdclk, 25000); 1681 } 1682 1683 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, 1684 const int voltage_level_max_cdclk[]) 1685 { 1686 int voltage_level; 1687 1688 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) { 1689 if (cdclk <= voltage_level_max_cdclk[voltage_level]) 1690 return voltage_level; 1691 } 1692 1693 MISSING_CASE(cdclk); 1694 return num_voltage_levels - 1; 1695 } 1696 1697 static u8 icl_calc_voltage_level(int cdclk) 1698 { 1699 static const int icl_voltage_level_max_cdclk[] = { 1700 [0] = 312000, 1701 [1] = 556800, 1702 [2] = 652800, 1703 }; 1704 1705 return calc_voltage_level(cdclk, 1706 ARRAY_SIZE(icl_voltage_level_max_cdclk), 1707 icl_voltage_level_max_cdclk); 1708 } 1709 1710 static u8 ehl_calc_voltage_level(int cdclk) 1711 { 1712 static const int ehl_voltage_level_max_cdclk[] = { 1713 [0] = 180000, 1714 [1] = 312000, 1715 [2] = 326400, 1716 /* 1717 * Bspec lists the limit as 556.8 MHz, but some JSL 1718 * development boards (at least) boot with 652.8 MHz 1719 */ 1720 [3] = 652800, 1721 }; 1722 1723 return calc_voltage_level(cdclk, 1724 ARRAY_SIZE(ehl_voltage_level_max_cdclk), 1725 ehl_voltage_level_max_cdclk); 1726 } 1727 1728 static u8 tgl_calc_voltage_level(int cdclk) 1729 { 1730 static const int tgl_voltage_level_max_cdclk[] = { 1731 [0] = 312000, 1732 [1] = 326400, 1733 [2] = 556800, 1734 [3] = 652800, 1735 }; 1736 1737 return calc_voltage_level(cdclk, 1738 ARRAY_SIZE(tgl_voltage_level_max_cdclk), 1739 tgl_voltage_level_max_cdclk); 1740 } 1741 1742 static u8 rplu_calc_voltage_level(int cdclk) 1743 { 1744 static const int rplu_voltage_level_max_cdclk[] = { 1745 [0] = 312000, 1746 [1] = 480000, 1747 [2] = 556800, 1748 [3] = 652800, 1749 }; 1750 1751 return calc_voltage_level(cdclk, 1752 ARRAY_SIZE(rplu_voltage_level_max_cdclk), 1753 rplu_voltage_level_max_cdclk); 1754 } 1755 1756 static u8 xe3lpd_calc_voltage_level(int cdclk) 1757 { 1758 /* 1759 * Starting with xe3lpd power controller does not need the voltage 1760 * index when doing the modeset update. This function is best left 1761 * defined but returning 0 to the mask. 1762 */ 1763 return 0; 1764 } 1765 1766 static void icl_readout_refclk(struct intel_display *display, 1767 struct intel_cdclk_config *cdclk_config) 1768 { 1769 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1770 1771 switch (dssm) { 1772 default: 1773 MISSING_CASE(dssm); 1774 fallthrough; 1775 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1776 cdclk_config->ref = 24000; 1777 break; 1778 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1779 cdclk_config->ref = 19200; 1780 break; 1781 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1782 cdclk_config->ref = 38400; 1783 break; 1784 } 1785 } 1786 1787 static void bxt_de_pll_readout(struct intel_display *display, 1788 struct intel_cdclk_config *cdclk_config) 1789 { 1790 u32 val, ratio; 1791 1792 if (display->platform.dg2) 1793 cdclk_config->ref = 38400; 1794 else if (DISPLAY_VER(display) >= 11) 1795 icl_readout_refclk(display, cdclk_config); 1796 else 1797 cdclk_config->ref = 19200; 1798 1799 val = intel_de_read(display, BXT_DE_PLL_ENABLE); 1800 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1801 (val & BXT_DE_PLL_LOCK) == 0) { 1802 /* 1803 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1804 * setting it to zero is a way to signal that. 1805 */ 1806 cdclk_config->vco = 0; 1807 return; 1808 } 1809 1810 /* 1811 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1812 * gen9lp had it in a separate PLL control register. 1813 */ 1814 if (DISPLAY_VER(display) >= 11) 1815 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1816 else 1817 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1818 1819 cdclk_config->vco = ratio * cdclk_config->ref; 1820 } 1821 1822 static void bxt_get_cdclk(struct intel_display *display, 1823 struct intel_cdclk_config *cdclk_config) 1824 { 1825 u32 squash_ctl = 0; 1826 u32 divider; 1827 int div; 1828 1829 bxt_de_pll_readout(display, cdclk_config); 1830 1831 if (DISPLAY_VER(display) >= 12) 1832 cdclk_config->bypass = cdclk_config->ref / 2; 1833 else if (DISPLAY_VER(display) >= 11) 1834 cdclk_config->bypass = 50000; 1835 else 1836 cdclk_config->bypass = cdclk_config->ref; 1837 1838 if (cdclk_config->vco == 0) { 1839 cdclk_config->cdclk = cdclk_config->bypass; 1840 goto out; 1841 } 1842 1843 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1844 1845 switch (divider) { 1846 case BXT_CDCLK_CD2X_DIV_SEL_1: 1847 div = 2; 1848 break; 1849 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1850 div = 3; 1851 break; 1852 case BXT_CDCLK_CD2X_DIV_SEL_2: 1853 div = 4; 1854 break; 1855 case BXT_CDCLK_CD2X_DIV_SEL_4: 1856 div = 8; 1857 break; 1858 default: 1859 MISSING_CASE(divider); 1860 return; 1861 } 1862 1863 if (HAS_CDCLK_SQUASH(display)) 1864 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); 1865 1866 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1867 u16 waveform; 1868 int size; 1869 1870 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1871 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1872 1873 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1874 cdclk_config->vco, size * div); 1875 } else { 1876 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1877 } 1878 1879 out: 1880 if (DISPLAY_VER(display) >= 20) 1881 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; 1882 /* 1883 * Can't read this out :( Let's assume it's 1884 * at least what the CDCLK frequency requires. 1885 */ 1886 cdclk_config->voltage_level = 1887 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); 1888 } 1889 1890 static void bxt_de_pll_disable(struct intel_display *display) 1891 { 1892 intel_de_write(display, BXT_DE_PLL_ENABLE, 0); 1893 1894 /* Timeout 200us */ 1895 if (intel_de_wait_for_clear_ms(display, 1896 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1897 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); 1898 1899 display->cdclk.hw.vco = 0; 1900 } 1901 1902 static void bxt_de_pll_enable(struct intel_display *display, int vco) 1903 { 1904 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1905 1906 intel_de_rmw(display, BXT_DE_PLL_CTL, 1907 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1908 1909 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1910 1911 /* Timeout 200us */ 1912 if (intel_de_wait_for_set_ms(display, 1913 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1914 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); 1915 1916 display->cdclk.hw.vco = vco; 1917 } 1918 1919 static void icl_cdclk_pll_disable(struct intel_display *display) 1920 { 1921 /* 1922 * Wa_13012396614: 1923 * Fixes: A sporadic race condition between MDCLK selection and PLL 1924 * enabling. 1925 * Workaround: 1926 * Change programming of MDCLK source selection in CDCLK_CTL: 1927 * - When disabling the CDCLK PLL, first set MDCLK source to be CD2XCLK. 1928 * - When enabling the CDCLK PLL, update MDCLK source selection only 1929 * after the PLL is enabled (which is already done as part of the 1930 * normal flow of _bxt_set_cdclk()). 1931 */ 1932 if (intel_display_wa(display, INTEL_DISPLAY_WA_13012396614)) 1933 intel_de_rmw(display, CDCLK_CTL, MDCLK_SOURCE_SEL_MASK, MDCLK_SOURCE_SEL_CD2XCLK); 1934 1935 intel_de_rmw(display, BXT_DE_PLL_ENABLE, 1936 BXT_DE_PLL_PLL_ENABLE, 0); 1937 1938 /* Timeout 200us */ 1939 if (intel_de_wait_for_clear_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1940 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); 1941 1942 display->cdclk.hw.vco = 0; 1943 } 1944 1945 static void icl_cdclk_pll_enable(struct intel_display *display, int vco) 1946 { 1947 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1948 u32 val; 1949 1950 val = ICL_CDCLK_PLL_RATIO(ratio); 1951 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1952 1953 val |= BXT_DE_PLL_PLL_ENABLE; 1954 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1955 1956 /* Timeout 200us */ 1957 if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1958 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); 1959 1960 display->cdclk.hw.vco = vco; 1961 } 1962 1963 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) 1964 { 1965 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1966 u32 val; 1967 1968 /* Write PLL ratio without disabling */ 1969 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1970 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1971 1972 /* Submit freq change request */ 1973 val |= BXT_DE_PLL_FREQ_REQ; 1974 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1975 1976 /* Timeout 200us */ 1977 if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, 1978 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1979 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); 1980 1981 val &= ~BXT_DE_PLL_FREQ_REQ; 1982 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1983 1984 display->cdclk.hw.vco = vco; 1985 } 1986 1987 static u32 bxt_cdclk_cd2x_pipe_mask(struct intel_display *display) 1988 { 1989 if (DISPLAY_VER(display) >= 11) 1990 return ICL_CDCLK_CD2X_PIPE_MASK; 1991 else 1992 return BXT_CDCLK_CD2X_PIPE_MASK; 1993 } 1994 1995 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) 1996 { 1997 if (DISPLAY_VER(display) >= 11) { 1998 if (pipe == INVALID_PIPE) 1999 return ICL_CDCLK_CD2X_PIPE_NONE; 2000 else 2001 return ICL_CDCLK_CD2X_PIPE(pipe); 2002 } else { 2003 if (pipe == INVALID_PIPE) 2004 return BXT_CDCLK_CD2X_PIPE_NONE; 2005 else 2006 return BXT_CDCLK_CD2X_PIPE(pipe); 2007 } 2008 } 2009 2010 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, 2011 int cdclk, int vco, u16 waveform) 2012 { 2013 u32 ret; 2014 2015 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 2016 switch (cdclk_divider(cdclk, vco, waveform)) { 2017 default: 2018 drm_WARN_ON(display->drm, 2019 cdclk != display->cdclk.hw.bypass); 2020 drm_WARN_ON(display->drm, vco != 0); 2021 fallthrough; 2022 case 2: 2023 ret = BXT_CDCLK_CD2X_DIV_SEL_1; 2024 break; 2025 case 3: 2026 ret = BXT_CDCLK_CD2X_DIV_SEL_1_5; 2027 break; 2028 case 4: 2029 ret = BXT_CDCLK_CD2X_DIV_SEL_2; 2030 break; 2031 case 8: 2032 ret = BXT_CDCLK_CD2X_DIV_SEL_4; 2033 break; 2034 } 2035 2036 /* 2037 * On Xe3_LPD onward, the expectation is to always have 2038 * BXT_CDCLK_CD2X_DIV_SEL_1 as the default. 2039 */ 2040 if (DISPLAY_VER(display) >= 30) 2041 drm_WARN_ON(display->drm, ret != BXT_CDCLK_CD2X_DIV_SEL_1); 2042 2043 return ret; 2044 } 2045 2046 static u16 cdclk_squash_waveform(struct intel_display *display, 2047 int cdclk) 2048 { 2049 const struct intel_cdclk_vals *table = display->cdclk.table; 2050 int i; 2051 2052 if (cdclk == display->cdclk.hw.bypass) 2053 return 0; 2054 2055 for (i = 0; table[i].refclk; i++) 2056 if (table[i].refclk == display->cdclk.hw.ref && 2057 table[i].cdclk == cdclk) 2058 return table[i].waveform; 2059 2060 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 2061 cdclk, display->cdclk.hw.ref); 2062 2063 return 0xffff; 2064 } 2065 2066 static void icl_cdclk_pll_update(struct intel_display *display, int vco) 2067 { 2068 if (display->cdclk.hw.vco != 0 && 2069 display->cdclk.hw.vco != vco) 2070 icl_cdclk_pll_disable(display); 2071 2072 if (display->cdclk.hw.vco != vco) 2073 icl_cdclk_pll_enable(display, vco); 2074 } 2075 2076 static void bxt_cdclk_pll_update(struct intel_display *display, int vco) 2077 { 2078 if (display->cdclk.hw.vco != 0 && 2079 display->cdclk.hw.vco != vco) 2080 bxt_de_pll_disable(display); 2081 2082 if (display->cdclk.hw.vco != vco) 2083 bxt_de_pll_enable(display, vco); 2084 } 2085 2086 static void dg2_cdclk_squash_program(struct intel_display *display, 2087 u16 waveform) 2088 { 2089 u32 squash_ctl = 0; 2090 2091 if (waveform) 2092 squash_ctl = CDCLK_SQUASH_ENABLE | 2093 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 2094 2095 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); 2096 } 2097 2098 static bool cdclk_pll_is_unknown(unsigned int vco) 2099 { 2100 /* 2101 * Ensure driver does not take the crawl path for the 2102 * case when the vco is set to ~0 in the 2103 * sanitize path. 2104 */ 2105 return vco == ~0; 2106 } 2107 2108 static bool mdclk_source_is_cdclk_pll(struct intel_display *display) 2109 { 2110 return DISPLAY_VER(display) >= 20; 2111 } 2112 2113 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) 2114 { 2115 if (mdclk_source_is_cdclk_pll(display)) 2116 return MDCLK_SOURCE_SEL_CDCLK_PLL; 2117 2118 return MDCLK_SOURCE_SEL_CD2XCLK; 2119 } 2120 2121 int intel_mdclk_cdclk_ratio(struct intel_display *display, 2122 const struct intel_cdclk_config *cdclk_config) 2123 { 2124 if (mdclk_source_is_cdclk_pll(display)) 2125 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); 2126 2127 /* Otherwise, source for MDCLK is CD2XCLK. */ 2128 return 2; 2129 } 2130 2131 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, 2132 const struct intel_cdclk_config *cdclk_config) 2133 { 2134 intel_dbuf_mdclk_cdclk_ratio_update(display, 2135 intel_mdclk_cdclk_ratio(display, cdclk_config), 2136 cdclk_config->joined_mbus); 2137 } 2138 2139 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, 2140 const struct intel_cdclk_config *old_cdclk_config, 2141 const struct intel_cdclk_config *new_cdclk_config, 2142 struct intel_cdclk_config *mid_cdclk_config) 2143 { 2144 u16 old_waveform, new_waveform, mid_waveform; 2145 int old_div, new_div, mid_div; 2146 2147 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 2148 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 2149 return false; 2150 2151 /* Return if both Squash and Crawl are not present */ 2152 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2153 return false; 2154 2155 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); 2156 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); 2157 2158 /* Return if Squash only or Crawl only is the desired action */ 2159 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 2160 old_cdclk_config->vco == new_cdclk_config->vco || 2161 old_waveform == new_waveform) 2162 return false; 2163 2164 old_div = cdclk_divider(old_cdclk_config->cdclk, 2165 old_cdclk_config->vco, old_waveform); 2166 new_div = cdclk_divider(new_cdclk_config->cdclk, 2167 new_cdclk_config->vco, new_waveform); 2168 2169 /* 2170 * Should not happen currently. We might need more midpoint 2171 * transitions if we need to also change the cd2x divider. 2172 */ 2173 if (drm_WARN_ON(display->drm, old_div != new_div)) 2174 return false; 2175 2176 *mid_cdclk_config = *new_cdclk_config; 2177 2178 /* 2179 * Populate the mid_cdclk_config accordingly. 2180 * - If moving to a higher cdclk, the desired action is squashing. 2181 * The mid cdclk config should have the new (squash) waveform. 2182 * - If moving to a lower cdclk, the desired action is crawling. 2183 * The mid cdclk config should have the new vco. 2184 */ 2185 2186 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 2187 mid_cdclk_config->vco = old_cdclk_config->vco; 2188 mid_div = old_div; 2189 mid_waveform = new_waveform; 2190 } else { 2191 mid_cdclk_config->vco = new_cdclk_config->vco; 2192 mid_div = new_div; 2193 mid_waveform = old_waveform; 2194 } 2195 2196 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 2197 mid_cdclk_config->vco, 2198 cdclk_squash_len * mid_div); 2199 2200 /* make sure the mid clock came out sane */ 2201 2202 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < 2203 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 2204 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > 2205 display->cdclk.max_cdclk_freq); 2206 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != 2207 mid_waveform); 2208 2209 return true; 2210 } 2211 2212 static bool pll_enable_wa_needed(struct intel_display *display) 2213 { 2214 return (DISPLAY_VERx100(display) == 2000 || 2215 DISPLAY_VERx100(display) == 1400 || 2216 display->platform.dg2) && 2217 display->cdclk.hw.vco > 0; 2218 } 2219 2220 static bool has_cd2x_pipe_select(struct intel_display *display) 2221 { 2222 return IS_DISPLAY_VER(display, 10, 20) || display->platform.broxton; 2223 } 2224 2225 static u32 bxt_cdclk_ctl(struct intel_display *display, 2226 const struct intel_cdclk_config *cdclk_config, 2227 enum pipe pipe) 2228 { 2229 int cdclk = cdclk_config->cdclk; 2230 int vco = cdclk_config->vco; 2231 u16 waveform; 2232 u32 val; 2233 2234 waveform = cdclk_squash_waveform(display, cdclk); 2235 2236 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform); 2237 2238 if (has_cd2x_pipe_select(display)) 2239 val |= bxt_cdclk_cd2x_pipe(display, pipe); 2240 2241 /* 2242 * Disable SSA Precharge when CD clock frequency < 500 MHz, 2243 * enable otherwise. 2244 */ 2245 if ((display->platform.geminilake || display->platform.broxton) && 2246 cdclk >= 500000) 2247 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 2248 2249 if (DISPLAY_VER(display) >= 20) { 2250 /* 2251 * Wa_13012396614 requires selecting CD2XCLK as MDCLK source 2252 * prior to disabling the PLL, which is already handled by 2253 * icl_cdclk_pll_disable(). Here we are just making sure 2254 * we keep the expected value. 2255 */ 2256 if (intel_display_wa(display, INTEL_DISPLAY_WA_13012396614) && 2257 vco == 0) 2258 val |= MDCLK_SOURCE_SEL_CD2XCLK; 2259 else 2260 val |= xe2lpd_mdclk_source_sel(display); 2261 } else { 2262 val |= skl_cdclk_decimal(cdclk); 2263 } 2264 2265 return val; 2266 } 2267 2268 static int bxt_cdclk_pcode_pre_notify(struct intel_display *display) 2269 { 2270 /* 2271 * BSpec requires us to wait up to 150usec, but that leads to 2272 * timeouts; the 2ms used here is based on experiment. 2273 */ 2274 return intel_parent_pcode_write_timeout(display, HSW_PCODE_DE_WRITE_FREQ_REQ, 2275 0x80000000, 2); 2276 } 2277 2278 static int bxt_cdclk_pcode_post_notify(struct intel_display *display, 2279 const struct intel_cdclk_config *cdclk_config) 2280 { 2281 /* 2282 * The timeout isn't specified, the 2ms used here is based on 2283 * experiment. 2284 * FIXME: Waiting for the request completion could be delayed 2285 * until the next PCODE request based on BSpec. 2286 */ 2287 return intel_parent_pcode_write_timeout(display, HSW_PCODE_DE_WRITE_FREQ_REQ, 2288 cdclk_config->voltage_level, 2); 2289 } 2290 2291 static void _bxt_set_cdclk(struct intel_display *display, 2292 const struct intel_cdclk_config *cdclk_config, 2293 enum pipe pipe) 2294 { 2295 int cdclk = cdclk_config->cdclk; 2296 int vco = cdclk_config->vco; 2297 2298 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && 2299 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { 2300 if (display->cdclk.hw.vco != vco) 2301 adlp_cdclk_pll_crawl(display, vco); 2302 } else if (DISPLAY_VER(display) >= 11) { 2303 /* wa_15010685871: dg2, mtl */ 2304 if (pll_enable_wa_needed(display)) 2305 dg2_cdclk_squash_program(display, 0); 2306 2307 icl_cdclk_pll_update(display, vco); 2308 } else { 2309 bxt_cdclk_pll_update(display, vco); 2310 } 2311 2312 if (HAS_CDCLK_SQUASH(display)) { 2313 u16 waveform = cdclk_squash_waveform(display, cdclk); 2314 2315 dg2_cdclk_squash_program(display, waveform); 2316 } 2317 2318 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); 2319 2320 if (pipe != INVALID_PIPE) 2321 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 2322 } 2323 2324 static void bxt_set_cdclk(struct intel_display *display, 2325 const struct intel_cdclk_config *cdclk_config, 2326 enum pipe pipe) 2327 { 2328 struct intel_cdclk_config mid_cdclk_config; 2329 int cdclk = cdclk_config->cdclk; 2330 2331 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) 2332 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2333 2334 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, 2335 cdclk_config, &mid_cdclk_config)) { 2336 _bxt_set_cdclk(display, &mid_cdclk_config, pipe); 2337 _bxt_set_cdclk(display, cdclk_config, pipe); 2338 } else { 2339 _bxt_set_cdclk(display, cdclk_config, pipe); 2340 } 2341 2342 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) 2343 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2344 2345 intel_update_cdclk(display); 2346 2347 /* 2348 * Can't read out the voltage level :( 2349 * Let's just assume everything is as expected. 2350 */ 2351 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; 2352 } 2353 2354 static void bxt_sanitize_cdclk(struct intel_display *display) 2355 { 2356 u32 cdctl, expected; 2357 int cdclk, vco; 2358 2359 intel_update_cdclk(display); 2360 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 2361 2362 if (display->cdclk.hw.vco == 0 || 2363 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) { 2364 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to PLL not enabled/locked\n"); 2365 goto sanitize; 2366 } 2367 2368 /* Make sure this is a legal cdclk value for the platform */ 2369 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); 2370 if (cdclk != display->cdclk.hw.cdclk) { 2371 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to bad CDCLK frequency\n"); 2372 goto sanitize; 2373 } 2374 2375 /* Make sure the VCO is correct for the cdclk */ 2376 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 2377 if (vco != display->cdclk.hw.vco) { 2378 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to bad VCO frequency\n"); 2379 goto sanitize; 2380 } 2381 2382 /* 2383 * Some BIOS versions leave an incorrect decimal frequency value and 2384 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 2385 * so sanitize this register. 2386 */ 2387 cdctl = intel_de_read(display, CDCLK_CTL); 2388 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); 2389 2390 /* 2391 * Let's ignore the pipe field, since BIOS could have configured the 2392 * dividers both syncing to an active pipe, or asynchronously 2393 * (PIPE_NONE). 2394 */ 2395 if (has_cd2x_pipe_select(display)) { 2396 cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display); 2397 cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2398 } 2399 2400 if (cdctl != expected) { 2401 if (DISPLAY_VER(display) < 20) { 2402 cdctl &= ~CDCLK_FREQ_DECIMAL_MASK; 2403 cdctl |= expected & CDCLK_FREQ_DECIMAL_MASK; 2404 } 2405 2406 if (cdctl != expected) { 2407 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to CDCLK_CTL 0x%x, expected 0x%x\n", 2408 intel_de_read(display, CDCLK_CTL), expected); 2409 goto sanitize; 2410 } 2411 2412 drm_dbg_kms(display->drm, "Sanitizing CDCLK decimal divider (CDCLK_CTL 0x%x, expected 0x%x)\n", 2413 intel_de_read(display, CDCLK_CTL), expected); 2414 2415 intel_de_write(display, CDCLK_CTL, expected); 2416 } 2417 2418 /* All well; nothing to sanitize */ 2419 return; 2420 2421 sanitize: 2422 /* force cdclk programming */ 2423 display->cdclk.hw.cdclk = 0; 2424 2425 /* force full PLL disable + enable */ 2426 display->cdclk.hw.vco = ~0; 2427 } 2428 2429 static void bxt_cdclk_init_hw(struct intel_display *display) 2430 { 2431 struct intel_cdclk_config cdclk_config; 2432 2433 bxt_sanitize_cdclk(display); 2434 2435 if (display->cdclk.hw.cdclk != 0 && 2436 display->cdclk.hw.vco != 0) 2437 return; 2438 2439 cdclk_config = display->cdclk.hw; 2440 2441 /* 2442 * FIXME: 2443 * - The initial CDCLK needs to be read from VBT. 2444 * Need to make this change after VBT has changes for BXT. 2445 */ 2446 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); 2447 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); 2448 cdclk_config.voltage_level = 2449 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2450 2451 intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2452 } 2453 2454 static void bxt_cdclk_uninit_hw(struct intel_display *display) 2455 { 2456 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 2457 2458 cdclk_config.cdclk = cdclk_config.bypass; 2459 cdclk_config.vco = 0; 2460 cdclk_config.voltage_level = 2461 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2462 2463 intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2464 } 2465 2466 /** 2467 * intel_cdclk_init_hw - Initialize CDCLK hardware 2468 * @display: display instance 2469 * 2470 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and 2471 * sanitizing the state of the hardware if needed. This is generally done only 2472 * during the display core initialization sequence, after which the DMC will 2473 * take care of turning CDCLK off/on as needed. 2474 */ 2475 void intel_cdclk_init_hw(struct intel_display *display) 2476 { 2477 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2478 bxt_cdclk_init_hw(display); 2479 else if (DISPLAY_VER(display) == 9) 2480 skl_cdclk_init_hw(display); 2481 } 2482 2483 /** 2484 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2485 * @display: display instance 2486 * 2487 * Uninitialize CDCLK. This is done only during the display core 2488 * uninitialization sequence. 2489 */ 2490 void intel_cdclk_uninit_hw(struct intel_display *display) 2491 { 2492 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2493 bxt_cdclk_uninit_hw(display); 2494 else if (DISPLAY_VER(display) == 9) 2495 skl_cdclk_uninit_hw(display); 2496 } 2497 2498 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, 2499 const struct intel_cdclk_config *a, 2500 const struct intel_cdclk_config *b) 2501 { 2502 u16 old_waveform; 2503 u16 new_waveform; 2504 2505 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); 2506 2507 if (a->vco == 0 || b->vco == 0) 2508 return false; 2509 2510 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2511 return false; 2512 2513 old_waveform = cdclk_squash_waveform(display, a->cdclk); 2514 new_waveform = cdclk_squash_waveform(display, b->cdclk); 2515 2516 return a->vco != b->vco && 2517 old_waveform != new_waveform; 2518 } 2519 2520 static bool intel_cdclk_can_crawl(struct intel_display *display, 2521 const struct intel_cdclk_config *a, 2522 const struct intel_cdclk_config *b) 2523 { 2524 int a_div, b_div; 2525 2526 if (!HAS_CDCLK_CRAWL(display)) 2527 return false; 2528 2529 /* 2530 * The vco and cd2x divider will change independently 2531 * from each, so we disallow cd2x change when crawling. 2532 */ 2533 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2534 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2535 2536 return a->vco != 0 && b->vco != 0 && 2537 a->vco != b->vco && 2538 a_div == b_div && 2539 a->ref == b->ref; 2540 } 2541 2542 static bool intel_cdclk_can_squash(struct intel_display *display, 2543 const struct intel_cdclk_config *a, 2544 const struct intel_cdclk_config *b) 2545 { 2546 /* 2547 * FIXME should store a bit more state in intel_cdclk_config 2548 * to differentiate squasher vs. cd2x divider properly. For 2549 * the moment all platforms with squasher use a fixed cd2x 2550 * divider. 2551 */ 2552 if (!HAS_CDCLK_SQUASH(display)) 2553 return false; 2554 2555 return a->cdclk != b->cdclk && 2556 a->vco != 0 && 2557 a->vco == b->vco && 2558 a->ref == b->ref; 2559 } 2560 2561 /** 2562 * intel_cdclk_clock_changed - Check whether the clock changed 2563 * @a: first CDCLK configuration 2564 * @b: second CDCLK configuration 2565 * 2566 * Returns: 2567 * True if CDCLK changed in a way that requires re-programming and 2568 * False otherwise. 2569 */ 2570 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, 2571 const struct intel_cdclk_config *b) 2572 { 2573 return a->cdclk != b->cdclk || 2574 a->vco != b->vco || 2575 a->ref != b->ref; 2576 } 2577 2578 /** 2579 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2580 * configurations requires only a cd2x divider update 2581 * @display: display instance 2582 * @a: first CDCLK configuration 2583 * @b: second CDCLK configuration 2584 * 2585 * Returns: 2586 * True if changing between the two CDCLK configurations 2587 * can be done with just a cd2x divider update, false if not. 2588 */ 2589 static bool intel_cdclk_can_cd2x_update(struct intel_display *display, 2590 const struct intel_cdclk_config *a, 2591 const struct intel_cdclk_config *b) 2592 { 2593 if (!has_cd2x_pipe_select(display)) 2594 return false; 2595 2596 /* 2597 * FIXME should store a bit more state in intel_cdclk_config 2598 * to differentiate squasher vs. cd2x divider properly. For 2599 * the moment all platforms with squasher use a fixed cd2x 2600 * divider. 2601 */ 2602 if (HAS_CDCLK_SQUASH(display)) 2603 return false; 2604 2605 return a->cdclk != b->cdclk && 2606 a->vco != 0 && 2607 a->vco == b->vco && 2608 a->ref == b->ref; 2609 } 2610 2611 /** 2612 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2613 * @a: first CDCLK configuration 2614 * @b: second CDCLK configuration 2615 * 2616 * Returns: 2617 * True if the CDCLK configurations don't match, false if they do. 2618 */ 2619 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2620 const struct intel_cdclk_config *b) 2621 { 2622 return intel_cdclk_clock_changed(a, b) || 2623 a->voltage_level != b->voltage_level; 2624 } 2625 2626 void intel_cdclk_dump_config(struct intel_display *display, 2627 const struct intel_cdclk_config *cdclk_config, 2628 const char *context) 2629 { 2630 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2631 context, cdclk_config->cdclk, cdclk_config->vco, 2632 cdclk_config->ref, cdclk_config->bypass, 2633 cdclk_config->voltage_level); 2634 } 2635 2636 static int dg2_cdclk_pcode_notify(struct intel_display *display, 2637 u8 voltage_level, 2638 u8 active_pipe_count, 2639 u16 cdclk, 2640 bool cdclk_update_valid, 2641 bool pipe_count_update_valid) 2642 { 2643 u32 update_mask = 0; 2644 2645 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); 2646 2647 if (cdclk_update_valid) 2648 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID; 2649 2650 if (pipe_count_update_valid) 2651 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; 2652 2653 return intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL, 2654 update_mask, 2655 SKL_CDCLK_READY_FOR_CHANGE, 2656 SKL_CDCLK_READY_FOR_CHANGE, 3); 2657 } 2658 2659 static void intel_set_cdclk(struct intel_display *display, 2660 const struct intel_cdclk_config *cdclk_config, 2661 enum pipe pipe, const char *context) 2662 { 2663 struct intel_encoder *encoder; 2664 2665 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) 2666 return; 2667 2668 if (drm_WARN_ON_ONCE(display->drm, !display->cdclk.funcs->set_cdclk)) 2669 return; 2670 2671 intel_cdclk_dump_config(display, cdclk_config, context); 2672 2673 for_each_intel_encoder_with_psr(display->drm, encoder) { 2674 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2675 2676 intel_psr_pause(intel_dp); 2677 } 2678 2679 intel_audio_cdclk_change_pre(display); 2680 2681 /* 2682 * Lock aux/gmbus while we change cdclk in case those 2683 * functions use cdclk. Not all platforms/ports do, 2684 * but we'll lock them all for simplicity. 2685 */ 2686 mutex_lock(&display->gmbus.mutex); 2687 for_each_intel_dp(display->drm, encoder) { 2688 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2689 2690 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2691 &display->gmbus.mutex); 2692 } 2693 2694 intel_cdclk_set_cdclk(display, cdclk_config, pipe); 2695 2696 for_each_intel_dp(display->drm, encoder) { 2697 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2698 2699 mutex_unlock(&intel_dp->aux.hw_mutex); 2700 } 2701 mutex_unlock(&display->gmbus.mutex); 2702 2703 for_each_intel_encoder_with_psr(display->drm, encoder) { 2704 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2705 2706 intel_psr_resume(intel_dp); 2707 } 2708 2709 intel_audio_cdclk_change_post(display); 2710 2711 if (drm_WARN(display->drm, 2712 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), 2713 "cdclk state doesn't match!\n")) { 2714 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); 2715 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); 2716 } 2717 } 2718 2719 static int dg2_power_well_count(struct intel_display *display, 2720 const struct intel_cdclk_state *cdclk_state) 2721 { 2722 return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0; 2723 } 2724 2725 static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state) 2726 { 2727 struct intel_display *display = to_intel_display(state); 2728 const struct intel_cdclk_state *old_cdclk_state = 2729 intel_atomic_get_old_cdclk_state(state); 2730 const struct intel_cdclk_state *new_cdclk_state = 2731 intel_atomic_get_new_cdclk_state(state); 2732 u8 voltage_level, num_active_pipes = 0; 2733 bool change_cdclk, update_pipe_count; 2734 unsigned int cdclk_mhz = 0; 2735 int ret; 2736 2737 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2738 &new_cdclk_state->actual) && 2739 dg2_power_well_count(display, old_cdclk_state) == 2740 dg2_power_well_count(display, new_cdclk_state)) 2741 return; 2742 2743 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ 2744 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX; 2745 2746 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2747 update_pipe_count = dg2_power_well_count(display, new_cdclk_state) > 2748 dg2_power_well_count(display, old_cdclk_state); 2749 2750 /* 2751 * According to "Sequence Before Frequency Change", 2752 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, 2753 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, 2754 * which basically means we choose the maximum of old and new CDCLK, if we know both 2755 */ 2756 if (change_cdclk) { 2757 unsigned int cdclk = max(new_cdclk_state->actual.cdclk, 2758 old_cdclk_state->actual.cdclk); 2759 2760 cdclk_mhz = DIV_ROUND_UP(cdclk, 1000); 2761 } 2762 2763 /* 2764 * According to "Sequence For Pipe Count Change", 2765 * if pipe count is increasing, set bits 25:16 to upcoming pipe count 2766 * (power well is enabled) 2767 * no action if it is decreasing, before the change 2768 */ 2769 if (update_pipe_count) 2770 num_active_pipes = dg2_power_well_count(display, new_cdclk_state); 2771 2772 ret = dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk_mhz, 2773 change_cdclk, update_pipe_count); 2774 if (ret) 2775 drm_err(display->drm, 2776 "Failed to inform PCODE about start of CDCLK change (%d)\n", ret); 2777 } 2778 2779 static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state) 2780 { 2781 struct intel_display *display = to_intel_display(state); 2782 const struct intel_cdclk_state *new_cdclk_state = 2783 intel_atomic_get_new_cdclk_state(state); 2784 const struct intel_cdclk_state *old_cdclk_state = 2785 intel_atomic_get_old_cdclk_state(state); 2786 u8 voltage_level, num_active_pipes = 0; 2787 bool update_cdclk, update_pipe_count; 2788 unsigned int cdclk_mhz = 0; 2789 int ret; 2790 2791 /* According to "Sequence After Frequency Change", set voltage to used level */ 2792 voltage_level = new_cdclk_state->actual.voltage_level; 2793 2794 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2795 update_pipe_count = dg2_power_well_count(display, new_cdclk_state) < 2796 dg2_power_well_count(display, old_cdclk_state); 2797 2798 /* 2799 * According to "Sequence After Frequency Change", 2800 * set bits 25:16 to current CDCLK 2801 */ 2802 if (update_cdclk) { 2803 unsigned int cdclk = new_cdclk_state->actual.cdclk; 2804 2805 cdclk_mhz = DIV_ROUND_UP(cdclk, 1000); 2806 } 2807 2808 /* 2809 * According to "Sequence For Pipe Count Change", 2810 * if pipe count is decreasing, set bits 25:16 to current pipe count, 2811 * after the change(power well is disabled) 2812 * no action if it is increasing, after the change 2813 */ 2814 if (update_pipe_count) 2815 num_active_pipes = dg2_power_well_count(display, new_cdclk_state); 2816 2817 ret = dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk_mhz, 2818 update_cdclk, update_pipe_count); 2819 if (ret) 2820 drm_err(display->drm, 2821 "Failed to inform PCODE about end of CDCLK change (%d)\n", ret); 2822 } 2823 2824 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) 2825 { 2826 const struct intel_cdclk_state *old_cdclk_state = 2827 intel_atomic_get_old_cdclk_state(state); 2828 const struct intel_cdclk_state *new_cdclk_state = 2829 intel_atomic_get_new_cdclk_state(state); 2830 2831 return new_cdclk_state && !new_cdclk_state->disable_pipes && 2832 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; 2833 } 2834 2835 /** 2836 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2837 * @state: intel atomic state 2838 * 2839 * Program the hardware before updating the HW plane state based on the 2840 * new CDCLK state, if necessary. 2841 */ 2842 void 2843 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2844 { 2845 struct intel_display *display = to_intel_display(state); 2846 const struct intel_cdclk_state *old_cdclk_state = 2847 intel_atomic_get_old_cdclk_state(state); 2848 const struct intel_cdclk_state *new_cdclk_state = 2849 intel_atomic_get_new_cdclk_state(state); 2850 struct intel_cdclk_config cdclk_config; 2851 enum pipe pipe; 2852 2853 if (!new_cdclk_state) 2854 return; 2855 2856 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2857 &new_cdclk_state->actual) && 2858 dg2_power_well_count(display, old_cdclk_state) == 2859 dg2_power_well_count(display, new_cdclk_state)) 2860 return; 2861 2862 if (new_cdclk_state->disable_pipes) { 2863 cdclk_config = new_cdclk_state->actual; 2864 pipe = INVALID_PIPE; 2865 } else { 2866 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { 2867 cdclk_config = new_cdclk_state->actual; 2868 pipe = new_cdclk_state->pipe; 2869 } else { 2870 cdclk_config = old_cdclk_state->actual; 2871 pipe = INVALID_PIPE; 2872 } 2873 2874 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, 2875 old_cdclk_state->actual.voltage_level); 2876 } 2877 2878 /* 2879 * mbus joining will be changed later by 2880 * intel_dbuf_mbus_{pre,post}_ddb_update() 2881 */ 2882 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; 2883 2884 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2885 2886 if (display->platform.dg2) 2887 dg2_cdclk_pcode_pre_notify(state); 2888 2889 intel_set_cdclk(display, &cdclk_config, pipe, 2890 "Pre changing CDCLK to"); 2891 } 2892 2893 /** 2894 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2895 * @state: intel atomic state 2896 * 2897 * Program the hardware after updating the HW plane state based on the 2898 * new CDCLK state, if necessary. 2899 */ 2900 void 2901 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2902 { 2903 struct intel_display *display = to_intel_display(state); 2904 const struct intel_cdclk_state *old_cdclk_state = 2905 intel_atomic_get_old_cdclk_state(state); 2906 const struct intel_cdclk_state *new_cdclk_state = 2907 intel_atomic_get_new_cdclk_state(state); 2908 enum pipe pipe; 2909 2910 if (!new_cdclk_state) 2911 return; 2912 2913 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2914 &new_cdclk_state->actual) && 2915 dg2_power_well_count(display, old_cdclk_state) == 2916 dg2_power_well_count(display, new_cdclk_state)) 2917 return; 2918 2919 if (!new_cdclk_state->disable_pipes && 2920 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) 2921 pipe = new_cdclk_state->pipe; 2922 else 2923 pipe = INVALID_PIPE; 2924 2925 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2926 2927 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, 2928 "Post changing CDCLK to"); 2929 2930 if (display->platform.dg2) 2931 dg2_cdclk_pcode_post_notify(state); 2932 } 2933 2934 /* pixels per CDCLK */ 2935 int intel_cdclk_ppc(struct intel_display *display, bool double_wide) 2936 { 2937 return HAS_2PPC(display) || double_wide ? 2 : 1; 2938 } 2939 2940 /* max pixel rate as % of CDCLK (not accounting for PPC) */ 2941 static int intel_cdclk_guardband(struct intel_display *display) 2942 { 2943 if (DISPLAY_VER(display) >= 9 || 2944 display->platform.broadwell || display->platform.haswell) 2945 return 100; 2946 else if (display->platform.cherryview) 2947 return 95; 2948 else 2949 return 90; 2950 } 2951 2952 static int _intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state, int pixel_rate) 2953 { 2954 struct intel_display *display = to_intel_display(crtc_state); 2955 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 2956 int guardband = intel_cdclk_guardband(display); 2957 2958 return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc); 2959 } 2960 2961 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2962 { 2963 return _intel_pixel_rate_to_cdclk(crtc_state, crtc_state->pixel_rate_cdclk); 2964 } 2965 2966 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2967 { 2968 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2969 struct intel_display *display = to_intel_display(crtc); 2970 struct intel_plane *plane; 2971 int min_cdclk = 0; 2972 2973 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 2974 min_cdclk = max(min_cdclk, crtc_state->plane_min_cdclk[plane->id]); 2975 2976 return min_cdclk; 2977 } 2978 2979 int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state) 2980 { 2981 int min_cdclk; 2982 2983 if (!crtc_state->hw.enable) 2984 return 0; 2985 2986 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2987 min_cdclk = max(min_cdclk, intel_crtc_bw_min_cdclk(crtc_state)); 2988 min_cdclk = max(min_cdclk, intel_fbc_min_cdclk(crtc_state)); 2989 min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state)); 2990 min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state)); 2991 min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state)); 2992 min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state)); 2993 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2994 2995 return min_cdclk; 2996 } 2997 2998 static int intel_cdclk_update_crtc_min_cdclk(struct intel_atomic_state *state, 2999 struct intel_crtc *crtc, 3000 int old_min_cdclk, int new_min_cdclk, 3001 bool *need_cdclk_calc) 3002 { 3003 struct intel_display *display = to_intel_display(state); 3004 struct intel_cdclk_state *cdclk_state; 3005 bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state); 3006 int ret; 3007 3008 if (new_min_cdclk == old_min_cdclk) 3009 return 0; 3010 3011 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 3012 return 0; 3013 3014 cdclk_state = intel_atomic_get_cdclk_state(state); 3015 if (IS_ERR(cdclk_state)) 3016 return PTR_ERR(cdclk_state); 3017 3018 old_min_cdclk = cdclk_state->min_cdclk[crtc->pipe]; 3019 3020 if (new_min_cdclk == old_min_cdclk) 3021 return 0; 3022 3023 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 3024 return 0; 3025 3026 cdclk_state->min_cdclk[crtc->pipe] = new_min_cdclk; 3027 3028 ret = intel_atomic_lock_global_state(&cdclk_state->base); 3029 if (ret) 3030 return ret; 3031 3032 *need_cdclk_calc = true; 3033 3034 drm_dbg_kms(display->drm, 3035 "[CRTC:%d:%s] min cdclk: %d kHz -> %d kHz\n", 3036 crtc->base.base.id, crtc->base.name, 3037 old_min_cdclk, new_min_cdclk); 3038 3039 return 0; 3040 } 3041 3042 static int intel_cdclk_update_crtc_min_voltage_level(struct intel_atomic_state *state, 3043 struct intel_crtc *crtc, 3044 u8 old_min_voltage_level, 3045 u8 new_min_voltage_level, 3046 bool *need_cdclk_calc) 3047 { 3048 struct intel_display *display = to_intel_display(state); 3049 struct intel_cdclk_state *cdclk_state; 3050 bool allow_voltage_level_decrease = intel_any_crtc_needs_modeset(state); 3051 int ret; 3052 3053 if (new_min_voltage_level == old_min_voltage_level) 3054 return 0; 3055 3056 if (!allow_voltage_level_decrease && 3057 new_min_voltage_level < old_min_voltage_level) 3058 return 0; 3059 3060 cdclk_state = intel_atomic_get_cdclk_state(state); 3061 if (IS_ERR(cdclk_state)) 3062 return PTR_ERR(cdclk_state); 3063 3064 old_min_voltage_level = cdclk_state->min_voltage_level[crtc->pipe]; 3065 3066 if (new_min_voltage_level == old_min_voltage_level) 3067 return 0; 3068 3069 if (!allow_voltage_level_decrease && 3070 new_min_voltage_level < old_min_voltage_level) 3071 return 0; 3072 3073 cdclk_state->min_voltage_level[crtc->pipe] = new_min_voltage_level; 3074 3075 ret = intel_atomic_lock_global_state(&cdclk_state->base); 3076 if (ret) 3077 return ret; 3078 3079 *need_cdclk_calc = true; 3080 3081 drm_dbg_kms(display->drm, 3082 "[CRTC:%d:%s] min voltage level: %d -> %d\n", 3083 crtc->base.base.id, crtc->base.name, 3084 old_min_voltage_level, new_min_voltage_level); 3085 3086 return 0; 3087 } 3088 3089 int intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state *state, 3090 int old_min_cdclk, int new_min_cdclk, 3091 bool *need_cdclk_calc) 3092 { 3093 struct intel_display *display = to_intel_display(state); 3094 struct intel_cdclk_state *cdclk_state; 3095 bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state); 3096 int ret; 3097 3098 if (new_min_cdclk == old_min_cdclk) 3099 return 0; 3100 3101 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 3102 return 0; 3103 3104 cdclk_state = intel_atomic_get_cdclk_state(state); 3105 if (IS_ERR(cdclk_state)) 3106 return PTR_ERR(cdclk_state); 3107 3108 old_min_cdclk = cdclk_state->dbuf_bw_min_cdclk; 3109 3110 if (new_min_cdclk == old_min_cdclk) 3111 return 0; 3112 3113 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 3114 return 0; 3115 3116 cdclk_state->dbuf_bw_min_cdclk = new_min_cdclk; 3117 3118 ret = intel_atomic_lock_global_state(&cdclk_state->base); 3119 if (ret) 3120 return ret; 3121 3122 *need_cdclk_calc = true; 3123 3124 drm_dbg_kms(display->drm, 3125 "dbuf bandwidth min cdclk: %d kHz -> %d kHz\n", 3126 old_min_cdclk, new_min_cdclk); 3127 3128 return 0; 3129 } 3130 3131 static bool glk_cdclk_audio_wa_needed(struct intel_display *display, 3132 const struct intel_cdclk_state *cdclk_state) 3133 { 3134 return display->platform.geminilake && 3135 cdclk_state->enabled_pipes && 3136 !is_power_of_2(cdclk_state->enabled_pipes); 3137 } 3138 3139 static int intel_compute_min_cdclk(struct intel_atomic_state *state) 3140 { 3141 struct intel_display *display = to_intel_display(state); 3142 struct intel_cdclk_state *cdclk_state = 3143 intel_atomic_get_new_cdclk_state(state); 3144 enum pipe pipe; 3145 int min_cdclk; 3146 3147 min_cdclk = cdclk_state->force_min_cdclk; 3148 min_cdclk = max(min_cdclk, cdclk_state->dbuf_bw_min_cdclk); 3149 for_each_pipe(display, pipe) 3150 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]); 3151 3152 /* 3153 * Avoid glk_force_audio_cdclk() causing excessive screen 3154 * blinking when multiple pipes are active by making sure 3155 * CDCLK frequency is always high enough for audio. With a 3156 * single active pipe we can always change CDCLK frequency 3157 * by changing the cd2x divider (see glk_cdclk_table[]) and 3158 * thus a full modeset won't be needed then. 3159 */ 3160 if (glk_cdclk_audio_wa_needed(display, cdclk_state)) 3161 min_cdclk = max(min_cdclk, 2 * 96000); 3162 3163 if (min_cdclk > display->cdclk.max_cdclk_freq) { 3164 drm_dbg_kms(display->drm, 3165 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 3166 min_cdclk, display->cdclk.max_cdclk_freq); 3167 return -EINVAL; 3168 } 3169 3170 return min_cdclk; 3171 } 3172 3173 /* 3174 * Account for port clock min voltage level requirements. 3175 * This only really does something on DISPLA_VER >= 11 but can be 3176 * called on earlier platforms as well. 3177 * 3178 * Note that this functions assumes that 0 is 3179 * the lowest voltage value, and higher values 3180 * correspond to increasingly higher voltages. 3181 * 3182 * Should that relationship no longer hold on 3183 * future platforms this code will need to be 3184 * adjusted. 3185 */ 3186 static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) 3187 { 3188 struct intel_display *display = to_intel_display(state); 3189 struct intel_cdclk_state *cdclk_state = 3190 intel_atomic_get_new_cdclk_state(state); 3191 struct intel_crtc *crtc; 3192 struct intel_crtc_state *crtc_state; 3193 u8 min_voltage_level; 3194 enum pipe pipe; 3195 3196 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 3197 int ret; 3198 3199 if (crtc_state->hw.enable) 3200 min_voltage_level = crtc_state->min_voltage_level; 3201 else 3202 min_voltage_level = 0; 3203 3204 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 3205 continue; 3206 3207 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 3208 3209 ret = intel_atomic_lock_global_state(&cdclk_state->base); 3210 if (ret) 3211 return ret; 3212 } 3213 3214 min_voltage_level = 0; 3215 for_each_pipe(display, pipe) 3216 min_voltage_level = max(min_voltage_level, 3217 cdclk_state->min_voltage_level[pipe]); 3218 3219 return min_voltage_level; 3220 } 3221 3222 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) 3223 { 3224 struct intel_display *display = to_intel_display(state); 3225 struct intel_cdclk_state *cdclk_state = 3226 intel_atomic_get_new_cdclk_state(state); 3227 int min_cdclk, cdclk; 3228 3229 min_cdclk = intel_compute_min_cdclk(state); 3230 if (min_cdclk < 0) 3231 return min_cdclk; 3232 3233 cdclk = vlv_calc_cdclk(display, min_cdclk); 3234 3235 cdclk_state->logical.cdclk = cdclk; 3236 cdclk_state->logical.voltage_level = 3237 vlv_calc_voltage_level(display, cdclk); 3238 3239 if (!cdclk_state->active_pipes) { 3240 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); 3241 3242 cdclk_state->actual.cdclk = cdclk; 3243 cdclk_state->actual.voltage_level = 3244 vlv_calc_voltage_level(display, cdclk); 3245 } else { 3246 cdclk_state->actual = cdclk_state->logical; 3247 } 3248 3249 return 0; 3250 } 3251 3252 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) 3253 { 3254 struct intel_cdclk_state *cdclk_state = 3255 intel_atomic_get_new_cdclk_state(state); 3256 int min_cdclk, cdclk; 3257 3258 min_cdclk = intel_compute_min_cdclk(state); 3259 if (min_cdclk < 0) 3260 return min_cdclk; 3261 3262 cdclk = bdw_calc_cdclk(min_cdclk); 3263 3264 cdclk_state->logical.cdclk = cdclk; 3265 cdclk_state->logical.voltage_level = 3266 bdw_calc_voltage_level(cdclk); 3267 3268 if (!cdclk_state->active_pipes) { 3269 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 3270 3271 cdclk_state->actual.cdclk = cdclk; 3272 cdclk_state->actual.voltage_level = 3273 bdw_calc_voltage_level(cdclk); 3274 } else { 3275 cdclk_state->actual = cdclk_state->logical; 3276 } 3277 3278 return 0; 3279 } 3280 3281 static int skl_dpll0_vco(struct intel_atomic_state *state) 3282 { 3283 struct intel_display *display = to_intel_display(state); 3284 struct intel_cdclk_state *cdclk_state = 3285 intel_atomic_get_new_cdclk_state(state); 3286 struct intel_crtc *crtc; 3287 struct intel_crtc_state *crtc_state; 3288 int vco; 3289 3290 vco = cdclk_state->logical.vco; 3291 if (!vco) 3292 vco = display->cdclk.skl_preferred_vco_freq; 3293 3294 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 3295 if (!crtc_state->hw.enable) 3296 continue; 3297 3298 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 3299 continue; 3300 3301 /* 3302 * DPLL0 VCO may need to be adjusted to get the correct 3303 * clock for eDP. This will affect cdclk as well. 3304 */ 3305 switch (crtc_state->port_clock / 2) { 3306 case 108000: 3307 case 216000: 3308 vco = 8640000; 3309 break; 3310 default: 3311 vco = 8100000; 3312 break; 3313 } 3314 } 3315 3316 return vco; 3317 } 3318 3319 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) 3320 { 3321 struct intel_cdclk_state *cdclk_state = 3322 intel_atomic_get_new_cdclk_state(state); 3323 int min_cdclk, cdclk, vco; 3324 3325 min_cdclk = intel_compute_min_cdclk(state); 3326 if (min_cdclk < 0) 3327 return min_cdclk; 3328 3329 vco = skl_dpll0_vco(state); 3330 3331 cdclk = skl_calc_cdclk(min_cdclk, vco); 3332 3333 cdclk_state->logical.vco = vco; 3334 cdclk_state->logical.cdclk = cdclk; 3335 cdclk_state->logical.voltage_level = 3336 skl_calc_voltage_level(cdclk); 3337 3338 if (!cdclk_state->active_pipes) { 3339 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 3340 3341 cdclk_state->actual.vco = vco; 3342 cdclk_state->actual.cdclk = cdclk; 3343 cdclk_state->actual.voltage_level = 3344 skl_calc_voltage_level(cdclk); 3345 } else { 3346 cdclk_state->actual = cdclk_state->logical; 3347 } 3348 3349 return 0; 3350 } 3351 3352 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) 3353 { 3354 struct intel_display *display = to_intel_display(state); 3355 struct intel_cdclk_state *cdclk_state = 3356 intel_atomic_get_new_cdclk_state(state); 3357 int min_cdclk, min_voltage_level, cdclk, vco; 3358 3359 min_cdclk = intel_compute_min_cdclk(state); 3360 if (min_cdclk < 0) 3361 return min_cdclk; 3362 3363 min_voltage_level = bxt_compute_min_voltage_level(state); 3364 if (min_voltage_level < 0) 3365 return min_voltage_level; 3366 3367 cdclk = bxt_calc_cdclk(display, min_cdclk); 3368 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3369 3370 cdclk_state->logical.vco = vco; 3371 cdclk_state->logical.cdclk = cdclk; 3372 cdclk_state->logical.voltage_level = 3373 max_t(int, min_voltage_level, 3374 intel_cdclk_calc_voltage_level(display, cdclk)); 3375 3376 if (!cdclk_state->active_pipes) { 3377 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); 3378 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3379 3380 cdclk_state->actual.vco = vco; 3381 cdclk_state->actual.cdclk = cdclk; 3382 cdclk_state->actual.voltage_level = 3383 intel_cdclk_calc_voltage_level(display, cdclk); 3384 } else { 3385 cdclk_state->actual = cdclk_state->logical; 3386 } 3387 3388 return 0; 3389 } 3390 3391 static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) 3392 { 3393 int min_cdclk; 3394 3395 /* 3396 * We can't change the cdclk frequency, but we still want to 3397 * check that the required minimum frequency doesn't exceed 3398 * the actual cdclk frequency. 3399 */ 3400 min_cdclk = intel_compute_min_cdclk(state); 3401 if (min_cdclk < 0) 3402 return min_cdclk; 3403 3404 return 0; 3405 } 3406 3407 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 3408 { 3409 struct intel_cdclk_state *cdclk_state; 3410 3411 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 3412 if (!cdclk_state) 3413 return NULL; 3414 3415 cdclk_state->pipe = INVALID_PIPE; 3416 cdclk_state->disable_pipes = false; 3417 3418 return &cdclk_state->base; 3419 } 3420 3421 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 3422 struct intel_global_state *state) 3423 { 3424 kfree(state); 3425 } 3426 3427 static const struct intel_global_state_funcs intel_cdclk_funcs = { 3428 .atomic_duplicate_state = intel_cdclk_duplicate_state, 3429 .atomic_destroy_state = intel_cdclk_destroy_state, 3430 }; 3431 3432 struct intel_cdclk_state * 3433 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 3434 { 3435 struct intel_display *display = to_intel_display(state); 3436 struct intel_global_state *cdclk_state; 3437 3438 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); 3439 if (IS_ERR(cdclk_state)) 3440 return ERR_CAST(cdclk_state); 3441 3442 return to_intel_cdclk_state(cdclk_state); 3443 } 3444 3445 static int intel_cdclk_modeset_checks(struct intel_atomic_state *state, 3446 bool *need_cdclk_calc) 3447 { 3448 struct intel_display *display = to_intel_display(state); 3449 const struct intel_cdclk_state *old_cdclk_state; 3450 struct intel_cdclk_state *new_cdclk_state; 3451 int ret; 3452 3453 if (!intel_any_crtc_enable_changed(state) && 3454 !intel_any_crtc_active_changed(state)) 3455 return 0; 3456 3457 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3458 if (IS_ERR(new_cdclk_state)) 3459 return PTR_ERR(new_cdclk_state); 3460 3461 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3462 3463 new_cdclk_state->enabled_pipes = 3464 intel_calc_enabled_pipes(state, old_cdclk_state->enabled_pipes); 3465 3466 new_cdclk_state->active_pipes = 3467 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 3468 3469 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3470 if (ret) 3471 return ret; 3472 3473 if (!old_cdclk_state->active_pipes != !new_cdclk_state->active_pipes) 3474 *need_cdclk_calc = true; 3475 3476 if (glk_cdclk_audio_wa_needed(display, old_cdclk_state) != 3477 glk_cdclk_audio_wa_needed(display, new_cdclk_state)) 3478 *need_cdclk_calc = true; 3479 3480 if (dg2_power_well_count(display, old_cdclk_state) != 3481 dg2_power_well_count(display, new_cdclk_state)) 3482 *need_cdclk_calc = true; 3483 3484 return 0; 3485 } 3486 3487 static int intel_crtcs_calc_min_cdclk(struct intel_atomic_state *state, 3488 bool *need_cdclk_calc) 3489 { 3490 const struct intel_crtc_state *old_crtc_state; 3491 const struct intel_crtc_state *new_crtc_state; 3492 struct intel_crtc *crtc; 3493 int ret; 3494 3495 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 3496 ret = intel_cdclk_update_crtc_min_cdclk(state, crtc, 3497 old_crtc_state->min_cdclk, 3498 new_crtc_state->min_cdclk, 3499 need_cdclk_calc); 3500 if (ret) 3501 return ret; 3502 3503 ret = intel_cdclk_update_crtc_min_voltage_level(state, crtc, 3504 old_crtc_state->min_voltage_level, 3505 new_crtc_state->min_voltage_level, 3506 need_cdclk_calc); 3507 if (ret) 3508 return ret; 3509 } 3510 3511 return 0; 3512 } 3513 3514 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus) 3515 { 3516 struct intel_cdclk_state *cdclk_state; 3517 3518 cdclk_state = intel_atomic_get_cdclk_state(state); 3519 if (IS_ERR(cdclk_state)) 3520 return PTR_ERR(cdclk_state); 3521 3522 cdclk_state->actual.joined_mbus = joined_mbus; 3523 cdclk_state->logical.joined_mbus = joined_mbus; 3524 3525 return intel_atomic_lock_global_state(&cdclk_state->base); 3526 } 3527 3528 int intel_cdclk_init(struct intel_display *display) 3529 { 3530 struct intel_cdclk_state *cdclk_state; 3531 3532 cdclk_state = kzalloc_obj(*cdclk_state); 3533 if (!cdclk_state) 3534 return -ENOMEM; 3535 3536 intel_atomic_global_obj_init(display, &display->cdclk.obj, 3537 &cdclk_state->base, &intel_cdclk_funcs); 3538 3539 return 0; 3540 } 3541 3542 static bool intel_cdclk_need_serialize(struct intel_display *display, 3543 const struct intel_cdclk_state *old_cdclk_state, 3544 const struct intel_cdclk_state *new_cdclk_state) 3545 { 3546 /* 3547 * We need to poke hw for DG2, because we notify PCode if 3548 * pipe power well count changes. 3549 */ 3550 return intel_cdclk_changed(&old_cdclk_state->actual, 3551 &new_cdclk_state->actual) || 3552 dg2_power_well_count(display, old_cdclk_state) != 3553 dg2_power_well_count(display, new_cdclk_state); 3554 } 3555 3556 static int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 3557 { 3558 struct intel_display *display = to_intel_display(state); 3559 const struct intel_cdclk_state *old_cdclk_state; 3560 struct intel_cdclk_state *new_cdclk_state; 3561 enum pipe pipe = INVALID_PIPE; 3562 int ret; 3563 3564 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3565 if (IS_ERR(new_cdclk_state)) 3566 return PTR_ERR(new_cdclk_state); 3567 3568 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3569 3570 ret = intel_cdclk_modeset_calc_cdclk(state); 3571 if (ret) 3572 return ret; 3573 3574 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { 3575 /* 3576 * Also serialize commits across all crtcs 3577 * if the actual hw needs to be poked. 3578 */ 3579 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 3580 if (ret) 3581 return ret; 3582 } else if (intel_cdclk_changed(&old_cdclk_state->logical, 3583 &new_cdclk_state->logical)) { 3584 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3585 if (ret) 3586 return ret; 3587 } else { 3588 return 0; 3589 } 3590 3591 if (is_power_of_2(new_cdclk_state->active_pipes) && 3592 intel_cdclk_can_cd2x_update(display, 3593 &old_cdclk_state->actual, 3594 &new_cdclk_state->actual)) { 3595 struct intel_crtc *crtc; 3596 struct intel_crtc_state *crtc_state; 3597 3598 pipe = ilog2(new_cdclk_state->active_pipes); 3599 crtc = intel_crtc_for_pipe(display, pipe); 3600 3601 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 3602 if (IS_ERR(crtc_state)) 3603 return PTR_ERR(crtc_state); 3604 3605 if (intel_crtc_needs_modeset(crtc_state)) 3606 pipe = INVALID_PIPE; 3607 } 3608 3609 if (intel_cdclk_can_crawl_and_squash(display, 3610 &old_cdclk_state->actual, 3611 &new_cdclk_state->actual)) { 3612 drm_dbg_kms(display->drm, 3613 "Can change cdclk via crawling and squashing\n"); 3614 } else if (intel_cdclk_can_squash(display, 3615 &old_cdclk_state->actual, 3616 &new_cdclk_state->actual)) { 3617 drm_dbg_kms(display->drm, 3618 "Can change cdclk via squashing\n"); 3619 } else if (intel_cdclk_can_crawl(display, 3620 &old_cdclk_state->actual, 3621 &new_cdclk_state->actual)) { 3622 drm_dbg_kms(display->drm, 3623 "Can change cdclk via crawling\n"); 3624 } else if (pipe != INVALID_PIPE) { 3625 new_cdclk_state->pipe = pipe; 3626 3627 drm_dbg_kms(display->drm, 3628 "Can change cdclk cd2x divider with pipe %c active\n", 3629 pipe_name(pipe)); 3630 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, 3631 &new_cdclk_state->actual)) { 3632 /* All pipes must be switched off while we change the cdclk. */ 3633 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); 3634 if (ret) 3635 return ret; 3636 3637 new_cdclk_state->disable_pipes = true; 3638 3639 drm_dbg_kms(display->drm, 3640 "Modeset required for cdclk change\n"); 3641 } 3642 3643 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != 3644 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { 3645 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); 3646 3647 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio); 3648 if (ret) 3649 return ret; 3650 } 3651 3652 drm_dbg_kms(display->drm, 3653 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 3654 new_cdclk_state->logical.cdclk, 3655 new_cdclk_state->actual.cdclk); 3656 drm_dbg_kms(display->drm, 3657 "New voltage level calculated to be logical %u, actual %u\n", 3658 new_cdclk_state->logical.voltage_level, 3659 new_cdclk_state->actual.voltage_level); 3660 3661 return 0; 3662 } 3663 3664 int intel_cdclk_atomic_check(struct intel_atomic_state *state) 3665 { 3666 const struct intel_cdclk_state *old_cdclk_state; 3667 struct intel_cdclk_state *new_cdclk_state; 3668 bool need_cdclk_calc = false; 3669 int ret; 3670 3671 ret = intel_cdclk_modeset_checks(state, &need_cdclk_calc); 3672 if (ret) 3673 return ret; 3674 3675 ret = intel_crtcs_calc_min_cdclk(state, &need_cdclk_calc); 3676 if (ret) 3677 return ret; 3678 3679 ret = intel_dbuf_bw_calc_min_cdclk(state, &need_cdclk_calc); 3680 if (ret) 3681 return ret; 3682 3683 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3684 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3685 3686 if (new_cdclk_state && 3687 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) { 3688 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3689 if (ret) 3690 return ret; 3691 3692 need_cdclk_calc = true; 3693 } 3694 3695 if (need_cdclk_calc) { 3696 ret = intel_modeset_calc_cdclk(state); 3697 if (ret) 3698 return ret; 3699 } 3700 3701 return 0; 3702 } 3703 3704 void intel_cdclk_update_hw_state(struct intel_display *display) 3705 { 3706 const struct intel_dbuf_bw_state *dbuf_bw_state = 3707 to_intel_dbuf_bw_state(display->dbuf_bw.obj.state); 3708 struct intel_cdclk_state *cdclk_state = 3709 to_intel_cdclk_state(display->cdclk.obj.state); 3710 struct intel_crtc *crtc; 3711 3712 cdclk_state->enabled_pipes = 0; 3713 cdclk_state->active_pipes = 0; 3714 3715 for_each_intel_crtc(display, crtc) { 3716 const struct intel_crtc_state *crtc_state = 3717 to_intel_crtc_state(crtc->base.state); 3718 enum pipe pipe = crtc->pipe; 3719 3720 if (crtc_state->hw.enable) 3721 cdclk_state->enabled_pipes |= BIT(pipe); 3722 if (crtc_state->hw.active) 3723 cdclk_state->active_pipes |= BIT(pipe); 3724 3725 cdclk_state->min_cdclk[pipe] = crtc_state->min_cdclk; 3726 cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level; 3727 } 3728 3729 cdclk_state->dbuf_bw_min_cdclk = intel_dbuf_bw_min_cdclk(display, dbuf_bw_state); 3730 } 3731 3732 void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc) 3733 { 3734 struct intel_display *display = to_intel_display(crtc); 3735 3736 intel_cdclk_update_hw_state(display); 3737 } 3738 3739 static int intel_compute_max_dotclk(struct intel_display *display) 3740 { 3741 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); 3742 int guardband = intel_cdclk_guardband(display); 3743 int max_cdclk_freq = display->cdclk.max_cdclk_freq; 3744 3745 return ppc * max_cdclk_freq * guardband / 100; 3746 } 3747 3748 /** 3749 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 3750 * @display: display instance 3751 * 3752 * Determine the maximum CDCLK frequency the platform supports, and also 3753 * derive the maximum dot clock frequency the maximum CDCLK frequency 3754 * allows. 3755 */ 3756 void intel_update_max_cdclk(struct intel_display *display) 3757 { 3758 if (DISPLAY_VER(display) >= 35) { 3759 display->cdclk.max_cdclk_freq = 787200; 3760 } else if (DISPLAY_VERx100(display) >= 3002) { 3761 display->cdclk.max_cdclk_freq = 480000; 3762 } else if (DISPLAY_VER(display) >= 30) { 3763 display->cdclk.max_cdclk_freq = 691200; 3764 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 3765 if (display->cdclk.hw.ref == 24000) 3766 display->cdclk.max_cdclk_freq = 552000; 3767 else 3768 display->cdclk.max_cdclk_freq = 556800; 3769 } else if (DISPLAY_VER(display) >= 11) { 3770 if (display->cdclk.hw.ref == 24000) 3771 display->cdclk.max_cdclk_freq = 648000; 3772 else 3773 display->cdclk.max_cdclk_freq = 652800; 3774 } else if (display->platform.geminilake) { 3775 display->cdclk.max_cdclk_freq = 316800; 3776 } else if (display->platform.broxton) { 3777 display->cdclk.max_cdclk_freq = 624000; 3778 } else if (DISPLAY_VER(display) == 9) { 3779 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3780 int max_cdclk, vco; 3781 3782 vco = display->cdclk.skl_preferred_vco_freq; 3783 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 3784 3785 /* 3786 * Use the lower (vco 8640) cdclk values as a 3787 * first guess. skl_calc_cdclk() will correct it 3788 * if the preferred vco is 8100 instead. 3789 */ 3790 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3791 max_cdclk = 617143; 3792 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3793 max_cdclk = 540000; 3794 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3795 max_cdclk = 432000; 3796 else 3797 max_cdclk = 308571; 3798 3799 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3800 } else if (display->platform.broadwell) { 3801 /* 3802 * FIXME with extra cooling we can allow 3803 * 540 MHz for ULX and 675 Mhz for ULT. 3804 * How can we know if extra cooling is 3805 * available? PCI ID, VTB, something else? 3806 */ 3807 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3808 display->cdclk.max_cdclk_freq = 450000; 3809 else if (display->platform.broadwell_ulx) 3810 display->cdclk.max_cdclk_freq = 450000; 3811 else if (display->platform.broadwell_ult) 3812 display->cdclk.max_cdclk_freq = 540000; 3813 else 3814 display->cdclk.max_cdclk_freq = 675000; 3815 } else if (display->platform.cherryview) { 3816 display->cdclk.max_cdclk_freq = 320000; 3817 } else if (display->platform.valleyview) { 3818 display->cdclk.max_cdclk_freq = 400000; 3819 } else { 3820 /* otherwise assume cdclk is fixed */ 3821 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; 3822 } 3823 3824 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); 3825 3826 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", 3827 display->cdclk.max_cdclk_freq); 3828 3829 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", 3830 display->cdclk.max_dotclk_freq); 3831 } 3832 3833 /** 3834 * intel_update_cdclk - Determine the current CDCLK frequency 3835 * @display: display instance 3836 * 3837 * Determine the current CDCLK frequency. 3838 */ 3839 void intel_update_cdclk(struct intel_display *display) 3840 { 3841 intel_cdclk_get_cdclk(display, &display->cdclk.hw); 3842 3843 /* 3844 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3845 * Programmng [sic] note: bit[9:2] should be programmed to the number 3846 * of cdclk that generates 4MHz reference clock freq which is used to 3847 * generate GMBus clock. This will vary with the cdclk freq. 3848 */ 3849 if (display->platform.valleyview || display->platform.cherryview) 3850 intel_de_write(display, GMBUSFREQ_VLV, 3851 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); 3852 } 3853 3854 static int dg1_rawclk(struct intel_display *display) 3855 { 3856 /* 3857 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3858 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3859 */ 3860 intel_de_write(display, PCH_RAWCLK_FREQ, 3861 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3862 3863 return 38400; 3864 } 3865 3866 static int cnp_rawclk(struct intel_display *display) 3867 { 3868 int divider, fraction; 3869 u32 rawclk; 3870 3871 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3872 /* 24 MHz */ 3873 divider = 24000; 3874 fraction = 0; 3875 } else { 3876 /* 19.2 MHz */ 3877 divider = 19000; 3878 fraction = 200; 3879 } 3880 3881 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3882 if (fraction) { 3883 int numerator = 1; 3884 3885 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3886 fraction) - 1); 3887 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 3888 rawclk |= ICP_RAWCLK_NUM(numerator); 3889 } 3890 3891 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); 3892 return divider + fraction; 3893 } 3894 3895 static int pch_rawclk(struct intel_display *display) 3896 { 3897 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3898 } 3899 3900 static int i9xx_hrawclk(struct intel_display *display) 3901 { 3902 /* hrawclock is 1/4 the FSB frequency */ 3903 return DIV_ROUND_CLOSEST(intel_fsb_freq(display), 4); 3904 } 3905 3906 /** 3907 * intel_read_rawclk - Determine the current RAWCLK frequency 3908 * @display: display instance 3909 * 3910 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3911 * frequency clock so this needs to done only once. 3912 */ 3913 u32 intel_read_rawclk(struct intel_display *display) 3914 { 3915 u32 freq; 3916 3917 if (INTEL_PCH_TYPE(display) >= PCH_MTL) 3918 /* 3919 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3920 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3921 * not need to be programmed." 3922 */ 3923 freq = 38400; 3924 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 3925 freq = dg1_rawclk(display); 3926 else if (INTEL_PCH_TYPE(display) >= PCH_CNP) 3927 freq = cnp_rawclk(display); 3928 else if (HAS_PCH_SPLIT(display)) 3929 freq = pch_rawclk(display); 3930 else if (display->platform.valleyview || display->platform.cherryview) 3931 freq = vlv_clock_get_hrawclk(display->drm); 3932 else if (DISPLAY_VER(display) >= 3) 3933 freq = i9xx_hrawclk(display); 3934 else 3935 /* no rawclk on other platforms, or no need to know it */ 3936 return 0; 3937 3938 return freq; 3939 } 3940 3941 static int i915_cdclk_info_show(struct seq_file *m, void *unused) 3942 { 3943 struct intel_display *display = m->private; 3944 3945 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); 3946 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); 3947 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); 3948 3949 return 0; 3950 } 3951 3952 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); 3953 3954 void intel_cdclk_debugfs_register(struct intel_display *display) 3955 { 3956 debugfs_create_file("i915_cdclk_info", 0444, display->drm->debugfs_root, 3957 display, &i915_cdclk_info_fops); 3958 } 3959 3960 static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = { 3961 .get_cdclk = bxt_get_cdclk, 3962 .set_cdclk = bxt_set_cdclk, 3963 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3964 .calc_voltage_level = xe3lpd_calc_voltage_level, 3965 }; 3966 3967 static const struct intel_cdclk_funcs mtl_cdclk_funcs = { 3968 .get_cdclk = bxt_get_cdclk, 3969 .set_cdclk = bxt_set_cdclk, 3970 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3971 .calc_voltage_level = rplu_calc_voltage_level, 3972 }; 3973 3974 static const struct intel_cdclk_funcs dg2_cdclk_funcs = { 3975 .get_cdclk = bxt_get_cdclk, 3976 .set_cdclk = bxt_set_cdclk, 3977 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3978 .calc_voltage_level = tgl_calc_voltage_level, 3979 }; 3980 3981 static const struct intel_cdclk_funcs rplu_cdclk_funcs = { 3982 .get_cdclk = bxt_get_cdclk, 3983 .set_cdclk = bxt_set_cdclk, 3984 .pre_notify = skl_cdclk_pcode_pre_notify, 3985 .post_notify = skl_cdclk_pcode_post_notify, 3986 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3987 .calc_voltage_level = rplu_calc_voltage_level, 3988 }; 3989 3990 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3991 .get_cdclk = bxt_get_cdclk, 3992 .set_cdclk = bxt_set_cdclk, 3993 .pre_notify = skl_cdclk_pcode_pre_notify, 3994 .post_notify = skl_cdclk_pcode_post_notify, 3995 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3996 .calc_voltage_level = tgl_calc_voltage_level, 3997 }; 3998 3999 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 4000 .get_cdclk = bxt_get_cdclk, 4001 .set_cdclk = bxt_set_cdclk, 4002 .pre_notify = skl_cdclk_pcode_pre_notify, 4003 .post_notify = skl_cdclk_pcode_post_notify, 4004 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 4005 .calc_voltage_level = ehl_calc_voltage_level, 4006 }; 4007 4008 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 4009 .get_cdclk = bxt_get_cdclk, 4010 .set_cdclk = bxt_set_cdclk, 4011 .pre_notify = skl_cdclk_pcode_pre_notify, 4012 .post_notify = skl_cdclk_pcode_post_notify, 4013 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 4014 .calc_voltage_level = icl_calc_voltage_level, 4015 }; 4016 4017 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 4018 .get_cdclk = bxt_get_cdclk, 4019 .set_cdclk = bxt_set_cdclk, 4020 .pre_notify = bxt_cdclk_pcode_pre_notify, 4021 .post_notify = bxt_cdclk_pcode_post_notify, 4022 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 4023 .calc_voltage_level = bxt_calc_voltage_level, 4024 }; 4025 4026 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 4027 .get_cdclk = skl_get_cdclk, 4028 .set_cdclk = skl_set_cdclk, 4029 .pre_notify = skl_cdclk_pcode_pre_notify, 4030 .post_notify = skl_cdclk_pcode_post_notify, 4031 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 4032 }; 4033 4034 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 4035 .get_cdclk = bdw_get_cdclk, 4036 .set_cdclk = bdw_set_cdclk, 4037 .pre_notify = bdw_cdclk_pcode_pre_notify, 4038 .post_notify = bdw_cdclk_pcode_post_notify, 4039 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 4040 }; 4041 4042 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 4043 .get_cdclk = vlv_get_cdclk, 4044 .set_cdclk = chv_set_cdclk, 4045 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 4046 }; 4047 4048 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 4049 .get_cdclk = vlv_get_cdclk, 4050 .set_cdclk = vlv_set_cdclk, 4051 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 4052 }; 4053 4054 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 4055 .get_cdclk = hsw_get_cdclk, 4056 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4057 }; 4058 4059 /* SNB, IVB, 965G, 945G */ 4060 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 4061 .get_cdclk = fixed_400mhz_get_cdclk, 4062 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4063 }; 4064 4065 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 4066 .get_cdclk = fixed_450mhz_get_cdclk, 4067 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4068 }; 4069 4070 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 4071 .get_cdclk = gm45_get_cdclk, 4072 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4073 }; 4074 4075 /* G45 uses G33 */ 4076 4077 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 4078 .get_cdclk = i965gm_get_cdclk, 4079 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4080 }; 4081 4082 /* i965G uses fixed 400 */ 4083 4084 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 4085 .get_cdclk = pnv_get_cdclk, 4086 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4087 }; 4088 4089 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 4090 .get_cdclk = g33_get_cdclk, 4091 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4092 }; 4093 4094 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 4095 .get_cdclk = i945gm_get_cdclk, 4096 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4097 }; 4098 4099 /* i945G uses fixed 400 */ 4100 4101 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 4102 .get_cdclk = i915gm_get_cdclk, 4103 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4104 }; 4105 4106 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 4107 .get_cdclk = fixed_333mhz_get_cdclk, 4108 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4109 }; 4110 4111 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 4112 .get_cdclk = fixed_266mhz_get_cdclk, 4113 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4114 }; 4115 4116 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 4117 .get_cdclk = i85x_get_cdclk, 4118 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4119 }; 4120 4121 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 4122 .get_cdclk = fixed_200mhz_get_cdclk, 4123 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4124 }; 4125 4126 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 4127 .get_cdclk = fixed_133mhz_get_cdclk, 4128 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4129 }; 4130 4131 /** 4132 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 4133 * @display: display instance 4134 */ 4135 void intel_init_cdclk_hooks(struct intel_display *display) 4136 { 4137 if (DISPLAY_VER(display) >= 35) { 4138 display->cdclk.funcs = &xe3lpd_cdclk_funcs; 4139 display->cdclk.table = xe3p_lpd_cdclk_table; 4140 } else if (DISPLAY_VER(display) >= 30) { 4141 display->cdclk.funcs = &xe3lpd_cdclk_funcs; 4142 display->cdclk.table = xe3lpd_cdclk_table; 4143 } else if (DISPLAY_VER(display) >= 20) { 4144 display->cdclk.funcs = &mtl_cdclk_funcs; 4145 display->cdclk.table = xe2lpd_cdclk_table; 4146 } else if (DISPLAY_VERx100(display) >= 1401) { 4147 display->cdclk.funcs = &mtl_cdclk_funcs; 4148 display->cdclk.table = xe2hpd_cdclk_table; 4149 } else if (DISPLAY_VER(display) >= 14) { 4150 display->cdclk.funcs = &mtl_cdclk_funcs; 4151 display->cdclk.table = mtl_cdclk_table; 4152 } else if (display->platform.dg2) { 4153 display->cdclk.funcs = &dg2_cdclk_funcs; 4154 display->cdclk.table = dg2_cdclk_table; 4155 } else if (display->platform.alderlake_p) { 4156 /* Wa_22011320316:adl-p[a0] */ 4157 if (intel_display_wa(display, INTEL_DISPLAY_WA_22011320316)) { 4158 display->cdclk.table = adlp_a_step_cdclk_table; 4159 display->cdclk.funcs = &tgl_cdclk_funcs; 4160 } else if (display->platform.alderlake_p_raptorlake_u) { 4161 display->cdclk.table = rplu_cdclk_table; 4162 display->cdclk.funcs = &rplu_cdclk_funcs; 4163 } else { 4164 display->cdclk.table = adlp_cdclk_table; 4165 display->cdclk.funcs = &tgl_cdclk_funcs; 4166 } 4167 } else if (display->platform.rocketlake) { 4168 display->cdclk.funcs = &tgl_cdclk_funcs; 4169 display->cdclk.table = rkl_cdclk_table; 4170 } else if (DISPLAY_VER(display) >= 12) { 4171 display->cdclk.funcs = &tgl_cdclk_funcs; 4172 display->cdclk.table = icl_cdclk_table; 4173 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 4174 display->cdclk.funcs = &ehl_cdclk_funcs; 4175 display->cdclk.table = icl_cdclk_table; 4176 } else if (DISPLAY_VER(display) >= 11) { 4177 display->cdclk.funcs = &icl_cdclk_funcs; 4178 display->cdclk.table = icl_cdclk_table; 4179 } else if (display->platform.geminilake || display->platform.broxton) { 4180 display->cdclk.funcs = &bxt_cdclk_funcs; 4181 if (display->platform.geminilake) 4182 display->cdclk.table = glk_cdclk_table; 4183 else 4184 display->cdclk.table = bxt_cdclk_table; 4185 } else if (DISPLAY_VER(display) == 9) { 4186 display->cdclk.funcs = &skl_cdclk_funcs; 4187 } else if (display->platform.broadwell) { 4188 display->cdclk.funcs = &bdw_cdclk_funcs; 4189 } else if (display->platform.haswell) { 4190 display->cdclk.funcs = &hsw_cdclk_funcs; 4191 } else if (display->platform.cherryview) { 4192 display->cdclk.funcs = &chv_cdclk_funcs; 4193 } else if (display->platform.valleyview) { 4194 display->cdclk.funcs = &vlv_cdclk_funcs; 4195 } else if (display->platform.sandybridge || display->platform.ivybridge) { 4196 display->cdclk.funcs = &fixed_400mhz_cdclk_funcs; 4197 } else if (display->platform.ironlake) { 4198 display->cdclk.funcs = &ilk_cdclk_funcs; 4199 } else if (display->platform.gm45) { 4200 display->cdclk.funcs = &gm45_cdclk_funcs; 4201 } else if (display->platform.g45) { 4202 display->cdclk.funcs = &g33_cdclk_funcs; 4203 } else if (display->platform.i965gm) { 4204 display->cdclk.funcs = &i965gm_cdclk_funcs; 4205 } else if (display->platform.i965g) { 4206 display->cdclk.funcs = &fixed_400mhz_cdclk_funcs; 4207 } else if (display->platform.pineview) { 4208 display->cdclk.funcs = &pnv_cdclk_funcs; 4209 } else if (display->platform.g33) { 4210 display->cdclk.funcs = &g33_cdclk_funcs; 4211 } else if (display->platform.i945gm) { 4212 display->cdclk.funcs = &i945gm_cdclk_funcs; 4213 } else if (display->platform.i945g) { 4214 display->cdclk.funcs = &fixed_400mhz_cdclk_funcs; 4215 } else if (display->platform.i915gm) { 4216 display->cdclk.funcs = &i915gm_cdclk_funcs; 4217 } else if (display->platform.i915g) { 4218 display->cdclk.funcs = &i915g_cdclk_funcs; 4219 } else if (display->platform.i865g) { 4220 display->cdclk.funcs = &i865g_cdclk_funcs; 4221 } else if (display->platform.i85x) { 4222 display->cdclk.funcs = &i85x_cdclk_funcs; 4223 } else if (display->platform.i845g) { 4224 display->cdclk.funcs = &i845g_cdclk_funcs; 4225 } else if (display->platform.i830) { 4226 display->cdclk.funcs = &i830_cdclk_funcs; 4227 } 4228 4229 if (drm_WARN(display->drm, !display->cdclk.funcs, 4230 "Unknown platform. Assuming i830\n")) 4231 display->cdclk.funcs = &i830_cdclk_funcs; 4232 } 4233 4234 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state) 4235 { 4236 return cdclk_state->logical.cdclk; 4237 } 4238 4239 int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state) 4240 { 4241 return cdclk_state->actual.cdclk; 4242 } 4243 4244 int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state) 4245 { 4246 return cdclk_state->actual.voltage_level; 4247 } 4248 4249 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe) 4250 { 4251 return cdclk_state->min_cdclk[pipe]; 4252 } 4253 4254 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state) 4255 { 4256 const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state; 4257 4258 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 4259 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 4260 4261 if (new_cdclk_state && 4262 (new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk || 4263 new_cdclk_state->actual.voltage_level != old_cdclk_state->actual.voltage_level)) 4264 return true; 4265 4266 return false; 4267 } 4268 4269 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk) 4270 { 4271 cdclk_state->force_min_cdclk = force_min_cdclk; 4272 } 4273 4274 void intel_cdclk_read_hw(struct intel_display *display) 4275 { 4276 struct intel_cdclk_state *cdclk_state; 4277 4278 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); 4279 4280 intel_update_cdclk(display); 4281 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 4282 cdclk_state->actual = display->cdclk.hw; 4283 cdclk_state->logical = display->cdclk.hw; 4284 } 4285 4286 static int calc_cdclk(const struct intel_crtc_state *crtc_state, int min_cdclk) 4287 { 4288 struct intel_display *display = to_intel_display(crtc_state); 4289 4290 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) { 4291 return bxt_calc_cdclk(display, min_cdclk); 4292 } else if (DISPLAY_VER(display) == 9) { 4293 int vco; 4294 4295 vco = display->cdclk.skl_preferred_vco_freq; 4296 if (vco == 0) 4297 vco = 8100000; 4298 4299 return skl_calc_cdclk(min_cdclk, vco); 4300 } else if (display->platform.broadwell) { 4301 return bdw_calc_cdclk(min_cdclk); 4302 } else if (display->platform.cherryview || display->platform.valleyview) { 4303 return vlv_calc_cdclk(display, min_cdclk); 4304 } else { 4305 return display->cdclk.max_cdclk_freq; 4306 } 4307 } 4308 4309 static unsigned int _intel_cdclk_prefill_adj(const struct intel_crtc_state *crtc_state, 4310 int clock, int min_cdclk) 4311 { 4312 struct intel_display *display = to_intel_display(crtc_state); 4313 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 4314 int cdclk = calc_cdclk(crtc_state, min_cdclk); 4315 4316 return min(0x10000, DIV_ROUND_UP_ULL((u64)clock << 16, ppc * cdclk)); 4317 } 4318 4319 unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) 4320 { 4321 /* FIXME use the actual min_cdclk for the pipe here */ 4322 return intel_cdclk_prefill_adjustment_worst(crtc_state); 4323 } 4324 4325 unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state) 4326 { 4327 int clock = crtc_state->hw.pipe_mode.crtc_clock; 4328 int min_cdclk; 4329 4330 /* 4331 * FIXME could perhaps consider a few more of the factors 4332 * that go the per-crtc min_cdclk. Namely anything that 4333 * only changes during full modesets. 4334 * 4335 * FIXME this assumes 1:1 scaling, but the other _worst() stuff 4336 * assumes max downscaling, so the final result will be 4337 * unrealistically bad. Figure out where the actual maximum value 4338 * lies and use that to compute a more realistic worst case 4339 * estimate... 4340 */ 4341 min_cdclk = _intel_pixel_rate_to_cdclk(crtc_state, clock); 4342 4343 return _intel_cdclk_prefill_adj(crtc_state, clock, min_cdclk); 4344 } 4345 4346 int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state, 4347 unsigned int prefill_lines_unadjusted, 4348 unsigned int prefill_lines_available) 4349 { 4350 struct intel_display *display = to_intel_display(crtc_state); 4351 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 4352 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 4353 4354 return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, prefill_lines_unadjusted), 4355 ppc * prefill_lines_available); 4356 } 4357