1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9
10 #include "pinctrl-msm.h"
11
12 enum {
13 SOUTH,
14 EAST,
15 WEST
16 };
17
18 static const char * const qcs615_tiles[] = {
19 [SOUTH] = "south",
20 [EAST] = "east",
21 [WEST] = "west"
22 };
23
24 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
25 { \
26 .grp = PINCTRL_PINGROUP("gpio" #id, \
27 gpio##id##_pins, \
28 ARRAY_SIZE(gpio##id##_pins)), \
29 .funcs = (int[]){ \
30 msm_mux_gpio, /* gpio mode */ \
31 msm_mux_##f1, \
32 msm_mux_##f2, \
33 msm_mux_##f3, \
34 msm_mux_##f4, \
35 msm_mux_##f5, \
36 msm_mux_##f6, \
37 msm_mux_##f7, \
38 msm_mux_##f8, \
39 msm_mux_##f9 \
40 }, \
41 .nfuncs = 10, \
42 .ctl_reg = 0x1000 * id, \
43 .io_reg = 0x1000 * id + 0x4, \
44 .intr_cfg_reg = 0x1000 * id + 0x8, \
45 .intr_status_reg = 0x1000 * id + 0xc, \
46 .tile = _tile, \
47 .mux_bit = 2, \
48 .pull_bit = 0, \
49 .drv_bit = 6, \
50 .oe_bit = 9, \
51 .in_bit = 0, \
52 .out_bit = 1, \
53 .intr_enable_bit = 0, \
54 .intr_status_bit = 0, \
55 .intr_target_bit = 5, \
56 .intr_target_kpss_val = 3, \
57 .intr_raw_status_bit = 4, \
58 .intr_polarity_bit = 1, \
59 .intr_detection_bit = 2, \
60 .intr_detection_width = 2, \
61 }
62
63 #define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \
64 { \
65 .grp = PINCTRL_PINGROUP(#pg_name, \
66 pg_name##_pins, \
67 ARRAY_SIZE(pg_name##_pins)), \
68 .ctl_reg = ctl, \
69 .io_reg = 0, \
70 .intr_cfg_reg = 0, \
71 .intr_status_reg = 0, \
72 .tile = _tile, \
73 .mux_bit = -1, \
74 .pull_bit = pull, \
75 .drv_bit = drv, \
76 .oe_bit = -1, \
77 .in_bit = -1, \
78 .out_bit = -1, \
79 .intr_enable_bit = -1, \
80 .intr_status_bit = -1, \
81 .intr_target_bit = -1, \
82 .intr_raw_status_bit = -1, \
83 .intr_polarity_bit = -1, \
84 .intr_detection_bit = -1, \
85 .intr_detection_width = -1, \
86 }
87
88 #define UFS_RESET(pg_name, offset) \
89 { \
90 .grp = PINCTRL_PINGROUP(#pg_name, \
91 pg_name##_pins, \
92 ARRAY_SIZE(pg_name##_pins)), \
93 .ctl_reg = offset, \
94 .io_reg = offset + 0x4, \
95 .intr_cfg_reg = 0, \
96 .intr_status_reg = 0, \
97 .tile = WEST, \
98 .mux_bit = -1, \
99 .pull_bit = 3, \
100 .drv_bit = 0, \
101 .oe_bit = -1, \
102 .in_bit = -1, \
103 .out_bit = 0, \
104 .intr_enable_bit = -1, \
105 .intr_status_bit = -1, \
106 .intr_target_bit = -1, \
107 .intr_raw_status_bit = -1, \
108 .intr_polarity_bit = -1, \
109 .intr_detection_bit = -1, \
110 .intr_detection_width = -1, \
111 }
112
113 static const struct pinctrl_pin_desc qcs615_pins[] = {
114 PINCTRL_PIN(0, "GPIO_0"),
115 PINCTRL_PIN(1, "GPIO_1"),
116 PINCTRL_PIN(2, "GPIO_2"),
117 PINCTRL_PIN(3, "GPIO_3"),
118 PINCTRL_PIN(4, "GPIO_4"),
119 PINCTRL_PIN(5, "GPIO_5"),
120 PINCTRL_PIN(6, "GPIO_6"),
121 PINCTRL_PIN(7, "GPIO_7"),
122 PINCTRL_PIN(8, "GPIO_8"),
123 PINCTRL_PIN(9, "GPIO_9"),
124 PINCTRL_PIN(10, "GPIO_10"),
125 PINCTRL_PIN(11, "GPIO_11"),
126 PINCTRL_PIN(12, "GPIO_12"),
127 PINCTRL_PIN(13, "GPIO_13"),
128 PINCTRL_PIN(14, "GPIO_14"),
129 PINCTRL_PIN(15, "GPIO_15"),
130 PINCTRL_PIN(16, "GPIO_16"),
131 PINCTRL_PIN(17, "GPIO_17"),
132 PINCTRL_PIN(18, "GPIO_18"),
133 PINCTRL_PIN(19, "GPIO_19"),
134 PINCTRL_PIN(20, "GPIO_20"),
135 PINCTRL_PIN(21, "GPIO_21"),
136 PINCTRL_PIN(22, "GPIO_22"),
137 PINCTRL_PIN(23, "GPIO_23"),
138 PINCTRL_PIN(24, "GPIO_24"),
139 PINCTRL_PIN(25, "GPIO_25"),
140 PINCTRL_PIN(26, "GPIO_26"),
141 PINCTRL_PIN(27, "GPIO_27"),
142 PINCTRL_PIN(28, "GPIO_28"),
143 PINCTRL_PIN(29, "GPIO_29"),
144 PINCTRL_PIN(30, "GPIO_30"),
145 PINCTRL_PIN(31, "GPIO_31"),
146 PINCTRL_PIN(32, "GPIO_32"),
147 PINCTRL_PIN(33, "GPIO_33"),
148 PINCTRL_PIN(34, "GPIO_34"),
149 PINCTRL_PIN(35, "GPIO_35"),
150 PINCTRL_PIN(36, "GPIO_36"),
151 PINCTRL_PIN(37, "GPIO_37"),
152 PINCTRL_PIN(38, "GPIO_38"),
153 PINCTRL_PIN(39, "GPIO_39"),
154 PINCTRL_PIN(40, "GPIO_40"),
155 PINCTRL_PIN(41, "GPIO_41"),
156 PINCTRL_PIN(42, "GPIO_42"),
157 PINCTRL_PIN(43, "GPIO_43"),
158 PINCTRL_PIN(44, "GPIO_44"),
159 PINCTRL_PIN(45, "GPIO_45"),
160 PINCTRL_PIN(46, "GPIO_46"),
161 PINCTRL_PIN(47, "GPIO_47"),
162 PINCTRL_PIN(48, "GPIO_48"),
163 PINCTRL_PIN(49, "GPIO_49"),
164 PINCTRL_PIN(50, "GPIO_50"),
165 PINCTRL_PIN(51, "GPIO_51"),
166 PINCTRL_PIN(52, "GPIO_52"),
167 PINCTRL_PIN(53, "GPIO_53"),
168 PINCTRL_PIN(54, "GPIO_54"),
169 PINCTRL_PIN(55, "GPIO_55"),
170 PINCTRL_PIN(56, "GPIO_56"),
171 PINCTRL_PIN(57, "GPIO_57"),
172 PINCTRL_PIN(58, "GPIO_58"),
173 PINCTRL_PIN(59, "GPIO_59"),
174 PINCTRL_PIN(60, "GPIO_60"),
175 PINCTRL_PIN(61, "GPIO_61"),
176 PINCTRL_PIN(62, "GPIO_62"),
177 PINCTRL_PIN(63, "GPIO_63"),
178 PINCTRL_PIN(64, "GPIO_64"),
179 PINCTRL_PIN(65, "GPIO_65"),
180 PINCTRL_PIN(66, "GPIO_66"),
181 PINCTRL_PIN(67, "GPIO_67"),
182 PINCTRL_PIN(68, "GPIO_68"),
183 PINCTRL_PIN(69, "GPIO_69"),
184 PINCTRL_PIN(70, "GPIO_70"),
185 PINCTRL_PIN(71, "GPIO_71"),
186 PINCTRL_PIN(72, "GPIO_72"),
187 PINCTRL_PIN(73, "GPIO_73"),
188 PINCTRL_PIN(74, "GPIO_74"),
189 PINCTRL_PIN(75, "GPIO_75"),
190 PINCTRL_PIN(76, "GPIO_76"),
191 PINCTRL_PIN(77, "GPIO_77"),
192 PINCTRL_PIN(78, "GPIO_78"),
193 PINCTRL_PIN(79, "GPIO_79"),
194 PINCTRL_PIN(80, "GPIO_80"),
195 PINCTRL_PIN(81, "GPIO_81"),
196 PINCTRL_PIN(82, "GPIO_82"),
197 PINCTRL_PIN(83, "GPIO_83"),
198 PINCTRL_PIN(84, "GPIO_84"),
199 PINCTRL_PIN(85, "GPIO_85"),
200 PINCTRL_PIN(86, "GPIO_86"),
201 PINCTRL_PIN(87, "GPIO_87"),
202 PINCTRL_PIN(88, "GPIO_88"),
203 PINCTRL_PIN(89, "GPIO_89"),
204 PINCTRL_PIN(90, "GPIO_90"),
205 PINCTRL_PIN(91, "GPIO_91"),
206 PINCTRL_PIN(92, "GPIO_92"),
207 PINCTRL_PIN(93, "GPIO_93"),
208 PINCTRL_PIN(94, "GPIO_94"),
209 PINCTRL_PIN(95, "GPIO_95"),
210 PINCTRL_PIN(96, "GPIO_96"),
211 PINCTRL_PIN(97, "GPIO_97"),
212 PINCTRL_PIN(98, "GPIO_98"),
213 PINCTRL_PIN(99, "GPIO_99"),
214 PINCTRL_PIN(100, "GPIO_100"),
215 PINCTRL_PIN(101, "GPIO_101"),
216 PINCTRL_PIN(102, "GPIO_102"),
217 PINCTRL_PIN(103, "GPIO_103"),
218 PINCTRL_PIN(104, "GPIO_104"),
219 PINCTRL_PIN(105, "GPIO_105"),
220 PINCTRL_PIN(106, "GPIO_106"),
221 PINCTRL_PIN(107, "GPIO_107"),
222 PINCTRL_PIN(108, "GPIO_108"),
223 PINCTRL_PIN(109, "GPIO_109"),
224 PINCTRL_PIN(110, "GPIO_110"),
225 PINCTRL_PIN(111, "GPIO_111"),
226 PINCTRL_PIN(112, "GPIO_112"),
227 PINCTRL_PIN(113, "GPIO_113"),
228 PINCTRL_PIN(114, "GPIO_114"),
229 PINCTRL_PIN(115, "GPIO_115"),
230 PINCTRL_PIN(116, "GPIO_116"),
231 PINCTRL_PIN(117, "GPIO_117"),
232 PINCTRL_PIN(118, "GPIO_118"),
233 PINCTRL_PIN(119, "GPIO_119"),
234 PINCTRL_PIN(120, "GPIO_120"),
235 PINCTRL_PIN(121, "GPIO_121"),
236 PINCTRL_PIN(122, "GPIO_122"),
237 PINCTRL_PIN(123, "UFS_RESET"),
238 PINCTRL_PIN(124, "SDC1_RCLK"),
239 PINCTRL_PIN(125, "SDC1_CLK"),
240 PINCTRL_PIN(126, "SDC1_CMD"),
241 PINCTRL_PIN(127, "SDC1_DATA"),
242 PINCTRL_PIN(128, "SDC2_CLK"),
243 PINCTRL_PIN(129, "SDC2_CMD"),
244 PINCTRL_PIN(130, "SDC2_DATA"),
245 };
246
247 #define DECLARE_MSM_GPIO_PINS(pin) \
248 static const unsigned int gpio##pin##_pins[] = { pin }
249 DECLARE_MSM_GPIO_PINS(0);
250 DECLARE_MSM_GPIO_PINS(1);
251 DECLARE_MSM_GPIO_PINS(2);
252 DECLARE_MSM_GPIO_PINS(3);
253 DECLARE_MSM_GPIO_PINS(4);
254 DECLARE_MSM_GPIO_PINS(5);
255 DECLARE_MSM_GPIO_PINS(6);
256 DECLARE_MSM_GPIO_PINS(7);
257 DECLARE_MSM_GPIO_PINS(8);
258 DECLARE_MSM_GPIO_PINS(9);
259 DECLARE_MSM_GPIO_PINS(10);
260 DECLARE_MSM_GPIO_PINS(11);
261 DECLARE_MSM_GPIO_PINS(12);
262 DECLARE_MSM_GPIO_PINS(13);
263 DECLARE_MSM_GPIO_PINS(14);
264 DECLARE_MSM_GPIO_PINS(15);
265 DECLARE_MSM_GPIO_PINS(16);
266 DECLARE_MSM_GPIO_PINS(17);
267 DECLARE_MSM_GPIO_PINS(18);
268 DECLARE_MSM_GPIO_PINS(19);
269 DECLARE_MSM_GPIO_PINS(20);
270 DECLARE_MSM_GPIO_PINS(21);
271 DECLARE_MSM_GPIO_PINS(22);
272 DECLARE_MSM_GPIO_PINS(23);
273 DECLARE_MSM_GPIO_PINS(24);
274 DECLARE_MSM_GPIO_PINS(25);
275 DECLARE_MSM_GPIO_PINS(26);
276 DECLARE_MSM_GPIO_PINS(27);
277 DECLARE_MSM_GPIO_PINS(28);
278 DECLARE_MSM_GPIO_PINS(29);
279 DECLARE_MSM_GPIO_PINS(30);
280 DECLARE_MSM_GPIO_PINS(31);
281 DECLARE_MSM_GPIO_PINS(32);
282 DECLARE_MSM_GPIO_PINS(33);
283 DECLARE_MSM_GPIO_PINS(34);
284 DECLARE_MSM_GPIO_PINS(35);
285 DECLARE_MSM_GPIO_PINS(36);
286 DECLARE_MSM_GPIO_PINS(37);
287 DECLARE_MSM_GPIO_PINS(38);
288 DECLARE_MSM_GPIO_PINS(39);
289 DECLARE_MSM_GPIO_PINS(40);
290 DECLARE_MSM_GPIO_PINS(41);
291 DECLARE_MSM_GPIO_PINS(42);
292 DECLARE_MSM_GPIO_PINS(43);
293 DECLARE_MSM_GPIO_PINS(44);
294 DECLARE_MSM_GPIO_PINS(45);
295 DECLARE_MSM_GPIO_PINS(46);
296 DECLARE_MSM_GPIO_PINS(47);
297 DECLARE_MSM_GPIO_PINS(48);
298 DECLARE_MSM_GPIO_PINS(49);
299 DECLARE_MSM_GPIO_PINS(50);
300 DECLARE_MSM_GPIO_PINS(51);
301 DECLARE_MSM_GPIO_PINS(52);
302 DECLARE_MSM_GPIO_PINS(53);
303 DECLARE_MSM_GPIO_PINS(54);
304 DECLARE_MSM_GPIO_PINS(55);
305 DECLARE_MSM_GPIO_PINS(56);
306 DECLARE_MSM_GPIO_PINS(57);
307 DECLARE_MSM_GPIO_PINS(58);
308 DECLARE_MSM_GPIO_PINS(59);
309 DECLARE_MSM_GPIO_PINS(60);
310 DECLARE_MSM_GPIO_PINS(61);
311 DECLARE_MSM_GPIO_PINS(62);
312 DECLARE_MSM_GPIO_PINS(63);
313 DECLARE_MSM_GPIO_PINS(64);
314 DECLARE_MSM_GPIO_PINS(65);
315 DECLARE_MSM_GPIO_PINS(66);
316 DECLARE_MSM_GPIO_PINS(67);
317 DECLARE_MSM_GPIO_PINS(68);
318 DECLARE_MSM_GPIO_PINS(69);
319 DECLARE_MSM_GPIO_PINS(70);
320 DECLARE_MSM_GPIO_PINS(71);
321 DECLARE_MSM_GPIO_PINS(72);
322 DECLARE_MSM_GPIO_PINS(73);
323 DECLARE_MSM_GPIO_PINS(74);
324 DECLARE_MSM_GPIO_PINS(75);
325 DECLARE_MSM_GPIO_PINS(76);
326 DECLARE_MSM_GPIO_PINS(77);
327 DECLARE_MSM_GPIO_PINS(78);
328 DECLARE_MSM_GPIO_PINS(79);
329 DECLARE_MSM_GPIO_PINS(80);
330 DECLARE_MSM_GPIO_PINS(81);
331 DECLARE_MSM_GPIO_PINS(82);
332 DECLARE_MSM_GPIO_PINS(83);
333 DECLARE_MSM_GPIO_PINS(84);
334 DECLARE_MSM_GPIO_PINS(85);
335 DECLARE_MSM_GPIO_PINS(86);
336 DECLARE_MSM_GPIO_PINS(87);
337 DECLARE_MSM_GPIO_PINS(88);
338 DECLARE_MSM_GPIO_PINS(89);
339 DECLARE_MSM_GPIO_PINS(90);
340 DECLARE_MSM_GPIO_PINS(91);
341 DECLARE_MSM_GPIO_PINS(92);
342 DECLARE_MSM_GPIO_PINS(93);
343 DECLARE_MSM_GPIO_PINS(94);
344 DECLARE_MSM_GPIO_PINS(95);
345 DECLARE_MSM_GPIO_PINS(96);
346 DECLARE_MSM_GPIO_PINS(97);
347 DECLARE_MSM_GPIO_PINS(98);
348 DECLARE_MSM_GPIO_PINS(99);
349 DECLARE_MSM_GPIO_PINS(100);
350 DECLARE_MSM_GPIO_PINS(101);
351 DECLARE_MSM_GPIO_PINS(102);
352 DECLARE_MSM_GPIO_PINS(103);
353 DECLARE_MSM_GPIO_PINS(104);
354 DECLARE_MSM_GPIO_PINS(105);
355 DECLARE_MSM_GPIO_PINS(106);
356 DECLARE_MSM_GPIO_PINS(107);
357 DECLARE_MSM_GPIO_PINS(108);
358 DECLARE_MSM_GPIO_PINS(109);
359 DECLARE_MSM_GPIO_PINS(110);
360 DECLARE_MSM_GPIO_PINS(111);
361 DECLARE_MSM_GPIO_PINS(112);
362 DECLARE_MSM_GPIO_PINS(113);
363 DECLARE_MSM_GPIO_PINS(114);
364 DECLARE_MSM_GPIO_PINS(115);
365 DECLARE_MSM_GPIO_PINS(116);
366 DECLARE_MSM_GPIO_PINS(117);
367 DECLARE_MSM_GPIO_PINS(118);
368 DECLARE_MSM_GPIO_PINS(119);
369 DECLARE_MSM_GPIO_PINS(120);
370 DECLARE_MSM_GPIO_PINS(121);
371 DECLARE_MSM_GPIO_PINS(122);
372
373 static const unsigned int ufs_reset_pins[] = { 123 };
374 static const unsigned int sdc1_rclk_pins[] = { 124 };
375 static const unsigned int sdc1_clk_pins[] = { 125 };
376 static const unsigned int sdc1_cmd_pins[] = { 126 };
377 static const unsigned int sdc1_data_pins[] = { 127 };
378 static const unsigned int sdc2_clk_pins[] = { 128 };
379 static const unsigned int sdc2_cmd_pins[] = { 129 };
380 static const unsigned int sdc2_data_pins[] = { 130 };
381
382 enum qcs615_functions {
383 msm_mux_gpio,
384 msm_mux_adsp_ext,
385 msm_mux_agera_pll,
386 msm_mux_aoss_cti,
387 msm_mux_atest_char,
388 msm_mux_atest_tsens,
389 msm_mux_atest_usb,
390 msm_mux_cam_mclk,
391 msm_mux_cci_async,
392 msm_mux_cci_i2c,
393 msm_mux_cci_timer,
394 msm_mux_copy_gp,
395 msm_mux_copy_phase,
396 msm_mux_cri_trng,
397 msm_mux_dbg_out_clk,
398 msm_mux_ddr_bist,
399 msm_mux_ddr_pxi,
400 msm_mux_dp_hot,
401 msm_mux_edp_hot,
402 msm_mux_edp_lcd,
403 msm_mux_emac_gcc,
404 msm_mux_emac_phy_intr,
405 msm_mux_forced_usb,
406 msm_mux_gcc_gp,
407 msm_mux_gp_pdm,
408 msm_mux_gps_tx,
409 msm_mux_hs0_mi2s,
410 msm_mux_hs1_mi2s,
411 msm_mux_jitter_bist,
412 msm_mux_ldo_en,
413 msm_mux_ldo_update,
414 msm_mux_m_voc,
415 msm_mux_mclk1,
416 msm_mux_mclk2,
417 msm_mux_mdp_vsync,
418 msm_mux_mdp_vsync0_out,
419 msm_mux_mdp_vsync1_out,
420 msm_mux_mdp_vsync2_out,
421 msm_mux_mdp_vsync3_out,
422 msm_mux_mdp_vsync4_out,
423 msm_mux_mdp_vsync5_out,
424 msm_mux_mi2s_1,
425 msm_mux_mss_lte,
426 msm_mux_nav_pps_in,
427 msm_mux_nav_pps_out,
428 msm_mux_pa_indicator_or,
429 msm_mux_pcie_clk_req,
430 msm_mux_pcie_ep_rst,
431 msm_mux_phase_flag,
432 msm_mux_pll_bist,
433 msm_mux_pll_bypassnl,
434 msm_mux_pll_reset_n,
435 msm_mux_prng_rosc,
436 msm_mux_qdss_cti,
437 msm_mux_qdss_gpio,
438 msm_mux_qlink_enable,
439 msm_mux_qlink_request,
440 msm_mux_qspi,
441 msm_mux_qup0,
442 msm_mux_qup1,
443 msm_mux_rgmii,
444 msm_mux_sd_write_protect,
445 msm_mux_sp_cmu,
446 msm_mux_ter_mi2s,
447 msm_mux_tgu_ch,
448 msm_mux_uim1,
449 msm_mux_uim2,
450 msm_mux_usb0_hs,
451 msm_mux_usb1_hs,
452 msm_mux_usb_phy_ps,
453 msm_mux_vfr_1,
454 msm_mux_vsense_trigger_mirnat,
455 msm_mux_wlan,
456 msm_mux_wsa_clk,
457 msm_mux_wsa_data,
458 msm_mux__,
459 };
460
461 static const char *const gpio_groups[] = {
462 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
463 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
464 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
465 "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
466 "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
467 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
468 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
469 "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
470 "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
471 "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59",
472 "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
473 "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71",
474 "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
475 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
476 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89",
477 "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
478 "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101",
479 "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
480 "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113",
481 "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119",
482 "gpio120", "gpio121", "gpio122",
483 };
484
485 static const char *const adsp_ext_groups[] = {
486 "gpio118",
487 };
488
489 static const char *const agera_pll_groups[] = {
490 "gpio28",
491 };
492
493 static const char *const aoss_cti_groups[] = {
494 "gpio76",
495 };
496
497 static const char *const atest_char_groups[] = {
498 "gpio84", "gpio85", "gpio86", "gpio87",
499 "gpio115", "gpio117", "gpio118", "gpio119",
500 "gpio120", "gpio121",
501 };
502
503 static const char *const atest_tsens_groups[] = {
504 "gpio7", "gpio29",
505 };
506
507 static const char *const atest_usb_groups[] = {
508 "gpio7", "gpio10", "gpio11", "gpio54",
509 "gpio55", "gpio67", "gpio68", "gpio76",
510 "gpio75", "gpio77",
511 };
512
513 static const char *const cam_mclk_groups[] = {
514 "gpio28", "gpio29", "gpio30", "gpio31",
515 };
516
517 static const char *const cci_async_groups[] = {
518 "gpio26", "gpio41", "gpio42",
519 };
520
521 static const char *const cci_i2c_groups[] = {
522 "gpio32", "gpio33", "gpio34", "gpio35",
523 };
524
525 static const char *const cci_timer_groups[] = {
526 "gpio37", "gpio38", "gpio39", "gpio41",
527 "gpio42",
528 };
529
530 static const char *const copy_gp_groups[] = {
531 "gpio86",
532 };
533
534 static const char *const copy_phase_groups[] = {
535 "gpio103",
536 };
537
538 static const char *const cri_trng_groups[] = {
539 "gpio60", "gpio61", "gpio62",
540 };
541
542 static const char *const dbg_out_clk_groups[] = {
543 "gpio11",
544 };
545
546 static const char *const ddr_bist_groups[] = {
547 "gpio7", "gpio8", "gpio9", "gpio10",
548 };
549
550 static const char *const ddr_pxi_groups[] = {
551 "gpio6", "gpio7", "gpio10", "gpio11",
552 "gpio12", "gpio13", "gpio54", "gpio55",
553 };
554
555 static const char *const dp_hot_groups[] = {
556 "gpio102", "gpio103", "gpio104",
557 };
558
559 static const char *const edp_hot_groups[] = {
560 "gpio113",
561 };
562
563 static const char *const edp_lcd_groups[] = {
564 "gpio119",
565 };
566
567 static const char *const emac_gcc_groups[] = {
568 "gpio101", "gpio102",
569 };
570
571 static const char *const emac_phy_intr_groups[] = {
572 "gpio89",
573 };
574
575 static const char *const forced_usb_groups[] = {
576 "gpio43",
577 };
578
579 static const char *const gcc_gp_groups[] = {
580 "gpio21", "gpio22", "gpio57", "gpio58",
581 "gpio59", "gpio78",
582 };
583
584 static const char *const gp_pdm_groups[] = {
585 "gpio8", "gpio54", "gpio63", "gpio66",
586 "gpio79", "gpio95",
587 };
588
589 static const char *const gps_tx_groups[] = {
590 "gpio53", "gpio54", "gpio56", "gpio57",
591 "gpio59", "gpio60",
592 };
593
594 static const char *const hs0_mi2s_groups[] = {
595 "gpio36", "gpio37", "gpio38", "gpio39",
596 };
597
598 static const char *const hs1_mi2s_groups[] = {
599 "gpio24", "gpio25", "gpio26", "gpio27",
600 };
601
602 static const char *const jitter_bist_groups[] = {
603 "gpio12", "gpio26",
604 };
605
606 static const char *const ldo_en_groups[] = {
607 "gpio97",
608 };
609
610 static const char *const ldo_update_groups[] = {
611 "gpio98",
612 };
613
614 static const char *const m_voc_groups[] = {
615 "gpio120",
616 };
617
618 static const char *const mclk1_groups[] = {
619 "gpio121",
620 };
621
622 static const char *const mclk2_groups[] = {
623 "gpio122",
624 };
625
626 static const char *const mdp_vsync_groups[] = {
627 "gpio81", "gpio82", "gpio83", "gpio90",
628 "gpio97", "gpio98",
629 };
630
631 static const char *const mdp_vsync0_out_groups[] = {
632 "gpio90",
633 };
634
635 static const char *const mdp_vsync1_out_groups[] = {
636 "gpio90",
637 };
638
639 static const char *const mdp_vsync2_out_groups[] = {
640 "gpio90",
641 };
642
643 static const char *const mdp_vsync3_out_groups[] = {
644 "gpio90",
645 };
646
647 static const char *const mdp_vsync4_out_groups[] = {
648 "gpio90",
649 };
650
651 static const char *const mdp_vsync5_out_groups[] = {
652 "gpio90",
653 };
654
655 static const char *const mi2s_1_groups[] = {
656 "gpio108", "gpio109", "gpio110", "gpio111",
657 };
658
659 static const char *const mss_lte_groups[] = {
660 "gpio106", "gpio107",
661 };
662
663 static const char *const nav_pps_in_groups[] = {
664 "gpio53", "gpio56", "gpio57", "gpio59",
665 "gpio60",
666 };
667
668 static const char *const nav_pps_out_groups[] = {
669 "gpio53", "gpio56", "gpio57", "gpio59",
670 "gpio60",
671 };
672
673 static const char *const pa_indicator_or_groups[] = {
674 "gpio53",
675 };
676
677 static const char *const pcie_clk_req_groups[] = {
678 "gpio90",
679 };
680
681 static const char *const pcie_ep_rst_groups[] = {
682 "gpio89",
683 };
684
685 static const char *const phase_flag_groups[] = {
686 "gpio10", "gpio18", "gpio19", "gpio20",
687 "gpio23", "gpio24", "gpio25", "gpio38",
688 "gpio40", "gpio41", "gpio42", "gpio43",
689 "gpio44", "gpio45", "gpio53", "gpio54",
690 "gpio55", "gpio67", "gpio68", "gpio75",
691 "gpio76", "gpio77", "gpio78", "gpio79",
692 "gpio80", "gpio82", "gpio84", "gpio92",
693 "gpio116", "gpio117", "gpio118", "gpio119",
694 };
695
696 static const char *const pll_bist_groups[] = {
697 "gpio27",
698 };
699
700 static const char *const pll_bypassnl_groups[] = {
701 "gpio13",
702 };
703
704 static const char *const pll_reset_n_groups[] = {
705 "gpio14",
706 };
707
708 static const char *const prng_rosc_groups[] = {
709 "gpio99", "gpio102",
710 };
711
712 static const char *const qdss_cti_groups[] = {
713 "gpio83", "gpio96", "gpio97", "gpio98",
714 "gpio103", "gpio104", "gpio112", "gpio113",
715 };
716
717 static const char *const qdss_gpio_groups[] = {
718 "gpio0", "gpio1", "gpio2", "gpio3",
719 "gpio6", "gpio7", "gpio8", "gpio9",
720 "gpio14", "gpio15", "gpio20", "gpio21",
721 "gpio28", "gpio29", "gpio30", "gpio31",
722 "gpio32", "gpio33", "gpio34", "gpio35",
723 "gpio44", "gpio45", "gpio46", "gpio47",
724 "gpio81", "gpio82", "gpio92", "gpio93",
725 "gpio94", "gpio95", "gpio108", "gpio109",
726 "gpio117", "gpio118", "gpio119", "gpio120",
727 };
728
729 static const char *const qlink_enable_groups[] = {
730 "gpio52",
731 };
732
733 static const char *const qlink_request_groups[] = {
734 "gpio51",
735 };
736
737 static const char *const qspi_groups[] = {
738 "gpio44", "gpio45", "gpio46", "gpio47",
739 "gpio48", "gpio49", "gpio50",
740 };
741
742 static const char *const qup0_groups[] = {
743 "gpio0", "gpio1", "gpio2", "gpio3",
744 "gpio4", "gpio5", "gpio16", "gpio17",
745 "gpio18", "gpio19",
746 };
747
748 static const char *const qup1_groups[] = {
749 "gpio6", "gpio7", "gpio8", "gpio9",
750 "gpio10", "gpio11", "gpio12", "gpio13",
751 "gpio14", "gpio15", "gpio20", "gpio21",
752 "gpio22", "gpio23",
753 };
754
755 static const char *const rgmii_groups[] = {
756 "gpio81", "gpio82", "gpio83", "gpio91",
757 "gpio92", "gpio93", "gpio94", "gpio95",
758 "gpio96", "gpio97", "gpio102", "gpio103",
759 "gpio112", "gpio113", "gpio114",
760 };
761
762 static const char *const sd_write_protect_groups[] = {
763 "gpio24",
764 };
765
766 static const char *const sp_cmu_groups[] = {
767 "gpio64",
768 };
769
770 static const char *const ter_mi2s_groups[] = {
771 "gpio115", "gpio116", "gpio117", "gpio118",
772 };
773
774 static const char *const tgu_ch_groups[] = {
775 "gpio89", "gpio90", "gpio91", "gpio92",
776 };
777
778 static const char *const uim1_groups[] = {
779 "gpio77", "gpio78", "gpio79", "gpio80",
780 };
781
782 static const char *const uim2_groups[] = {
783 "gpio73", "gpio74", "gpio75", "gpio76",
784 };
785
786 static const char *const usb0_hs_groups[] = {
787 "gpio88",
788 };
789
790 static const char *const usb1_hs_groups[] = {
791 "gpio89",
792 };
793
794 static const char *const usb_phy_ps_groups[] = {
795 "gpio104",
796 };
797
798 static const char *const vfr_1_groups[] = {
799 "gpio92",
800 };
801
802 static const char *const vsense_trigger_mirnat_groups[] = {
803 "gpio7",
804 };
805
806 static const char *const wlan_groups[] = {
807 "gpio16", "gpio17", "gpio47", "gpio48",
808 };
809
810 static const char *const wsa_clk_groups[] = {
811 "gpio111",
812 };
813
814 static const char *const wsa_data_groups[] = {
815 "gpio110",
816 };
817
818 static const struct pinfunction qcs615_functions[] = {
819 MSM_GPIO_PIN_FUNCTION(gpio),
820 MSM_PIN_FUNCTION(adsp_ext),
821 MSM_PIN_FUNCTION(agera_pll),
822 MSM_PIN_FUNCTION(aoss_cti),
823 MSM_PIN_FUNCTION(atest_char),
824 MSM_PIN_FUNCTION(atest_tsens),
825 MSM_PIN_FUNCTION(atest_usb),
826 MSM_PIN_FUNCTION(cam_mclk),
827 MSM_PIN_FUNCTION(cci_async),
828 MSM_PIN_FUNCTION(cci_i2c),
829 MSM_PIN_FUNCTION(cci_timer),
830 MSM_PIN_FUNCTION(copy_gp),
831 MSM_PIN_FUNCTION(copy_phase),
832 MSM_PIN_FUNCTION(cri_trng),
833 MSM_PIN_FUNCTION(dbg_out_clk),
834 MSM_PIN_FUNCTION(ddr_bist),
835 MSM_PIN_FUNCTION(ddr_pxi),
836 MSM_PIN_FUNCTION(dp_hot),
837 MSM_PIN_FUNCTION(edp_hot),
838 MSM_PIN_FUNCTION(edp_lcd),
839 MSM_PIN_FUNCTION(emac_gcc),
840 MSM_PIN_FUNCTION(emac_phy_intr),
841 MSM_PIN_FUNCTION(forced_usb),
842 MSM_PIN_FUNCTION(gcc_gp),
843 MSM_PIN_FUNCTION(gp_pdm),
844 MSM_PIN_FUNCTION(gps_tx),
845 MSM_PIN_FUNCTION(hs0_mi2s),
846 MSM_PIN_FUNCTION(hs1_mi2s),
847 MSM_PIN_FUNCTION(jitter_bist),
848 MSM_PIN_FUNCTION(ldo_en),
849 MSM_PIN_FUNCTION(ldo_update),
850 MSM_PIN_FUNCTION(m_voc),
851 MSM_PIN_FUNCTION(mclk1),
852 MSM_PIN_FUNCTION(mclk2),
853 MSM_PIN_FUNCTION(mdp_vsync),
854 MSM_PIN_FUNCTION(mdp_vsync0_out),
855 MSM_PIN_FUNCTION(mdp_vsync1_out),
856 MSM_PIN_FUNCTION(mdp_vsync2_out),
857 MSM_PIN_FUNCTION(mdp_vsync3_out),
858 MSM_PIN_FUNCTION(mdp_vsync4_out),
859 MSM_PIN_FUNCTION(mdp_vsync5_out),
860 MSM_PIN_FUNCTION(mi2s_1),
861 MSM_PIN_FUNCTION(mss_lte),
862 MSM_PIN_FUNCTION(nav_pps_in),
863 MSM_PIN_FUNCTION(nav_pps_out),
864 MSM_PIN_FUNCTION(pa_indicator_or),
865 MSM_PIN_FUNCTION(pcie_clk_req),
866 MSM_PIN_FUNCTION(pcie_ep_rst),
867 MSM_PIN_FUNCTION(phase_flag),
868 MSM_PIN_FUNCTION(pll_bist),
869 MSM_PIN_FUNCTION(pll_bypassnl),
870 MSM_PIN_FUNCTION(pll_reset_n),
871 MSM_PIN_FUNCTION(prng_rosc),
872 MSM_PIN_FUNCTION(qdss_cti),
873 MSM_PIN_FUNCTION(qdss_gpio),
874 MSM_PIN_FUNCTION(qlink_enable),
875 MSM_PIN_FUNCTION(qlink_request),
876 MSM_PIN_FUNCTION(qspi),
877 MSM_PIN_FUNCTION(qup0),
878 MSM_PIN_FUNCTION(qup1),
879 MSM_PIN_FUNCTION(rgmii),
880 MSM_PIN_FUNCTION(sd_write_protect),
881 MSM_PIN_FUNCTION(sp_cmu),
882 MSM_PIN_FUNCTION(ter_mi2s),
883 MSM_PIN_FUNCTION(tgu_ch),
884 MSM_PIN_FUNCTION(uim1),
885 MSM_PIN_FUNCTION(uim2),
886 MSM_PIN_FUNCTION(usb0_hs),
887 MSM_PIN_FUNCTION(usb1_hs),
888 MSM_PIN_FUNCTION(usb_phy_ps),
889 MSM_PIN_FUNCTION(vfr_1),
890 MSM_PIN_FUNCTION(vsense_trigger_mirnat),
891 MSM_PIN_FUNCTION(wlan),
892 MSM_PIN_FUNCTION(wsa_clk),
893 MSM_PIN_FUNCTION(wsa_data),
894 };
895
896 /* Every pin is maintained as a single group, and missing or non-existing pin
897 * would be maintained as dummy group to synchronize pin group index with
898 * pin descriptor registered with pinctrl core.
899 * Clients would not be able to request these dummy pin groups.
900 */
901 static const struct msm_pingroup qcs615_groups[] = {
902 [0] = PINGROUP(0, WEST, qup0, _, qdss_gpio, _, _, _, _, _, _),
903 [1] = PINGROUP(1, WEST, qup0, _, qdss_gpio, _, _, _, _, _, _),
904 [2] = PINGROUP(2, WEST, qup0, _, qdss_gpio, _, _, _, _, _, _),
905 [3] = PINGROUP(3, WEST, qup0, _, qdss_gpio, _, _, _, _, _, _),
906 [4] = PINGROUP(4, WEST, qup0, _, _, _, _, _, _, _, _),
907 [5] = PINGROUP(5, WEST, qup0, _, _, _, _, _, _, _, _),
908 [6] = PINGROUP(6, EAST, qup1, qdss_gpio, ddr_pxi, _, _, _, _, _, _),
909 [7] = PINGROUP(7, EAST, qup1, ddr_bist, qdss_gpio, atest_tsens,
910 vsense_trigger_mirnat, atest_usb, ddr_pxi, _, _),
911 [8] = PINGROUP(8, EAST, qup1, gp_pdm, ddr_bist, qdss_gpio, _, _, _, _, _),
912 [9] = PINGROUP(9, EAST, qup1, ddr_bist, qdss_gpio, _, _, _, _, _, _),
913 [10] = PINGROUP(10, EAST, qup1, ddr_bist, _, phase_flag, atest_usb, ddr_pxi, _, _, _),
914 [11] = PINGROUP(11, EAST, qup1, dbg_out_clk, atest_usb, ddr_pxi, _, _, _, _, _),
915 [12] = PINGROUP(12, EAST, qup1, jitter_bist, ddr_pxi, _, _, _, _, _, _),
916 [13] = PINGROUP(13, EAST, qup1, pll_bypassnl, _, ddr_pxi, _, _, _, _, _),
917 [14] = PINGROUP(14, EAST, qup1, pll_reset_n, _, qdss_gpio, _, _, _, _, _),
918 [15] = PINGROUP(15, EAST, qup1, qdss_gpio, _, _, _, _, _, _, _),
919 [16] = PINGROUP(16, WEST, qup0, _, wlan, _, _, _, _, _, _),
920 [17] = PINGROUP(17, WEST, qup0, _, wlan, _, _, _, _, _, _),
921 [18] = PINGROUP(18, WEST, qup0, _, phase_flag, _, _, _, _, _, _),
922 [19] = PINGROUP(19, WEST, qup0, _, phase_flag, _, _, _, _, _, _),
923 [20] = PINGROUP(20, SOUTH, qup1, _, phase_flag, qdss_gpio, _, _, _, _, _),
924 [21] = PINGROUP(21, SOUTH, qup1, gcc_gp, _, qdss_gpio, _, _, _, _, _),
925 [22] = PINGROUP(22, SOUTH, qup1, gcc_gp, _, _, _, _, _, _, _),
926 [23] = PINGROUP(23, SOUTH, qup1, _, phase_flag, _, _, _, _, _, _),
927 [24] = PINGROUP(24, EAST, hs1_mi2s, sd_write_protect, _, phase_flag, _, _, _, _, _),
928 [25] = PINGROUP(25, EAST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _),
929 [26] = PINGROUP(26, EAST, cci_async, hs1_mi2s, jitter_bist, _, _, _, _, _, _),
930 [27] = PINGROUP(27, EAST, hs1_mi2s, pll_bist, _, _, _, _, _, _, _),
931 [28] = PINGROUP(28, EAST, cam_mclk, agera_pll, qdss_gpio, _, _, _, _, _, _),
932 [29] = PINGROUP(29, EAST, cam_mclk, _, qdss_gpio, atest_tsens, _, _, _, _, _),
933 [30] = PINGROUP(30, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
934 [31] = PINGROUP(31, EAST, cam_mclk, _, qdss_gpio, _, _, _, _, _, _),
935 [32] = PINGROUP(32, EAST, cci_i2c, _, qdss_gpio, _, _, _, _, _, _),
936 [33] = PINGROUP(33, EAST, cci_i2c, _, qdss_gpio, _, _, _, _, _, _),
937 [34] = PINGROUP(34, EAST, cci_i2c, _, qdss_gpio, _, _, _, _, _, _),
938 [35] = PINGROUP(35, EAST, cci_i2c, _, qdss_gpio, _, _, _, _, _, _),
939 [36] = PINGROUP(36, EAST, hs0_mi2s, _, _, _, _, _, _, _, _),
940 [37] = PINGROUP(37, EAST, cci_timer, hs0_mi2s, _, _, _, _, _, _, _),
941 [38] = PINGROUP(38, EAST, cci_timer, hs0_mi2s, _, phase_flag, _, _, _, _, _),
942 [39] = PINGROUP(39, EAST, cci_timer, hs0_mi2s, _, _, _, _, _, _, _),
943 [40] = PINGROUP(40, EAST, _, phase_flag, _, _, _, _, _, _, _),
944 [41] = PINGROUP(41, EAST, cci_async, cci_timer, _, phase_flag, _, _, _, _, _),
945 [42] = PINGROUP(42, EAST, cci_async, cci_timer, _, phase_flag, _, _, _, _, _),
946 [43] = PINGROUP(43, SOUTH, _, phase_flag, forced_usb, _, _, _, _, _, _),
947 [44] = PINGROUP(44, EAST, qspi, _, phase_flag, qdss_gpio, _, _, _, _, _),
948 [45] = PINGROUP(45, EAST, qspi, _, phase_flag, qdss_gpio, _, _, _, _, _),
949 [46] = PINGROUP(46, EAST, qspi, _, qdss_gpio, _, _, _, _, _, _),
950 [47] = PINGROUP(47, EAST, qspi, _, qdss_gpio, wlan, _, _, _, _, _),
951 [48] = PINGROUP(48, EAST, qspi, _, wlan, _, _, _, _, _, _),
952 [49] = PINGROUP(49, EAST, qspi, _, _, _, _, _, _, _, _),
953 [50] = PINGROUP(50, EAST, qspi, _, _, _, _, _, _, _, _),
954 [51] = PINGROUP(51, SOUTH, qlink_request, _, _, _, _, _, _, _, _),
955 [52] = PINGROUP(52, SOUTH, qlink_enable, _, _, _, _, _, _, _, _),
956 [53] = PINGROUP(53, SOUTH, pa_indicator_or, nav_pps_in, nav_pps_out, gps_tx, _,
957 phase_flag, _, _, _),
958 [54] = PINGROUP(54, SOUTH, _, gps_tx, gp_pdm, _, phase_flag, atest_usb, ddr_pxi, _, _),
959 [55] = PINGROUP(55, SOUTH, _, _, phase_flag, atest_usb, ddr_pxi, _, _, _, _),
960 [56] = PINGROUP(56, SOUTH, _, nav_pps_in, nav_pps_out, gps_tx, _, _, _, _, _),
961 [57] = PINGROUP(57, SOUTH, _, nav_pps_in, gps_tx, nav_pps_out, gcc_gp, _, _, _, _),
962 [58] = PINGROUP(58, SOUTH, _, gcc_gp, _, _, _, _, _, _, _),
963 [59] = PINGROUP(59, SOUTH, _, nav_pps_in, nav_pps_out, gps_tx, gcc_gp, _, _, _, _),
964 [60] = PINGROUP(60, SOUTH, _, nav_pps_in, nav_pps_out, gps_tx, cri_trng, _, _, _, _),
965 [61] = PINGROUP(61, SOUTH, _, cri_trng, _, _, _, _, _, _, _),
966 [62] = PINGROUP(62, SOUTH, _, cri_trng, _, _, _, _, _, _, _),
967 [63] = PINGROUP(63, SOUTH, _, _, gp_pdm, _, _, _, _, _, _),
968 [64] = PINGROUP(64, SOUTH, _, sp_cmu, _, _, _, _, _, _, _),
969 [65] = PINGROUP(65, SOUTH, _, _, _, _, _, _, _, _, _),
970 [66] = PINGROUP(66, SOUTH, _, gp_pdm, _, _, _, _, _, _, _),
971 [67] = PINGROUP(67, SOUTH, _, _, _, phase_flag, atest_usb, _, _, _, _),
972 [68] = PINGROUP(68, SOUTH, _, _, _, phase_flag, atest_usb, _, _, _, _),
973 [69] = PINGROUP(69, SOUTH, _, _, _, _, _, _, _, _, _),
974 [70] = PINGROUP(70, SOUTH, _, _, _, _, _, _, _, _, _),
975 [71] = PINGROUP(71, SOUTH, _, _, _, _, _, _, _, _, _),
976 [72] = PINGROUP(72, SOUTH, _, _, _, _, _, _, _, _, _),
977 [73] = PINGROUP(73, SOUTH, uim2, _, _, _, _, _, _, _, _),
978 [74] = PINGROUP(74, SOUTH, uim2, _, _, _, _, _, _, _, _),
979 [75] = PINGROUP(75, SOUTH, uim2, _, phase_flag, atest_usb, _, _, _, _, _),
980 [76] = PINGROUP(76, SOUTH, uim2, _, phase_flag, atest_usb, aoss_cti, _, _, _, _),
981 [77] = PINGROUP(77, SOUTH, uim1, _, phase_flag, atest_usb, _, _, _, _, _),
982 [78] = PINGROUP(78, SOUTH, uim1, gcc_gp, _, phase_flag, _, _, _, _, _),
983 [79] = PINGROUP(79, SOUTH, uim1, gp_pdm, _, phase_flag, _, _, _, _, _),
984 [80] = PINGROUP(80, SOUTH, uim1, _, phase_flag, _, _, _, _, _, _),
985 [81] = PINGROUP(81, WEST, rgmii, mdp_vsync, _, qdss_gpio, _, _, _, _, _),
986 [82] = PINGROUP(82, WEST, rgmii, mdp_vsync, _, phase_flag, qdss_gpio, _, _, _, _),
987 [83] = PINGROUP(83, WEST, rgmii, mdp_vsync, _, qdss_cti, _, _, _, _, _),
988 [84] = PINGROUP(84, SOUTH, _, phase_flag, atest_char, _, _, _, _, _, _),
989 [85] = PINGROUP(85, SOUTH, _, atest_char, _, _, _, _, _, _, _),
990 [86] = PINGROUP(86, SOUTH, copy_gp, _, atest_char, _, _, _, _, _, _),
991 [87] = PINGROUP(87, SOUTH, _, atest_char, _, _, _, _, _, _, _),
992 [88] = PINGROUP(88, WEST, _, usb0_hs, _, _, _, _, _, _, _),
993 [89] = PINGROUP(89, WEST, emac_phy_intr, pcie_ep_rst, tgu_ch, usb1_hs, _, _, _, _, _),
994 [90] = PINGROUP(90, WEST, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out,
995 mdp_vsync2_out, mdp_vsync3_out, mdp_vsync4_out, mdp_vsync5_out,
996 pcie_clk_req, tgu_ch),
997 [91] = PINGROUP(91, WEST, rgmii, tgu_ch, _, _, _, _, _, _, _),
998 [92] = PINGROUP(92, WEST, rgmii, vfr_1, tgu_ch, _, phase_flag, qdss_gpio, _, _, _),
999 [93] = PINGROUP(93, WEST, rgmii, qdss_gpio, _, _, _, _, _, _, _),
1000 [94] = PINGROUP(94, WEST, rgmii, qdss_gpio, _, _, _, _, _, _, _),
1001 [95] = PINGROUP(95, WEST, rgmii, gp_pdm, qdss_gpio, _, _, _, _, _, _),
1002 [96] = PINGROUP(96, WEST, rgmii, qdss_cti, _, _, _, _, _, _, _),
1003 [97] = PINGROUP(97, WEST, rgmii, mdp_vsync, ldo_en, qdss_cti, _, _, _, _, _),
1004 [98] = PINGROUP(98, WEST, mdp_vsync, ldo_update, qdss_cti, _, _, _, _, _, _),
1005 [99] = PINGROUP(99, EAST, prng_rosc, _, _, _, _, _, _, _, _),
1006 [100] = PINGROUP(100, WEST, _, _, _, _, _, _, _, _, _),
1007 [101] = PINGROUP(101, WEST, emac_gcc, _, _, _, _, _, _, _, _),
1008 [102] = PINGROUP(102, WEST, rgmii, dp_hot, emac_gcc, prng_rosc, _, _, _, _, _),
1009 [103] = PINGROUP(103, WEST, rgmii, dp_hot, copy_phase, qdss_cti, _, _, _, _, _),
1010 [104] = PINGROUP(104, WEST, usb_phy_ps, _, qdss_cti, dp_hot, _, _, _, _, _),
1011 [105] = PINGROUP(105, SOUTH, _, _, _, _, _, _, _, _, _),
1012 [106] = PINGROUP(106, EAST, mss_lte, _, _, _, _, _, _, _, _),
1013 [107] = PINGROUP(107, EAST, mss_lte, _, _, _, _, _, _, _, _),
1014 [108] = PINGROUP(108, SOUTH, mi2s_1, _, qdss_gpio, _, _, _, _, _, _),
1015 [109] = PINGROUP(109, SOUTH, mi2s_1, _, qdss_gpio, _, _, _, _, _, _),
1016 [110] = PINGROUP(110, SOUTH, wsa_data, mi2s_1, _, _, _, _, _, _, _),
1017 [111] = PINGROUP(111, SOUTH, wsa_clk, mi2s_1, _, _, _, _, _, _, _),
1018 [112] = PINGROUP(112, WEST, rgmii, _, qdss_cti, _, _, _, _, _, _),
1019 [113] = PINGROUP(113, WEST, rgmii, edp_hot, _, qdss_cti, _, _, _, _, _),
1020 [114] = PINGROUP(114, WEST, rgmii, _, _, _, _, _, _, _, _),
1021 [115] = PINGROUP(115, SOUTH, ter_mi2s, atest_char, _, _, _, _, _, _, _),
1022 [116] = PINGROUP(116, SOUTH, ter_mi2s, _, phase_flag, _, _, _, _, _, _),
1023 [117] = PINGROUP(117, SOUTH, ter_mi2s, _, phase_flag, qdss_gpio, atest_char, _, _, _, _),
1024 [118] = PINGROUP(118, SOUTH, ter_mi2s, adsp_ext, _, phase_flag, qdss_gpio, atest_char,
1025 _, _, _),
1026 [119] = PINGROUP(119, SOUTH, edp_lcd, _, phase_flag, qdss_gpio, atest_char, _, _, _, _),
1027 [120] = PINGROUP(120, SOUTH, m_voc, qdss_gpio, atest_char, _, _, _, _, _, _),
1028 [121] = PINGROUP(121, SOUTH, mclk1, atest_char, _, _, _, _, _, _, _),
1029 [122] = PINGROUP(122, SOUTH, mclk2, _, _, _, _, _, _, _, _),
1030 [123] = UFS_RESET(ufs_reset, 0x9f000),
1031 [124] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x9a000, 15, 0),
1032 [125] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x9a000, 13, 6),
1033 [126] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x9a000, 11, 3),
1034 [127] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x9a000, 9, 0),
1035 [128] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x98000, 14, 6),
1036 [129] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x98000, 11, 3),
1037 [130] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x98000, 9, 0),
1038 };
1039
1040 static const struct msm_gpio_wakeirq_map qcs615_pdc_map[] = {
1041 { 1, 45 }, { 3, 31 }, { 7, 55 }, { 9, 110 }, { 11, 34 },
1042 { 13, 33 }, { 14, 35 }, { 17, 46 }, { 19, 48 }, { 21, 83 },
1043 { 22, 36 }, { 26, 38 }, { 35, 37 }, { 39, 125 }, { 41, 47 },
1044 { 47, 49 }, { 48, 51 }, { 50, 52 }, { 51, 123 }, { 55, 56 },
1045 { 56, 57 }, { 57, 58 }, { 60, 60 }, { 71, 54 }, { 80, 73 },
1046 { 81, 64 }, { 82, 50 }, { 83, 65 }, { 84, 92 }, { 85, 99 },
1047 { 86, 67 }, { 87, 84 }, { 88, 124 }, { 89, 122 }, { 90, 69 },
1048 { 92, 88 }, { 93, 75 }, { 94, 91 }, { 95, 72 }, { 96, 82 },
1049 { 97, 74 }, { 98, 95 }, { 99, 94 }, { 100, 100 }, { 101, 40 },
1050 { 102, 93 }, { 103, 77 }, { 104, 78 }, { 105, 96 }, { 107, 97 },
1051 { 108, 111 }, { 112, 112 }, { 113, 113 }, { 117, 85 }, { 118, 102 },
1052 { 119, 87 }, { 120, 114 }, { 121, 89 }, { 122, 90 },
1053 };
1054
1055 static const struct msm_pinctrl_soc_data qcs615_tlmm = {
1056 .pins = qcs615_pins,
1057 .npins = ARRAY_SIZE(qcs615_pins),
1058 .functions = qcs615_functions,
1059 .nfunctions = ARRAY_SIZE(qcs615_functions),
1060 .groups = qcs615_groups,
1061 .ngroups = ARRAY_SIZE(qcs615_groups),
1062 .ngpios = 124,
1063 .tiles = qcs615_tiles,
1064 .ntiles = ARRAY_SIZE(qcs615_tiles),
1065 .wakeirq_map = qcs615_pdc_map,
1066 .nwakeirq_map = ARRAY_SIZE(qcs615_pdc_map),
1067 .wakeirq_dual_edge_errata = true,
1068 };
1069
1070 static const struct of_device_id qcs615_tlmm_of_match[] = {
1071 {
1072 .compatible = "qcom,qcs615-tlmm",
1073 },
1074 {},
1075 };
1076
qcs615_tlmm_probe(struct platform_device * pdev)1077 static int qcs615_tlmm_probe(struct platform_device *pdev)
1078 {
1079 return msm_pinctrl_probe(pdev, &qcs615_tlmm);
1080 }
1081
1082 static struct platform_driver qcs615_tlmm_driver = {
1083 .driver = {
1084 .name = "qcs615-tlmm",
1085 .of_match_table = qcs615_tlmm_of_match,
1086 },
1087 .probe = qcs615_tlmm_probe,
1088 };
1089
qcs615_tlmm_init(void)1090 static int __init qcs615_tlmm_init(void)
1091 {
1092 return platform_driver_register(&qcs615_tlmm_driver);
1093 }
1094 arch_initcall(qcs615_tlmm_init);
1095
qcs615_tlmm_exit(void)1096 static void __exit qcs615_tlmm_exit(void)
1097 {
1098 platform_driver_unregister(&qcs615_tlmm_driver);
1099 }
1100 module_exit(qcs615_tlmm_exit);
1101
1102 MODULE_DESCRIPTION("QTI QCS615 TLMM driver");
1103 MODULE_LICENSE("GPL");
1104 MODULE_DEVICE_TABLE(of, qcs615_tlmm_of_match);
1105