1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2006 Intel Corporation. */ 3 4 /* 5 * e100.c: Intel(R) PRO/100 ethernet driver 6 * 7 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on 8 * original e100 driver, but better described as a munging of 9 * e100, e1000, eepro100, tg3, 8139cp, and other drivers. 10 * 11 * References: 12 * Intel 8255x 10/100 Mbps Ethernet Controller Family, 13 * Open Source Software Developers Manual, 14 * http://sourceforge.net/projects/e1000 15 * 16 * 17 * Theory of Operation 18 * 19 * I. General 20 * 21 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet 22 * controller family, which includes the 82557, 82558, 82559, 82550, 23 * 82551, and 82562 devices. 82558 and greater controllers 24 * integrate the Intel 82555 PHY. The controllers are used in 25 * server and client network interface cards, as well as in 26 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx 27 * configurations. 8255x supports a 32-bit linear addressing 28 * mode and operates at 33Mhz PCI clock rate. 29 * 30 * II. Driver Operation 31 * 32 * Memory-mapped mode is used exclusively to access the device's 33 * shared-memory structure, the Control/Status Registers (CSR). All 34 * setup, configuration, and control of the device, including queuing 35 * of Tx, Rx, and configuration commands is through the CSR. 36 * cmd_lock serializes accesses to the CSR command register. cb_lock 37 * protects the shared Command Block List (CBL). 38 * 39 * 8255x is highly MII-compliant and all access to the PHY go 40 * through the Management Data Interface (MDI). Consequently, the 41 * driver leverages the mii.c library shared with other MII-compliant 42 * devices. 43 * 44 * Big- and Little-Endian byte order as well as 32- and 64-bit 45 * archs are supported. Weak-ordered memory and non-cache-coherent 46 * archs are supported. 47 * 48 * III. Transmit 49 * 50 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked 51 * together in a fixed-size ring (CBL) thus forming the flexible mode 52 * memory structure. A TCB marked with the suspend-bit indicates 53 * the end of the ring. The last TCB processed suspends the 54 * controller, and the controller can be restarted by issue a CU 55 * resume command to continue from the suspend point, or a CU start 56 * command to start at a given position in the ring. 57 * 58 * Non-Tx commands (config, multicast setup, etc) are linked 59 * into the CBL ring along with Tx commands. The common structure 60 * used for both Tx and non-Tx commands is the Command Block (CB). 61 * 62 * cb_to_use is the next CB to use for queuing a command; cb_to_clean 63 * is the next CB to check for completion; cb_to_send is the first 64 * CB to start on in case of a previous failure to resume. CB clean 65 * up happens in interrupt context in response to a CU interrupt. 66 * cbs_avail keeps track of number of free CB resources available. 67 * 68 * Hardware padding of short packets to minimum packet size is 69 * enabled. 82557 pads with 7Eh, while the later controllers pad 70 * with 00h. 71 * 72 * IV. Receive 73 * 74 * The Receive Frame Area (RFA) comprises a ring of Receive Frame 75 * Descriptors (RFD) + data buffer, thus forming the simplified mode 76 * memory structure. Rx skbs are allocated to contain both the RFD 77 * and the data buffer, but the RFD is pulled off before the skb is 78 * indicated. The data buffer is aligned such that encapsulated 79 * protocol headers are u32-aligned. Since the RFD is part of the 80 * mapped shared memory, and completion status is contained within 81 * the RFD, the RFD must be dma_sync'ed to maintain a consistent 82 * view from software and hardware. 83 * 84 * In order to keep updates to the RFD link field from colliding with 85 * hardware writes to mark packets complete, we use the feature that 86 * hardware will not write to a size 0 descriptor and mark the previous 87 * packet as end-of-list (EL). After updating the link, we remove EL 88 * and only then restore the size such that hardware may use the 89 * previous-to-end RFD. 90 * 91 * Under typical operation, the receive unit (RU) is start once, 92 * and the controller happily fills RFDs as frames arrive. If 93 * replacement RFDs cannot be allocated, or the RU goes non-active, 94 * the RU must be restarted. Frame arrival generates an interrupt, 95 * and Rx indication and re-allocation happen in the same context, 96 * therefore no locking is required. A software-generated interrupt 97 * is generated from the watchdog to recover from a failed allocation 98 * scenario where all Rx resources have been indicated and none re- 99 * placed. 100 * 101 * V. Miscellaneous 102 * 103 * VLAN offloading of tagging, stripping and filtering is not 104 * supported, but driver will accommodate the extra 4-byte VLAN tag 105 * for processing by upper layers. Tx/Rx Checksum offloading is not 106 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is 107 * not supported (hardware limitation). 108 * 109 * MagicPacket(tm) WoL support is enabled/disabled via ethtool. 110 * 111 * Thanks to JC (jchapman@katalix.com) for helping with 112 * testing/troubleshooting the development driver. 113 * 114 * TODO: 115 * o several entry points race with dev->close 116 * o check for tx-no-resources/stop Q races with tx clean/wake Q 117 * 118 * FIXES: 119 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com> 120 * - Stratus87247: protect MDI control register manipulations 121 * 2009/06/01 - Andreas Mohr <andi at lisas dot de> 122 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs 123 */ 124 125 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 126 127 #include <linux/hardirq.h> 128 #include <linux/interrupt.h> 129 #include <linux/module.h> 130 #include <linux/moduleparam.h> 131 #include <linux/kernel.h> 132 #include <linux/types.h> 133 #include <linux/sched.h> 134 #include <linux/slab.h> 135 #include <linux/delay.h> 136 #include <linux/init.h> 137 #include <linux/pci.h> 138 #include <linux/dma-mapping.h> 139 #include <linux/dmapool.h> 140 #include <linux/netdevice.h> 141 #include <linux/etherdevice.h> 142 #include <linux/mii.h> 143 #include <linux/if_vlan.h> 144 #include <linux/skbuff.h> 145 #include <linux/ethtool.h> 146 #include <linux/string.h> 147 #include <linux/firmware.h> 148 #include <linux/rtnetlink.h> 149 #include <linux/unaligned.h> 150 151 152 #define DRV_NAME "e100" 153 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver" 154 #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation" 155 156 #define E100_WATCHDOG_PERIOD (2 * HZ) 157 #define E100_NAPI_WEIGHT 16 158 159 #define FIRMWARE_D101M "e100/d101m_ucode.bin" 160 #define FIRMWARE_D101S "e100/d101s_ucode.bin" 161 #define FIRMWARE_D102E "e100/d102e_ucode.bin" 162 163 MODULE_DESCRIPTION(DRV_DESCRIPTION); 164 MODULE_LICENSE("GPL v2"); 165 MODULE_FIRMWARE(FIRMWARE_D101M); 166 MODULE_FIRMWARE(FIRMWARE_D101S); 167 MODULE_FIRMWARE(FIRMWARE_D102E); 168 169 static int debug = 3; 170 static int eeprom_bad_csum_allow = 0; 171 static int use_io = 0; 172 module_param(debug, int, 0); 173 module_param(eeprom_bad_csum_allow, int, 0444); 174 module_param(use_io, int, 0444); 175 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 176 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums"); 177 MODULE_PARM_DESC(use_io, "Force use of i/o access mode"); 178 179 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\ 180 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \ 181 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich } 182 static const struct pci_device_id e100_id_table[] = { 183 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0), 184 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0), 185 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3), 186 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3), 187 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3), 188 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3), 189 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3), 190 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4), 191 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4), 192 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4), 193 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4), 194 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4), 195 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4), 196 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5), 197 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5), 198 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5), 199 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5), 200 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5), 201 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5), 202 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5), 203 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5), 204 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0), 205 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6), 206 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6), 207 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6), 208 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6), 209 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6), 210 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6), 211 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6), 212 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6), 213 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7), 214 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7), 215 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7), 216 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7), 217 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7), 218 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7), 219 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0), 220 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0), 221 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2), 222 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2), 223 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2), 224 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7), 225 { 0, } 226 }; 227 MODULE_DEVICE_TABLE(pci, e100_id_table); 228 229 enum mac { 230 mac_82557_D100_A = 0, 231 mac_82557_D100_B = 1, 232 mac_82557_D100_C = 2, 233 mac_82558_D101_A4 = 4, 234 mac_82558_D101_B0 = 5, 235 mac_82559_D101M = 8, 236 mac_82559_D101S = 9, 237 mac_82550_D102 = 12, 238 mac_82550_D102_C = 13, 239 mac_82551_E = 14, 240 mac_82551_F = 15, 241 mac_82551_10 = 16, 242 mac_unknown = 0xFF, 243 }; 244 245 enum phy { 246 phy_100a = 0x000003E0, 247 phy_100c = 0x035002A8, 248 phy_82555_tx = 0x015002A8, 249 phy_nsc_tx = 0x5C002000, 250 phy_82562_et = 0x033002A8, 251 phy_82562_em = 0x032002A8, 252 phy_82562_ek = 0x031002A8, 253 phy_82562_eh = 0x017002A8, 254 phy_82552_v = 0xd061004d, 255 phy_unknown = 0xFFFFFFFF, 256 }; 257 258 /* CSR (Control/Status Registers) */ 259 struct csr { 260 struct { 261 u8 status; 262 u8 stat_ack; 263 u8 cmd_lo; 264 u8 cmd_hi; 265 u32 gen_ptr; 266 } scb; 267 u32 port; 268 u16 flash_ctrl; 269 u8 eeprom_ctrl_lo; 270 u8 eeprom_ctrl_hi; 271 u32 mdi_ctrl; 272 u32 rx_dma_count; 273 }; 274 275 enum scb_status { 276 rus_no_res = 0x08, 277 rus_ready = 0x10, 278 rus_mask = 0x3C, 279 }; 280 281 enum ru_state { 282 RU_SUSPENDED = 0, 283 RU_RUNNING = 1, 284 RU_UNINITIALIZED = -1, 285 }; 286 287 enum scb_stat_ack { 288 stat_ack_not_ours = 0x00, 289 stat_ack_sw_gen = 0x04, 290 stat_ack_rnr = 0x10, 291 stat_ack_cu_idle = 0x20, 292 stat_ack_frame_rx = 0x40, 293 stat_ack_cu_cmd_done = 0x80, 294 stat_ack_not_present = 0xFF, 295 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), 296 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), 297 }; 298 299 enum scb_cmd_hi { 300 irq_mask_none = 0x00, 301 irq_mask_all = 0x01, 302 irq_sw_gen = 0x02, 303 }; 304 305 enum scb_cmd_lo { 306 cuc_nop = 0x00, 307 ruc_start = 0x01, 308 ruc_load_base = 0x06, 309 cuc_start = 0x10, 310 cuc_resume = 0x20, 311 cuc_dump_addr = 0x40, 312 cuc_dump_stats = 0x50, 313 cuc_load_base = 0x60, 314 cuc_dump_reset = 0x70, 315 }; 316 317 enum cuc_dump { 318 cuc_dump_complete = 0x0000A005, 319 cuc_dump_reset_complete = 0x0000A007, 320 }; 321 322 enum port { 323 software_reset = 0x0000, 324 selftest = 0x0001, 325 selective_reset = 0x0002, 326 }; 327 328 enum eeprom_ctrl_lo { 329 eesk = 0x01, 330 eecs = 0x02, 331 eedi = 0x04, 332 eedo = 0x08, 333 }; 334 335 enum mdi_ctrl { 336 mdi_write = 0x04000000, 337 mdi_read = 0x08000000, 338 mdi_ready = 0x10000000, 339 }; 340 341 enum eeprom_op { 342 op_write = 0x05, 343 op_read = 0x06, 344 op_ewds = 0x10, 345 op_ewen = 0x13, 346 }; 347 348 enum eeprom_offsets { 349 eeprom_cnfg_mdix = 0x03, 350 eeprom_phy_iface = 0x06, 351 eeprom_id = 0x0A, 352 eeprom_config_asf = 0x0D, 353 eeprom_smbus_addr = 0x90, 354 }; 355 356 enum eeprom_cnfg_mdix { 357 eeprom_mdix_enabled = 0x0080, 358 }; 359 360 enum eeprom_phy_iface { 361 NoSuchPhy = 0, 362 I82553AB, 363 I82553C, 364 I82503, 365 DP83840, 366 S80C240, 367 S80C24, 368 I82555, 369 DP83840A = 10, 370 }; 371 372 enum eeprom_id { 373 eeprom_id_wol = 0x0020, 374 }; 375 376 enum eeprom_config_asf { 377 eeprom_asf = 0x8000, 378 eeprom_gcl = 0x4000, 379 }; 380 381 enum cb_status { 382 cb_complete = 0x8000, 383 cb_ok = 0x2000, 384 }; 385 386 /* 387 * cb_command - Command Block flags 388 * @cb_tx_nc: 0: controller does CRC (normal), 1: CRC from skb memory 389 */ 390 enum cb_command { 391 cb_nop = 0x0000, 392 cb_iaaddr = 0x0001, 393 cb_config = 0x0002, 394 cb_multi = 0x0003, 395 cb_tx = 0x0004, 396 cb_ucode = 0x0005, 397 cb_dump = 0x0006, 398 cb_tx_sf = 0x0008, 399 cb_tx_nc = 0x0010, 400 cb_cid = 0x1f00, 401 cb_i = 0x2000, 402 cb_s = 0x4000, 403 cb_el = 0x8000, 404 }; 405 406 struct rfd { 407 __le16 status; 408 __le16 command; 409 __le32 link; 410 __le32 rbd; 411 __le16 actual_size; 412 __le16 size; 413 }; 414 415 struct rx { 416 struct rx *next, *prev; 417 struct sk_buff *skb; 418 dma_addr_t dma_addr; 419 }; 420 421 #if defined(__BIG_ENDIAN_BITFIELD) 422 #define X(a,b) b,a 423 #else 424 #define X(a,b) a,b 425 #endif 426 struct config { 427 /*0*/ u8 X(byte_count:6, pad0:2); 428 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1); 429 /*2*/ u8 adaptive_ifs; 430 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1), 431 term_write_cache_line:1), pad3:4); 432 /*4*/ u8 X(rx_dma_max_count:7, pad4:1); 433 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1); 434 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1), 435 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1), 436 rx_save_overruns : 1), rx_save_bad_frames : 1); 437 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2), 438 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1), 439 tx_dynamic_tbd:1); 440 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1); 441 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1), 442 link_status_wake:1), arp_wake:1), mcmatch_wake:1); 443 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2), 444 loopback:2); 445 /*11*/ u8 X(linear_priority:3, pad11:5); 446 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4); 447 /*13*/ u8 ip_addr_lo; 448 /*14*/ u8 ip_addr_hi; 449 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1), 450 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1), 451 pad15_2:1), crs_or_cdt:1); 452 /*16*/ u8 fc_delay_lo; 453 /*17*/ u8 fc_delay_hi; 454 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1), 455 rx_long_ok:1), fc_priority_threshold:3), pad18:1); 456 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1), 457 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1), 458 full_duplex_force:1), full_duplex_pin:1); 459 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1); 460 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4); 461 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6); 462 u8 pad_d102[9]; 463 }; 464 465 #define E100_MAX_MULTICAST_ADDRS 64 466 struct multi { 467 __le16 count; 468 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/]; 469 }; 470 471 /* Important: keep total struct u32-aligned */ 472 #define UCODE_SIZE 134 473 struct cb { 474 __le16 status; 475 __le16 command; 476 __le32 link; 477 union { 478 u8 iaaddr[ETH_ALEN]; 479 __le32 ucode[UCODE_SIZE]; 480 struct config config; 481 struct multi multi; 482 struct { 483 u32 tbd_array; 484 u16 tcb_byte_count; 485 u8 threshold; 486 u8 tbd_count; 487 struct { 488 __le32 buf_addr; 489 __le16 size; 490 u16 eol; 491 } tbd; 492 } tcb; 493 __le32 dump_buffer_addr; 494 } u; 495 struct cb *next, *prev; 496 dma_addr_t dma_addr; 497 struct sk_buff *skb; 498 }; 499 500 enum loopback { 501 lb_none = 0, lb_mac = 1, lb_phy = 3, 502 }; 503 504 struct stats { 505 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions, 506 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, 507 tx_multiple_collisions, tx_total_collisions; 508 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors, 509 rx_resource_errors, rx_overrun_errors, rx_cdt_errors, 510 rx_short_frame_errors; 511 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; 512 __le16 xmt_tco_frames, rcv_tco_frames; 513 __le32 complete; 514 }; 515 516 struct mem { 517 struct { 518 u32 signature; 519 u32 result; 520 } selftest; 521 struct stats stats; 522 u8 dump_buf[596]; 523 }; 524 525 struct param_range { 526 u32 min; 527 u32 max; 528 u32 count; 529 }; 530 531 struct params { 532 struct param_range rfds; 533 struct param_range cbs; 534 }; 535 536 struct nic { 537 /* Begin: frequently used values: keep adjacent for cache effect */ 538 u32 msg_enable ____cacheline_aligned; 539 struct net_device *netdev; 540 struct pci_dev *pdev; 541 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data); 542 543 struct rx *rxs ____cacheline_aligned; 544 struct rx *rx_to_use; 545 struct rx *rx_to_clean; 546 struct rfd blank_rfd; 547 enum ru_state ru_running; 548 549 spinlock_t cb_lock ____cacheline_aligned; 550 spinlock_t cmd_lock; 551 struct csr __iomem *csr; 552 enum scb_cmd_lo cuc_cmd; 553 unsigned int cbs_avail; 554 struct napi_struct napi; 555 struct cb *cbs; 556 struct cb *cb_to_use; 557 struct cb *cb_to_send; 558 struct cb *cb_to_clean; 559 __le16 tx_command; 560 /* End: frequently used values: keep adjacent for cache effect */ 561 562 enum { 563 ich = (1 << 0), 564 promiscuous = (1 << 1), 565 multicast_all = (1 << 2), 566 wol_magic = (1 << 3), 567 ich_10h_workaround = (1 << 4), 568 } flags ____cacheline_aligned; 569 570 enum mac mac; 571 enum phy phy; 572 struct params params; 573 struct timer_list watchdog; 574 struct mii_if_info mii; 575 struct work_struct tx_timeout_task; 576 enum loopback loopback; 577 578 struct mem *mem; 579 dma_addr_t dma_addr; 580 581 struct dma_pool *cbs_pool; 582 dma_addr_t cbs_dma_addr; 583 u8 adaptive_ifs; 584 u8 tx_threshold; 585 u32 tx_frames; 586 u32 tx_collisions; 587 u32 tx_deferred; 588 u32 tx_single_collisions; 589 u32 tx_multiple_collisions; 590 u32 tx_fc_pause; 591 u32 tx_tco_frames; 592 593 u32 rx_fc_pause; 594 u32 rx_fc_unsupported; 595 u32 rx_tco_frames; 596 u32 rx_short_frame_errors; 597 u32 rx_over_length_errors; 598 599 u16 eeprom_wc; 600 __le16 eeprom[256]; 601 spinlock_t mdio_lock; 602 const struct firmware *fw; 603 }; 604 e100_write_flush(struct nic * nic)605 static inline void e100_write_flush(struct nic *nic) 606 { 607 /* Flush previous PCI writes through intermediate bridges 608 * by doing a benign read */ 609 (void)ioread8(&nic->csr->scb.status); 610 } 611 e100_enable_irq(struct nic * nic)612 static void e100_enable_irq(struct nic *nic) 613 { 614 unsigned long flags; 615 616 spin_lock_irqsave(&nic->cmd_lock, flags); 617 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi); 618 e100_write_flush(nic); 619 spin_unlock_irqrestore(&nic->cmd_lock, flags); 620 } 621 e100_disable_irq(struct nic * nic)622 static void e100_disable_irq(struct nic *nic) 623 { 624 unsigned long flags; 625 626 spin_lock_irqsave(&nic->cmd_lock, flags); 627 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi); 628 e100_write_flush(nic); 629 spin_unlock_irqrestore(&nic->cmd_lock, flags); 630 } 631 e100_hw_reset(struct nic * nic)632 static void e100_hw_reset(struct nic *nic) 633 { 634 /* Put CU and RU into idle with a selective reset to get 635 * device off of PCI bus */ 636 iowrite32(selective_reset, &nic->csr->port); 637 e100_write_flush(nic); udelay(20); 638 639 /* Now fully reset device */ 640 iowrite32(software_reset, &nic->csr->port); 641 e100_write_flush(nic); udelay(20); 642 643 /* Mask off our interrupt line - it's unmasked after reset */ 644 e100_disable_irq(nic); 645 } 646 e100_self_test(struct nic * nic)647 static int e100_self_test(struct nic *nic) 648 { 649 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest); 650 651 /* Passing the self-test is a pretty good indication 652 * that the device can DMA to/from host memory */ 653 654 nic->mem->selftest.signature = 0; 655 nic->mem->selftest.result = 0xFFFFFFFF; 656 657 iowrite32(selftest | dma_addr, &nic->csr->port); 658 e100_write_flush(nic); 659 /* Wait 10 msec for self-test to complete */ 660 msleep(10); 661 662 /* Interrupts are enabled after self-test */ 663 e100_disable_irq(nic); 664 665 /* Check results of self-test */ 666 if (nic->mem->selftest.result != 0) { 667 netif_err(nic, hw, nic->netdev, 668 "Self-test failed: result=0x%08X\n", 669 nic->mem->selftest.result); 670 return -ETIMEDOUT; 671 } 672 if (nic->mem->selftest.signature == 0) { 673 netif_err(nic, hw, nic->netdev, "Self-test failed: timed out\n"); 674 return -ETIMEDOUT; 675 } 676 677 return 0; 678 } 679 e100_eeprom_write(struct nic * nic,u16 addr_len,u16 addr,__le16 data)680 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data) 681 { 682 u32 cmd_addr_data[3]; 683 u8 ctrl; 684 int i, j; 685 686 /* Three cmds: write/erase enable, write data, write/erase disable */ 687 cmd_addr_data[0] = op_ewen << (addr_len - 2); 688 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) | 689 le16_to_cpu(data); 690 cmd_addr_data[2] = op_ewds << (addr_len - 2); 691 692 /* Bit-bang cmds to write word to eeprom */ 693 for (j = 0; j < 3; j++) { 694 695 /* Chip select */ 696 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo); 697 e100_write_flush(nic); udelay(4); 698 699 for (i = 31; i >= 0; i--) { 700 ctrl = (cmd_addr_data[j] & (1 << i)) ? 701 eecs | eedi : eecs; 702 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo); 703 e100_write_flush(nic); udelay(4); 704 705 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo); 706 e100_write_flush(nic); udelay(4); 707 } 708 /* Wait 10 msec for cmd to complete */ 709 msleep(10); 710 711 /* Chip deselect */ 712 iowrite8(0, &nic->csr->eeprom_ctrl_lo); 713 e100_write_flush(nic); udelay(4); 714 } 715 }; 716 717 /* General technique stolen from the eepro100 driver - very clever */ e100_eeprom_read(struct nic * nic,u16 * addr_len,u16 addr)718 static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr) 719 { 720 u32 cmd_addr_data; 721 u16 data = 0; 722 u8 ctrl; 723 int i; 724 725 cmd_addr_data = ((op_read << *addr_len) | addr) << 16; 726 727 /* Chip select */ 728 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo); 729 e100_write_flush(nic); udelay(4); 730 731 /* Bit-bang to read word from eeprom */ 732 for (i = 31; i >= 0; i--) { 733 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs; 734 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo); 735 e100_write_flush(nic); udelay(4); 736 737 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo); 738 e100_write_flush(nic); udelay(4); 739 740 /* Eeprom drives a dummy zero to EEDO after receiving 741 * complete address. Use this to adjust addr_len. */ 742 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo); 743 if (!(ctrl & eedo) && i > 16) { 744 *addr_len -= (i - 16); 745 i = 17; 746 } 747 748 data = (data << 1) | (ctrl & eedo ? 1 : 0); 749 } 750 751 /* Chip deselect */ 752 iowrite8(0, &nic->csr->eeprom_ctrl_lo); 753 e100_write_flush(nic); udelay(4); 754 755 return cpu_to_le16(data); 756 }; 757 758 /* Load entire EEPROM image into driver cache and validate checksum */ e100_eeprom_load(struct nic * nic)759 static int e100_eeprom_load(struct nic *nic) 760 { 761 u16 addr, addr_len = 8, checksum = 0; 762 763 /* Try reading with an 8-bit addr len to discover actual addr len */ 764 e100_eeprom_read(nic, &addr_len, 0); 765 nic->eeprom_wc = 1 << addr_len; 766 767 for (addr = 0; addr < nic->eeprom_wc; addr++) { 768 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr); 769 if (addr < nic->eeprom_wc - 1) 770 checksum += le16_to_cpu(nic->eeprom[addr]); 771 } 772 773 /* The checksum, stored in the last word, is calculated such that 774 * the sum of words should be 0xBABA */ 775 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) { 776 netif_err(nic, probe, nic->netdev, "EEPROM corrupted\n"); 777 if (!eeprom_bad_csum_allow) 778 return -EAGAIN; 779 } 780 781 return 0; 782 } 783 784 /* Save (portion of) driver EEPROM cache to device and update checksum */ e100_eeprom_save(struct nic * nic,u16 start,u16 count)785 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count) 786 { 787 u16 addr, addr_len = 8, checksum = 0; 788 789 /* Try reading with an 8-bit addr len to discover actual addr len */ 790 e100_eeprom_read(nic, &addr_len, 0); 791 nic->eeprom_wc = 1 << addr_len; 792 793 if (start + count >= nic->eeprom_wc) 794 return -EINVAL; 795 796 for (addr = start; addr < start + count; addr++) 797 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]); 798 799 /* The checksum, stored in the last word, is calculated such that 800 * the sum of words should be 0xBABA */ 801 for (addr = 0; addr < nic->eeprom_wc - 1; addr++) 802 checksum += le16_to_cpu(nic->eeprom[addr]); 803 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum); 804 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1, 805 nic->eeprom[nic->eeprom_wc - 1]); 806 807 return 0; 808 } 809 810 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */ 811 #define E100_WAIT_SCB_FAST 20 /* delay like the old code */ e100_exec_cmd(struct nic * nic,u8 cmd,dma_addr_t dma_addr)812 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr) 813 { 814 unsigned long flags; 815 unsigned int i; 816 int err = 0; 817 818 spin_lock_irqsave(&nic->cmd_lock, flags); 819 820 /* Previous command is accepted when SCB clears */ 821 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) { 822 if (likely(!ioread8(&nic->csr->scb.cmd_lo))) 823 break; 824 cpu_relax(); 825 if (unlikely(i > E100_WAIT_SCB_FAST)) 826 udelay(5); 827 } 828 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) { 829 err = -EAGAIN; 830 goto err_unlock; 831 } 832 833 if (unlikely(cmd != cuc_resume)) 834 iowrite32(dma_addr, &nic->csr->scb.gen_ptr); 835 iowrite8(cmd, &nic->csr->scb.cmd_lo); 836 837 err_unlock: 838 spin_unlock_irqrestore(&nic->cmd_lock, flags); 839 840 return err; 841 } 842 e100_exec_cb(struct nic * nic,struct sk_buff * skb,int (* cb_prepare)(struct nic *,struct cb *,struct sk_buff *))843 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb, 844 int (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *)) 845 { 846 struct cb *cb; 847 unsigned long flags; 848 int err; 849 850 spin_lock_irqsave(&nic->cb_lock, flags); 851 852 if (unlikely(!nic->cbs_avail)) { 853 err = -ENOMEM; 854 goto err_unlock; 855 } 856 857 cb = nic->cb_to_use; 858 nic->cb_to_use = cb->next; 859 nic->cbs_avail--; 860 cb->skb = skb; 861 862 err = cb_prepare(nic, cb, skb); 863 if (err) 864 goto err_unlock; 865 866 if (unlikely(!nic->cbs_avail)) 867 err = -ENOSPC; 868 869 870 /* Order is important otherwise we'll be in a race with h/w: 871 * set S-bit in current first, then clear S-bit in previous. */ 872 cb->command |= cpu_to_le16(cb_s); 873 dma_wmb(); 874 cb->prev->command &= cpu_to_le16(~cb_s); 875 876 while (nic->cb_to_send != nic->cb_to_use) { 877 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd, 878 nic->cb_to_send->dma_addr))) { 879 /* Ok, here's where things get sticky. It's 880 * possible that we can't schedule the command 881 * because the controller is too busy, so 882 * let's just queue the command and try again 883 * when another command is scheduled. */ 884 if (err == -ENOSPC) { 885 //request a reset 886 schedule_work(&nic->tx_timeout_task); 887 } 888 break; 889 } else { 890 nic->cuc_cmd = cuc_resume; 891 nic->cb_to_send = nic->cb_to_send->next; 892 } 893 } 894 895 err_unlock: 896 spin_unlock_irqrestore(&nic->cb_lock, flags); 897 898 return err; 899 } 900 mdio_read(struct net_device * netdev,int addr,int reg)901 static int mdio_read(struct net_device *netdev, int addr, int reg) 902 { 903 struct nic *nic = netdev_priv(netdev); 904 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0); 905 } 906 mdio_write(struct net_device * netdev,int addr,int reg,int data)907 static void mdio_write(struct net_device *netdev, int addr, int reg, int data) 908 { 909 struct nic *nic = netdev_priv(netdev); 910 911 nic->mdio_ctrl(nic, addr, mdi_write, reg, data); 912 } 913 914 /* the standard mdio_ctrl() function for usual MII-compliant hardware */ mdio_ctrl_hw(struct nic * nic,u32 addr,u32 dir,u32 reg,u16 data)915 static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data) 916 { 917 u32 data_out = 0; 918 unsigned int i; 919 unsigned long flags; 920 921 922 /* 923 * Stratus87247: we shouldn't be writing the MDI control 924 * register until the Ready bit shows True. Also, since 925 * manipulation of the MDI control registers is a multi-step 926 * procedure it should be done under lock. 927 */ 928 spin_lock_irqsave(&nic->mdio_lock, flags); 929 for (i = 100; i; --i) { 930 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready) 931 break; 932 udelay(20); 933 } 934 if (unlikely(!i)) { 935 netdev_err(nic->netdev, "e100.mdio_ctrl won't go Ready\n"); 936 spin_unlock_irqrestore(&nic->mdio_lock, flags); 937 return 0; /* No way to indicate timeout error */ 938 } 939 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl); 940 941 for (i = 0; i < 100; i++) { 942 udelay(20); 943 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready) 944 break; 945 } 946 spin_unlock_irqrestore(&nic->mdio_lock, flags); 947 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, 948 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n", 949 dir == mdi_read ? "READ" : "WRITE", 950 addr, reg, data, data_out); 951 return (u16)data_out; 952 } 953 954 /* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */ mdio_ctrl_phy_82552_v(struct nic * nic,u32 addr,u32 dir,u32 reg,u16 data)955 static u16 mdio_ctrl_phy_82552_v(struct nic *nic, 956 u32 addr, 957 u32 dir, 958 u32 reg, 959 u16 data) 960 { 961 if ((reg == MII_BMCR) && (dir == mdi_write)) { 962 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) { 963 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id, 964 MII_ADVERTISE); 965 966 /* 967 * Workaround Si issue where sometimes the part will not 968 * autoneg to 100Mbps even when advertised. 969 */ 970 if (advert & ADVERTISE_100FULL) 971 data |= BMCR_SPEED100 | BMCR_FULLDPLX; 972 else if (advert & ADVERTISE_100HALF) 973 data |= BMCR_SPEED100; 974 } 975 } 976 return mdio_ctrl_hw(nic, addr, dir, reg, data); 977 } 978 979 /* Fully software-emulated mdio_ctrl() function for cards without 980 * MII-compliant PHYs. 981 * For now, this is mainly geared towards 80c24 support; in case of further 982 * requirements for other types (i82503, ...?) either extend this mechanism 983 * or split it, whichever is cleaner. 984 */ mdio_ctrl_phy_mii_emulated(struct nic * nic,u32 addr,u32 dir,u32 reg,u16 data)985 static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic, 986 u32 addr, 987 u32 dir, 988 u32 reg, 989 u16 data) 990 { 991 /* might need to allocate a netdev_priv'ed register array eventually 992 * to be able to record state changes, but for now 993 * some fully hardcoded register handling ought to be ok I guess. */ 994 995 if (dir == mdi_read) { 996 switch (reg) { 997 case MII_BMCR: 998 /* Auto-negotiation, right? */ 999 return BMCR_ANENABLE | 1000 BMCR_FULLDPLX; 1001 case MII_BMSR: 1002 return BMSR_LSTATUS /* for mii_link_ok() */ | 1003 BMSR_ANEGCAPABLE | 1004 BMSR_10FULL; 1005 case MII_ADVERTISE: 1006 /* 80c24 is a "combo card" PHY, right? */ 1007 return ADVERTISE_10HALF | 1008 ADVERTISE_10FULL; 1009 default: 1010 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, 1011 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n", 1012 dir == mdi_read ? "READ" : "WRITE", 1013 addr, reg, data); 1014 return 0xFFFF; 1015 } 1016 } else { 1017 switch (reg) { 1018 default: 1019 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, 1020 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n", 1021 dir == mdi_read ? "READ" : "WRITE", 1022 addr, reg, data); 1023 return 0xFFFF; 1024 } 1025 } 1026 } e100_phy_supports_mii(struct nic * nic)1027 static inline int e100_phy_supports_mii(struct nic *nic) 1028 { 1029 /* for now, just check it by comparing whether we 1030 are using MII software emulation. 1031 */ 1032 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated); 1033 } 1034 e100_get_defaults(struct nic * nic)1035 static void e100_get_defaults(struct nic *nic) 1036 { 1037 struct param_range rfds = { .min = 16, .max = 256, .count = 256 }; 1038 struct param_range cbs = { .min = 64, .max = 256, .count = 128 }; 1039 1040 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */ 1041 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision; 1042 if (nic->mac == mac_unknown) 1043 nic->mac = mac_82557_D100_A; 1044 1045 nic->params.rfds = rfds; 1046 nic->params.cbs = cbs; 1047 1048 /* Quadwords to DMA into FIFO before starting frame transmit */ 1049 nic->tx_threshold = 0xE0; 1050 1051 /* no interrupt for every tx completion, delay = 256us if not 557 */ 1052 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf | 1053 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i)); 1054 1055 /* Template for a freshly allocated RFD */ 1056 nic->blank_rfd.command = 0; 1057 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF); 1058 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN); 1059 1060 /* MII setup */ 1061 nic->mii.phy_id_mask = 0x1F; 1062 nic->mii.reg_num_mask = 0x1F; 1063 nic->mii.dev = nic->netdev; 1064 nic->mii.mdio_read = mdio_read; 1065 nic->mii.mdio_write = mdio_write; 1066 } 1067 e100_configure(struct nic * nic,struct cb * cb,struct sk_buff * skb)1068 static int e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb) 1069 { 1070 struct config *config = &cb->u.config; 1071 u8 *c = (u8 *)config; 1072 struct net_device *netdev = nic->netdev; 1073 1074 cb->command = cpu_to_le16(cb_config); 1075 1076 memset(config, 0, sizeof(struct config)); 1077 1078 config->byte_count = 0x16; /* bytes in this struct */ 1079 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */ 1080 config->direct_rx_dma = 0x1; /* reserved */ 1081 config->standard_tcb = 0x1; /* 1=standard, 0=extended */ 1082 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */ 1083 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */ 1084 config->tx_underrun_retry = 0x3; /* # of underrun retries */ 1085 if (e100_phy_supports_mii(nic)) 1086 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */ 1087 config->pad10 = 0x6; 1088 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */ 1089 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */ 1090 config->ifs = 0x6; /* x16 = inter frame spacing */ 1091 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */ 1092 config->pad15_1 = 0x1; 1093 config->pad15_2 = 0x1; 1094 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */ 1095 config->fc_delay_hi = 0x40; /* time delay for fc frame */ 1096 config->tx_padding = 0x1; /* 1=pad short frames */ 1097 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */ 1098 config->pad18 = 0x1; 1099 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */ 1100 config->pad20_1 = 0x1F; 1101 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */ 1102 config->pad21_1 = 0x5; 1103 1104 config->adaptive_ifs = nic->adaptive_ifs; 1105 config->loopback = nic->loopback; 1106 1107 if (nic->mii.force_media && nic->mii.full_duplex) 1108 config->full_duplex_force = 0x1; /* 1=force, 0=auto */ 1109 1110 if (nic->flags & promiscuous || nic->loopback) { 1111 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */ 1112 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */ 1113 config->promiscuous_mode = 0x1; /* 1=on, 0=off */ 1114 } 1115 1116 if (unlikely(netdev->features & NETIF_F_RXFCS)) 1117 config->rx_crc_transfer = 0x1; /* 1=save, 0=discard */ 1118 1119 if (nic->flags & multicast_all) 1120 config->multicast_all = 0x1; /* 1=accept, 0=no */ 1121 1122 /* disable WoL when up */ 1123 if (netif_running(nic->netdev) || !(nic->flags & wol_magic)) 1124 config->magic_packet_disable = 0x1; /* 1=off, 0=on */ 1125 1126 if (nic->mac >= mac_82558_D101_A4) { 1127 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */ 1128 config->mwi_enable = 0x1; /* 1=enable, 0=disable */ 1129 config->standard_tcb = 0x0; /* 1=standard, 0=extended */ 1130 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */ 1131 if (nic->mac >= mac_82559_D101M) { 1132 config->tno_intr = 0x1; /* TCO stats enable */ 1133 /* Enable TCO in extended config */ 1134 if (nic->mac >= mac_82551_10) { 1135 config->byte_count = 0x20; /* extended bytes */ 1136 config->rx_d102_mode = 0x1; /* GMRC for TCO */ 1137 } 1138 } else { 1139 config->standard_stat_counter = 0x0; 1140 } 1141 } 1142 1143 if (netdev->features & NETIF_F_RXALL) { 1144 config->rx_save_overruns = 0x1; /* 1=save, 0=discard */ 1145 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */ 1146 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */ 1147 } 1148 1149 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[00-07]=%8ph\n", 1150 c + 0); 1151 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[08-15]=%8ph\n", 1152 c + 8); 1153 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[16-23]=%8ph\n", 1154 c + 16); 1155 return 0; 1156 } 1157 1158 /************************************************************************* 1159 * CPUSaver parameters 1160 * 1161 * All CPUSaver parameters are 16-bit literals that are part of a 1162 * "move immediate value" instruction. By changing the value of 1163 * the literal in the instruction before the code is loaded, the 1164 * driver can change the algorithm. 1165 * 1166 * INTDELAY - This loads the dead-man timer with its initial value. 1167 * When this timer expires the interrupt is asserted, and the 1168 * timer is reset each time a new packet is received. (see 1169 * BUNDLEMAX below to set the limit on number of chained packets) 1170 * The current default is 0x600 or 1536. Experiments show that 1171 * the value should probably stay within the 0x200 - 0x1000. 1172 * 1173 * BUNDLEMAX - 1174 * This sets the maximum number of frames that will be bundled. In 1175 * some situations, such as the TCP windowing algorithm, it may be 1176 * better to limit the growth of the bundle size than let it go as 1177 * high as it can, because that could cause too much added latency. 1178 * The default is six, because this is the number of packets in the 1179 * default TCP window size. A value of 1 would make CPUSaver indicate 1180 * an interrupt for every frame received. If you do not want to put 1181 * a limit on the bundle size, set this value to xFFFF. 1182 * 1183 * BUNDLESMALL - 1184 * This contains a bit-mask describing the minimum size frame that 1185 * will be bundled. The default masks the lower 7 bits, which means 1186 * that any frame less than 128 bytes in length will not be bundled, 1187 * but will instead immediately generate an interrupt. This does 1188 * not affect the current bundle in any way. Any frame that is 128 1189 * bytes or large will be bundled normally. This feature is meant 1190 * to provide immediate indication of ACK frames in a TCP environment. 1191 * Customers were seeing poor performance when a machine with CPUSaver 1192 * enabled was sending but not receiving. The delay introduced when 1193 * the ACKs were received was enough to reduce total throughput, because 1194 * the sender would sit idle until the ACK was finally seen. 1195 * 1196 * The current default is 0xFF80, which masks out the lower 7 bits. 1197 * This means that any frame which is x7F (127) bytes or smaller 1198 * will cause an immediate interrupt. Because this value must be a 1199 * bit mask, there are only a few valid values that can be used. To 1200 * turn this feature off, the driver can write the value xFFFF to the 1201 * lower word of this instruction (in the same way that the other 1202 * parameters are used). Likewise, a value of 0xF800 (2047) would 1203 * cause an interrupt to be generated for every frame, because all 1204 * standard Ethernet frames are <= 2047 bytes in length. 1205 *************************************************************************/ 1206 1207 /* if you wish to disable the ucode functionality, while maintaining the 1208 * workarounds it provides, set the following defines to: 1209 * BUNDLESMALL 0 1210 * BUNDLEMAX 1 1211 * INTDELAY 1 1212 */ 1213 #define BUNDLESMALL 1 1214 #define BUNDLEMAX (u16)6 1215 #define INTDELAY (u16)1536 /* 0x600 */ 1216 1217 /* Initialize firmware */ e100_request_firmware(struct nic * nic)1218 static const struct firmware *e100_request_firmware(struct nic *nic) 1219 { 1220 const char *fw_name; 1221 const struct firmware *fw = nic->fw; 1222 u8 timer, bundle, min_size; 1223 int err = 0; 1224 bool required = false; 1225 1226 /* do not load u-code for ICH devices */ 1227 if (nic->flags & ich) 1228 return NULL; 1229 1230 /* Search for ucode match against h/w revision 1231 * 1232 * Based on comments in the source code for the FreeBSD fxp 1233 * driver, the FIRMWARE_D102E ucode includes both CPUSaver and 1234 * 1235 * "fixes for bugs in the B-step hardware (specifically, bugs 1236 * with Inline Receive)." 1237 * 1238 * So we must fail if it cannot be loaded. 1239 * 1240 * The other microcode files are only required for the optional 1241 * CPUSaver feature. Nice to have, but no reason to fail. 1242 */ 1243 if (nic->mac == mac_82559_D101M) { 1244 fw_name = FIRMWARE_D101M; 1245 } else if (nic->mac == mac_82559_D101S) { 1246 fw_name = FIRMWARE_D101S; 1247 } else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10) { 1248 fw_name = FIRMWARE_D102E; 1249 required = true; 1250 } else { /* No ucode on other devices */ 1251 return NULL; 1252 } 1253 1254 /* If the firmware has not previously been loaded, request a pointer 1255 * to it. If it was previously loaded, we are reinitializing the 1256 * adapter, possibly in a resume from hibernate, in which case 1257 * request_firmware() cannot be used. 1258 */ 1259 if (!fw) 1260 err = request_firmware(&fw, fw_name, &nic->pdev->dev); 1261 1262 if (err) { 1263 if (required) { 1264 netif_err(nic, probe, nic->netdev, 1265 "Failed to load firmware \"%s\": %d\n", 1266 fw_name, err); 1267 return ERR_PTR(err); 1268 } else { 1269 netif_info(nic, probe, nic->netdev, 1270 "CPUSaver disabled. Needs \"%s\": %d\n", 1271 fw_name, err); 1272 return NULL; 1273 } 1274 } 1275 1276 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes 1277 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */ 1278 if (fw->size != UCODE_SIZE * 4 + 3) { 1279 netif_err(nic, probe, nic->netdev, 1280 "Firmware \"%s\" has wrong size %zu\n", 1281 fw_name, fw->size); 1282 release_firmware(fw); 1283 return ERR_PTR(-EINVAL); 1284 } 1285 1286 /* Read timer, bundle and min_size from end of firmware blob */ 1287 timer = fw->data[UCODE_SIZE * 4]; 1288 bundle = fw->data[UCODE_SIZE * 4 + 1]; 1289 min_size = fw->data[UCODE_SIZE * 4 + 2]; 1290 1291 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE || 1292 min_size >= UCODE_SIZE) { 1293 netif_err(nic, probe, nic->netdev, 1294 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n", 1295 fw_name, timer, bundle, min_size); 1296 release_firmware(fw); 1297 return ERR_PTR(-EINVAL); 1298 } 1299 1300 /* OK, firmware is validated and ready to use. Save a pointer 1301 * to it in the nic */ 1302 nic->fw = fw; 1303 return fw; 1304 } 1305 e100_setup_ucode(struct nic * nic,struct cb * cb,struct sk_buff * skb)1306 static int e100_setup_ucode(struct nic *nic, struct cb *cb, 1307 struct sk_buff *skb) 1308 { 1309 const struct firmware *fw = (void *)skb; 1310 u8 timer, bundle, min_size; 1311 1312 /* It's not a real skb; we just abused the fact that e100_exec_cb 1313 will pass it through to here... */ 1314 cb->skb = NULL; 1315 1316 /* firmware is stored as little endian already */ 1317 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4); 1318 1319 /* Read timer, bundle and min_size from end of firmware blob */ 1320 timer = fw->data[UCODE_SIZE * 4]; 1321 bundle = fw->data[UCODE_SIZE * 4 + 1]; 1322 min_size = fw->data[UCODE_SIZE * 4 + 2]; 1323 1324 /* Insert user-tunable settings in cb->u.ucode */ 1325 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000); 1326 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY); 1327 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000); 1328 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX); 1329 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000); 1330 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80); 1331 1332 cb->command = cpu_to_le16(cb_ucode | cb_el); 1333 return 0; 1334 } 1335 e100_load_ucode_wait(struct nic * nic)1336 static inline int e100_load_ucode_wait(struct nic *nic) 1337 { 1338 const struct firmware *fw; 1339 int err = 0, counter = 50; 1340 struct cb *cb = nic->cb_to_clean; 1341 1342 fw = e100_request_firmware(nic); 1343 /* If it's NULL, then no ucode is required */ 1344 if (IS_ERR_OR_NULL(fw)) 1345 return PTR_ERR_OR_ZERO(fw); 1346 1347 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode))) 1348 netif_err(nic, probe, nic->netdev, 1349 "ucode cmd failed with error %d\n", err); 1350 1351 /* must restart cuc */ 1352 nic->cuc_cmd = cuc_start; 1353 1354 /* wait for completion */ 1355 e100_write_flush(nic); 1356 udelay(10); 1357 1358 /* wait for possibly (ouch) 500ms */ 1359 while (!(cb->status & cpu_to_le16(cb_complete))) { 1360 msleep(10); 1361 if (!--counter) break; 1362 } 1363 1364 /* ack any interrupts, something could have been set */ 1365 iowrite8(~0, &nic->csr->scb.stat_ack); 1366 1367 /* if the command failed, or is not OK, notify and return */ 1368 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) { 1369 netif_err(nic, probe, nic->netdev, "ucode load failed\n"); 1370 err = -EPERM; 1371 } 1372 1373 return err; 1374 } 1375 e100_setup_iaaddr(struct nic * nic,struct cb * cb,struct sk_buff * skb)1376 static int e100_setup_iaaddr(struct nic *nic, struct cb *cb, 1377 struct sk_buff *skb) 1378 { 1379 cb->command = cpu_to_le16(cb_iaaddr); 1380 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN); 1381 return 0; 1382 } 1383 e100_dump(struct nic * nic,struct cb * cb,struct sk_buff * skb)1384 static int e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb) 1385 { 1386 cb->command = cpu_to_le16(cb_dump); 1387 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr + 1388 offsetof(struct mem, dump_buf)); 1389 return 0; 1390 } 1391 e100_phy_check_without_mii(struct nic * nic)1392 static int e100_phy_check_without_mii(struct nic *nic) 1393 { 1394 u8 phy_type; 1395 int without_mii; 1396 1397 phy_type = (le16_to_cpu(nic->eeprom[eeprom_phy_iface]) >> 8) & 0x0f; 1398 1399 switch (phy_type) { 1400 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */ 1401 case I82503: /* Non-MII PHY; UNTESTED! */ 1402 case S80C24: /* Non-MII PHY; tested and working */ 1403 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24": 1404 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 1405 * doesn't have a programming interface of any sort. The 1406 * media is sensed automatically based on how the link partner 1407 * is configured. This is, in essence, manual configuration. 1408 */ 1409 netif_info(nic, probe, nic->netdev, 1410 "found MII-less i82503 or 80c24 or other PHY\n"); 1411 1412 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated; 1413 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */ 1414 1415 /* these might be needed for certain MII-less cards... 1416 * nic->flags |= ich; 1417 * nic->flags |= ich_10h_workaround; */ 1418 1419 without_mii = 1; 1420 break; 1421 default: 1422 without_mii = 0; 1423 break; 1424 } 1425 return without_mii; 1426 } 1427 1428 #define NCONFIG_AUTO_SWITCH 0x0080 1429 #define MII_NSC_CONG MII_RESV1 1430 #define NSC_CONG_ENABLE 0x0100 1431 #define NSC_CONG_TXREADY 0x0400 e100_phy_init(struct nic * nic)1432 static int e100_phy_init(struct nic *nic) 1433 { 1434 struct net_device *netdev = nic->netdev; 1435 u32 addr; 1436 u16 bmcr, stat, id_lo, id_hi, cong; 1437 1438 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */ 1439 for (addr = 0; addr < 32; addr++) { 1440 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr; 1441 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR); 1442 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR); 1443 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR); 1444 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0)))) 1445 break; 1446 } 1447 if (addr == 32) { 1448 /* uhoh, no PHY detected: check whether we seem to be some 1449 * weird, rare variant which is *known* to not have any MII. 1450 * But do this AFTER MII checking only, since this does 1451 * lookup of EEPROM values which may easily be unreliable. */ 1452 if (e100_phy_check_without_mii(nic)) 1453 return 0; /* simply return and hope for the best */ 1454 else { 1455 /* for unknown cases log a fatal error */ 1456 netif_err(nic, hw, nic->netdev, 1457 "Failed to locate any known PHY, aborting\n"); 1458 return -EAGAIN; 1459 } 1460 } else 1461 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, 1462 "phy_addr = %d\n", nic->mii.phy_id); 1463 1464 /* Get phy ID */ 1465 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1); 1466 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2); 1467 nic->phy = (u32)id_hi << 16 | (u32)id_lo; 1468 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, 1469 "phy ID = 0x%08X\n", nic->phy); 1470 1471 /* Select the phy and isolate the rest */ 1472 for (addr = 0; addr < 32; addr++) { 1473 if (addr != nic->mii.phy_id) { 1474 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE); 1475 } else if (nic->phy != phy_82552_v) { 1476 bmcr = mdio_read(netdev, addr, MII_BMCR); 1477 mdio_write(netdev, addr, MII_BMCR, 1478 bmcr & ~BMCR_ISOLATE); 1479 } 1480 } 1481 /* 1482 * Workaround for 82552: 1483 * Clear the ISOLATE bit on selected phy_id last (mirrored on all 1484 * other phy_id's) using bmcr value from addr discovery loop above. 1485 */ 1486 if (nic->phy == phy_82552_v) 1487 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, 1488 bmcr & ~BMCR_ISOLATE); 1489 1490 /* Handle National tx phys */ 1491 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF 1492 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) { 1493 /* Disable congestion control */ 1494 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG); 1495 cong |= NSC_CONG_TXREADY; 1496 cong &= ~NSC_CONG_ENABLE; 1497 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong); 1498 } 1499 1500 if (nic->phy == phy_82552_v) { 1501 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE); 1502 1503 /* assign special tweaked mdio_ctrl() function */ 1504 nic->mdio_ctrl = mdio_ctrl_phy_82552_v; 1505 1506 /* Workaround Si not advertising flow-control during autoneg */ 1507 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1508 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert); 1509 1510 /* Reset for the above changes to take effect */ 1511 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR); 1512 bmcr |= BMCR_RESET; 1513 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr); 1514 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) && 1515 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) && 1516 (le16_to_cpu(nic->eeprom[eeprom_cnfg_mdix]) & eeprom_mdix_enabled))) { 1517 /* enable/disable MDI/MDI-X auto-switching. */ 1518 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, 1519 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH); 1520 } 1521 1522 return 0; 1523 } 1524 e100_hw_init(struct nic * nic)1525 static int e100_hw_init(struct nic *nic) 1526 { 1527 int err = 0; 1528 1529 e100_hw_reset(nic); 1530 1531 netif_err(nic, hw, nic->netdev, "e100_hw_init\n"); 1532 if ((err = e100_self_test(nic))) 1533 return err; 1534 1535 if ((err = e100_phy_init(nic))) 1536 return err; 1537 if ((err = e100_exec_cmd(nic, cuc_load_base, 0))) 1538 return err; 1539 if ((err = e100_exec_cmd(nic, ruc_load_base, 0))) 1540 return err; 1541 if ((err = e100_load_ucode_wait(nic))) 1542 return err; 1543 if ((err = e100_exec_cb(nic, NULL, e100_configure))) 1544 return err; 1545 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr))) 1546 return err; 1547 if ((err = e100_exec_cmd(nic, cuc_dump_addr, 1548 nic->dma_addr + offsetof(struct mem, stats)))) 1549 return err; 1550 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0))) 1551 return err; 1552 1553 e100_disable_irq(nic); 1554 1555 return 0; 1556 } 1557 e100_multi(struct nic * nic,struct cb * cb,struct sk_buff * skb)1558 static int e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb) 1559 { 1560 struct net_device *netdev = nic->netdev; 1561 struct netdev_hw_addr *ha; 1562 u16 i, count = min(netdev_mc_count(netdev), E100_MAX_MULTICAST_ADDRS); 1563 1564 cb->command = cpu_to_le16(cb_multi); 1565 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN); 1566 i = 0; 1567 netdev_for_each_mc_addr(ha, netdev) { 1568 if (i == count) 1569 break; 1570 memcpy(&cb->u.multi.addr[i++ * ETH_ALEN], &ha->addr, 1571 ETH_ALEN); 1572 } 1573 return 0; 1574 } 1575 e100_set_multicast_list(struct net_device * netdev)1576 static void e100_set_multicast_list(struct net_device *netdev) 1577 { 1578 struct nic *nic = netdev_priv(netdev); 1579 1580 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, 1581 "mc_count=%d, flags=0x%04X\n", 1582 netdev_mc_count(netdev), netdev->flags); 1583 1584 if (netdev->flags & IFF_PROMISC) 1585 nic->flags |= promiscuous; 1586 else 1587 nic->flags &= ~promiscuous; 1588 1589 if (netdev->flags & IFF_ALLMULTI || 1590 netdev_mc_count(netdev) > E100_MAX_MULTICAST_ADDRS) 1591 nic->flags |= multicast_all; 1592 else 1593 nic->flags &= ~multicast_all; 1594 1595 e100_exec_cb(nic, NULL, e100_configure); 1596 e100_exec_cb(nic, NULL, e100_multi); 1597 } 1598 e100_update_stats(struct nic * nic)1599 static void e100_update_stats(struct nic *nic) 1600 { 1601 struct net_device *dev = nic->netdev; 1602 struct net_device_stats *ns = &dev->stats; 1603 struct stats *s = &nic->mem->stats; 1604 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause : 1605 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames : 1606 &s->complete; 1607 1608 /* Device's stats reporting may take several microseconds to 1609 * complete, so we're always waiting for results of the 1610 * previous command. */ 1611 1612 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) { 1613 *complete = 0; 1614 nic->tx_frames = le32_to_cpu(s->tx_good_frames); 1615 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions); 1616 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions); 1617 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions); 1618 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs); 1619 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns); 1620 ns->collisions += nic->tx_collisions; 1621 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) + 1622 le32_to_cpu(s->tx_lost_crs); 1623 nic->rx_short_frame_errors += 1624 le32_to_cpu(s->rx_short_frame_errors); 1625 ns->rx_length_errors = nic->rx_short_frame_errors + 1626 nic->rx_over_length_errors; 1627 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors); 1628 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors); 1629 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors); 1630 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors); 1631 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors); 1632 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) + 1633 le32_to_cpu(s->rx_alignment_errors) + 1634 le32_to_cpu(s->rx_short_frame_errors) + 1635 le32_to_cpu(s->rx_cdt_errors); 1636 nic->tx_deferred += le32_to_cpu(s->tx_deferred); 1637 nic->tx_single_collisions += 1638 le32_to_cpu(s->tx_single_collisions); 1639 nic->tx_multiple_collisions += 1640 le32_to_cpu(s->tx_multiple_collisions); 1641 if (nic->mac >= mac_82558_D101_A4) { 1642 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause); 1643 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause); 1644 nic->rx_fc_unsupported += 1645 le32_to_cpu(s->fc_rcv_unsupported); 1646 if (nic->mac >= mac_82559_D101M) { 1647 nic->tx_tco_frames += 1648 le16_to_cpu(s->xmt_tco_frames); 1649 nic->rx_tco_frames += 1650 le16_to_cpu(s->rcv_tco_frames); 1651 } 1652 } 1653 } 1654 1655 1656 if (e100_exec_cmd(nic, cuc_dump_reset, 0)) 1657 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev, 1658 "exec cuc_dump_reset failed\n"); 1659 } 1660 e100_adjust_adaptive_ifs(struct nic * nic,int speed,int duplex)1661 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex) 1662 { 1663 /* Adjust inter-frame-spacing (IFS) between two transmits if 1664 * we're getting collisions on a half-duplex connection. */ 1665 1666 if (duplex == DUPLEX_HALF) { 1667 u32 prev = nic->adaptive_ifs; 1668 u32 min_frames = (speed == SPEED_100) ? 1000 : 100; 1669 1670 if ((nic->tx_frames / 32 < nic->tx_collisions) && 1671 (nic->tx_frames > min_frames)) { 1672 if (nic->adaptive_ifs < 60) 1673 nic->adaptive_ifs += 5; 1674 } else if (nic->tx_frames < min_frames) { 1675 if (nic->adaptive_ifs >= 5) 1676 nic->adaptive_ifs -= 5; 1677 } 1678 if (nic->adaptive_ifs != prev) 1679 e100_exec_cb(nic, NULL, e100_configure); 1680 } 1681 } 1682 e100_watchdog(struct timer_list * t)1683 static void e100_watchdog(struct timer_list *t) 1684 { 1685 struct nic *nic = from_timer(nic, t, watchdog); 1686 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET }; 1687 u32 speed; 1688 1689 netif_printk(nic, timer, KERN_DEBUG, nic->netdev, 1690 "right now = %ld\n", jiffies); 1691 1692 /* mii library handles link maintenance tasks */ 1693 1694 mii_ethtool_gset(&nic->mii, &cmd); 1695 speed = ethtool_cmd_speed(&cmd); 1696 1697 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) { 1698 netdev_info(nic->netdev, "NIC Link is Up %u Mbps %s Duplex\n", 1699 speed == SPEED_100 ? 100 : 10, 1700 cmd.duplex == DUPLEX_FULL ? "Full" : "Half"); 1701 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) { 1702 netdev_info(nic->netdev, "NIC Link is Down\n"); 1703 } 1704 1705 mii_check_link(&nic->mii); 1706 1707 /* Software generated interrupt to recover from (rare) Rx 1708 * allocation failure. 1709 * Unfortunately have to use a spinlock to not re-enable interrupts 1710 * accidentally, due to hardware that shares a register between the 1711 * interrupt mask bit and the SW Interrupt generation bit */ 1712 spin_lock_irq(&nic->cmd_lock); 1713 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi); 1714 e100_write_flush(nic); 1715 spin_unlock_irq(&nic->cmd_lock); 1716 1717 e100_update_stats(nic); 1718 e100_adjust_adaptive_ifs(nic, speed, cmd.duplex); 1719 1720 if (nic->mac <= mac_82557_D100_C) 1721 /* Issue a multicast command to workaround a 557 lock up */ 1722 e100_set_multicast_list(nic->netdev); 1723 1724 if (nic->flags & ich && speed == SPEED_10 && cmd.duplex == DUPLEX_HALF) 1725 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */ 1726 nic->flags |= ich_10h_workaround; 1727 else 1728 nic->flags &= ~ich_10h_workaround; 1729 1730 mod_timer(&nic->watchdog, 1731 round_jiffies(jiffies + E100_WATCHDOG_PERIOD)); 1732 } 1733 e100_xmit_prepare(struct nic * nic,struct cb * cb,struct sk_buff * skb)1734 static int e100_xmit_prepare(struct nic *nic, struct cb *cb, 1735 struct sk_buff *skb) 1736 { 1737 dma_addr_t dma_addr; 1738 cb->command = nic->tx_command; 1739 1740 dma_addr = dma_map_single(&nic->pdev->dev, skb->data, skb->len, 1741 DMA_TO_DEVICE); 1742 /* If we can't map the skb, have the upper layer try later */ 1743 if (dma_mapping_error(&nic->pdev->dev, dma_addr)) 1744 return -ENOMEM; 1745 1746 /* 1747 * Use the last 4 bytes of the SKB payload packet as the CRC, used for 1748 * testing, ie sending frames with bad CRC. 1749 */ 1750 if (unlikely(skb->no_fcs)) 1751 cb->command |= cpu_to_le16(cb_tx_nc); 1752 else 1753 cb->command &= ~cpu_to_le16(cb_tx_nc); 1754 1755 /* interrupt every 16 packets regardless of delay */ 1756 if ((nic->cbs_avail & ~15) == nic->cbs_avail) 1757 cb->command |= cpu_to_le16(cb_i); 1758 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd); 1759 cb->u.tcb.tcb_byte_count = 0; 1760 cb->u.tcb.threshold = nic->tx_threshold; 1761 cb->u.tcb.tbd_count = 1; 1762 cb->u.tcb.tbd.buf_addr = cpu_to_le32(dma_addr); 1763 cb->u.tcb.tbd.size = cpu_to_le16(skb->len); 1764 skb_tx_timestamp(skb); 1765 return 0; 1766 } 1767 e100_xmit_frame(struct sk_buff * skb,struct net_device * netdev)1768 static netdev_tx_t e100_xmit_frame(struct sk_buff *skb, 1769 struct net_device *netdev) 1770 { 1771 struct nic *nic = netdev_priv(netdev); 1772 int err; 1773 1774 if (nic->flags & ich_10h_workaround) { 1775 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang. 1776 Issue a NOP command followed by a 1us delay before 1777 issuing the Tx command. */ 1778 if (e100_exec_cmd(nic, cuc_nop, 0)) 1779 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev, 1780 "exec cuc_nop failed\n"); 1781 udelay(1); 1782 } 1783 1784 err = e100_exec_cb(nic, skb, e100_xmit_prepare); 1785 1786 switch (err) { 1787 case -ENOSPC: 1788 /* We queued the skb, but now we're out of space. */ 1789 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev, 1790 "No space for CB\n"); 1791 netif_stop_queue(netdev); 1792 break; 1793 case -ENOMEM: 1794 /* This is a hard error - log it. */ 1795 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev, 1796 "Out of Tx resources, returning skb\n"); 1797 netif_stop_queue(netdev); 1798 return NETDEV_TX_BUSY; 1799 } 1800 1801 return NETDEV_TX_OK; 1802 } 1803 e100_tx_clean(struct nic * nic)1804 static int e100_tx_clean(struct nic *nic) 1805 { 1806 struct net_device *dev = nic->netdev; 1807 struct cb *cb; 1808 int tx_cleaned = 0; 1809 1810 spin_lock(&nic->cb_lock); 1811 1812 /* Clean CBs marked complete */ 1813 for (cb = nic->cb_to_clean; 1814 cb->status & cpu_to_le16(cb_complete); 1815 cb = nic->cb_to_clean = cb->next) { 1816 dma_rmb(); /* read skb after status */ 1817 netif_printk(nic, tx_done, KERN_DEBUG, nic->netdev, 1818 "cb[%d]->status = 0x%04X\n", 1819 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)), 1820 cb->status); 1821 1822 if (likely(cb->skb != NULL)) { 1823 dev->stats.tx_packets++; 1824 dev->stats.tx_bytes += cb->skb->len; 1825 1826 dma_unmap_single(&nic->pdev->dev, 1827 le32_to_cpu(cb->u.tcb.tbd.buf_addr), 1828 le16_to_cpu(cb->u.tcb.tbd.size), 1829 DMA_TO_DEVICE); 1830 dev_kfree_skb_any(cb->skb); 1831 cb->skb = NULL; 1832 tx_cleaned = 1; 1833 } 1834 cb->status = 0; 1835 nic->cbs_avail++; 1836 } 1837 1838 spin_unlock(&nic->cb_lock); 1839 1840 /* Recover from running out of Tx resources in xmit_frame */ 1841 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev))) 1842 netif_wake_queue(nic->netdev); 1843 1844 return tx_cleaned; 1845 } 1846 e100_clean_cbs(struct nic * nic)1847 static void e100_clean_cbs(struct nic *nic) 1848 { 1849 if (nic->cbs) { 1850 while (nic->cbs_avail != nic->params.cbs.count) { 1851 struct cb *cb = nic->cb_to_clean; 1852 if (cb->skb) { 1853 dma_unmap_single(&nic->pdev->dev, 1854 le32_to_cpu(cb->u.tcb.tbd.buf_addr), 1855 le16_to_cpu(cb->u.tcb.tbd.size), 1856 DMA_TO_DEVICE); 1857 dev_kfree_skb(cb->skb); 1858 } 1859 nic->cb_to_clean = nic->cb_to_clean->next; 1860 nic->cbs_avail++; 1861 } 1862 dma_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr); 1863 nic->cbs = NULL; 1864 nic->cbs_avail = 0; 1865 } 1866 nic->cuc_cmd = cuc_start; 1867 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = 1868 nic->cbs; 1869 } 1870 e100_alloc_cbs(struct nic * nic)1871 static int e100_alloc_cbs(struct nic *nic) 1872 { 1873 struct cb *cb; 1874 unsigned int i, count = nic->params.cbs.count; 1875 1876 nic->cuc_cmd = cuc_start; 1877 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL; 1878 nic->cbs_avail = 0; 1879 1880 nic->cbs = dma_pool_zalloc(nic->cbs_pool, GFP_KERNEL, 1881 &nic->cbs_dma_addr); 1882 if (!nic->cbs) 1883 return -ENOMEM; 1884 1885 for (cb = nic->cbs, i = 0; i < count; cb++, i++) { 1886 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs; 1887 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1; 1888 1889 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb); 1890 cb->link = cpu_to_le32(nic->cbs_dma_addr + 1891 ((i+1) % count) * sizeof(struct cb)); 1892 } 1893 1894 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs; 1895 nic->cbs_avail = count; 1896 1897 return 0; 1898 } 1899 e100_start_receiver(struct nic * nic,struct rx * rx)1900 static inline void e100_start_receiver(struct nic *nic, struct rx *rx) 1901 { 1902 if (!nic->rxs) return; 1903 if (RU_SUSPENDED != nic->ru_running) return; 1904 1905 /* handle init time starts */ 1906 if (!rx) rx = nic->rxs; 1907 1908 /* (Re)start RU if suspended or idle and RFA is non-NULL */ 1909 if (rx->skb) { 1910 e100_exec_cmd(nic, ruc_start, rx->dma_addr); 1911 nic->ru_running = RU_RUNNING; 1912 } 1913 } 1914 1915 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) e100_rx_alloc_skb(struct nic * nic,struct rx * rx)1916 static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx) 1917 { 1918 if (!(rx->skb = netdev_alloc_skb_ip_align(nic->netdev, RFD_BUF_LEN))) 1919 return -ENOMEM; 1920 1921 /* Init, and map the RFD. */ 1922 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd)); 1923 rx->dma_addr = dma_map_single(&nic->pdev->dev, rx->skb->data, 1924 RFD_BUF_LEN, DMA_BIDIRECTIONAL); 1925 1926 if (dma_mapping_error(&nic->pdev->dev, rx->dma_addr)) { 1927 dev_kfree_skb_any(rx->skb); 1928 rx->skb = NULL; 1929 rx->dma_addr = 0; 1930 return -ENOMEM; 1931 } 1932 1933 /* Link the RFD to end of RFA by linking previous RFD to 1934 * this one. We are safe to touch the previous RFD because 1935 * it is protected by the before last buffer's el bit being set */ 1936 if (rx->prev->skb) { 1937 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data; 1938 put_unaligned_le32(rx->dma_addr, &prev_rfd->link); 1939 dma_sync_single_for_device(&nic->pdev->dev, 1940 rx->prev->dma_addr, 1941 sizeof(struct rfd), 1942 DMA_BIDIRECTIONAL); 1943 } 1944 1945 return 0; 1946 } 1947 e100_rx_indicate(struct nic * nic,struct rx * rx,unsigned int * work_done,unsigned int work_to_do)1948 static int e100_rx_indicate(struct nic *nic, struct rx *rx, 1949 unsigned int *work_done, unsigned int work_to_do) 1950 { 1951 struct net_device *dev = nic->netdev; 1952 struct sk_buff *skb = rx->skb; 1953 struct rfd *rfd = (struct rfd *)skb->data; 1954 u16 rfd_status, actual_size; 1955 u16 fcs_pad = 0; 1956 1957 if (unlikely(work_done && *work_done >= work_to_do)) 1958 return -EAGAIN; 1959 1960 /* Need to sync before taking a peek at cb_complete bit */ 1961 dma_sync_single_for_cpu(&nic->pdev->dev, rx->dma_addr, 1962 sizeof(struct rfd), DMA_BIDIRECTIONAL); 1963 rfd_status = le16_to_cpu(rfd->status); 1964 1965 netif_printk(nic, rx_status, KERN_DEBUG, nic->netdev, 1966 "status=0x%04X\n", rfd_status); 1967 dma_rmb(); /* read size after status bit */ 1968 1969 /* If data isn't ready, nothing to indicate */ 1970 if (unlikely(!(rfd_status & cb_complete))) { 1971 /* If the next buffer has the el bit, but we think the receiver 1972 * is still running, check to see if it really stopped while 1973 * we had interrupts off. 1974 * This allows for a fast restart without re-enabling 1975 * interrupts */ 1976 if ((le16_to_cpu(rfd->command) & cb_el) && 1977 (RU_RUNNING == nic->ru_running)) 1978 1979 if (ioread8(&nic->csr->scb.status) & rus_no_res) 1980 nic->ru_running = RU_SUSPENDED; 1981 dma_sync_single_for_device(&nic->pdev->dev, rx->dma_addr, 1982 sizeof(struct rfd), 1983 DMA_FROM_DEVICE); 1984 return -ENODATA; 1985 } 1986 1987 /* Get actual data size */ 1988 if (unlikely(dev->features & NETIF_F_RXFCS)) 1989 fcs_pad = 4; 1990 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF; 1991 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd))) 1992 actual_size = RFD_BUF_LEN - sizeof(struct rfd); 1993 1994 /* Get data */ 1995 dma_unmap_single(&nic->pdev->dev, rx->dma_addr, RFD_BUF_LEN, 1996 DMA_BIDIRECTIONAL); 1997 1998 /* If this buffer has the el bit, but we think the receiver 1999 * is still running, check to see if it really stopped while 2000 * we had interrupts off. 2001 * This allows for a fast restart without re-enabling interrupts. 2002 * This can happen when the RU sees the size change but also sees 2003 * the el bit set. */ 2004 if ((le16_to_cpu(rfd->command) & cb_el) && 2005 (RU_RUNNING == nic->ru_running)) { 2006 2007 if (ioread8(&nic->csr->scb.status) & rus_no_res) 2008 nic->ru_running = RU_SUSPENDED; 2009 } 2010 2011 /* Pull off the RFD and put the actual data (minus eth hdr) */ 2012 skb_reserve(skb, sizeof(struct rfd)); 2013 skb_put(skb, actual_size); 2014 skb->protocol = eth_type_trans(skb, nic->netdev); 2015 2016 /* If we are receiving all frames, then don't bother 2017 * checking for errors. 2018 */ 2019 if (unlikely(dev->features & NETIF_F_RXALL)) { 2020 if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad) 2021 /* Received oversized frame, but keep it. */ 2022 nic->rx_over_length_errors++; 2023 goto process_skb; 2024 } 2025 2026 if (unlikely(!(rfd_status & cb_ok))) { 2027 /* Don't indicate if hardware indicates errors */ 2028 dev_kfree_skb_any(skb); 2029 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad) { 2030 /* Don't indicate oversized frames */ 2031 nic->rx_over_length_errors++; 2032 dev_kfree_skb_any(skb); 2033 } else { 2034 process_skb: 2035 dev->stats.rx_packets++; 2036 dev->stats.rx_bytes += (actual_size - fcs_pad); 2037 netif_receive_skb(skb); 2038 if (work_done) 2039 (*work_done)++; 2040 } 2041 2042 rx->skb = NULL; 2043 2044 return 0; 2045 } 2046 e100_rx_clean(struct nic * nic,unsigned int * work_done,unsigned int work_to_do)2047 static void e100_rx_clean(struct nic *nic, unsigned int *work_done, 2048 unsigned int work_to_do) 2049 { 2050 struct rx *rx; 2051 int restart_required = 0, err = 0; 2052 struct rx *old_before_last_rx, *new_before_last_rx; 2053 struct rfd *old_before_last_rfd, *new_before_last_rfd; 2054 2055 /* Indicate newly arrived packets */ 2056 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) { 2057 err = e100_rx_indicate(nic, rx, work_done, work_to_do); 2058 /* Hit quota or no more to clean */ 2059 if (-EAGAIN == err || -ENODATA == err) 2060 break; 2061 } 2062 2063 2064 /* On EAGAIN, hit quota so have more work to do, restart once 2065 * cleanup is complete. 2066 * Else, are we already rnr? then pay attention!!! this ensures that 2067 * the state machine progression never allows a start with a 2068 * partially cleaned list, avoiding a race between hardware 2069 * and rx_to_clean when in NAPI mode */ 2070 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running) 2071 restart_required = 1; 2072 2073 old_before_last_rx = nic->rx_to_use->prev->prev; 2074 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data; 2075 2076 /* Alloc new skbs to refill list */ 2077 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) { 2078 if (unlikely(e100_rx_alloc_skb(nic, rx))) 2079 break; /* Better luck next time (see watchdog) */ 2080 } 2081 2082 new_before_last_rx = nic->rx_to_use->prev->prev; 2083 if (new_before_last_rx != old_before_last_rx) { 2084 /* Set the el-bit on the buffer that is before the last buffer. 2085 * This lets us update the next pointer on the last buffer 2086 * without worrying about hardware touching it. 2087 * We set the size to 0 to prevent hardware from touching this 2088 * buffer. 2089 * When the hardware hits the before last buffer with el-bit 2090 * and size of 0, it will RNR interrupt, the RUS will go into 2091 * the No Resources state. It will not complete nor write to 2092 * this buffer. */ 2093 new_before_last_rfd = 2094 (struct rfd *)new_before_last_rx->skb->data; 2095 new_before_last_rfd->size = 0; 2096 new_before_last_rfd->command |= cpu_to_le16(cb_el); 2097 dma_sync_single_for_device(&nic->pdev->dev, 2098 new_before_last_rx->dma_addr, 2099 sizeof(struct rfd), 2100 DMA_BIDIRECTIONAL); 2101 2102 /* Now that we have a new stopping point, we can clear the old 2103 * stopping point. We must sync twice to get the proper 2104 * ordering on the hardware side of things. */ 2105 old_before_last_rfd->command &= ~cpu_to_le16(cb_el); 2106 dma_sync_single_for_device(&nic->pdev->dev, 2107 old_before_last_rx->dma_addr, 2108 sizeof(struct rfd), 2109 DMA_BIDIRECTIONAL); 2110 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN 2111 + ETH_FCS_LEN); 2112 dma_sync_single_for_device(&nic->pdev->dev, 2113 old_before_last_rx->dma_addr, 2114 sizeof(struct rfd), 2115 DMA_BIDIRECTIONAL); 2116 } 2117 2118 if (restart_required) { 2119 // ack the rnr? 2120 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack); 2121 e100_start_receiver(nic, nic->rx_to_clean); 2122 if (work_done) 2123 (*work_done)++; 2124 } 2125 } 2126 e100_rx_clean_list(struct nic * nic)2127 static void e100_rx_clean_list(struct nic *nic) 2128 { 2129 struct rx *rx; 2130 unsigned int i, count = nic->params.rfds.count; 2131 2132 nic->ru_running = RU_UNINITIALIZED; 2133 2134 if (nic->rxs) { 2135 for (rx = nic->rxs, i = 0; i < count; rx++, i++) { 2136 if (rx->skb) { 2137 dma_unmap_single(&nic->pdev->dev, 2138 rx->dma_addr, RFD_BUF_LEN, 2139 DMA_BIDIRECTIONAL); 2140 dev_kfree_skb(rx->skb); 2141 } 2142 } 2143 kfree(nic->rxs); 2144 nic->rxs = NULL; 2145 } 2146 2147 nic->rx_to_use = nic->rx_to_clean = NULL; 2148 } 2149 e100_rx_alloc_list(struct nic * nic)2150 static int e100_rx_alloc_list(struct nic *nic) 2151 { 2152 struct rx *rx; 2153 unsigned int i, count = nic->params.rfds.count; 2154 struct rfd *before_last; 2155 2156 nic->rx_to_use = nic->rx_to_clean = NULL; 2157 nic->ru_running = RU_UNINITIALIZED; 2158 2159 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_KERNEL))) 2160 return -ENOMEM; 2161 2162 for (rx = nic->rxs, i = 0; i < count; rx++, i++) { 2163 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs; 2164 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1; 2165 if (e100_rx_alloc_skb(nic, rx)) { 2166 e100_rx_clean_list(nic); 2167 return -ENOMEM; 2168 } 2169 } 2170 /* Set the el-bit on the buffer that is before the last buffer. 2171 * This lets us update the next pointer on the last buffer without 2172 * worrying about hardware touching it. 2173 * We set the size to 0 to prevent hardware from touching this buffer. 2174 * When the hardware hits the before last buffer with el-bit and size 2175 * of 0, it will RNR interrupt, the RU will go into the No Resources 2176 * state. It will not complete nor write to this buffer. */ 2177 rx = nic->rxs->prev->prev; 2178 before_last = (struct rfd *)rx->skb->data; 2179 before_last->command |= cpu_to_le16(cb_el); 2180 before_last->size = 0; 2181 dma_sync_single_for_device(&nic->pdev->dev, rx->dma_addr, 2182 sizeof(struct rfd), DMA_BIDIRECTIONAL); 2183 2184 nic->rx_to_use = nic->rx_to_clean = nic->rxs; 2185 nic->ru_running = RU_SUSPENDED; 2186 2187 return 0; 2188 } 2189 e100_intr(int irq,void * dev_id)2190 static irqreturn_t e100_intr(int irq, void *dev_id) 2191 { 2192 struct net_device *netdev = dev_id; 2193 struct nic *nic = netdev_priv(netdev); 2194 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack); 2195 2196 netif_printk(nic, intr, KERN_DEBUG, nic->netdev, 2197 "stat_ack = 0x%02X\n", stat_ack); 2198 2199 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */ 2200 stat_ack == stat_ack_not_present) /* Hardware is ejected */ 2201 return IRQ_NONE; 2202 2203 /* Ack interrupt(s) */ 2204 iowrite8(stat_ack, &nic->csr->scb.stat_ack); 2205 2206 /* We hit Receive No Resource (RNR); restart RU after cleaning */ 2207 if (stat_ack & stat_ack_rnr) 2208 nic->ru_running = RU_SUSPENDED; 2209 2210 if (likely(napi_schedule_prep(&nic->napi))) { 2211 e100_disable_irq(nic); 2212 __napi_schedule(&nic->napi); 2213 } 2214 2215 return IRQ_HANDLED; 2216 } 2217 e100_poll(struct napi_struct * napi,int budget)2218 static int e100_poll(struct napi_struct *napi, int budget) 2219 { 2220 struct nic *nic = container_of(napi, struct nic, napi); 2221 unsigned int work_done = 0; 2222 2223 e100_rx_clean(nic, &work_done, budget); 2224 e100_tx_clean(nic); 2225 2226 /* If budget fully consumed, continue polling */ 2227 if (work_done == budget) 2228 return budget; 2229 2230 /* only re-enable interrupt if stack agrees polling is really done */ 2231 if (likely(napi_complete_done(napi, work_done))) 2232 e100_enable_irq(nic); 2233 2234 return work_done; 2235 } 2236 2237 #ifdef CONFIG_NET_POLL_CONTROLLER e100_netpoll(struct net_device * netdev)2238 static void e100_netpoll(struct net_device *netdev) 2239 { 2240 struct nic *nic = netdev_priv(netdev); 2241 2242 e100_disable_irq(nic); 2243 e100_intr(nic->pdev->irq, netdev); 2244 e100_tx_clean(nic); 2245 e100_enable_irq(nic); 2246 } 2247 #endif 2248 e100_set_mac_address(struct net_device * netdev,void * p)2249 static int e100_set_mac_address(struct net_device *netdev, void *p) 2250 { 2251 struct nic *nic = netdev_priv(netdev); 2252 struct sockaddr *addr = p; 2253 2254 if (!is_valid_ether_addr(addr->sa_data)) 2255 return -EADDRNOTAVAIL; 2256 2257 eth_hw_addr_set(netdev, addr->sa_data); 2258 e100_exec_cb(nic, NULL, e100_setup_iaaddr); 2259 2260 return 0; 2261 } 2262 e100_asf(struct nic * nic)2263 static int e100_asf(struct nic *nic) 2264 { 2265 /* ASF can be enabled from eeprom */ 2266 return (nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) && 2267 (le16_to_cpu(nic->eeprom[eeprom_config_asf]) & eeprom_asf) && 2268 !(le16_to_cpu(nic->eeprom[eeprom_config_asf]) & eeprom_gcl) && 2269 ((le16_to_cpu(nic->eeprom[eeprom_smbus_addr]) & 0xFF) != 0xFE); 2270 } 2271 e100_up(struct nic * nic)2272 static int e100_up(struct nic *nic) 2273 { 2274 int err; 2275 2276 if ((err = e100_rx_alloc_list(nic))) 2277 return err; 2278 if ((err = e100_alloc_cbs(nic))) 2279 goto err_rx_clean_list; 2280 if ((err = e100_hw_init(nic))) 2281 goto err_clean_cbs; 2282 e100_set_multicast_list(nic->netdev); 2283 e100_start_receiver(nic, NULL); 2284 mod_timer(&nic->watchdog, jiffies); 2285 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED, 2286 nic->netdev->name, nic->netdev))) 2287 goto err_no_irq; 2288 netif_wake_queue(nic->netdev); 2289 napi_enable(&nic->napi); 2290 /* enable ints _after_ enabling poll, preventing a race between 2291 * disable ints+schedule */ 2292 e100_enable_irq(nic); 2293 return 0; 2294 2295 err_no_irq: 2296 del_timer_sync(&nic->watchdog); 2297 err_clean_cbs: 2298 e100_clean_cbs(nic); 2299 err_rx_clean_list: 2300 e100_rx_clean_list(nic); 2301 return err; 2302 } 2303 e100_down(struct nic * nic)2304 static void e100_down(struct nic *nic) 2305 { 2306 /* wait here for poll to complete */ 2307 napi_disable(&nic->napi); 2308 netif_stop_queue(nic->netdev); 2309 e100_hw_reset(nic); 2310 free_irq(nic->pdev->irq, nic->netdev); 2311 del_timer_sync(&nic->watchdog); 2312 netif_carrier_off(nic->netdev); 2313 e100_clean_cbs(nic); 2314 e100_rx_clean_list(nic); 2315 } 2316 e100_tx_timeout(struct net_device * netdev,unsigned int txqueue)2317 static void e100_tx_timeout(struct net_device *netdev, unsigned int txqueue) 2318 { 2319 struct nic *nic = netdev_priv(netdev); 2320 2321 /* Reset outside of interrupt context, to avoid request_irq 2322 * in interrupt context */ 2323 schedule_work(&nic->tx_timeout_task); 2324 } 2325 e100_tx_timeout_task(struct work_struct * work)2326 static void e100_tx_timeout_task(struct work_struct *work) 2327 { 2328 struct nic *nic = container_of(work, struct nic, tx_timeout_task); 2329 struct net_device *netdev = nic->netdev; 2330 2331 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev, 2332 "scb.status=0x%02X\n", ioread8(&nic->csr->scb.status)); 2333 2334 rtnl_lock(); 2335 if (netif_running(netdev)) { 2336 e100_down(netdev_priv(netdev)); 2337 e100_up(netdev_priv(netdev)); 2338 } 2339 rtnl_unlock(); 2340 } 2341 e100_loopback_test(struct nic * nic,enum loopback loopback_mode)2342 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode) 2343 { 2344 int err; 2345 struct sk_buff *skb; 2346 2347 /* Use driver resources to perform internal MAC or PHY 2348 * loopback test. A single packet is prepared and transmitted 2349 * in loopback mode, and the test passes if the received 2350 * packet compares byte-for-byte to the transmitted packet. */ 2351 2352 if ((err = e100_rx_alloc_list(nic))) 2353 return err; 2354 if ((err = e100_alloc_cbs(nic))) 2355 goto err_clean_rx; 2356 2357 /* ICH PHY loopback is broken so do MAC loopback instead */ 2358 if (nic->flags & ich && loopback_mode == lb_phy) 2359 loopback_mode = lb_mac; 2360 2361 nic->loopback = loopback_mode; 2362 if ((err = e100_hw_init(nic))) 2363 goto err_loopback_none; 2364 2365 if (loopback_mode == lb_phy) 2366 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 2367 BMCR_LOOPBACK); 2368 2369 e100_start_receiver(nic, NULL); 2370 2371 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) { 2372 err = -ENOMEM; 2373 goto err_loopback_none; 2374 } 2375 skb_put(skb, ETH_DATA_LEN); 2376 memset(skb->data, 0xFF, ETH_DATA_LEN); 2377 e100_xmit_frame(skb, nic->netdev); 2378 2379 msleep(10); 2380 2381 dma_sync_single_for_cpu(&nic->pdev->dev, nic->rx_to_clean->dma_addr, 2382 RFD_BUF_LEN, DMA_BIDIRECTIONAL); 2383 2384 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd), 2385 skb->data, ETH_DATA_LEN)) 2386 err = -EAGAIN; 2387 2388 err_loopback_none: 2389 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0); 2390 nic->loopback = lb_none; 2391 e100_clean_cbs(nic); 2392 e100_hw_reset(nic); 2393 err_clean_rx: 2394 e100_rx_clean_list(nic); 2395 return err; 2396 } 2397 2398 #define MII_LED_CONTROL 0x1B 2399 #define E100_82552_LED_OVERRIDE 0x19 2400 #define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */ 2401 #define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */ 2402 e100_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * cmd)2403 static int e100_get_link_ksettings(struct net_device *netdev, 2404 struct ethtool_link_ksettings *cmd) 2405 { 2406 struct nic *nic = netdev_priv(netdev); 2407 2408 mii_ethtool_get_link_ksettings(&nic->mii, cmd); 2409 2410 return 0; 2411 } 2412 e100_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * cmd)2413 static int e100_set_link_ksettings(struct net_device *netdev, 2414 const struct ethtool_link_ksettings *cmd) 2415 { 2416 struct nic *nic = netdev_priv(netdev); 2417 int err; 2418 2419 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET); 2420 err = mii_ethtool_set_link_ksettings(&nic->mii, cmd); 2421 e100_exec_cb(nic, NULL, e100_configure); 2422 2423 return err; 2424 } 2425 e100_get_drvinfo(struct net_device * netdev,struct ethtool_drvinfo * info)2426 static void e100_get_drvinfo(struct net_device *netdev, 2427 struct ethtool_drvinfo *info) 2428 { 2429 struct nic *nic = netdev_priv(netdev); 2430 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 2431 strscpy(info->bus_info, pci_name(nic->pdev), 2432 sizeof(info->bus_info)); 2433 } 2434 2435 #define E100_PHY_REGS 0x1D e100_get_regs_len(struct net_device * netdev)2436 static int e100_get_regs_len(struct net_device *netdev) 2437 { 2438 struct nic *nic = netdev_priv(netdev); 2439 2440 /* We know the number of registers, and the size of the dump buffer. 2441 * Calculate the total size in bytes. 2442 */ 2443 return (1 + E100_PHY_REGS) * sizeof(u32) + sizeof(nic->mem->dump_buf); 2444 } 2445 e100_get_regs(struct net_device * netdev,struct ethtool_regs * regs,void * p)2446 static void e100_get_regs(struct net_device *netdev, 2447 struct ethtool_regs *regs, void *p) 2448 { 2449 struct nic *nic = netdev_priv(netdev); 2450 u32 *buff = p; 2451 int i; 2452 2453 regs->version = (1 << 24) | nic->pdev->revision; 2454 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 | 2455 ioread8(&nic->csr->scb.cmd_lo) << 16 | 2456 ioread16(&nic->csr->scb.status); 2457 for (i = 0; i < E100_PHY_REGS; i++) 2458 /* Note that we read the registers in reverse order. This 2459 * ordering is the ABI apparently used by ethtool and other 2460 * applications. 2461 */ 2462 buff[1 + i] = mdio_read(netdev, nic->mii.phy_id, 2463 E100_PHY_REGS - 1 - i); 2464 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf)); 2465 e100_exec_cb(nic, NULL, e100_dump); 2466 msleep(10); 2467 memcpy(&buff[1 + E100_PHY_REGS], nic->mem->dump_buf, 2468 sizeof(nic->mem->dump_buf)); 2469 } 2470 e100_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)2471 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2472 { 2473 struct nic *nic = netdev_priv(netdev); 2474 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0; 2475 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0; 2476 } 2477 e100_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)2478 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2479 { 2480 struct nic *nic = netdev_priv(netdev); 2481 2482 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) || 2483 !device_can_wakeup(&nic->pdev->dev)) 2484 return -EOPNOTSUPP; 2485 2486 if (wol->wolopts) 2487 nic->flags |= wol_magic; 2488 else 2489 nic->flags &= ~wol_magic; 2490 2491 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts); 2492 2493 e100_exec_cb(nic, NULL, e100_configure); 2494 2495 return 0; 2496 } 2497 e100_get_msglevel(struct net_device * netdev)2498 static u32 e100_get_msglevel(struct net_device *netdev) 2499 { 2500 struct nic *nic = netdev_priv(netdev); 2501 return nic->msg_enable; 2502 } 2503 e100_set_msglevel(struct net_device * netdev,u32 value)2504 static void e100_set_msglevel(struct net_device *netdev, u32 value) 2505 { 2506 struct nic *nic = netdev_priv(netdev); 2507 nic->msg_enable = value; 2508 } 2509 e100_nway_reset(struct net_device * netdev)2510 static int e100_nway_reset(struct net_device *netdev) 2511 { 2512 struct nic *nic = netdev_priv(netdev); 2513 return mii_nway_restart(&nic->mii); 2514 } 2515 e100_get_link(struct net_device * netdev)2516 static u32 e100_get_link(struct net_device *netdev) 2517 { 2518 struct nic *nic = netdev_priv(netdev); 2519 return mii_link_ok(&nic->mii); 2520 } 2521 e100_get_eeprom_len(struct net_device * netdev)2522 static int e100_get_eeprom_len(struct net_device *netdev) 2523 { 2524 struct nic *nic = netdev_priv(netdev); 2525 return nic->eeprom_wc << 1; 2526 } 2527 2528 #define E100_EEPROM_MAGIC 0x1234 e100_get_eeprom(struct net_device * netdev,struct ethtool_eeprom * eeprom,u8 * bytes)2529 static int e100_get_eeprom(struct net_device *netdev, 2530 struct ethtool_eeprom *eeprom, u8 *bytes) 2531 { 2532 struct nic *nic = netdev_priv(netdev); 2533 2534 eeprom->magic = E100_EEPROM_MAGIC; 2535 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len); 2536 2537 return 0; 2538 } 2539 e100_set_eeprom(struct net_device * netdev,struct ethtool_eeprom * eeprom,u8 * bytes)2540 static int e100_set_eeprom(struct net_device *netdev, 2541 struct ethtool_eeprom *eeprom, u8 *bytes) 2542 { 2543 struct nic *nic = netdev_priv(netdev); 2544 2545 if (eeprom->magic != E100_EEPROM_MAGIC) 2546 return -EINVAL; 2547 2548 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len); 2549 2550 return e100_eeprom_save(nic, eeprom->offset >> 1, 2551 (eeprom->len >> 1) + 1); 2552 } 2553 e100_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)2554 static void e100_get_ringparam(struct net_device *netdev, 2555 struct ethtool_ringparam *ring, 2556 struct kernel_ethtool_ringparam *kernel_ring, 2557 struct netlink_ext_ack *extack) 2558 { 2559 struct nic *nic = netdev_priv(netdev); 2560 struct param_range *rfds = &nic->params.rfds; 2561 struct param_range *cbs = &nic->params.cbs; 2562 2563 ring->rx_max_pending = rfds->max; 2564 ring->tx_max_pending = cbs->max; 2565 ring->rx_pending = rfds->count; 2566 ring->tx_pending = cbs->count; 2567 } 2568 e100_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)2569 static int e100_set_ringparam(struct net_device *netdev, 2570 struct ethtool_ringparam *ring, 2571 struct kernel_ethtool_ringparam *kernel_ring, 2572 struct netlink_ext_ack *extack) 2573 { 2574 struct nic *nic = netdev_priv(netdev); 2575 struct param_range *rfds = &nic->params.rfds; 2576 struct param_range *cbs = &nic->params.cbs; 2577 2578 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 2579 return -EINVAL; 2580 2581 if (netif_running(netdev)) 2582 e100_down(nic); 2583 rfds->count = max(ring->rx_pending, rfds->min); 2584 rfds->count = min(rfds->count, rfds->max); 2585 cbs->count = max(ring->tx_pending, cbs->min); 2586 cbs->count = min(cbs->count, cbs->max); 2587 netif_info(nic, drv, nic->netdev, "Ring Param settings: rx: %d, tx %d\n", 2588 rfds->count, cbs->count); 2589 if (netif_running(netdev)) 2590 e100_up(nic); 2591 2592 return 0; 2593 } 2594 2595 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = { 2596 "Link test (on/offline)", 2597 "Eeprom test (on/offline)", 2598 "Self test (offline)", 2599 "Mac loopback (offline)", 2600 "Phy loopback (offline)", 2601 }; 2602 #define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test) 2603 e100_diag_test(struct net_device * netdev,struct ethtool_test * test,u64 * data)2604 static void e100_diag_test(struct net_device *netdev, 2605 struct ethtool_test *test, u64 *data) 2606 { 2607 struct ethtool_cmd cmd; 2608 struct nic *nic = netdev_priv(netdev); 2609 int i; 2610 2611 memset(data, 0, E100_TEST_LEN * sizeof(u64)); 2612 data[0] = !mii_link_ok(&nic->mii); 2613 data[1] = e100_eeprom_load(nic); 2614 if (test->flags & ETH_TEST_FL_OFFLINE) { 2615 2616 /* save speed, duplex & autoneg settings */ 2617 mii_ethtool_gset(&nic->mii, &cmd); 2618 2619 if (netif_running(netdev)) 2620 e100_down(nic); 2621 data[2] = e100_self_test(nic); 2622 data[3] = e100_loopback_test(nic, lb_mac); 2623 data[4] = e100_loopback_test(nic, lb_phy); 2624 2625 /* restore speed, duplex & autoneg settings */ 2626 mii_ethtool_sset(&nic->mii, &cmd); 2627 2628 if (netif_running(netdev)) 2629 e100_up(nic); 2630 } 2631 for (i = 0; i < E100_TEST_LEN; i++) 2632 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0; 2633 2634 msleep_interruptible(4 * 1000); 2635 } 2636 e100_set_phys_id(struct net_device * netdev,enum ethtool_phys_id_state state)2637 static int e100_set_phys_id(struct net_device *netdev, 2638 enum ethtool_phys_id_state state) 2639 { 2640 struct nic *nic = netdev_priv(netdev); 2641 enum led_state { 2642 led_on = 0x01, 2643 led_off = 0x04, 2644 led_on_559 = 0x05, 2645 led_on_557 = 0x07, 2646 }; 2647 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE : 2648 MII_LED_CONTROL; 2649 u16 leds = 0; 2650 2651 switch (state) { 2652 case ETHTOOL_ID_ACTIVE: 2653 return 2; 2654 2655 case ETHTOOL_ID_ON: 2656 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_ON : 2657 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559; 2658 break; 2659 2660 case ETHTOOL_ID_OFF: 2661 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_OFF : led_off; 2662 break; 2663 2664 case ETHTOOL_ID_INACTIVE: 2665 break; 2666 } 2667 2668 mdio_write(netdev, nic->mii.phy_id, led_reg, leds); 2669 return 0; 2670 } 2671 2672 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = { 2673 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", 2674 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", 2675 "rx_length_errors", "rx_over_errors", "rx_crc_errors", 2676 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", 2677 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", 2678 "tx_heartbeat_errors", "tx_window_errors", 2679 /* device-specific stats */ 2680 "tx_deferred", "tx_single_collisions", "tx_multi_collisions", 2681 "tx_flow_control_pause", "rx_flow_control_pause", 2682 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets", 2683 "rx_short_frame_errors", "rx_over_length_errors", 2684 }; 2685 #define E100_NET_STATS_LEN 21 2686 #define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats) 2687 e100_get_sset_count(struct net_device * netdev,int sset)2688 static int e100_get_sset_count(struct net_device *netdev, int sset) 2689 { 2690 switch (sset) { 2691 case ETH_SS_TEST: 2692 return E100_TEST_LEN; 2693 case ETH_SS_STATS: 2694 return E100_STATS_LEN; 2695 default: 2696 return -EOPNOTSUPP; 2697 } 2698 } 2699 e100_get_ethtool_stats(struct net_device * netdev,struct ethtool_stats * stats,u64 * data)2700 static void e100_get_ethtool_stats(struct net_device *netdev, 2701 struct ethtool_stats *stats, u64 *data) 2702 { 2703 struct nic *nic = netdev_priv(netdev); 2704 int i; 2705 2706 for (i = 0; i < E100_NET_STATS_LEN; i++) 2707 data[i] = ((unsigned long *)&netdev->stats)[i]; 2708 2709 data[i++] = nic->tx_deferred; 2710 data[i++] = nic->tx_single_collisions; 2711 data[i++] = nic->tx_multiple_collisions; 2712 data[i++] = nic->tx_fc_pause; 2713 data[i++] = nic->rx_fc_pause; 2714 data[i++] = nic->rx_fc_unsupported; 2715 data[i++] = nic->tx_tco_frames; 2716 data[i++] = nic->rx_tco_frames; 2717 data[i++] = nic->rx_short_frame_errors; 2718 data[i++] = nic->rx_over_length_errors; 2719 } 2720 e100_get_strings(struct net_device * netdev,u32 stringset,u8 * data)2721 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2722 { 2723 switch (stringset) { 2724 case ETH_SS_TEST: 2725 memcpy(data, e100_gstrings_test, sizeof(e100_gstrings_test)); 2726 break; 2727 case ETH_SS_STATS: 2728 memcpy(data, e100_gstrings_stats, sizeof(e100_gstrings_stats)); 2729 break; 2730 } 2731 } 2732 2733 static const struct ethtool_ops e100_ethtool_ops = { 2734 .get_drvinfo = e100_get_drvinfo, 2735 .get_regs_len = e100_get_regs_len, 2736 .get_regs = e100_get_regs, 2737 .get_wol = e100_get_wol, 2738 .set_wol = e100_set_wol, 2739 .get_msglevel = e100_get_msglevel, 2740 .set_msglevel = e100_set_msglevel, 2741 .nway_reset = e100_nway_reset, 2742 .get_link = e100_get_link, 2743 .get_eeprom_len = e100_get_eeprom_len, 2744 .get_eeprom = e100_get_eeprom, 2745 .set_eeprom = e100_set_eeprom, 2746 .get_ringparam = e100_get_ringparam, 2747 .set_ringparam = e100_set_ringparam, 2748 .self_test = e100_diag_test, 2749 .get_strings = e100_get_strings, 2750 .set_phys_id = e100_set_phys_id, 2751 .get_ethtool_stats = e100_get_ethtool_stats, 2752 .get_sset_count = e100_get_sset_count, 2753 .get_ts_info = ethtool_op_get_ts_info, 2754 .get_link_ksettings = e100_get_link_ksettings, 2755 .set_link_ksettings = e100_set_link_ksettings, 2756 }; 2757 e100_do_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2758 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2759 { 2760 struct nic *nic = netdev_priv(netdev); 2761 2762 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL); 2763 } 2764 e100_alloc(struct nic * nic)2765 static int e100_alloc(struct nic *nic) 2766 { 2767 nic->mem = dma_alloc_coherent(&nic->pdev->dev, sizeof(struct mem), 2768 &nic->dma_addr, GFP_KERNEL); 2769 return nic->mem ? 0 : -ENOMEM; 2770 } 2771 e100_free(struct nic * nic)2772 static void e100_free(struct nic *nic) 2773 { 2774 if (nic->mem) { 2775 dma_free_coherent(&nic->pdev->dev, sizeof(struct mem), 2776 nic->mem, nic->dma_addr); 2777 nic->mem = NULL; 2778 } 2779 } 2780 e100_open(struct net_device * netdev)2781 static int e100_open(struct net_device *netdev) 2782 { 2783 struct nic *nic = netdev_priv(netdev); 2784 int err = 0; 2785 2786 netif_carrier_off(netdev); 2787 if ((err = e100_up(nic))) 2788 netif_err(nic, ifup, nic->netdev, "Cannot open interface, aborting\n"); 2789 return err; 2790 } 2791 e100_close(struct net_device * netdev)2792 static int e100_close(struct net_device *netdev) 2793 { 2794 e100_down(netdev_priv(netdev)); 2795 return 0; 2796 } 2797 e100_set_features(struct net_device * netdev,netdev_features_t features)2798 static int e100_set_features(struct net_device *netdev, 2799 netdev_features_t features) 2800 { 2801 struct nic *nic = netdev_priv(netdev); 2802 netdev_features_t changed = features ^ netdev->features; 2803 2804 if (!(changed & (NETIF_F_RXFCS | NETIF_F_RXALL))) 2805 return 0; 2806 2807 netdev->features = features; 2808 e100_exec_cb(nic, NULL, e100_configure); 2809 return 1; 2810 } 2811 2812 static const struct net_device_ops e100_netdev_ops = { 2813 .ndo_open = e100_open, 2814 .ndo_stop = e100_close, 2815 .ndo_start_xmit = e100_xmit_frame, 2816 .ndo_validate_addr = eth_validate_addr, 2817 .ndo_set_rx_mode = e100_set_multicast_list, 2818 .ndo_set_mac_address = e100_set_mac_address, 2819 .ndo_eth_ioctl = e100_do_ioctl, 2820 .ndo_tx_timeout = e100_tx_timeout, 2821 #ifdef CONFIG_NET_POLL_CONTROLLER 2822 .ndo_poll_controller = e100_netpoll, 2823 #endif 2824 .ndo_set_features = e100_set_features, 2825 }; 2826 e100_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2827 static int e100_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2828 { 2829 struct net_device *netdev; 2830 struct nic *nic; 2831 int err; 2832 2833 if (!(netdev = alloc_etherdev(sizeof(struct nic)))) 2834 return -ENOMEM; 2835 2836 netdev->hw_features |= NETIF_F_RXFCS; 2837 netdev->priv_flags |= IFF_SUPP_NOFCS; 2838 netdev->hw_features |= NETIF_F_RXALL; 2839 2840 netdev->netdev_ops = &e100_netdev_ops; 2841 netdev->ethtool_ops = &e100_ethtool_ops; 2842 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD; 2843 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 2844 2845 nic = netdev_priv(netdev); 2846 netif_napi_add_weight(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT); 2847 nic->netdev = netdev; 2848 nic->pdev = pdev; 2849 nic->msg_enable = (1 << debug) - 1; 2850 nic->mdio_ctrl = mdio_ctrl_hw; 2851 pci_set_drvdata(pdev, netdev); 2852 2853 if ((err = pci_enable_device(pdev))) { 2854 netif_err(nic, probe, nic->netdev, "Cannot enable PCI device, aborting\n"); 2855 goto err_out_free_dev; 2856 } 2857 2858 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2859 netif_err(nic, probe, nic->netdev, "Cannot find proper PCI device base address, aborting\n"); 2860 err = -ENODEV; 2861 goto err_out_disable_pdev; 2862 } 2863 2864 if ((err = pci_request_regions(pdev, DRV_NAME))) { 2865 netif_err(nic, probe, nic->netdev, "Cannot obtain PCI resources, aborting\n"); 2866 goto err_out_disable_pdev; 2867 } 2868 2869 if ((err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))) { 2870 netif_err(nic, probe, nic->netdev, "No usable DMA configuration, aborting\n"); 2871 goto err_out_free_res; 2872 } 2873 2874 SET_NETDEV_DEV(netdev, &pdev->dev); 2875 2876 if (use_io) 2877 netif_info(nic, probe, nic->netdev, "using i/o access mode\n"); 2878 2879 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr)); 2880 if (!nic->csr) { 2881 netif_err(nic, probe, nic->netdev, "Cannot map device registers, aborting\n"); 2882 err = -ENOMEM; 2883 goto err_out_free_res; 2884 } 2885 2886 if (ent->driver_data) 2887 nic->flags |= ich; 2888 else 2889 nic->flags &= ~ich; 2890 2891 e100_get_defaults(nic); 2892 2893 /* D100 MAC doesn't allow rx of vlan packets with normal MTU */ 2894 if (nic->mac < mac_82558_D101_A4) 2895 netdev->features |= NETIF_F_VLAN_CHALLENGED; 2896 2897 /* locks must be initialized before calling hw_reset */ 2898 spin_lock_init(&nic->cb_lock); 2899 spin_lock_init(&nic->cmd_lock); 2900 spin_lock_init(&nic->mdio_lock); 2901 2902 /* Reset the device before pci_set_master() in case device is in some 2903 * funky state and has an interrupt pending - hint: we don't have the 2904 * interrupt handler registered yet. */ 2905 e100_hw_reset(nic); 2906 2907 pci_set_master(pdev); 2908 2909 timer_setup(&nic->watchdog, e100_watchdog, 0); 2910 2911 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task); 2912 2913 if ((err = e100_alloc(nic))) { 2914 netif_err(nic, probe, nic->netdev, "Cannot alloc driver memory, aborting\n"); 2915 goto err_out_iounmap; 2916 } 2917 2918 if ((err = e100_eeprom_load(nic))) 2919 goto err_out_free; 2920 2921 e100_phy_init(nic); 2922 2923 eth_hw_addr_set(netdev, (u8 *)nic->eeprom); 2924 if (!is_valid_ether_addr(netdev->dev_addr)) { 2925 if (!eeprom_bad_csum_allow) { 2926 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, aborting\n"); 2927 err = -EAGAIN; 2928 goto err_out_free; 2929 } else { 2930 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, you MUST configure one.\n"); 2931 } 2932 } 2933 2934 /* Wol magic packet can be enabled from eeprom */ 2935 if ((nic->mac >= mac_82558_D101_A4) && 2936 (le16_to_cpu(nic->eeprom[eeprom_id]) & eeprom_id_wol)) { 2937 nic->flags |= wol_magic; 2938 device_set_wakeup_enable(&pdev->dev, true); 2939 } 2940 2941 /* ack any pending wake events, disable PME */ 2942 pci_pme_active(pdev, false); 2943 2944 strcpy(netdev->name, "eth%d"); 2945 if ((err = register_netdev(netdev))) { 2946 netif_err(nic, probe, nic->netdev, "Cannot register net device, aborting\n"); 2947 goto err_out_free; 2948 } 2949 nic->cbs_pool = dma_pool_create(netdev->name, 2950 &nic->pdev->dev, 2951 nic->params.cbs.max * sizeof(struct cb), 2952 sizeof(u32), 2953 0); 2954 if (!nic->cbs_pool) { 2955 netif_err(nic, probe, nic->netdev, "Cannot create DMA pool, aborting\n"); 2956 err = -ENOMEM; 2957 goto err_out_pool; 2958 } 2959 netif_info(nic, probe, nic->netdev, 2960 "addr 0x%llx, irq %d, MAC addr %pM\n", 2961 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0), 2962 pdev->irq, netdev->dev_addr); 2963 2964 return 0; 2965 2966 err_out_pool: 2967 unregister_netdev(netdev); 2968 err_out_free: 2969 e100_free(nic); 2970 err_out_iounmap: 2971 pci_iounmap(pdev, nic->csr); 2972 err_out_free_res: 2973 pci_release_regions(pdev); 2974 err_out_disable_pdev: 2975 pci_disable_device(pdev); 2976 err_out_free_dev: 2977 free_netdev(netdev); 2978 return err; 2979 } 2980 e100_remove(struct pci_dev * pdev)2981 static void e100_remove(struct pci_dev *pdev) 2982 { 2983 struct net_device *netdev = pci_get_drvdata(pdev); 2984 2985 if (netdev) { 2986 struct nic *nic = netdev_priv(netdev); 2987 unregister_netdev(netdev); 2988 e100_free(nic); 2989 pci_iounmap(pdev, nic->csr); 2990 dma_pool_destroy(nic->cbs_pool); 2991 free_netdev(netdev); 2992 pci_release_regions(pdev); 2993 pci_disable_device(pdev); 2994 } 2995 } 2996 2997 #define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */ 2998 #define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */ 2999 #define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */ __e100_shutdown(struct pci_dev * pdev,bool * enable_wake)3000 static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake) 3001 { 3002 struct net_device *netdev = pci_get_drvdata(pdev); 3003 struct nic *nic = netdev_priv(netdev); 3004 3005 netif_device_detach(netdev); 3006 3007 if (netif_running(netdev)) 3008 e100_down(nic); 3009 3010 if ((nic->flags & wol_magic) | e100_asf(nic)) { 3011 /* enable reverse auto-negotiation */ 3012 if (nic->phy == phy_82552_v) { 3013 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id, 3014 E100_82552_SMARTSPEED); 3015 3016 mdio_write(netdev, nic->mii.phy_id, 3017 E100_82552_SMARTSPEED, smartspeed | 3018 E100_82552_REV_ANEG | E100_82552_ANEG_NOW); 3019 } 3020 *enable_wake = true; 3021 } else { 3022 *enable_wake = false; 3023 } 3024 3025 pci_disable_device(pdev); 3026 } 3027 __e100_power_off(struct pci_dev * pdev,bool wake)3028 static int __e100_power_off(struct pci_dev *pdev, bool wake) 3029 { 3030 if (wake) 3031 return pci_prepare_to_sleep(pdev); 3032 3033 pci_wake_from_d3(pdev, false); 3034 pci_set_power_state(pdev, PCI_D3hot); 3035 3036 return 0; 3037 } 3038 e100_suspend(struct device * dev_d)3039 static int e100_suspend(struct device *dev_d) 3040 { 3041 bool wake; 3042 3043 __e100_shutdown(to_pci_dev(dev_d), &wake); 3044 3045 return 0; 3046 } 3047 e100_resume(struct device * dev_d)3048 static int e100_resume(struct device *dev_d) 3049 { 3050 struct net_device *netdev = dev_get_drvdata(dev_d); 3051 struct nic *nic = netdev_priv(netdev); 3052 int err; 3053 3054 err = pci_enable_device(to_pci_dev(dev_d)); 3055 if (err) { 3056 netdev_err(netdev, "Resume cannot enable PCI device, aborting\n"); 3057 return err; 3058 } 3059 pci_set_master(to_pci_dev(dev_d)); 3060 3061 /* disable reverse auto-negotiation */ 3062 if (nic->phy == phy_82552_v) { 3063 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id, 3064 E100_82552_SMARTSPEED); 3065 3066 mdio_write(netdev, nic->mii.phy_id, 3067 E100_82552_SMARTSPEED, 3068 smartspeed & ~(E100_82552_REV_ANEG)); 3069 } 3070 3071 if (netif_running(netdev)) 3072 e100_up(nic); 3073 3074 netif_device_attach(netdev); 3075 3076 return 0; 3077 } 3078 e100_shutdown(struct pci_dev * pdev)3079 static void e100_shutdown(struct pci_dev *pdev) 3080 { 3081 bool wake; 3082 __e100_shutdown(pdev, &wake); 3083 if (system_state == SYSTEM_POWER_OFF) 3084 __e100_power_off(pdev, wake); 3085 } 3086 3087 /* ------------------ PCI Error Recovery infrastructure -------------- */ 3088 /** 3089 * e100_io_error_detected - called when PCI error is detected. 3090 * @pdev: Pointer to PCI device 3091 * @state: The current pci connection state 3092 */ e100_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3093 static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 3094 { 3095 struct net_device *netdev = pci_get_drvdata(pdev); 3096 struct nic *nic = netdev_priv(netdev); 3097 3098 netif_device_detach(netdev); 3099 3100 if (state == pci_channel_io_perm_failure) 3101 return PCI_ERS_RESULT_DISCONNECT; 3102 3103 if (netif_running(netdev)) 3104 e100_down(nic); 3105 pci_disable_device(pdev); 3106 3107 /* Request a slot reset. */ 3108 return PCI_ERS_RESULT_NEED_RESET; 3109 } 3110 3111 /** 3112 * e100_io_slot_reset - called after the pci bus has been reset. 3113 * @pdev: Pointer to PCI device 3114 * 3115 * Restart the card from scratch. 3116 */ e100_io_slot_reset(struct pci_dev * pdev)3117 static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev) 3118 { 3119 struct net_device *netdev = pci_get_drvdata(pdev); 3120 struct nic *nic = netdev_priv(netdev); 3121 3122 if (pci_enable_device(pdev)) { 3123 pr_err("Cannot re-enable PCI device after reset\n"); 3124 return PCI_ERS_RESULT_DISCONNECT; 3125 } 3126 pci_set_master(pdev); 3127 3128 /* Only one device per card can do a reset */ 3129 if (0 != PCI_FUNC(pdev->devfn)) 3130 return PCI_ERS_RESULT_RECOVERED; 3131 e100_hw_reset(nic); 3132 e100_phy_init(nic); 3133 3134 return PCI_ERS_RESULT_RECOVERED; 3135 } 3136 3137 /** 3138 * e100_io_resume - resume normal operations 3139 * @pdev: Pointer to PCI device 3140 * 3141 * Resume normal operations after an error recovery 3142 * sequence has been completed. 3143 */ e100_io_resume(struct pci_dev * pdev)3144 static void e100_io_resume(struct pci_dev *pdev) 3145 { 3146 struct net_device *netdev = pci_get_drvdata(pdev); 3147 struct nic *nic = netdev_priv(netdev); 3148 3149 /* ack any pending wake events, disable PME */ 3150 pci_enable_wake(pdev, PCI_D0, 0); 3151 3152 netif_device_attach(netdev); 3153 if (netif_running(netdev)) { 3154 e100_open(netdev); 3155 mod_timer(&nic->watchdog, jiffies); 3156 } 3157 } 3158 3159 static const struct pci_error_handlers e100_err_handler = { 3160 .error_detected = e100_io_error_detected, 3161 .slot_reset = e100_io_slot_reset, 3162 .resume = e100_io_resume, 3163 }; 3164 3165 static DEFINE_SIMPLE_DEV_PM_OPS(e100_pm_ops, e100_suspend, e100_resume); 3166 3167 static struct pci_driver e100_driver = { 3168 .name = DRV_NAME, 3169 .id_table = e100_id_table, 3170 .probe = e100_probe, 3171 .remove = e100_remove, 3172 3173 /* Power Management hooks */ 3174 .driver.pm = pm_sleep_ptr(&e100_pm_ops), 3175 3176 .shutdown = e100_shutdown, 3177 .err_handler = &e100_err_handler, 3178 }; 3179 e100_init_module(void)3180 static int __init e100_init_module(void) 3181 { 3182 if (((1 << debug) - 1) & NETIF_MSG_DRV) { 3183 pr_info("%s\n", DRV_DESCRIPTION); 3184 pr_info("%s\n", DRV_COPYRIGHT); 3185 } 3186 return pci_register_driver(&e100_driver); 3187 } 3188 e100_cleanup_module(void)3189 static void __exit e100_cleanup_module(void) 3190 { 3191 pci_unregister_driver(&e100_driver); 3192 } 3193 3194 module_init(e100_init_module); 3195 module_exit(e100_cleanup_module); 3196