1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Arm Limited. All rights reserved. 4 * 5 * Coresight Address Translation Unit support 6 * 7 * Author: Suzuki K Poulose <suzuki.poulose@arm.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/amba/bus.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/platform_device.h> 17 #include <linux/slab.h> 18 19 #include "coresight-catu.h" 20 #include "coresight-priv.h" 21 #include "coresight-tmc.h" 22 23 #define csdev_to_catu_drvdata(csdev) \ 24 dev_get_drvdata(csdev->dev.parent) 25 26 /* Verbose output for CATU table contents */ 27 #ifdef CATU_DEBUG 28 #define catu_dbg(x, ...) dev_dbg(x, __VA_ARGS__) 29 #else 30 #define catu_dbg(x, ...) do {} while (0) 31 #endif 32 33 struct catu_etr_buf { 34 struct tmc_sg_table *catu_table; 35 dma_addr_t sladdr; 36 }; 37 38 /* 39 * CATU uses a page size of 4KB for page tables as well as data pages. 40 * Each 64bit entry in the table has the following format. 41 * 42 * 63 12 1 0 43 * ------------------------------------ 44 * | Address [63-12] | SBZ | V| 45 * ------------------------------------ 46 * 47 * Where bit[0] V indicates if the address is valid or not. 48 * Each 4K table pages have upto 256 data page pointers, taking upto 2K 49 * size. There are two Link pointers, pointing to the previous and next 50 * table pages respectively at the end of the 4K page. (i.e, entry 510 51 * and 511). 52 * E.g, a table of two pages could look like : 53 * 54 * Table Page 0 Table Page 1 55 * SLADDR ===> x------------------x x--> x-----------------x 56 * INADDR ->| Page 0 | V | | | Page 256 | V | <- INADDR+1M 57 * |------------------| | |-----------------| 58 * INADDR+4K ->| Page 1 | V | | | | 59 * |------------------| | |-----------------| 60 * | Page 2 | V | | | | 61 * |------------------| | |-----------------| 62 * | ... | V | | | ... | 63 * |------------------| | |-----------------| 64 * INADDR+1020K| Page 255 | V | | | Page 511 | V | 65 * SLADDR+2K==>|------------------| | |-----------------| 66 * | UNUSED | | | | | 67 * |------------------| | | | 68 * | UNUSED | | | | | 69 * |------------------| | | | 70 * | ... | | | | | 71 * |------------------| | |-----------------| 72 * | IGNORED | 0 | | | Table Page 0| 1 | 73 * |------------------| | |-----------------| 74 * | Table Page 1| 1 |--x | IGNORED | 0 | 75 * x------------------x x-----------------x 76 * SLADDR+4K==> 77 * 78 * The base input address (used by the ETR, programmed in INADDR_{LO,HI}) 79 * must be aligned to 1MB (the size addressable by a single page table). 80 * The CATU maps INADDR{LO:HI} to the first page in the table pointed 81 * to by SLADDR{LO:HI} and so on. 82 * 83 */ 84 typedef u64 cate_t; 85 86 #define CATU_PAGE_SHIFT 12 87 #define CATU_PAGE_SIZE (1UL << CATU_PAGE_SHIFT) 88 #define CATU_PAGES_PER_SYSPAGE (PAGE_SIZE / CATU_PAGE_SIZE) 89 90 /* Page pointers are only allocated in the first 2K half */ 91 #define CATU_PTRS_PER_PAGE ((CATU_PAGE_SIZE >> 1) / sizeof(cate_t)) 92 #define CATU_PTRS_PER_SYSPAGE (CATU_PAGES_PER_SYSPAGE * CATU_PTRS_PER_PAGE) 93 #define CATU_LINK_PREV ((CATU_PAGE_SIZE / sizeof(cate_t)) - 2) 94 #define CATU_LINK_NEXT ((CATU_PAGE_SIZE / sizeof(cate_t)) - 1) 95 96 #define CATU_ADDR_SHIFT 12 97 #define CATU_ADDR_MASK ~(((cate_t)1 << CATU_ADDR_SHIFT) - 1) 98 #define CATU_ENTRY_VALID ((cate_t)0x1) 99 #define CATU_VALID_ENTRY(addr) \ 100 (((cate_t)(addr) & CATU_ADDR_MASK) | CATU_ENTRY_VALID) 101 #define CATU_ENTRY_ADDR(entry) ((cate_t)(entry) & ~((cate_t)CATU_ENTRY_VALID)) 102 103 /* CATU expects the INADDR to be aligned to 1M. */ 104 #define CATU_DEFAULT_INADDR (1ULL << 20) 105 106 /* 107 * catu_get_table : Retrieve the table pointers for the given @offset 108 * within the buffer. The buffer is wrapped around to a valid offset. 109 * 110 * Returns : The CPU virtual address for the beginning of the table 111 * containing the data page pointer for @offset. If @daddrp is not NULL, 112 * @daddrp points the DMA address of the beginning of the table. 113 */ 114 static cate_t *catu_get_table(struct tmc_sg_table *catu_table, unsigned long offset, 115 dma_addr_t *daddrp) 116 { 117 unsigned long buf_size = tmc_sg_table_buf_size(catu_table); 118 unsigned int table_nr, pg_idx, pg_offset; 119 struct tmc_pages *table_pages = &catu_table->table_pages; 120 void *ptr; 121 122 /* Make sure offset is within the range */ 123 offset %= buf_size; 124 125 /* 126 * Each table can address 1MB and a single kernel page can 127 * contain "CATU_PAGES_PER_SYSPAGE" CATU tables. 128 */ 129 table_nr = offset >> 20; 130 /* Find the table page where the table_nr lies in */ 131 pg_idx = table_nr / CATU_PAGES_PER_SYSPAGE; 132 pg_offset = (table_nr % CATU_PAGES_PER_SYSPAGE) * CATU_PAGE_SIZE; 133 if (daddrp) 134 *daddrp = table_pages->daddrs[pg_idx] + pg_offset; 135 ptr = page_address(table_pages->pages[pg_idx]); 136 return (cate_t *)((unsigned long)ptr + pg_offset); 137 } 138 139 #ifdef CATU_DEBUG 140 static void catu_dump_table(struct tmc_sg_table *catu_table) 141 { 142 int i; 143 cate_t *table; 144 unsigned long table_end, buf_size, offset = 0; 145 146 buf_size = tmc_sg_table_buf_size(catu_table); 147 dev_dbg(catu_table->dev, 148 "Dump table %p, tdaddr: %llx\n", 149 catu_table, catu_table->table_daddr); 150 151 while (offset < buf_size) { 152 table_end = offset + SZ_1M < buf_size ? 153 offset + SZ_1M : buf_size; 154 table = catu_get_table(catu_table, offset, NULL); 155 for (i = 0; offset < table_end; i++, offset += CATU_PAGE_SIZE) 156 dev_dbg(catu_table->dev, "%d: %llx\n", i, table[i]); 157 dev_dbg(catu_table->dev, "Prev : %llx, Next: %llx\n", 158 table[CATU_LINK_PREV], table[CATU_LINK_NEXT]); 159 dev_dbg(catu_table->dev, "== End of sub-table ==="); 160 } 161 dev_dbg(catu_table->dev, "== End of Table ==="); 162 } 163 164 #else 165 static void catu_dump_table(struct tmc_sg_table *catu_table) 166 { 167 } 168 #endif 169 170 static cate_t catu_make_entry(dma_addr_t addr) 171 { 172 return addr ? CATU_VALID_ENTRY(addr) : 0; 173 } 174 175 /* 176 * catu_populate_table : Populate the given CATU table. 177 * The table is always populated as a circular table. 178 * i.e, the "prev" link of the "first" table points to the "last" 179 * table and the "next" link of the "last" table points to the 180 * "first" table. The buffer should be made linear by calling 181 * catu_set_table(). 182 */ 183 static void 184 catu_populate_table(struct tmc_sg_table *catu_table) 185 { 186 int i; 187 int sys_pidx; /* Index to current system data page */ 188 int catu_pidx; /* Index of CATU page within the system data page */ 189 unsigned long offset, buf_size, table_end; 190 dma_addr_t data_daddr; 191 dma_addr_t prev_taddr, next_taddr, cur_taddr; 192 cate_t *table_ptr, *next_table; 193 194 buf_size = tmc_sg_table_buf_size(catu_table); 195 sys_pidx = catu_pidx = 0; 196 offset = 0; 197 198 table_ptr = catu_get_table(catu_table, 0, &cur_taddr); 199 prev_taddr = 0; /* Prev link for the first table */ 200 201 while (offset < buf_size) { 202 /* 203 * The @offset is always 1M aligned here and we have an 204 * empty table @table_ptr to fill. Each table can address 205 * upto 1MB data buffer. The last table may have fewer 206 * entries if the buffer size is not aligned. 207 */ 208 table_end = (offset + SZ_1M) < buf_size ? 209 (offset + SZ_1M) : buf_size; 210 for (i = 0; offset < table_end; 211 i++, offset += CATU_PAGE_SIZE) { 212 213 data_daddr = catu_table->data_pages.daddrs[sys_pidx] + 214 catu_pidx * CATU_PAGE_SIZE; 215 catu_dbg(catu_table->dev, 216 "[table %5ld:%03d] 0x%llx\n", 217 (offset >> 20), i, data_daddr); 218 table_ptr[i] = catu_make_entry(data_daddr); 219 /* Move the pointers for data pages */ 220 catu_pidx = (catu_pidx + 1) % CATU_PAGES_PER_SYSPAGE; 221 if (catu_pidx == 0) 222 sys_pidx++; 223 } 224 225 /* 226 * If we have finished all the valid entries, fill the rest of 227 * the table (i.e, last table page) with invalid entries, 228 * to fail the lookups. 229 */ 230 if (offset == buf_size) { 231 memset(&table_ptr[i], 0, 232 sizeof(cate_t) * (CATU_PTRS_PER_PAGE - i)); 233 next_taddr = 0; 234 } else { 235 next_table = catu_get_table(catu_table, 236 offset, &next_taddr); 237 } 238 239 table_ptr[CATU_LINK_PREV] = catu_make_entry(prev_taddr); 240 table_ptr[CATU_LINK_NEXT] = catu_make_entry(next_taddr); 241 242 catu_dbg(catu_table->dev, 243 "[table%5ld]: Cur: 0x%llx Prev: 0x%llx, Next: 0x%llx\n", 244 (offset >> 20) - 1, cur_taddr, prev_taddr, next_taddr); 245 246 /* Update the prev/next addresses */ 247 if (next_taddr) { 248 prev_taddr = cur_taddr; 249 cur_taddr = next_taddr; 250 table_ptr = next_table; 251 } 252 } 253 254 /* Sync the table for device */ 255 tmc_sg_table_sync_table(catu_table); 256 } 257 258 static struct tmc_sg_table * 259 catu_init_sg_table(struct device *catu_dev, int node, 260 ssize_t size, void **pages) 261 { 262 int nr_tpages; 263 struct tmc_sg_table *catu_table; 264 265 /* 266 * Each table can address upto 1MB and we can have 267 * CATU_PAGES_PER_SYSPAGE tables in a system page. 268 */ 269 nr_tpages = DIV_ROUND_UP(size, CATU_PAGES_PER_SYSPAGE * SZ_1M); 270 catu_table = tmc_alloc_sg_table(catu_dev, node, nr_tpages, 271 size >> PAGE_SHIFT, pages); 272 if (IS_ERR(catu_table)) 273 return catu_table; 274 275 catu_populate_table(catu_table); 276 dev_dbg(catu_dev, 277 "Setup table %p, size %ldKB, %d table pages\n", 278 catu_table, (unsigned long)size >> 10, nr_tpages); 279 catu_dump_table(catu_table); 280 return catu_table; 281 } 282 283 static void catu_free_etr_buf(struct etr_buf *etr_buf) 284 { 285 struct catu_etr_buf *catu_buf; 286 287 if (!etr_buf || etr_buf->mode != ETR_MODE_CATU || !etr_buf->private) 288 return; 289 290 catu_buf = etr_buf->private; 291 tmc_free_sg_table(catu_buf->catu_table); 292 kfree(catu_buf); 293 } 294 295 static ssize_t catu_get_data_etr_buf(struct etr_buf *etr_buf, u64 offset, 296 size_t len, char **bufpp) 297 { 298 struct catu_etr_buf *catu_buf = etr_buf->private; 299 300 return tmc_sg_table_get_data(catu_buf->catu_table, offset, len, bufpp); 301 } 302 303 static void catu_sync_etr_buf(struct etr_buf *etr_buf, u64 rrp, u64 rwp) 304 { 305 struct catu_etr_buf *catu_buf = etr_buf->private; 306 struct tmc_sg_table *catu_table = catu_buf->catu_table; 307 u64 r_offset, w_offset; 308 309 /* 310 * ETR started off at etr_buf->hwaddr. Convert the RRP/RWP to 311 * offsets within the trace buffer. 312 */ 313 r_offset = rrp - etr_buf->hwaddr; 314 w_offset = rwp - etr_buf->hwaddr; 315 316 if (!etr_buf->full) { 317 etr_buf->len = w_offset - r_offset; 318 if (w_offset < r_offset) 319 etr_buf->len += etr_buf->size; 320 } else { 321 etr_buf->len = etr_buf->size; 322 } 323 324 etr_buf->offset = r_offset; 325 tmc_sg_table_sync_data_range(catu_table, r_offset, etr_buf->len); 326 } 327 328 static int catu_alloc_etr_buf(struct tmc_drvdata *tmc_drvdata, 329 struct etr_buf *etr_buf, int node, void **pages) 330 { 331 struct coresight_device *csdev; 332 struct tmc_sg_table *catu_table; 333 struct catu_etr_buf *catu_buf; 334 335 csdev = tmc_etr_get_catu_device(tmc_drvdata); 336 if (!csdev) 337 return -ENODEV; 338 catu_buf = kzalloc_obj(*catu_buf); 339 if (!catu_buf) 340 return -ENOMEM; 341 342 catu_table = catu_init_sg_table(&csdev->dev, node, 343 etr_buf->size, pages); 344 if (IS_ERR(catu_table)) { 345 kfree(catu_buf); 346 return PTR_ERR(catu_table); 347 } 348 349 etr_buf->mode = ETR_MODE_CATU; 350 etr_buf->private = catu_buf; 351 etr_buf->hwaddr = CATU_DEFAULT_INADDR; 352 353 catu_buf->catu_table = catu_table; 354 /* Get the table base address */ 355 catu_buf->sladdr = catu_table->table_daddr; 356 357 return 0; 358 } 359 360 static const struct etr_buf_operations etr_catu_buf_ops = { 361 .alloc = catu_alloc_etr_buf, 362 .free = catu_free_etr_buf, 363 .sync = catu_sync_etr_buf, 364 .get_data = catu_get_data_etr_buf, 365 }; 366 367 static struct attribute *catu_mgmt_attrs[] = { 368 coresight_simple_reg32(devid, CORESIGHT_DEVID), 369 coresight_simple_reg32(control, CATU_CONTROL), 370 coresight_simple_reg32(status, CATU_STATUS), 371 coresight_simple_reg32(mode, CATU_MODE), 372 coresight_simple_reg32(axictrl, CATU_AXICTRL), 373 coresight_simple_reg32(irqen, CATU_IRQEN), 374 coresight_simple_reg64(sladdr, CATU_SLADDRLO, CATU_SLADDRHI), 375 coresight_simple_reg64(inaddr, CATU_INADDRLO, CATU_INADDRHI), 376 NULL, 377 }; 378 379 static const struct attribute_group catu_mgmt_group = { 380 .attrs = catu_mgmt_attrs, 381 .name = "mgmt", 382 }; 383 384 static const struct attribute_group *catu_groups[] = { 385 &catu_mgmt_group, 386 NULL, 387 }; 388 389 390 static int catu_wait_for_ready(struct catu_drvdata *drvdata) 391 { 392 struct csdev_access *csa = &drvdata->csdev->access; 393 394 return coresight_timeout(csa, CATU_STATUS, CATU_STATUS_READY, 1); 395 } 396 397 static int catu_enable_hw(struct catu_drvdata *drvdata, enum cs_mode cs_mode, 398 struct coresight_path *path) 399 { 400 int rc; 401 u32 control, mode; 402 struct etr_buf *etr_buf = NULL; 403 struct device *dev = &drvdata->csdev->dev; 404 struct coresight_device *csdev = drvdata->csdev; 405 struct coresight_device *etrdev; 406 union coresight_dev_subtype etr_subtype = { 407 .sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM 408 }; 409 410 if (catu_wait_for_ready(drvdata)) 411 dev_warn(dev, "Timeout while waiting for READY\n"); 412 413 control = catu_read_control(drvdata); 414 if (control & BIT(CATU_CONTROL_ENABLE)) { 415 dev_warn(dev, "CATU is already enabled\n"); 416 return -EBUSY; 417 } 418 419 rc = coresight_claim_device_unlocked(csdev); 420 if (rc) 421 return rc; 422 423 etrdev = coresight_find_input_type( 424 csdev->pdata, CORESIGHT_DEV_TYPE_SINK, etr_subtype); 425 if (etrdev) { 426 etr_buf = tmc_etr_get_buffer(etrdev, cs_mode, path); 427 if (IS_ERR(etr_buf)) 428 return PTR_ERR(etr_buf); 429 } 430 control |= BIT(CATU_CONTROL_ENABLE); 431 432 if (etr_buf && etr_buf->mode == ETR_MODE_CATU) { 433 struct catu_etr_buf *catu_buf = etr_buf->private; 434 435 mode = CATU_MODE_TRANSLATE; 436 catu_write_axictrl(drvdata, CATU_OS_AXICTRL); 437 catu_write_sladdr(drvdata, catu_buf->sladdr); 438 catu_write_inaddr(drvdata, CATU_DEFAULT_INADDR); 439 } else { 440 mode = CATU_MODE_PASS_THROUGH; 441 catu_write_sladdr(drvdata, 0); 442 catu_write_inaddr(drvdata, 0); 443 } 444 445 catu_write_irqen(drvdata, 0); 446 catu_write_mode(drvdata, mode); 447 catu_write_control(drvdata, control); 448 dev_dbg(dev, "Enabled in %s mode\n", 449 (mode == CATU_MODE_PASS_THROUGH) ? 450 "Pass through" : 451 "Translate"); 452 return 0; 453 } 454 455 static int catu_enable(struct coresight_device *csdev, enum cs_mode mode, 456 struct coresight_path *path) 457 { 458 int rc = 0; 459 struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev); 460 461 guard(raw_spinlock_irqsave)(&catu_drvdata->spinlock); 462 if (csdev->refcnt == 0) { 463 CS_UNLOCK(catu_drvdata->base); 464 rc = catu_enable_hw(catu_drvdata, mode, path); 465 CS_LOCK(catu_drvdata->base); 466 } 467 if (!rc) 468 csdev->refcnt++; 469 return rc; 470 } 471 472 static int catu_disable_hw(struct catu_drvdata *drvdata) 473 { 474 int rc = 0; 475 struct device *dev = &drvdata->csdev->dev; 476 struct coresight_device *csdev = drvdata->csdev; 477 478 catu_write_control(drvdata, 0); 479 coresight_disclaim_device_unlocked(csdev); 480 if (catu_wait_for_ready(drvdata)) { 481 dev_info(dev, "Timeout while waiting for READY\n"); 482 rc = -EAGAIN; 483 } 484 485 dev_dbg(dev, "Disabled\n"); 486 return rc; 487 } 488 489 static int catu_disable(struct coresight_device *csdev, struct coresight_path *path) 490 { 491 int rc = 0; 492 struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev); 493 494 guard(raw_spinlock_irqsave)(&catu_drvdata->spinlock); 495 if (--csdev->refcnt == 0) { 496 CS_UNLOCK(catu_drvdata->base); 497 rc = catu_disable_hw(catu_drvdata); 498 CS_LOCK(catu_drvdata->base); 499 } 500 return rc; 501 } 502 503 static const struct coresight_ops_helper catu_helper_ops = { 504 .enable = catu_enable, 505 .disable = catu_disable, 506 }; 507 508 static const struct coresight_ops catu_ops = { 509 .helper_ops = &catu_helper_ops, 510 }; 511 512 static int __catu_probe(struct device *dev, struct resource *res) 513 { 514 int ret = 0; 515 u32 dma_mask; 516 struct catu_drvdata *drvdata; 517 struct coresight_desc catu_desc; 518 struct coresight_platform_data *pdata = NULL; 519 void __iomem *base; 520 521 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 522 if (!drvdata) 523 return -ENOMEM; 524 525 dev_set_drvdata(dev, drvdata); 526 527 ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); 528 if (ret) 529 return ret; 530 531 catu_desc.name = coresight_alloc_device_name("catu", dev); 532 if (!catu_desc.name) 533 return -ENOMEM; 534 535 base = devm_ioremap_resource(dev, res); 536 if (IS_ERR(base)) { 537 ret = PTR_ERR(base); 538 goto out; 539 } 540 541 /* Setup dma mask for the device */ 542 dma_mask = readl_relaxed(base + CORESIGHT_DEVID) & 0x3f; 543 switch (dma_mask) { 544 case 32: 545 case 40: 546 case 44: 547 case 48: 548 case 52: 549 case 56: 550 case 64: 551 break; 552 default: 553 /* Default to the 40bits as supported by TMC-ETR */ 554 dma_mask = 40; 555 } 556 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(dma_mask)); 557 if (ret) 558 goto out; 559 560 pdata = coresight_get_platform_data(dev); 561 if (IS_ERR(pdata)) { 562 ret = PTR_ERR(pdata); 563 goto out; 564 } 565 dev->platform_data = pdata; 566 567 drvdata->base = base; 568 raw_spin_lock_init(&drvdata->spinlock); 569 catu_desc.access = CSDEV_ACCESS_IOMEM(base); 570 catu_desc.pdata = pdata; 571 catu_desc.dev = dev; 572 catu_desc.groups = catu_groups; 573 catu_desc.type = CORESIGHT_DEV_TYPE_HELPER; 574 catu_desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CATU; 575 catu_desc.ops = &catu_ops; 576 577 coresight_clear_self_claim_tag(&catu_desc.access); 578 drvdata->csdev = coresight_register(&catu_desc); 579 if (IS_ERR(drvdata->csdev)) 580 ret = PTR_ERR(drvdata->csdev); 581 out: 582 return ret; 583 } 584 585 static int catu_probe(struct amba_device *adev, const struct amba_id *id) 586 { 587 int ret; 588 589 ret = __catu_probe(&adev->dev, &adev->res); 590 if (!ret) 591 pm_runtime_put(&adev->dev); 592 593 return ret; 594 } 595 596 static void __catu_remove(struct device *dev) 597 { 598 struct catu_drvdata *drvdata = dev_get_drvdata(dev); 599 600 coresight_unregister(drvdata->csdev); 601 } 602 603 static void catu_remove(struct amba_device *adev) 604 { 605 __catu_remove(&adev->dev); 606 } 607 608 static const struct amba_id catu_ids[] = { 609 CS_AMBA_ID(0x000bb9ee), 610 {}, 611 }; 612 613 MODULE_DEVICE_TABLE(amba, catu_ids); 614 615 static struct amba_driver catu_driver = { 616 .drv = { 617 .name = "coresight-catu", 618 .suppress_bind_attrs = true, 619 }, 620 .probe = catu_probe, 621 .remove = catu_remove, 622 .id_table = catu_ids, 623 }; 624 625 static int catu_platform_probe(struct platform_device *pdev) 626 { 627 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 628 int ret = 0; 629 630 pm_runtime_get_noresume(&pdev->dev); 631 pm_runtime_set_active(&pdev->dev); 632 pm_runtime_enable(&pdev->dev); 633 634 ret = __catu_probe(&pdev->dev, res); 635 pm_runtime_put(&pdev->dev); 636 if (ret) 637 pm_runtime_disable(&pdev->dev); 638 639 return ret; 640 } 641 642 static void catu_platform_remove(struct platform_device *pdev) 643 { 644 struct catu_drvdata *drvdata = dev_get_drvdata(&pdev->dev); 645 646 if (WARN_ON(!drvdata)) 647 return; 648 649 __catu_remove(&pdev->dev); 650 pm_runtime_disable(&pdev->dev); 651 } 652 653 #ifdef CONFIG_PM 654 static int catu_runtime_suspend(struct device *dev) 655 { 656 struct catu_drvdata *drvdata = dev_get_drvdata(dev); 657 658 clk_disable_unprepare(drvdata->atclk); 659 clk_disable_unprepare(drvdata->pclk); 660 661 return 0; 662 } 663 664 static int catu_runtime_resume(struct device *dev) 665 { 666 struct catu_drvdata *drvdata = dev_get_drvdata(dev); 667 int ret; 668 669 ret = clk_prepare_enable(drvdata->pclk); 670 if (ret) 671 return ret; 672 673 ret = clk_prepare_enable(drvdata->atclk); 674 if (ret) 675 clk_disable_unprepare(drvdata->pclk); 676 677 return ret; 678 } 679 #endif 680 681 static const struct dev_pm_ops catu_dev_pm_ops = { 682 SET_RUNTIME_PM_OPS(catu_runtime_suspend, catu_runtime_resume, NULL) 683 }; 684 685 #ifdef CONFIG_ACPI 686 static const struct acpi_device_id catu_acpi_ids[] = { 687 {"ARMHC9CA", 0, 0, 0}, /* ARM CoreSight CATU */ 688 {}, 689 }; 690 691 MODULE_DEVICE_TABLE(acpi, catu_acpi_ids); 692 #endif 693 694 static struct platform_driver catu_platform_driver = { 695 .probe = catu_platform_probe, 696 .remove = catu_platform_remove, 697 .driver = { 698 .name = "coresight-catu-platform", 699 .acpi_match_table = ACPI_PTR(catu_acpi_ids), 700 .suppress_bind_attrs = true, 701 .pm = &catu_dev_pm_ops, 702 }, 703 }; 704 705 static int __init catu_init(void) 706 { 707 int ret; 708 709 ret = coresight_init_driver("catu", &catu_driver, &catu_platform_driver); 710 tmc_etr_set_catu_ops(&etr_catu_buf_ops); 711 return ret; 712 } 713 714 static void __exit catu_exit(void) 715 { 716 tmc_etr_remove_catu_ops(); 717 coresight_remove_driver(&catu_driver, &catu_platform_driver); 718 } 719 720 module_init(catu_init); 721 module_exit(catu_exit); 722 723 MODULE_AUTHOR("Suzuki K Poulose <suzuki.poulose@arm.com>"); 724 MODULE_DESCRIPTION("Arm CoreSight Address Translation Unit (CATU) Driver"); 725 MODULE_LICENSE("GPL v2"); 726